@@ -0,0 +1,68 | |||||
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1 | LIBRARY ieee; | |||
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2 | USE ieee.std_logic_1164.ALL; | |||
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3 | ||||
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4 | ENTITY lpp_lfr_ms_reg_head IS | |||
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5 | ||||
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6 | PORT ( | |||
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7 | clk : IN STD_LOGIC; | |||
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8 | rstn : IN STD_LOGIC; | |||
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9 | ||||
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10 | in_wen : IN STD_LOGIC; | |||
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11 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |||
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12 | in_full : IN STD_LOGIC; | |||
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13 | in_empty : IN STD_LOGIC; | |||
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14 | ||||
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15 | out_wen : OUT STD_LOGIC; | |||
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16 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |||
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17 | out_full : OUT STD_LOGIC | |||
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18 | ); | |||
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19 | ||||
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20 | END lpp_lfr_ms_reg_head; | |||
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21 | ||||
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22 | ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS | |||
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23 | TYPE fsm_state_reg_head IS (REG_EMPTY, REG_FULL); | |||
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24 | SIGNAL fsm_state : fsm_state_reg_head; | |||
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25 | ||||
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26 | SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |||
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27 | SIGNAL out_wen_s : STD_LOGIC; | |||
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28 | BEGIN -- Beh | |||
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29 | ||||
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30 | PROCESS (clk, rstn) | |||
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31 | BEGIN | |||
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32 | IF rstn = '0' THEN | |||
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33 | fsm_state <= REG_EMPTY; | |||
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34 | reg_data <= (OTHERS => '0'); | |||
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35 | out_wen_s <= '1'; | |||
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36 | ELSIF clk'event AND clk = '1' THEN | |||
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37 | out_wen_s <= '1'; | |||
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38 | ||||
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39 | CASE fsm_state IS | |||
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40 | WHEN REG_EMPTY => | |||
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41 | reg_data <= in_data; | |||
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42 | IF in_wen = '0' AND in_full = '1' THEN | |||
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43 | fsm_state <= REG_FULL; | |||
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44 | END IF; | |||
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45 | WHEN REG_FULL => | |||
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46 | IF in_empty = '1' THEN | |||
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47 | out_wen_s <= '0'; | |||
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48 | IF in_wen = '0' THEN | |||
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49 | reg_data <= in_data; | |||
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50 | ELSE | |||
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51 | fsm_state <= REG_EMPTY; | |||
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52 | END IF; | |||
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53 | END IF; | |||
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54 | WHEN OTHERS => NULL; | |||
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55 | END CASE; | |||
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56 | ||||
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57 | END IF; | |||
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58 | END PROCESS; | |||
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59 | ||||
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60 | out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full; | |||
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61 | ||||
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62 | out_data <= reg_data WHEN fsm_state = REG_FULL ELSE in_data; | |||
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63 | ||||
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64 | out_wen <= '0' WHEN out_wen_s = '0' ELSE | |||
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65 | '1' WHEN fsm_state = REG_FULL ELSE | |||
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66 | in_wen; | |||
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67 | ||||
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68 | END Beh; |
@@ -1,439 +1,440 | |||||
1 | VHDLIB=../.. |
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1 | VHDLIB=../.. | |
2 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
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2 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
3 |
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3 | |||
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
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4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
5 | TOP=TB |
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5 | TOP=TB | |
6 |
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6 | |||
7 | CMD_VLIB=vlib |
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7 | CMD_VLIB=vlib | |
8 | CMD_VMAP=vmap |
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8 | CMD_VMAP=vmap | |
9 | CMD_VCOM=@vcom -quiet -93 -work |
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9 | CMD_VCOM=@vcom -quiet -93 -work | |
10 |
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10 | |||
11 | ################## project specific targets ########################## |
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11 | ################## project specific targets ########################## | |
12 |
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12 | |||
13 | all: |
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13 | all: | |
14 | @echo "make vsim" |
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14 | @echo "make vsim" | |
15 | @echo "make libs" |
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15 | @echo "make libs" | |
16 | @echo "make clean" |
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16 | @echo "make clean" | |
17 | @echo "make vcom_grlib vcom_lpp vcom_tb" |
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17 | @echo "make vcom_grlib vcom_lpp vcom_tb" | |
18 |
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18 | |||
19 | run: |
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19 | run: | |
20 | @vsim work.TB -do run.do |
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20 | @vsim work.TB -do run.do | |
21 | # @vsim work.TB |
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21 | # @vsim work.TB | |
22 | # @vsim lpp.lpp_lfr_ms |
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22 | # @vsim lpp.lpp_lfr_ms | |
23 |
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23 | |||
24 | vsim: libs vcom run |
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24 | vsim: libs vcom run | |
25 |
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25 | |||
26 | libs: |
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26 | libs: | |
27 | @$(CMD_VLIB) modelsim |
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27 | @$(CMD_VLIB) modelsim | |
28 | @$(CMD_VMAP) modelsim modelsim |
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28 | @$(CMD_VMAP) modelsim modelsim | |
29 | @$(CMD_VLIB) modelsim/techmap |
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29 | @$(CMD_VLIB) modelsim/techmap | |
30 | @$(CMD_VMAP) techmap modelsim/techmap |
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30 | @$(CMD_VMAP) techmap modelsim/techmap | |
31 | @$(CMD_VLIB) modelsim/grlib |
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31 | @$(CMD_VLIB) modelsim/grlib | |
32 | @$(CMD_VMAP) grlib modelsim/grlib |
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32 | @$(CMD_VMAP) grlib modelsim/grlib | |
33 | @$(CMD_VLIB) modelsim/gaisler |
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33 | @$(CMD_VLIB) modelsim/gaisler | |
34 | @$(CMD_VMAP) gaisler modelsim/gaisler |
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34 | @$(CMD_VMAP) gaisler modelsim/gaisler | |
35 | @$(CMD_VLIB) modelsim/work |
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35 | @$(CMD_VLIB) modelsim/work | |
36 | @$(CMD_VMAP) work modelsim/work |
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36 | @$(CMD_VMAP) work modelsim/work | |
37 | @$(CMD_VLIB) modelsim/lpp |
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37 | @$(CMD_VLIB) modelsim/lpp | |
38 | @$(CMD_VMAP) lpp modelsim/lpp |
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38 | @$(CMD_VMAP) lpp modelsim/lpp | |
39 | @echo "libs done" |
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39 | @echo "libs done" | |
40 |
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40 | |||
41 |
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41 | |||
42 | clean: |
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42 | clean: | |
43 | @rm -Rf modelsim |
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43 | @rm -Rf modelsim | |
44 | @rm -Rf modelsim.ini |
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44 | @rm -Rf modelsim.ini | |
45 | @rm -Rf *~ |
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45 | @rm -Rf *~ | |
46 | @rm -Rf transcript |
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46 | @rm -Rf transcript | |
47 | @rm -Rf wlft* |
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47 | @rm -Rf wlft* | |
48 | @rm -Rf *.wlf |
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48 | @rm -Rf *.wlf | |
49 | @rm -Rf vish_stacktrace.vstf |
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49 | @rm -Rf vish_stacktrace.vstf | |
50 | @rm -Rf libs.do |
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50 | @rm -Rf libs.do | |
51 |
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51 | |||
52 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb |
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52 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb | |
53 |
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53 | |||
54 |
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54 | |||
55 | vcom_tb: |
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55 | vcom_tb: | |
56 | ## $(CMD_VCOM) lpp lpp_memory.vhd |
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56 | ## $(CMD_VCOM) lpp lpp_memory.vhd | |
57 | ## $(CMD_VCOM) lpp lppFIFOxN.vhd |
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57 | ## $(CMD_VCOM) lpp lppFIFOxN.vhd | |
58 | ## $(CMD_VCOM) lpp lpp_FIFO.vhd |
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58 | ## $(CMD_VCOM) lpp lpp_FIFO.vhd | |
59 | ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd |
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59 | ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd | |
60 | $(CMD_VCOM) work TB.vhd |
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60 | $(CMD_VCOM) work TB.vhd | |
61 | @echo "vcom done" |
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61 | @echo "vcom done" | |
62 |
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62 | |||
63 | vcom_grlib: |
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63 | vcom_grlib: | |
64 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd |
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64 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd | |
65 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd |
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65 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd | |
66 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd |
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66 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd | |
67 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd |
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67 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd | |
68 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd |
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68 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd | |
69 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd |
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69 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd | |
70 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd |
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70 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd | |
71 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd |
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71 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd | |
72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd |
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72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd | |
73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd |
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73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd | |
74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd |
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74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd | |
75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd |
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75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd | |
76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd |
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76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd | |
77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd |
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77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd | |
78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd |
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78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd | |
79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd |
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79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd | |
80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd |
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80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd | |
81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd |
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81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd | |
82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd |
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82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd | |
83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd |
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83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd | |
84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd |
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84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd | |
85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd |
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85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd | |
86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd |
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86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd | |
87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd |
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87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd | |
88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd |
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88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd | |
89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd |
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89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd | |
90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd |
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90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd | |
91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd |
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91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd | |
92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd |
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92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd | |
93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd |
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93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd | |
94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd |
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94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd | |
95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd |
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95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd | |
96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd |
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96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd | |
97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd |
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97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd | |
98 | @echo "vcom grlib done" |
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98 | @echo "vcom grlib done" | |
99 |
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99 | |||
100 | vcom_gaisler: |
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100 | vcom_gaisler: | |
101 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd |
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101 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd | |
102 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd |
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102 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd | |
103 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd |
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103 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd | |
104 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd |
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104 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd | |
105 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd |
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105 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd | |
106 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd |
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106 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd | |
107 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd |
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107 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd | |
108 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd |
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108 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd | |
109 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd |
|
109 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd | |
110 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd |
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110 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd | |
111 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd |
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111 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd | |
112 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd |
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112 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd | |
113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd |
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113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd | |
114 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd |
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114 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd | |
115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd |
|
115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd | |
116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd |
|
116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd | |
117 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd |
|
117 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd | |
118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd |
|
118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd | |
119 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd |
|
119 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd | |
120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd |
|
120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd | |
121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd |
|
121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd | |
122 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd |
|
122 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd | |
123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd |
|
123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd | |
124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd |
|
124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd | |
125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd |
|
125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd | |
126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd |
|
126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd | |
127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd |
|
127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd | |
128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd |
|
128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd | |
129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd |
|
129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd | |
130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd |
|
130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd | |
131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd |
|
131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd | |
132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd |
|
132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd | |
133 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd |
|
133 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd | |
134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd |
|
134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd | |
135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd |
|
135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd | |
136 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd |
|
136 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd | |
137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd |
|
137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd | |
138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd |
|
138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd | |
139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd |
|
139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd | |
140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd |
|
140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd | |
141 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd |
|
141 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd | |
142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd |
|
142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd | |
143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd |
|
143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd | |
144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd |
|
144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd | |
145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd |
|
145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd | |
146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd |
|
146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd | |
147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd |
|
147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd | |
148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd |
|
148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd | |
149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd |
|
149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd | |
150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd |
|
150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd | |
151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd |
|
151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd | |
152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd |
|
152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd | |
153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd |
|
153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd | |
154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd |
|
154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd | |
155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd |
|
155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd | |
156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd |
|
156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd | |
157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd |
|
157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd | |
158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd |
|
158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd | |
159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd |
|
159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd | |
160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd |
|
160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd | |
161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd |
|
161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd | |
162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd |
|
162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd | |
163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd |
|
163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd | |
164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd |
|
164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd | |
165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd |
|
165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd | |
166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd |
|
166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd | |
167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd |
|
167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd | |
168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd |
|
168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd | |
169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd |
|
169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd | |
170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd |
|
170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd | |
171 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd |
|
171 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd | |
172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd |
|
172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd | |
173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd |
|
173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd | |
174 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd |
|
174 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd | |
175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd |
|
175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd | |
176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd |
|
176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd | |
177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd |
|
177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd | |
178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd |
|
178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd | |
179 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd |
|
179 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd | |
180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd |
|
180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd | |
181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd |
|
181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd | |
182 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd |
|
182 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd | |
183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd |
|
183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd | |
184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd |
|
184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd | |
185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd |
|
185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd | |
186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd |
|
186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd | |
187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd |
|
187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd | |
188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd |
|
188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd | |
189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd |
|
189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd | |
190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd |
|
190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd | |
191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd |
|
191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd | |
192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd |
|
192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd | |
193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd |
|
193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd | |
194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd |
|
194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd | |
195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd |
|
195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd | |
196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd |
|
196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd | |
197 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd |
|
197 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd | |
198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd |
|
198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd | |
199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd |
|
199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd | |
200 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd |
|
200 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd | |
201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd |
|
201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd | |
202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd |
|
202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd | |
203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd |
|
203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd | |
204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd |
|
204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd | |
205 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd |
|
205 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd | |
206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd |
|
206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd | |
207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd |
|
207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd | |
208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd |
|
208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd | |
209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd |
|
209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd | |
210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd |
|
210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd | |
211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd |
|
211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd | |
212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd |
|
212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd | |
213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd |
|
213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd | |
214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd |
|
214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd | |
215 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd |
|
215 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd | |
216 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd |
|
216 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd | |
217 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd |
|
217 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd | |
218 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd |
|
218 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd | |
219 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd |
|
219 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd | |
220 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd |
|
220 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd | |
221 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd |
|
221 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd | |
222 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd |
|
222 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd | |
223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd |
|
223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd | |
224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd |
|
224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd | |
225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd |
|
225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd | |
226 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd |
|
226 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd | |
227 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd |
|
227 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd | |
228 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd |
|
228 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd | |
229 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd |
|
229 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd | |
230 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd |
|
230 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd | |
231 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd |
|
231 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd | |
232 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd |
|
232 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd | |
233 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd |
|
233 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd | |
234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd |
|
234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd | |
235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd |
|
235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd | |
236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd |
|
236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd | |
237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd |
|
237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd | |
238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd |
|
238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd | |
239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd |
|
239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd | |
240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd |
|
240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd | |
241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd |
|
241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd | |
242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd |
|
242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd | |
243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd |
|
243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd | |
244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd |
|
244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd | |
245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd |
|
245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd | |
246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd |
|
246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd | |
247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd |
|
247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd | |
248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd |
|
248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd | |
249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd |
|
249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd | |
250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd |
|
250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd | |
251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd |
|
251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd | |
252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd |
|
252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd | |
253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd |
|
253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd | |
254 | @echo "vcom gaisler done" |
|
254 | @echo "vcom gaisler done" | |
255 |
|
255 | |||
256 | vcom_techmap: |
|
256 | vcom_techmap: | |
257 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd |
|
257 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd | |
258 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd |
|
258 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd | |
259 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd |
|
259 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd | |
260 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd |
|
260 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd | |
261 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd |
|
261 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd | |
262 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd |
|
262 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd | |
263 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd |
|
263 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd | |
264 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd |
|
264 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd | |
265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd |
|
265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd | |
266 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd |
|
266 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd | |
267 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd |
|
267 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd | |
268 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd |
|
268 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd | |
269 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd |
|
269 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd | |
270 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd |
|
270 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd | |
271 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd |
|
271 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd | |
272 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd |
|
272 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd | |
273 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd |
|
273 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd | |
274 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd |
|
274 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd | |
275 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd |
|
275 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd | |
276 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd |
|
276 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd | |
277 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd |
|
277 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd | |
278 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd |
|
278 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd | |
279 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd |
|
279 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd | |
280 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd |
|
280 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd | |
281 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd |
|
281 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd | |
282 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd |
|
282 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd | |
283 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd |
|
283 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd | |
284 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd |
|
284 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd | |
285 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd |
|
285 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd | |
286 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd |
|
286 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd | |
287 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd |
|
287 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd | |
288 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd |
|
288 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd | |
289 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd |
|
289 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd | |
290 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd |
|
290 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd | |
291 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd |
|
291 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd | |
292 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd |
|
292 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd | |
293 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd |
|
293 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd | |
294 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd |
|
294 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd | |
295 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd |
|
295 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd | |
296 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd |
|
296 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd | |
297 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd |
|
297 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd | |
298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd |
|
298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd | |
299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd |
|
299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd | |
300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd |
|
300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd | |
301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd |
|
301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd | |
302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd |
|
302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd | |
303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd |
|
303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd | |
304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd |
|
304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd | |
305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd |
|
305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd | |
306 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd |
|
306 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd | |
307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd |
|
307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd | |
308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd |
|
308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd | |
309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd |
|
309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd | |
310 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd |
|
310 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd | |
311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd |
|
311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd | |
312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd |
|
312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd | |
313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd |
|
313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd | |
314 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd |
|
314 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd | |
315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd |
|
315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd | |
316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd |
|
316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd | |
317 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd |
|
317 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd | |
318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd |
|
318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd | |
319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd |
|
319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd | |
320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd |
|
320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd | |
321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd |
|
321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd | |
322 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd |
|
322 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd | |
323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd |
|
323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd | |
324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd |
|
324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd | |
325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd |
|
325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd | |
326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd |
|
326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd | |
327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd |
|
327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd | |
328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd |
|
328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd | |
329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd |
|
329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd | |
330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd |
|
330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd | |
331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd |
|
331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd | |
332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd |
|
332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd | |
333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd |
|
333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd | |
334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd |
|
334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd | |
335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd |
|
335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd | |
336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd |
|
336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd | |
337 | @echo "vcom techmap done" |
|
337 | @echo "vcom techmap done" | |
338 |
|
338 | |||
339 | vcom_lpp: |
|
339 | vcom_lpp: | |
340 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd |
|
340 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd | |
341 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd |
|
341 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |
342 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
|
342 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |
343 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd |
|
343 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd | |
344 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
|
344 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |
345 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd |
|
345 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd | |
346 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
346 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |
347 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
347 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |
348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |
349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |
350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |
351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |
352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |
353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |
355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |
356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |
357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |
358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |
359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |
360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |
361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |
362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |
363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |
364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |
365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |
366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |
367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
|
370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd |
|
371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd | |
372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd |
|
372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd |
|
374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |
375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd |
|
375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd | |
376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd |
|
377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd | |
378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd |
|
378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd | |
379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd |
|
379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd | |
380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd |
|
380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd | |
381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd |
|
381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd | |
382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd |
|
383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd | |
384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd |
|
384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd | |
385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd |
|
385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd | |
386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd |
|
386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd | |
387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd |
|
387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd | |
388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd |
|
388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd | |
389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd |
|
389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd | |
390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd |
|
390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd | |
391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd |
|
391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd | |
392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd |
|
392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd | |
393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd |
|
393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd | |
394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd |
|
394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd | |
395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd |
|
395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd | |
396 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd |
|
396 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd | |
397 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
397 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
398 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd |
|
398 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd | |
399 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd |
|
399 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd | |
400 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd |
|
400 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd | |
401 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd |
|
401 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd | |
|
402 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd | |||
402 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
403 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |
403 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd |
|
404 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |
404 | @echo "vcom lpp done" |
|
405 | @echo "vcom lpp done" | |
405 |
|
406 | |||
406 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
407 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
407 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
408 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |
408 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
409 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |
409 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
410 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |
410 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
411 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |
411 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
412 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |
412 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
413 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |
413 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
414 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |
414 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
415 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
415 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
416 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |
416 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
417 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |
417 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
418 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |
418 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
419 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |
419 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
420 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |
420 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
421 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |
421 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
422 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |
422 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
423 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |
423 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
424 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |
424 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
425 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |
425 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
426 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |
426 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
427 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |
427 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
428 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |
428 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
429 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
429 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
430 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
430 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
431 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
431 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
|
432 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
432 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd |
|
433 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |
433 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd |
|
434 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |
434 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd |
|
435 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd | |
435 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd |
|
436 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd | |
436 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd |
|
437 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd | |
437 | # @echo "vcom lpp done" |
|
438 | # @echo "vcom lpp done" | |
438 |
|
439 | |||
439 | #include Makefile_vcom_lpp |
|
440 | #include Makefile_vcom_lpp |
@@ -1,44 +1,74 | |||||
1 | onerror {resume} |
|
1 | onerror {resume} | |
2 | quietly WaveActivateNextPane {} 0 |
|
2 | quietly WaveActivateNextPane {} 0 | |
3 | add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0) |
|
3 | add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0) | |
4 | add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1) |
|
4 | add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1) | |
5 | add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2) |
|
5 | add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2) | |
6 | add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5) |
|
6 | add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5) | |
7 | add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4) |
|
7 | add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4) | |
8 | add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3) |
|
8 | add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3) | |
9 | add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8) |
|
9 | add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8) | |
10 | add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7) |
|
10 | add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7) | |
11 | add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6) |
|
11 | add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6) | |
12 | add wave -noupdate -group debug /tb/lpp_lfr_ms_1/debug_reg |
|
12 | add wave -noupdate -expand -group debug /tb/lpp_lfr_ms_1/debug_reg | |
13 | add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbi |
|
13 | add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi | |
14 | add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbo |
|
14 | add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbo | |
15 | add wave -noupdate -group debug /tb/ready_reg |
|
15 | add wave -noupdate -expand -group debug /tb/ready_reg | |
16 | add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(0) |
|
16 | add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0) | |
17 | add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(1) |
|
17 | add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1) | |
18 | add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(2) |
|
18 | add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2) | |
19 |
add wave -noupdate |
|
19 | add wave -noupdate /tb/lpp_lfr_apbreg_1/debug_signal | |
20 | add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_ms_1/observation_vector_0(2) {-color Blue} /tb/lpp_lfr_ms_1/observation_vector_0(0) {-color Blue}} /tb/lpp_lfr_ms_1/observation_vector_0 |
|
20 | add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_ms_1/observation_vector_0(2) {-color Blue -height 15} /tb/lpp_lfr_ms_1/observation_vector_0(0) {-color Blue -height 15}} /tb/lpp_lfr_ms_1/observation_vector_0 | |
21 | add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1 |
|
21 | add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1 | |
22 | add wave -noupdate -divider {New Divider} |
|
22 | add wave -noupdate -divider {New Divider} | |
23 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter |
|
23 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter | |
24 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_out |
|
24 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_out | |
25 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_wait |
|
25 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_wait | |
|
26 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_bad_component_error | |||
|
27 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_buffer_full | |||
|
28 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_input_fifo_write | |||
|
29 | add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen | |||
|
30 | add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren | |||
|
31 | add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty | |||
|
32 | add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full | |||
|
33 | add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full | |||
|
34 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onnewmatrix {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onerror {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_bad_component_error {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/reg_sp | |||
|
35 | add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_valid | |||
|
36 | add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_read | |||
|
37 | add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_data | |||
|
38 | add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_load | |||
|
39 | add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_pong | |||
|
40 | add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_im | |||
|
41 | add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_re | |||
|
42 | add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_valid | |||
|
43 | add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_ready | |||
|
44 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft | |||
|
45 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel | |||
|
46 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_wen | |||
|
47 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_data | |||
|
48 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full | |||
|
49 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_empty | |||
|
50 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/fsm_state | |||
|
51 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data | |||
|
52 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen_s | |||
|
53 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen | |||
|
54 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_data | |||
|
55 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_full | |||
26 | TreeUpdate [SetDefaultTree] |
|
56 | TreeUpdate [SetDefaultTree] | |
27 |
WaveRestoreCursors {{Cursor 1} { |
|
57 | WaveRestoreCursors {{Cursor 1} {41374417240 ps} 0} {{Cursor 2} {62390873400 ps} 0} | |
28 |
configure wave -namecolwidth |
|
58 | configure wave -namecolwidth 419 | |
29 | configure wave -valuecolwidth 112 |
|
59 | configure wave -valuecolwidth 112 | |
30 | configure wave -justifyvalue left |
|
60 | configure wave -justifyvalue left | |
31 | configure wave -signalnamewidth 0 |
|
61 | configure wave -signalnamewidth 0 | |
32 | configure wave -snapdistance 10 |
|
62 | configure wave -snapdistance 10 | |
33 | configure wave -datasetprefix 0 |
|
63 | configure wave -datasetprefix 0 | |
34 | configure wave -rowmargin 4 |
|
64 | configure wave -rowmargin 4 | |
35 | configure wave -childrowmargin 2 |
|
65 | configure wave -childrowmargin 2 | |
36 | configure wave -gridoffset 0 |
|
66 | configure wave -gridoffset 0 | |
37 | configure wave -gridperiod 1 |
|
67 | configure wave -gridperiod 1 | |
38 | configure wave -griddelta 40 |
|
68 | configure wave -griddelta 40 | |
39 | configure wave -timeline 0 |
|
69 | configure wave -timeline 0 | |
40 | configure wave -timelineunits ps |
|
70 | configure wave -timelineunits ps | |
41 | update |
|
71 | update | |
42 |
WaveRestoreZoom { |
|
72 | WaveRestoreZoom {62074549955 ps} {63157132736 ps} | |
43 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 |
|
73 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 | |
44 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 |
|
74 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 |
@@ -1,1009 +1,1035 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_memory.ALL; |
|
6 | USE lpp.lpp_memory.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.spectral_matrix_package.ALL; |
|
8 | USE lpp.spectral_matrix_package.ALL; | |
9 | USE lpp.lpp_dma_pkg.ALL; |
|
9 | USE lpp.lpp_dma_pkg.ALL; | |
10 | USE lpp.lpp_Header.ALL; |
|
10 | USE lpp.lpp_Header.ALL; | |
11 | USE lpp.lpp_matrix.ALL; |
|
11 | USE lpp.lpp_matrix.ALL; | |
12 | USE lpp.lpp_matrix.ALL; |
|
12 | USE lpp.lpp_matrix.ALL; | |
13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
14 | USE lpp.lpp_fft.ALL; |
|
14 | USE lpp.lpp_fft.ALL; | |
15 | USE lpp.fft_components.ALL; |
|
15 | USE lpp.fft_components.ALL; | |
16 |
|
16 | |||
17 | ENTITY lpp_lfr_ms IS |
|
17 | ENTITY lpp_lfr_ms IS | |
18 | GENERIC ( |
|
18 | GENERIC ( | |
19 | Mem_use : INTEGER := use_RAM |
|
19 | Mem_use : INTEGER := use_RAM | |
20 | ); |
|
20 | ); | |
21 | PORT ( |
|
21 | PORT ( | |
22 | clk : IN STD_LOGIC; |
|
22 | clk : IN STD_LOGIC; | |
23 | rstn : IN STD_LOGIC; |
|
23 | rstn : IN STD_LOGIC; | |
24 |
|
24 | |||
25 | --------------------------------------------------------------------------- |
|
25 | --------------------------------------------------------------------------- | |
26 | -- DATA INPUT |
|
26 | -- DATA INPUT | |
27 | --------------------------------------------------------------------------- |
|
27 | --------------------------------------------------------------------------- | |
28 | -- TIME |
|
28 | -- TIME | |
29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
31 | -- |
|
31 | -- | |
32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
34 | -- |
|
34 | -- | |
35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
37 | -- |
|
37 | -- | |
38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
40 |
|
40 | |||
41 | --------------------------------------------------------------------------- |
|
41 | --------------------------------------------------------------------------- | |
42 | -- DMA |
|
42 | -- DMA | |
43 | --------------------------------------------------------------------------- |
|
43 | --------------------------------------------------------------------------- | |
44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
46 | dma_valid : OUT STD_LOGIC; |
|
46 | dma_valid : OUT STD_LOGIC; | |
47 | dma_valid_burst : OUT STD_LOGIC; |
|
47 | dma_valid_burst : OUT STD_LOGIC; | |
48 | dma_ren : IN STD_LOGIC; |
|
48 | dma_ren : IN STD_LOGIC; | |
49 | dma_done : IN STD_LOGIC; |
|
49 | dma_done : IN STD_LOGIC; | |
50 |
|
50 | |||
51 | -- Reg out |
|
51 | -- Reg out | |
52 | ready_matrix_f0 : OUT STD_LOGIC; |
|
52 | ready_matrix_f0 : OUT STD_LOGIC; | |
53 | ready_matrix_f1 : OUT STD_LOGIC; |
|
53 | ready_matrix_f1 : OUT STD_LOGIC; | |
54 | ready_matrix_f2 : OUT STD_LOGIC; |
|
54 | ready_matrix_f2 : OUT STD_LOGIC; | |
55 | error_bad_component_error : OUT STD_LOGIC; |
|
55 | error_bad_component_error : OUT STD_LOGIC; | |
56 | error_buffer_full : OUT STD_LOGIC; |
|
56 | error_buffer_full : OUT STD_LOGIC; | |
57 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
57 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
58 |
|
58 | |||
59 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
60 | -- |
|
60 | -- | |
61 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
61 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
62 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
62 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
63 |
|
63 | |||
64 | -- Reg In |
|
64 | -- Reg In | |
65 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
65 | status_ready_matrix_f0 : IN STD_LOGIC; | |
66 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
66 | status_ready_matrix_f1 : IN STD_LOGIC; | |
67 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
67 | status_ready_matrix_f2 : IN STD_LOGIC; | |
68 |
|
68 | |||
69 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
69 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
70 | config_active_interruption_onError : IN STD_LOGIC; |
|
70 | config_active_interruption_onError : IN STD_LOGIC; | |
71 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
71 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
72 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
72 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
73 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
74 |
|
74 | |||
75 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
75 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
76 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
76 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
77 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
77 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
78 |
|
78 | |||
79 | ); |
|
79 | ); | |
80 | END; |
|
80 | END; | |
81 |
|
81 | |||
82 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
82 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
83 |
|
83 | |||
84 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
84 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
85 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
85 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
86 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
86 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
87 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
88 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
88 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
89 |
|
89 | |||
90 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
90 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
91 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
91 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
92 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
92 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
93 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
93 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
94 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
94 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
95 |
|
95 | |||
96 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
96 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
97 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
97 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
98 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
98 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
99 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
99 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
100 |
|
100 | |||
101 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
101 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
102 |
|
102 | |||
103 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
103 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
104 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
104 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
105 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
105 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
106 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
106 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
107 |
|
107 | |||
108 | SIGNAL error_wen_f0 : STD_LOGIC; |
|
108 | SIGNAL error_wen_f0 : STD_LOGIC; | |
109 | SIGNAL error_wen_f1 : STD_LOGIC; |
|
109 | SIGNAL error_wen_f1 : STD_LOGIC; | |
110 | SIGNAL error_wen_f2 : STD_LOGIC; |
|
110 | SIGNAL error_wen_f2 : STD_LOGIC; | |
111 |
|
111 | |||
112 | SIGNAL one_sample_f1_full : STD_LOGIC; |
|
112 | SIGNAL one_sample_f1_full : STD_LOGIC; | |
113 | SIGNAL one_sample_f1_wen : STD_LOGIC; |
|
113 | SIGNAL one_sample_f1_wen : STD_LOGIC; | |
114 | SIGNAL one_sample_f2_full : STD_LOGIC; |
|
114 | SIGNAL one_sample_f2_full : STD_LOGIC; | |
115 | SIGNAL one_sample_f2_wen : STD_LOGIC; |
|
115 | SIGNAL one_sample_f2_wen : STD_LOGIC; | |
116 |
|
116 | |||
117 | ----------------------------------------------------------------------------- |
|
117 | ----------------------------------------------------------------------------- | |
118 | -- FSM / SWITCH SELECT CHANNEL |
|
118 | -- FSM / SWITCH SELECT CHANNEL | |
119 | ----------------------------------------------------------------------------- |
|
119 | ----------------------------------------------------------------------------- | |
120 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
|
120 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); | |
121 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
|
121 | SIGNAL state_fsm_select_channel : fsm_select_channel; | |
122 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; |
|
122 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; | |
123 |
|
123 | |||
124 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
124 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
125 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
125 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
126 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
126 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
127 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
127 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
128 |
|
128 | |||
129 | ----------------------------------------------------------------------------- |
|
129 | ----------------------------------------------------------------------------- | |
130 | -- FSM LOAD FFT |
|
130 | -- FSM LOAD FFT | |
131 | ----------------------------------------------------------------------------- |
|
131 | ----------------------------------------------------------------------------- | |
132 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); |
|
132 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); | |
133 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
|
133 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; | |
134 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; |
|
134 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; | |
135 |
|
135 | |||
136 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
136 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
137 | SIGNAL sample_load : STD_LOGIC; |
|
137 | SIGNAL sample_load : STD_LOGIC; | |
138 | SIGNAL sample_valid : STD_LOGIC; |
|
138 | SIGNAL sample_valid : STD_LOGIC; | |
139 | SIGNAL sample_valid_r : STD_LOGIC; |
|
139 | SIGNAL sample_valid_r : STD_LOGIC; | |
140 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
140 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
141 |
|
141 | |||
142 |
|
142 | |||
143 | ----------------------------------------------------------------------------- |
|
143 | ----------------------------------------------------------------------------- | |
144 | -- FFT |
|
144 | -- FFT | |
145 | ----------------------------------------------------------------------------- |
|
145 | ----------------------------------------------------------------------------- | |
146 | SIGNAL fft_read : STD_LOGIC; |
|
146 | SIGNAL fft_read : STD_LOGIC; | |
147 | SIGNAL fft_pong : STD_LOGIC; |
|
147 | SIGNAL fft_pong : STD_LOGIC; | |
148 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
148 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
149 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
149 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
150 | SIGNAL fft_data_valid : STD_LOGIC; |
|
150 | SIGNAL fft_data_valid : STD_LOGIC; | |
151 | SIGNAL fft_ready : STD_LOGIC; |
|
151 | SIGNAL fft_ready : STD_LOGIC; | |
152 | ----------------------------------------------------------------------------- |
|
152 | ----------------------------------------------------------------------------- | |
153 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
153 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
154 | ----------------------------------------------------------------------------- |
|
154 | ----------------------------------------------------------------------------- | |
155 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); |
|
155 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); | |
156 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; |
|
156 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; | |
157 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
157 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
158 | SIGNAL current_fifo_empty : STD_LOGIC; |
|
158 | SIGNAL current_fifo_empty : STD_LOGIC; | |
159 | SIGNAL current_fifo_locked : STD_LOGIC; |
|
159 | SIGNAL current_fifo_locked : STD_LOGIC; | |
160 | SIGNAL current_fifo_full : STD_LOGIC; |
|
160 | SIGNAL current_fifo_full : STD_LOGIC; | |
161 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
161 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
162 |
|
162 | |||
163 | ----------------------------------------------------------------------------- |
|
163 | ----------------------------------------------------------------------------- | |
164 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
164 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
165 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
165 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
166 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
166 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
167 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
167 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
168 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
168 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
169 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
169 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
170 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
170 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
171 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
171 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
172 | ----------------------------------------------------------------------------- |
|
172 | ----------------------------------------------------------------------------- | |
173 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
173 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
174 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
174 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
175 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
175 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
176 |
|
176 | |||
177 | SIGNAL SM_correlation_start : STD_LOGIC; |
|
177 | SIGNAL SM_correlation_start : STD_LOGIC; | |
178 | SIGNAL SM_correlation_auto : STD_LOGIC; |
|
178 | SIGNAL SM_correlation_auto : STD_LOGIC; | |
179 | SIGNAL SM_correlation_done : STD_LOGIC; |
|
179 | SIGNAL SM_correlation_done : STD_LOGIC; | |
180 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; |
|
180 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; | |
181 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; |
|
181 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; | |
182 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; |
|
182 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; | |
183 | SIGNAL SM_correlation_begin : STD_LOGIC; |
|
183 | SIGNAL SM_correlation_begin : STD_LOGIC; | |
184 |
|
184 | |||
185 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; |
|
185 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; | |
186 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
187 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; |
|
187 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; | |
188 |
|
188 | |||
189 | SIGNAL current_matrix_write : STD_LOGIC; |
|
189 | SIGNAL current_matrix_write : STD_LOGIC; | |
190 | SIGNAL current_matrix_wait_empty : STD_LOGIC; |
|
190 | SIGNAL current_matrix_wait_empty : STD_LOGIC; | |
191 | ----------------------------------------------------------------------------- |
|
191 | ----------------------------------------------------------------------------- | |
192 | SIGNAL fifo_0_ready : STD_LOGIC; |
|
192 | SIGNAL fifo_0_ready : STD_LOGIC; | |
193 | SIGNAL fifo_1_ready : STD_LOGIC; |
|
193 | SIGNAL fifo_1_ready : STD_LOGIC; | |
194 | SIGNAL fifo_ongoing : STD_LOGIC; |
|
194 | SIGNAL fifo_ongoing : STD_LOGIC; | |
195 |
|
195 | |||
196 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; |
|
196 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; | |
197 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; |
|
197 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; | |
198 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
199 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
199 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
200 | ----------------------------------------------------------------------------- |
|
200 | ----------------------------------------------------------------------------- | |
201 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
201 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
202 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
202 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
203 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
203 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
204 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
204 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
205 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
205 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
206 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
206 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
207 |
|
207 | |||
208 | ----------------------------------------------------------------------------- |
|
208 | ----------------------------------------------------------------------------- | |
209 | -- TIME REG & INFOs |
|
209 | -- TIME REG & INFOs | |
210 | ----------------------------------------------------------------------------- |
|
210 | ----------------------------------------------------------------------------- | |
211 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
211 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
212 |
|
212 | |||
213 | SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
213 | SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
214 | SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
214 | SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
215 | SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
215 | SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
216 | SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
216 | SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
217 |
|
217 | |||
218 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
218 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
219 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
219 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
220 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
220 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
221 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
221 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
222 |
|
222 | |||
223 | --SIGNAL time_update_f0_A : STD_LOGIC; |
|
223 | --SIGNAL time_update_f0_A : STD_LOGIC; | |
224 | --SIGNAL time_update_f0_B : STD_LOGIC; |
|
224 | --SIGNAL time_update_f0_B : STD_LOGIC; | |
225 | --SIGNAL time_update_f1 : STD_LOGIC; |
|
225 | --SIGNAL time_update_f1 : STD_LOGIC; | |
226 | --SIGNAL time_update_f2 : STD_LOGIC; |
|
226 | --SIGNAL time_update_f2 : STD_LOGIC; | |
227 | -- |
|
227 | -- | |
228 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
228 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
229 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
229 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
230 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
230 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
231 |
|
231 | |||
232 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
232 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
233 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
233 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
234 | SIGNAL status_component_fifo_0_end : STD_LOGIC; |
|
234 | SIGNAL status_component_fifo_0_end : STD_LOGIC; | |
235 | SIGNAL status_component_fifo_1_end : STD_LOGIC; |
|
235 | SIGNAL status_component_fifo_1_end : STD_LOGIC; | |
236 | ----------------------------------------------------------------------------- |
|
236 | ----------------------------------------------------------------------------- | |
237 | SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); |
|
237 | SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); | |
238 |
|
238 | |||
239 | SIGNAL fft_ready_reg : STD_LOGIC; |
|
239 | SIGNAL fft_ready_reg : STD_LOGIC; | |
240 | SIGNAL fft_ready_rising_down : STD_LOGIC; |
|
240 | SIGNAL fft_ready_rising_down : STD_LOGIC; | |
241 |
|
241 | |||
242 | SIGNAL sample_load_reg : STD_LOGIC; |
|
242 | SIGNAL sample_load_reg : STD_LOGIC; | |
243 | SIGNAL sample_load_rising_down : STD_LOGIC; |
|
243 | SIGNAL sample_load_rising_down : STD_LOGIC; | |
|
244 | ||||
|
245 | ----------------------------------------------------------------------------- | |||
|
246 | SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
247 | SIGNAL sample_f1_wen_head_in : STD_LOGIC; | |||
|
248 | SIGNAL sample_f1_wen_head_out : STD_LOGIC; | |||
|
249 | SIGNAL sample_f1_full_head_in : STD_LOGIC; | |||
|
250 | SIGNAL sample_f1_full_head_out : STD_LOGIC; | |||
|
251 | SIGNAL sample_f1_empty_head_in : STD_LOGIC; | |||
|
252 | ||||
|
253 | SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
244 |
|
254 | |||
245 | BEGIN |
|
255 | BEGIN | |
246 |
|
256 | |||
247 |
|
257 | |||
248 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; |
|
258 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; | |
249 |
|
259 | |||
250 |
|
260 | |||
251 | switch_f0_inst : spectral_matrix_switch_f0 |
|
261 | switch_f0_inst : spectral_matrix_switch_f0 | |
252 | PORT MAP ( |
|
262 | PORT MAP ( | |
253 | clk => clk, |
|
263 | clk => clk, | |
254 | rstn => rstn, |
|
264 | rstn => rstn, | |
255 |
|
265 | |||
256 | sample_wen => sample_f0_wen, |
|
266 | sample_wen => sample_f0_wen, | |
257 |
|
267 | |||
258 | fifo_A_empty => sample_f0_A_empty, |
|
268 | fifo_A_empty => sample_f0_A_empty, | |
259 | fifo_A_full => sample_f0_A_full, |
|
269 | fifo_A_full => sample_f0_A_full, | |
260 | fifo_A_wen => sample_f0_A_wen, |
|
270 | fifo_A_wen => sample_f0_A_wen, | |
261 |
|
271 | |||
262 | fifo_B_empty => sample_f0_B_empty, |
|
272 | fifo_B_empty => sample_f0_B_empty, | |
263 | fifo_B_full => sample_f0_B_full, |
|
273 | fifo_B_full => sample_f0_B_full, | |
264 | fifo_B_wen => sample_f0_B_wen, |
|
274 | fifo_B_wen => sample_f0_B_wen, | |
265 |
|
275 | |||
266 | error_wen => error_wen_f0); -- TODO |
|
276 | error_wen => error_wen_f0); -- TODO | |
267 |
|
277 | |||
268 | ----------------------------------------------------------------------------- |
|
278 | ----------------------------------------------------------------------------- | |
269 | -- FIFO IN |
|
279 | -- FIFO IN | |
270 | ----------------------------------------------------------------------------- |
|
280 | ----------------------------------------------------------------------------- | |
271 | lppFIFOxN_f0_a : lppFIFOxN |
|
281 | lppFIFOxN_f0_a : lppFIFOxN | |
272 | GENERIC MAP ( |
|
282 | GENERIC MAP ( | |
273 | tech => 0, |
|
283 | tech => 0, | |
274 | Mem_use => Mem_use, |
|
284 | Mem_use => Mem_use, | |
275 | Data_sz => 16, |
|
285 | Data_sz => 16, | |
276 | Addr_sz => 8, |
|
286 | Addr_sz => 8, | |
277 | FifoCnt => 5) |
|
287 | FifoCnt => 5) | |
278 | PORT MAP ( |
|
288 | PORT MAP ( | |
279 | clk => clk, |
|
289 | clk => clk, | |
280 | rstn => rstn, |
|
290 | rstn => rstn, | |
281 |
|
291 | |||
282 | ReUse => (OTHERS => '0'), |
|
292 | ReUse => (OTHERS => '0'), | |
283 |
|
293 | |||
284 | wen => sample_f0_A_wen, |
|
294 | wen => sample_f0_A_wen, | |
285 | wdata => sample_f0_wdata, |
|
295 | wdata => sample_f0_wdata, | |
286 |
|
296 | |||
287 | ren => sample_f0_A_ren, |
|
297 | ren => sample_f0_A_ren, | |
288 | rdata => sample_f0_A_rdata, |
|
298 | rdata => sample_f0_A_rdata, | |
289 |
|
299 | |||
290 | empty => sample_f0_A_empty, |
|
300 | empty => sample_f0_A_empty, | |
291 | full => sample_f0_A_full, |
|
301 | full => sample_f0_A_full, | |
292 | almost_full => OPEN); |
|
302 | almost_full => OPEN); | |
293 |
|
303 | |||
294 | lppFIFOxN_f0_b : lppFIFOxN |
|
304 | lppFIFOxN_f0_b : lppFIFOxN | |
295 | GENERIC MAP ( |
|
305 | GENERIC MAP ( | |
296 | tech => 0, |
|
306 | tech => 0, | |
297 | Mem_use => Mem_use, |
|
307 | Mem_use => Mem_use, | |
298 | Data_sz => 16, |
|
308 | Data_sz => 16, | |
299 | Addr_sz => 8, |
|
309 | Addr_sz => 8, | |
300 | FifoCnt => 5) |
|
310 | FifoCnt => 5) | |
301 | PORT MAP ( |
|
311 | PORT MAP ( | |
302 | clk => clk, |
|
312 | clk => clk, | |
303 | rstn => rstn, |
|
313 | rstn => rstn, | |
304 |
|
314 | |||
305 | ReUse => (OTHERS => '0'), |
|
315 | ReUse => (OTHERS => '0'), | |
306 |
|
316 | |||
307 | wen => sample_f0_B_wen, |
|
317 | wen => sample_f0_B_wen, | |
308 | wdata => sample_f0_wdata, |
|
318 | wdata => sample_f0_wdata, | |
309 | ren => sample_f0_B_ren, |
|
319 | ren => sample_f0_B_ren, | |
310 | rdata => sample_f0_B_rdata, |
|
320 | rdata => sample_f0_B_rdata, | |
311 | empty => sample_f0_B_empty, |
|
321 | empty => sample_f0_B_empty, | |
312 | full => sample_f0_B_full, |
|
322 | full => sample_f0_B_full, | |
313 | almost_full => OPEN); |
|
323 | almost_full => OPEN); | |
314 |
|
324 | |||
315 | ----------------------------------------------------------------------------- |
|
325 | ----------------------------------------------------------------------------- | |
316 | -- sample_f1_wen in |
|
326 | -- sample_f1_wen in | |
317 | -- sample_f1_wdata in |
|
327 | -- sample_f1_wdata in | |
318 | -- sample_f1_full OUT |
|
328 | -- sample_f1_full OUT | |
319 |
|
329 | |||
|
330 | sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; | |||
|
331 | sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; | |||
|
332 | sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; | |||
|
333 | ||||
|
334 | lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head | |||
|
335 | PORT MAP ( | |||
|
336 | clk => clk, | |||
|
337 | rstn => rstn, | |||
|
338 | in_wen => sample_f1_wen_head_in, | |||
|
339 | in_data => sample_f1_wdata, | |||
|
340 | in_full => sample_f1_full_head_in, | |||
|
341 | in_empty => sample_f1_empty_head_in, | |||
|
342 | out_wen => sample_f1_wen_head_out, | |||
|
343 | out_data => sample_f1_wdata_head, | |||
|
344 | out_full => sample_f1_full_head_out); | |||
320 |
|
345 | |||
|
346 | sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; | |||
321 |
|
347 | |||
322 |
|
348 | |||
323 | lppFIFOxN_f1 : lppFIFOxN |
|
349 | lppFIFOxN_f1 : lppFIFOxN | |
324 | GENERIC MAP ( |
|
350 | GENERIC MAP ( | |
325 | tech => 0, |
|
351 | tech => 0, | |
326 | Mem_use => Mem_use, |
|
352 | Mem_use => Mem_use, | |
327 | Data_sz => 16, |
|
353 | Data_sz => 16, | |
328 | Addr_sz => 8, |
|
354 | Addr_sz => 8, | |
329 | FifoCnt => 5) |
|
355 | FifoCnt => 5) | |
330 | PORT MAP ( |
|
356 | PORT MAP ( | |
331 | clk => clk, |
|
357 | clk => clk, | |
332 | rstn => rstn, |
|
358 | rstn => rstn, | |
333 |
|
359 | |||
334 | ReUse => (OTHERS => '0'), |
|
360 | ReUse => (OTHERS => '0'), | |
335 |
|
361 | |||
336 | wen => sample_f1_wen, |
|
362 | wen => sample_f1_wen_head, | |
337 | wdata => sample_f1_wdata, |
|
363 | wdata => sample_f1_wdata_head, | |
338 | ren => sample_f1_ren, |
|
364 | ren => sample_f1_ren, | |
339 | rdata => sample_f1_rdata, |
|
365 | rdata => sample_f1_rdata, | |
340 | empty => sample_f1_empty, |
|
366 | empty => sample_f1_empty, | |
341 | full => sample_f1_full, |
|
367 | full => sample_f1_full, | |
342 | almost_full => sample_f1_almost_full); |
|
368 | almost_full => sample_f1_almost_full); | |
343 |
|
369 | |||
344 |
|
370 | |||
345 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; |
|
371 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; | |
346 |
|
372 | |||
347 | PROCESS (clk, rstn) |
|
373 | PROCESS (clk, rstn) | |
348 | BEGIN -- PROCESS |
|
374 | BEGIN -- PROCESS | |
349 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
375 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
350 | one_sample_f1_full <= '0'; |
|
376 | one_sample_f1_full <= '0'; | |
351 | error_wen_f1 <= '0'; |
|
377 | error_wen_f1 <= '0'; | |
352 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
378 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
353 |
IF sample_f1_full = |
|
379 | IF sample_f1_full_head_out = '0' THEN | |
354 | one_sample_f1_full <= '0'; |
|
380 | one_sample_f1_full <= '0'; | |
355 | ELSE |
|
381 | ELSE | |
356 | one_sample_f1_full <= '1'; |
|
382 | one_sample_f1_full <= '1'; | |
357 | END IF; |
|
383 | END IF; | |
358 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; |
|
384 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; | |
359 | END IF; |
|
385 | END IF; | |
360 | END PROCESS; |
|
386 | END PROCESS; | |
361 |
|
387 | |||
362 | ----------------------------------------------------------------------------- |
|
388 | ----------------------------------------------------------------------------- | |
363 |
|
389 | |||
364 |
|
390 | |||
365 | lppFIFOxN_f2 : lppFIFOxN |
|
391 | lppFIFOxN_f2 : lppFIFOxN | |
366 | GENERIC MAP ( |
|
392 | GENERIC MAP ( | |
367 | tech => 0, |
|
393 | tech => 0, | |
368 | Mem_use => Mem_use, |
|
394 | Mem_use => Mem_use, | |
369 | Data_sz => 16, |
|
395 | Data_sz => 16, | |
370 | Addr_sz => 8, |
|
396 | Addr_sz => 8, | |
371 | FifoCnt => 5) |
|
397 | FifoCnt => 5) | |
372 | PORT MAP ( |
|
398 | PORT MAP ( | |
373 | clk => clk, |
|
399 | clk => clk, | |
374 | rstn => rstn, |
|
400 | rstn => rstn, | |
375 |
|
401 | |||
376 | ReUse => (OTHERS => '0'), |
|
402 | ReUse => (OTHERS => '0'), | |
377 |
|
403 | |||
378 | wen => sample_f2_wen, |
|
404 | wen => sample_f2_wen, | |
379 | wdata => sample_f2_wdata, |
|
405 | wdata => sample_f2_wdata, | |
380 | ren => sample_f2_ren, |
|
406 | ren => sample_f2_ren, | |
381 | rdata => sample_f2_rdata, |
|
407 | rdata => sample_f2_rdata, | |
382 | empty => sample_f2_empty, |
|
408 | empty => sample_f2_empty, | |
383 | full => sample_f2_full, |
|
409 | full => sample_f2_full, | |
384 | almost_full => OPEN); |
|
410 | almost_full => OPEN); | |
385 |
|
411 | |||
386 |
|
412 | |||
387 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; |
|
413 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; | |
388 |
|
414 | |||
389 | PROCESS (clk, rstn) |
|
415 | PROCESS (clk, rstn) | |
390 | BEGIN -- PROCESS |
|
416 | BEGIN -- PROCESS | |
391 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
417 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
392 | one_sample_f2_full <= '0'; |
|
418 | one_sample_f2_full <= '0'; | |
393 | error_wen_f2 <= '0'; |
|
419 | error_wen_f2 <= '0'; | |
394 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
420 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
395 | IF sample_f2_full = "00000" THEN |
|
421 | IF sample_f2_full = "00000" THEN | |
396 | one_sample_f2_full <= '0'; |
|
422 | one_sample_f2_full <= '0'; | |
397 | ELSE |
|
423 | ELSE | |
398 | one_sample_f2_full <= '1'; |
|
424 | one_sample_f2_full <= '1'; | |
399 | END IF; |
|
425 | END IF; | |
400 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; |
|
426 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; | |
401 | END IF; |
|
427 | END IF; | |
402 | END PROCESS; |
|
428 | END PROCESS; | |
403 |
|
429 | |||
404 | ----------------------------------------------------------------------------- |
|
430 | ----------------------------------------------------------------------------- | |
405 | -- FSM SELECT CHANNEL |
|
431 | -- FSM SELECT CHANNEL | |
406 | ----------------------------------------------------------------------------- |
|
432 | ----------------------------------------------------------------------------- | |
407 | PROCESS (clk, rstn) |
|
433 | PROCESS (clk, rstn) | |
408 | BEGIN |
|
434 | BEGIN | |
409 | IF rstn = '0' THEN |
|
435 | IF rstn = '0' THEN | |
410 | state_fsm_select_channel <= IDLE; |
|
436 | state_fsm_select_channel <= IDLE; | |
411 | ELSIF clk'EVENT AND clk = '1' THEN |
|
437 | ELSIF clk'EVENT AND clk = '1' THEN | |
412 | CASE state_fsm_select_channel IS |
|
438 | CASE state_fsm_select_channel IS | |
413 | WHEN IDLE => |
|
439 | WHEN IDLE => | |
414 | IF sample_f1_full = "11111" THEN |
|
440 | IF sample_f1_full = "11111" THEN | |
415 | state_fsm_select_channel <= SWITCH_F1; |
|
441 | state_fsm_select_channel <= SWITCH_F1; | |
416 | ELSIF sample_f1_almost_full = "00000" THEN |
|
442 | ELSIF sample_f1_almost_full = "00000" THEN | |
417 | IF sample_f0_A_full = "11111" THEN |
|
443 | IF sample_f0_A_full = "11111" THEN | |
418 | state_fsm_select_channel <= SWITCH_F0_A; |
|
444 | state_fsm_select_channel <= SWITCH_F0_A; | |
419 | ELSIF sample_f0_B_full = "11111" THEN |
|
445 | ELSIF sample_f0_B_full = "11111" THEN | |
420 | state_fsm_select_channel <= SWITCH_F0_B; |
|
446 | state_fsm_select_channel <= SWITCH_F0_B; | |
421 | ELSIF sample_f2_full = "11111" THEN |
|
447 | ELSIF sample_f2_full = "11111" THEN | |
422 | state_fsm_select_channel <= SWITCH_F2; |
|
448 | state_fsm_select_channel <= SWITCH_F2; | |
423 | END IF; |
|
449 | END IF; | |
424 | END IF; |
|
450 | END IF; | |
425 |
|
451 | |||
426 | WHEN SWITCH_F0_A => |
|
452 | WHEN SWITCH_F0_A => | |
427 | IF sample_f0_A_empty = "11111" THEN |
|
453 | IF sample_f0_A_empty = "11111" THEN | |
428 | state_fsm_select_channel <= IDLE; |
|
454 | state_fsm_select_channel <= IDLE; | |
429 | END IF; |
|
455 | END IF; | |
430 | WHEN SWITCH_F0_B => |
|
456 | WHEN SWITCH_F0_B => | |
431 | IF sample_f0_B_empty = "11111" THEN |
|
457 | IF sample_f0_B_empty = "11111" THEN | |
432 | state_fsm_select_channel <= IDLE; |
|
458 | state_fsm_select_channel <= IDLE; | |
433 | END IF; |
|
459 | END IF; | |
434 | WHEN SWITCH_F1 => |
|
460 | WHEN SWITCH_F1 => | |
435 | IF sample_f1_empty = "11111" THEN |
|
461 | IF sample_f1_empty = "11111" THEN | |
436 | state_fsm_select_channel <= IDLE; |
|
462 | state_fsm_select_channel <= IDLE; | |
437 | END IF; |
|
463 | END IF; | |
438 | WHEN SWITCH_F2 => |
|
464 | WHEN SWITCH_F2 => | |
439 | IF sample_f2_empty = "11111" THEN |
|
465 | IF sample_f2_empty = "11111" THEN | |
440 | state_fsm_select_channel <= IDLE; |
|
466 | state_fsm_select_channel <= IDLE; | |
441 | END IF; |
|
467 | END IF; | |
442 | WHEN OTHERS => NULL; |
|
468 | WHEN OTHERS => NULL; | |
443 | END CASE; |
|
469 | END CASE; | |
444 |
|
470 | |||
445 | END IF; |
|
471 | END IF; | |
446 | END PROCESS; |
|
472 | END PROCESS; | |
447 |
|
473 | |||
448 | PROCESS (clk, rstn) |
|
474 | PROCESS (clk, rstn) | |
449 | BEGIN |
|
475 | BEGIN | |
450 | IF rstn = '0' THEN |
|
476 | IF rstn = '0' THEN | |
451 | pre_state_fsm_select_channel <= IDLE; |
|
477 | pre_state_fsm_select_channel <= IDLE; | |
452 | ELSIF clk'EVENT AND clk = '1' THEN |
|
478 | ELSIF clk'EVENT AND clk = '1' THEN | |
453 | pre_state_fsm_select_channel <= state_fsm_select_channel; |
|
479 | pre_state_fsm_select_channel <= state_fsm_select_channel; | |
454 | END IF; |
|
480 | END IF; | |
455 | END PROCESS; |
|
481 | END PROCESS; | |
456 |
|
482 | |||
457 |
|
483 | |||
458 | ----------------------------------------------------------------------------- |
|
484 | ----------------------------------------------------------------------------- | |
459 | -- SWITCH SELECT CHANNEL |
|
485 | -- SWITCH SELECT CHANNEL | |
460 | ----------------------------------------------------------------------------- |
|
486 | ----------------------------------------------------------------------------- | |
461 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
487 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
462 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
488 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
463 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
489 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
464 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
490 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
465 | (OTHERS => '1'); |
|
491 | (OTHERS => '1'); | |
466 |
|
492 | |||
467 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
493 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
468 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
494 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
469 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
495 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
470 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
496 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
471 | (OTHERS => '0'); |
|
497 | (OTHERS => '0'); | |
472 |
|
498 | |||
473 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE |
|
499 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE | |
474 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE |
|
500 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE | |
475 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE |
|
501 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE | |
476 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
502 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
477 |
|
503 | |||
478 |
|
504 | |||
479 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); |
|
505 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); | |
480 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); |
|
506 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); | |
481 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); |
|
507 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); | |
482 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); |
|
508 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); | |
483 |
|
509 | |||
484 |
|
510 | |||
485 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
511 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
486 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
512 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
487 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
513 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
488 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 |
|
514 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 | |
489 |
|
515 | |||
490 | ----------------------------------------------------------------------------- |
|
516 | ----------------------------------------------------------------------------- | |
491 | -- FSM LOAD FFT |
|
517 | -- FSM LOAD FFT | |
492 | ----------------------------------------------------------------------------- |
|
518 | ----------------------------------------------------------------------------- | |
493 |
|
519 | |||
494 | sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE |
|
520 | sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE | |
495 | sample_ren_s WHEN sample_load = '1' ELSE |
|
521 | sample_ren_s WHEN sample_load = '1' ELSE | |
496 | (OTHERS => '1'); |
|
522 | (OTHERS => '1'); | |
497 |
|
523 | |||
498 | PROCESS (clk, rstn) |
|
524 | PROCESS (clk, rstn) | |
499 | BEGIN |
|
525 | BEGIN | |
500 | IF rstn = '0' THEN |
|
526 | IF rstn = '0' THEN | |
501 | sample_ren_s <= (OTHERS => '1'); |
|
527 | sample_ren_s <= (OTHERS => '1'); | |
502 | state_fsm_load_FFT <= IDLE; |
|
528 | state_fsm_load_FFT <= IDLE; | |
503 | status_MS_input <= (OTHERS => '0'); |
|
529 | status_MS_input <= (OTHERS => '0'); | |
504 | --next_state_fsm_load_FFT <= IDLE; |
|
530 | --next_state_fsm_load_FFT <= IDLE; | |
505 | --sample_valid <= '0'; |
|
531 | --sample_valid <= '0'; | |
506 | ELSIF clk'EVENT AND clk = '1' THEN |
|
532 | ELSIF clk'EVENT AND clk = '1' THEN | |
507 | CASE state_fsm_load_FFT IS |
|
533 | CASE state_fsm_load_FFT IS | |
508 | WHEN IDLE => |
|
534 | WHEN IDLE => | |
509 | --sample_valid <= '0'; |
|
535 | --sample_valid <= '0'; | |
510 | sample_ren_s <= (OTHERS => '1'); |
|
536 | sample_ren_s <= (OTHERS => '1'); | |
511 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
537 | IF sample_full = "11111" AND sample_load = '1' THEN | |
512 | state_fsm_load_FFT <= FIFO_1; |
|
538 | state_fsm_load_FFT <= FIFO_1; | |
513 | status_MS_input <= status_channel; |
|
539 | status_MS_input <= status_channel; | |
514 | END IF; |
|
540 | END IF; | |
515 |
|
541 | |||
516 | WHEN FIFO_1 => |
|
542 | WHEN FIFO_1 => | |
517 | sample_ren_s <= "1111" & NOT(sample_load); |
|
543 | sample_ren_s <= "1111" & NOT(sample_load); | |
518 | IF sample_empty(0) = '1' THEN |
|
544 | IF sample_empty(0) = '1' THEN | |
519 | sample_ren_s <= (OTHERS => '1'); |
|
545 | sample_ren_s <= (OTHERS => '1'); | |
520 | state_fsm_load_FFT <= FIFO_2; |
|
546 | state_fsm_load_FFT <= FIFO_2; | |
521 | END IF; |
|
547 | END IF; | |
522 |
|
548 | |||
523 | WHEN FIFO_2 => |
|
549 | WHEN FIFO_2 => | |
524 | sample_ren_s <= "111" & NOT(sample_load) & '1'; |
|
550 | sample_ren_s <= "111" & NOT(sample_load) & '1'; | |
525 | IF sample_empty(1) = '1' THEN |
|
551 | IF sample_empty(1) = '1' THEN | |
526 | sample_ren_s <= (OTHERS => '1'); |
|
552 | sample_ren_s <= (OTHERS => '1'); | |
527 | state_fsm_load_FFT <= FIFO_3; |
|
553 | state_fsm_load_FFT <= FIFO_3; | |
528 | END IF; |
|
554 | END IF; | |
529 |
|
555 | |||
530 | WHEN FIFO_3 => |
|
556 | WHEN FIFO_3 => | |
531 | sample_ren_s <= "11" & NOT(sample_load) & "11"; |
|
557 | sample_ren_s <= "11" & NOT(sample_load) & "11"; | |
532 | IF sample_empty(2) = '1' THEN |
|
558 | IF sample_empty(2) = '1' THEN | |
533 | sample_ren_s <= (OTHERS => '1'); |
|
559 | sample_ren_s <= (OTHERS => '1'); | |
534 | state_fsm_load_FFT <= FIFO_4; |
|
560 | state_fsm_load_FFT <= FIFO_4; | |
535 | END IF; |
|
561 | END IF; | |
536 |
|
562 | |||
537 | WHEN FIFO_4 => |
|
563 | WHEN FIFO_4 => | |
538 | sample_ren_s <= '1' & NOT(sample_load) & "111"; |
|
564 | sample_ren_s <= '1' & NOT(sample_load) & "111"; | |
539 | IF sample_empty(3) = '1' THEN |
|
565 | IF sample_empty(3) = '1' THEN | |
540 | sample_ren_s <= (OTHERS => '1'); |
|
566 | sample_ren_s <= (OTHERS => '1'); | |
541 | state_fsm_load_FFT <= FIFO_5; |
|
567 | state_fsm_load_FFT <= FIFO_5; | |
542 | END IF; |
|
568 | END IF; | |
543 |
|
569 | |||
544 | WHEN FIFO_5 => |
|
570 | WHEN FIFO_5 => | |
545 | sample_ren_s <= NOT(sample_load) & "1111"; |
|
571 | sample_ren_s <= NOT(sample_load) & "1111"; | |
546 | IF sample_empty(4) = '1' THEN |
|
572 | IF sample_empty(4) = '1' THEN | |
547 | sample_ren_s <= (OTHERS => '1'); |
|
573 | sample_ren_s <= (OTHERS => '1'); | |
548 | state_fsm_load_FFT <= IDLE; |
|
574 | state_fsm_load_FFT <= IDLE; | |
549 | END IF; |
|
575 | END IF; | |
550 | WHEN OTHERS => NULL; |
|
576 | WHEN OTHERS => NULL; | |
551 | END CASE; |
|
577 | END CASE; | |
552 | END IF; |
|
578 | END IF; | |
553 | END PROCESS; |
|
579 | END PROCESS; | |
554 |
|
580 | |||
555 | PROCESS (clk, rstn) |
|
581 | PROCESS (clk, rstn) | |
556 | BEGIN |
|
582 | BEGIN | |
557 | IF rstn = '0' THEN |
|
583 | IF rstn = '0' THEN | |
558 | sample_valid_r <= '0'; |
|
584 | sample_valid_r <= '0'; | |
559 | next_state_fsm_load_FFT <= IDLE; |
|
585 | next_state_fsm_load_FFT <= IDLE; | |
560 | ELSIF clk'EVENT AND clk = '1' THEN |
|
586 | ELSIF clk'EVENT AND clk = '1' THEN | |
561 | next_state_fsm_load_FFT <= state_fsm_load_FFT; |
|
587 | next_state_fsm_load_FFT <= state_fsm_load_FFT; | |
562 | IF sample_ren_s = "11111" THEN |
|
588 | IF sample_ren_s = "11111" THEN | |
563 | sample_valid_r <= '0'; |
|
589 | sample_valid_r <= '0'; | |
564 | ELSE |
|
590 | ELSE | |
565 | sample_valid_r <= '1'; |
|
591 | sample_valid_r <= '1'; | |
566 | END IF; |
|
592 | END IF; | |
567 | END IF; |
|
593 | END IF; | |
568 | END PROCESS; |
|
594 | END PROCESS; | |
569 |
|
595 | |||
570 | sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; |
|
596 | sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; | |
571 |
|
597 | |||
572 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE |
|
598 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE | |
573 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE |
|
599 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE | |
574 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE |
|
600 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE | |
575 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE |
|
601 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE | |
576 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
602 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE | |
577 |
|
603 | |||
578 | ----------------------------------------------------------------------------- |
|
604 | ----------------------------------------------------------------------------- | |
579 | -- FFT |
|
605 | -- FFT | |
580 | ----------------------------------------------------------------------------- |
|
606 | ----------------------------------------------------------------------------- | |
581 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT |
|
607 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT | |
582 | PORT MAP ( |
|
608 | PORT MAP ( | |
583 | clk => clk, |
|
609 | clk => clk, | |
584 | rstn => rstn, |
|
610 | rstn => rstn, | |
585 | sample_valid => sample_valid, |
|
611 | sample_valid => sample_valid, | |
586 | fft_read => fft_read, |
|
612 | fft_read => fft_read, | |
587 | sample_data => sample_data, |
|
613 | sample_data => sample_data, | |
588 | sample_load => sample_load, |
|
614 | sample_load => sample_load, | |
589 | fft_pong => fft_pong, |
|
615 | fft_pong => fft_pong, | |
590 | fft_data_im => fft_data_im, |
|
616 | fft_data_im => fft_data_im, | |
591 | fft_data_re => fft_data_re, |
|
617 | fft_data_re => fft_data_re, | |
592 | fft_data_valid => fft_data_valid, |
|
618 | fft_data_valid => fft_data_valid, | |
593 | fft_ready => fft_ready); |
|
619 | fft_ready => fft_ready); | |
594 |
|
620 | |||
595 | observation_vector_0(11 DOWNTO 0) <= "000" & --11 10 |
|
621 | observation_vector_0(11 DOWNTO 0) <= "000" & --11 10 | |
596 | fft_ongoing_counter & --9 8 |
|
622 | fft_ongoing_counter & --9 8 | |
597 | sample_load_rising_down & --7 |
|
623 | sample_load_rising_down & --7 | |
598 | fft_ready_rising_down & --6 |
|
624 | fft_ready_rising_down & --6 | |
599 | fft_ready & --5 |
|
625 | fft_ready & --5 | |
600 | fft_data_valid & --4 |
|
626 | fft_data_valid & --4 | |
601 | fft_pong & --3 |
|
627 | fft_pong & --3 | |
602 | sample_load & --2 |
|
628 | sample_load & --2 | |
603 | fft_read & --1 |
|
629 | fft_read & --1 | |
604 | sample_valid; --0 |
|
630 | sample_valid; --0 | |
605 |
|
631 | |||
606 | ----------------------------------------------------------------------------- |
|
632 | ----------------------------------------------------------------------------- | |
607 | fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; |
|
633 | fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; | |
608 | sample_load_rising_down <= sample_load_reg AND NOT sample_load; |
|
634 | sample_load_rising_down <= sample_load_reg AND NOT sample_load; | |
609 |
|
635 | |||
610 | PROCESS (clk, rstn) |
|
636 | PROCESS (clk, rstn) | |
611 | BEGIN |
|
637 | BEGIN | |
612 | IF rstn = '0' THEN |
|
638 | IF rstn = '0' THEN | |
613 | fft_ready_reg <= '0'; |
|
639 | fft_ready_reg <= '0'; | |
614 | sample_load_reg <= '0'; |
|
640 | sample_load_reg <= '0'; | |
615 |
|
641 | |||
616 | fft_ongoing_counter <= '0'; |
|
642 | fft_ongoing_counter <= '0'; | |
617 | ELSIF clk'event AND clk = '1' THEN |
|
643 | ELSIF clk'event AND clk = '1' THEN | |
618 | fft_ready_reg <= fft_ready; |
|
644 | fft_ready_reg <= fft_ready; | |
619 | sample_load_reg <= sample_load; |
|
645 | sample_load_reg <= sample_load; | |
620 |
|
646 | |||
621 | IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN |
|
647 | IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN | |
622 | fft_ongoing_counter <= '0'; |
|
648 | fft_ongoing_counter <= '0'; | |
623 |
|
649 | |||
624 | -- CASE fft_ongoing_counter IS |
|
650 | -- CASE fft_ongoing_counter IS | |
625 | -- WHEN "01" => fft_ongoing_counter <= "00"; |
|
651 | -- WHEN "01" => fft_ongoing_counter <= "00"; | |
626 | ---- WHEN "10" => fft_ongoing_counter <= "01"; |
|
652 | ---- WHEN "10" => fft_ongoing_counter <= "01"; | |
627 | -- WHEN OTHERS => NULL; |
|
653 | -- WHEN OTHERS => NULL; | |
628 | -- END CASE; |
|
654 | -- END CASE; | |
629 | ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN |
|
655 | ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN | |
630 | fft_ongoing_counter <= '1'; |
|
656 | fft_ongoing_counter <= '1'; | |
631 | -- CASE fft_ongoing_counter IS |
|
657 | -- CASE fft_ongoing_counter IS | |
632 | -- WHEN "00" => fft_ongoing_counter <= "01"; |
|
658 | -- WHEN "00" => fft_ongoing_counter <= "01"; | |
633 | ---- WHEN "01" => fft_ongoing_counter <= "10"; |
|
659 | ---- WHEN "01" => fft_ongoing_counter <= "10"; | |
634 | -- WHEN OTHERS => NULL; |
|
660 | -- WHEN OTHERS => NULL; | |
635 | -- END CASE; |
|
661 | -- END CASE; | |
636 | END IF; |
|
662 | END IF; | |
637 |
|
663 | |||
638 | END IF; |
|
664 | END IF; | |
639 | END PROCESS; |
|
665 | END PROCESS; | |
640 |
|
666 | |||
641 | ----------------------------------------------------------------------------- |
|
667 | ----------------------------------------------------------------------------- | |
642 | PROCESS (clk, rstn) |
|
668 | PROCESS (clk, rstn) | |
643 | BEGIN |
|
669 | BEGIN | |
644 | IF rstn = '0' THEN |
|
670 | IF rstn = '0' THEN | |
645 | state_fsm_load_MS_memory <= IDLE; |
|
671 | state_fsm_load_MS_memory <= IDLE; | |
646 | current_fifo_load <= "00001"; |
|
672 | current_fifo_load <= "00001"; | |
647 | ELSIF clk'EVENT AND clk = '1' THEN |
|
673 | ELSIF clk'EVENT AND clk = '1' THEN | |
648 | CASE state_fsm_load_MS_memory IS |
|
674 | CASE state_fsm_load_MS_memory IS | |
649 | WHEN IDLE => |
|
675 | WHEN IDLE => | |
650 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN |
|
676 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN | |
651 | state_fsm_load_MS_memory <= LOAD_FIFO; |
|
677 | state_fsm_load_MS_memory <= LOAD_FIFO; | |
652 | END IF; |
|
678 | END IF; | |
653 | WHEN LOAD_FIFO => |
|
679 | WHEN LOAD_FIFO => | |
654 | IF current_fifo_full = '1' THEN |
|
680 | IF current_fifo_full = '1' THEN | |
655 | state_fsm_load_MS_memory <= TRASH_FFT; |
|
681 | state_fsm_load_MS_memory <= TRASH_FFT; | |
656 | END IF; |
|
682 | END IF; | |
657 | WHEN TRASH_FFT => |
|
683 | WHEN TRASH_FFT => | |
658 | IF fft_ready = '0' THEN |
|
684 | IF fft_ready = '0' THEN | |
659 | state_fsm_load_MS_memory <= IDLE; |
|
685 | state_fsm_load_MS_memory <= IDLE; | |
660 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); |
|
686 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); | |
661 | END IF; |
|
687 | END IF; | |
662 | WHEN OTHERS => NULL; |
|
688 | WHEN OTHERS => NULL; | |
663 | END CASE; |
|
689 | END CASE; | |
664 |
|
690 | |||
665 | END IF; |
|
691 | END IF; | |
666 | END PROCESS; |
|
692 | END PROCESS; | |
667 |
|
693 | |||
668 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE |
|
694 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE | |
669 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE |
|
695 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE | |
670 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE |
|
696 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE | |
671 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE |
|
697 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE | |
672 | MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
698 | MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
673 |
|
699 | |||
674 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE |
|
700 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE | |
675 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE |
|
701 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE | |
676 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE |
|
702 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE | |
677 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE |
|
703 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE | |
678 | MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
704 | MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
679 |
|
705 | |||
680 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE |
|
706 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE | |
681 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE |
|
707 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE | |
682 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE |
|
708 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE | |
683 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE |
|
709 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE | |
684 | MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
710 | MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
685 |
|
711 | |||
686 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; |
|
712 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; | |
687 |
|
713 | |||
688 | all_fifo : FOR I IN 4 DOWNTO 0 GENERATE |
|
714 | all_fifo : FOR I IN 4 DOWNTO 0 GENERATE | |
689 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' |
|
715 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' | |
690 | AND state_fsm_load_MS_memory = LOAD_FIFO |
|
716 | AND state_fsm_load_MS_memory = LOAD_FIFO | |
691 | AND current_fifo_load(I) = '1' |
|
717 | AND current_fifo_load(I) = '1' | |
692 | ELSE '1'; |
|
718 | ELSE '1'; | |
693 | END GENERATE all_fifo; |
|
719 | END GENERATE all_fifo; | |
694 |
|
720 | |||
695 | PROCESS (clk, rstn) |
|
721 | PROCESS (clk, rstn) | |
696 | BEGIN |
|
722 | BEGIN | |
697 | IF rstn = '0' THEN |
|
723 | IF rstn = '0' THEN | |
698 | MEM_IN_SM_wen <= (OTHERS => '1'); |
|
724 | MEM_IN_SM_wen <= (OTHERS => '1'); | |
699 | ELSIF clk'EVENT AND clk = '1' THEN |
|
725 | ELSIF clk'EVENT AND clk = '1' THEN | |
700 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; |
|
726 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; | |
701 | END IF; |
|
727 | END IF; | |
702 | END PROCESS; |
|
728 | END PROCESS; | |
703 |
|
729 | |||
704 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & |
|
730 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & | |
705 | (fft_data_im & fft_data_re) & |
|
731 | (fft_data_im & fft_data_re) & | |
706 | (fft_data_im & fft_data_re) & |
|
732 | (fft_data_im & fft_data_re) & | |
707 | (fft_data_im & fft_data_re) & |
|
733 | (fft_data_im & fft_data_re) & | |
708 | (fft_data_im & fft_data_re); |
|
734 | (fft_data_im & fft_data_re); | |
709 | ----------------------------------------------------------------------------- |
|
735 | ----------------------------------------------------------------------------- | |
710 |
|
736 | |||
711 |
|
737 | |||
712 | ----------------------------------------------------------------------------- |
|
738 | ----------------------------------------------------------------------------- | |
713 | Mem_In_SpectralMatrix : lppFIFOxN |
|
739 | Mem_In_SpectralMatrix : lppFIFOxN | |
714 | GENERIC MAP ( |
|
740 | GENERIC MAP ( | |
715 | tech => 0, |
|
741 | tech => 0, | |
716 | Mem_use => Mem_use, |
|
742 | Mem_use => Mem_use, | |
717 | Data_sz => 32, --16, |
|
743 | Data_sz => 32, --16, | |
718 | Addr_sz => 7, --8 |
|
744 | Addr_sz => 7, --8 | |
719 | FifoCnt => 5) |
|
745 | FifoCnt => 5) | |
720 | PORT MAP ( |
|
746 | PORT MAP ( | |
721 | clk => clk, |
|
747 | clk => clk, | |
722 | rstn => rstn, |
|
748 | rstn => rstn, | |
723 |
|
749 | |||
724 | ReUse => MEM_IN_SM_ReUse, |
|
750 | ReUse => MEM_IN_SM_ReUse, | |
725 |
|
751 | |||
726 | wen => MEM_IN_SM_wen, |
|
752 | wen => MEM_IN_SM_wen, | |
727 | wdata => MEM_IN_SM_wData, |
|
753 | wdata => MEM_IN_SM_wData, | |
728 |
|
754 | |||
729 | ren => MEM_IN_SM_ren, |
|
755 | ren => MEM_IN_SM_ren, | |
730 | rdata => MEM_IN_SM_rData, |
|
756 | rdata => MEM_IN_SM_rData, | |
731 | full => MEM_IN_SM_Full, |
|
757 | full => MEM_IN_SM_Full, | |
732 | empty => MEM_IN_SM_Empty, |
|
758 | empty => MEM_IN_SM_Empty, | |
733 | almost_full => OPEN); |
|
759 | almost_full => OPEN); | |
734 |
|
760 | |||
735 | ----------------------------------------------------------------------------- |
|
761 | ----------------------------------------------------------------------------- | |
736 |
|
762 | |||
737 | observation_vector_1(11 DOWNTO 0) <= '0' & |
|
763 | observation_vector_1(11 DOWNTO 0) <= '0' & | |
738 | SM_correlation_done & --4 |
|
764 | SM_correlation_done & --4 | |
739 | SM_correlation_auto & --3 |
|
765 | SM_correlation_auto & --3 | |
740 | SM_correlation_start & |
|
766 | SM_correlation_start & | |
741 | SM_correlation_start & --7 |
|
767 | SM_correlation_start & --7 | |
742 | status_MS_input(1 DOWNTO 0)& --6..5 |
|
768 | status_MS_input(1 DOWNTO 0)& --6..5 | |
743 | MEM_IN_SM_locked(4 DOWNTO 0); --4..0 |
|
769 | MEM_IN_SM_locked(4 DOWNTO 0); --4..0 | |
744 |
|
770 | |||
745 | ----------------------------------------------------------------------------- |
|
771 | ----------------------------------------------------------------------------- | |
746 | MS_control_1 : MS_control |
|
772 | MS_control_1 : MS_control | |
747 | PORT MAP ( |
|
773 | PORT MAP ( | |
748 | clk => clk, |
|
774 | clk => clk, | |
749 | rstn => rstn, |
|
775 | rstn => rstn, | |
750 |
|
776 | |||
751 | current_status_ms => status_MS_input, |
|
777 | current_status_ms => status_MS_input, | |
752 |
|
778 | |||
753 | fifo_in_lock => MEM_IN_SM_locked, |
|
779 | fifo_in_lock => MEM_IN_SM_locked, | |
754 | fifo_in_data => MEM_IN_SM_rdata, |
|
780 | fifo_in_data => MEM_IN_SM_rdata, | |
755 | fifo_in_full => MEM_IN_SM_Full, |
|
781 | fifo_in_full => MEM_IN_SM_Full, | |
756 | fifo_in_empty => MEM_IN_SM_Empty, |
|
782 | fifo_in_empty => MEM_IN_SM_Empty, | |
757 | fifo_in_ren => MEM_IN_SM_ren, |
|
783 | fifo_in_ren => MEM_IN_SM_ren, | |
758 | fifo_in_reuse => MEM_IN_SM_ReUse, |
|
784 | fifo_in_reuse => MEM_IN_SM_ReUse, | |
759 |
|
785 | |||
760 | fifo_out_data => SM_in_data, |
|
786 | fifo_out_data => SM_in_data, | |
761 | fifo_out_ren => SM_in_ren, |
|
787 | fifo_out_ren => SM_in_ren, | |
762 | fifo_out_empty => SM_in_empty, |
|
788 | fifo_out_empty => SM_in_empty, | |
763 |
|
789 | |||
764 | current_status_component => status_component, |
|
790 | current_status_component => status_component, | |
765 |
|
791 | |||
766 | correlation_start => SM_correlation_start, |
|
792 | correlation_start => SM_correlation_start, | |
767 | correlation_auto => SM_correlation_auto, |
|
793 | correlation_auto => SM_correlation_auto, | |
768 | correlation_done => SM_correlation_done); |
|
794 | correlation_done => SM_correlation_done); | |
769 |
|
795 | |||
770 |
|
796 | |||
771 | MS_calculation_1 : MS_calculation |
|
797 | MS_calculation_1 : MS_calculation | |
772 | PORT MAP ( |
|
798 | PORT MAP ( | |
773 | clk => clk, |
|
799 | clk => clk, | |
774 | rstn => rstn, |
|
800 | rstn => rstn, | |
775 |
|
801 | |||
776 | fifo_in_data => SM_in_data, |
|
802 | fifo_in_data => SM_in_data, | |
777 | fifo_in_ren => SM_in_ren, |
|
803 | fifo_in_ren => SM_in_ren, | |
778 | fifo_in_empty => SM_in_empty, |
|
804 | fifo_in_empty => SM_in_empty, | |
779 |
|
805 | |||
780 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO |
|
806 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO | |
781 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO |
|
807 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO | |
782 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO |
|
808 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO | |
783 |
|
809 | |||
784 | correlation_start => SM_correlation_start, |
|
810 | correlation_start => SM_correlation_start, | |
785 | correlation_auto => SM_correlation_auto, |
|
811 | correlation_auto => SM_correlation_auto, | |
786 | correlation_begin => SM_correlation_begin, |
|
812 | correlation_begin => SM_correlation_begin, | |
787 | correlation_done => SM_correlation_done); |
|
813 | correlation_done => SM_correlation_done); | |
788 |
|
814 | |||
789 | ----------------------------------------------------------------------------- |
|
815 | ----------------------------------------------------------------------------- | |
790 | PROCESS (clk, rstn) |
|
816 | PROCESS (clk, rstn) | |
791 | BEGIN -- PROCESS |
|
817 | BEGIN -- PROCESS | |
792 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
818 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
793 | current_matrix_write <= '0'; |
|
819 | current_matrix_write <= '0'; | |
794 | current_matrix_wait_empty <= '1'; |
|
820 | current_matrix_wait_empty <= '1'; | |
795 | status_component_fifo_0 <= (OTHERS => '0'); |
|
821 | status_component_fifo_0 <= (OTHERS => '0'); | |
796 | status_component_fifo_1 <= (OTHERS => '0'); |
|
822 | status_component_fifo_1 <= (OTHERS => '0'); | |
797 | status_component_fifo_0_end <= '0'; |
|
823 | status_component_fifo_0_end <= '0'; | |
798 | status_component_fifo_1_end <= '0'; |
|
824 | status_component_fifo_1_end <= '0'; | |
799 | SM_correlation_done_reg1 <= '0'; |
|
825 | SM_correlation_done_reg1 <= '0'; | |
800 | SM_correlation_done_reg2 <= '0'; |
|
826 | SM_correlation_done_reg2 <= '0'; | |
801 | SM_correlation_done_reg3 <= '0'; |
|
827 | SM_correlation_done_reg3 <= '0'; | |
802 |
|
828 | |||
803 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
829 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
804 | SM_correlation_done_reg1 <= SM_correlation_done; |
|
830 | SM_correlation_done_reg1 <= SM_correlation_done; | |
805 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; |
|
831 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; | |
806 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; |
|
832 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; | |
807 | status_component_fifo_0_end <= '0'; |
|
833 | status_component_fifo_0_end <= '0'; | |
808 | status_component_fifo_1_end <= '0'; |
|
834 | status_component_fifo_1_end <= '0'; | |
809 | IF SM_correlation_begin = '1' THEN |
|
835 | IF SM_correlation_begin = '1' THEN | |
810 | IF current_matrix_write = '0' THEN |
|
836 | IF current_matrix_write = '0' THEN | |
811 | status_component_fifo_0 <= status_component; |
|
837 | status_component_fifo_0 <= status_component; | |
812 | ELSE |
|
838 | ELSE | |
813 | status_component_fifo_1 <= status_component; |
|
839 | status_component_fifo_1 <= status_component; | |
814 | END IF; |
|
840 | END IF; | |
815 | END IF; |
|
841 | END IF; | |
816 |
|
842 | |||
817 | IF SM_correlation_done_reg3 = '1' THEN |
|
843 | IF SM_correlation_done_reg3 = '1' THEN | |
818 | IF current_matrix_write = '0' THEN |
|
844 | IF current_matrix_write = '0' THEN | |
819 | status_component_fifo_0_end <= '1'; |
|
845 | status_component_fifo_0_end <= '1'; | |
820 | ELSE |
|
846 | ELSE | |
821 | status_component_fifo_1_end <= '1'; |
|
847 | status_component_fifo_1_end <= '1'; | |
822 | END IF; |
|
848 | END IF; | |
823 | current_matrix_wait_empty <= '1'; |
|
849 | current_matrix_wait_empty <= '1'; | |
824 | current_matrix_write <= NOT current_matrix_write; |
|
850 | current_matrix_write <= NOT current_matrix_write; | |
825 | END IF; |
|
851 | END IF; | |
826 |
|
852 | |||
827 | IF current_matrix_wait_empty <= '1' THEN |
|
853 | IF current_matrix_wait_empty <= '1' THEN | |
828 | IF current_matrix_write = '0' THEN |
|
854 | IF current_matrix_write = '0' THEN | |
829 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); |
|
855 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); | |
830 | ELSE |
|
856 | ELSE | |
831 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); |
|
857 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); | |
832 | END IF; |
|
858 | END IF; | |
833 | END IF; |
|
859 | END IF; | |
834 |
|
860 | |||
835 | END IF; |
|
861 | END IF; | |
836 | END PROCESS; |
|
862 | END PROCESS; | |
837 |
|
863 | |||
838 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE |
|
864 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE | |
839 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE |
|
865 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE | |
840 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE |
|
866 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE | |
841 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE |
|
867 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE | |
842 | '1' WHEN current_matrix_wait_empty = '1' ELSE |
|
868 | '1' WHEN current_matrix_wait_empty = '1' ELSE | |
843 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE |
|
869 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE | |
844 | MEM_OUT_SM_Full(1); |
|
870 | MEM_OUT_SM_Full(1); | |
845 |
|
871 | |||
846 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; |
|
872 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; | |
847 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; |
|
873 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; | |
848 |
|
874 | |||
849 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; |
|
875 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; | |
850 | ----------------------------------------------------------------------------- |
|
876 | ----------------------------------------------------------------------------- | |
851 |
|
877 | |||
852 | Mem_Out_SpectralMatrix : lppFIFOxN |
|
878 | Mem_Out_SpectralMatrix : lppFIFOxN | |
853 | GENERIC MAP ( |
|
879 | GENERIC MAP ( | |
854 | tech => 0, |
|
880 | tech => 0, | |
855 | Mem_use => Mem_use, |
|
881 | Mem_use => Mem_use, | |
856 | Data_sz => 32, |
|
882 | Data_sz => 32, | |
857 | Addr_sz => 8, |
|
883 | Addr_sz => 8, | |
858 | FifoCnt => 2) |
|
884 | FifoCnt => 2) | |
859 | PORT MAP ( |
|
885 | PORT MAP ( | |
860 | clk => clk, |
|
886 | clk => clk, | |
861 | rstn => rstn, |
|
887 | rstn => rstn, | |
862 |
|
888 | |||
863 | ReUse => (OTHERS => '0'), |
|
889 | ReUse => (OTHERS => '0'), | |
864 |
|
890 | |||
865 | wen => MEM_OUT_SM_Write, |
|
891 | wen => MEM_OUT_SM_Write, | |
866 | wdata => MEM_OUT_SM_Data_in, |
|
892 | wdata => MEM_OUT_SM_Data_in, | |
867 |
|
893 | |||
868 | ren => MEM_OUT_SM_Read, |
|
894 | ren => MEM_OUT_SM_Read, | |
869 | rdata => MEM_OUT_SM_Data_out, |
|
895 | rdata => MEM_OUT_SM_Data_out, | |
870 |
|
896 | |||
871 | full => MEM_OUT_SM_Full, |
|
897 | full => MEM_OUT_SM_Full, | |
872 | empty => MEM_OUT_SM_Empty, |
|
898 | empty => MEM_OUT_SM_Empty, | |
873 | almost_full => OPEN); |
|
899 | almost_full => OPEN); | |
874 |
|
900 | |||
875 | ----------------------------------------------------------------------------- |
|
901 | ----------------------------------------------------------------------------- | |
876 | -- MEM_OUT_SM_Read <= "00"; |
|
902 | -- MEM_OUT_SM_Read <= "00"; | |
877 | PROCESS (clk, rstn) |
|
903 | PROCESS (clk, rstn) | |
878 | BEGIN |
|
904 | BEGIN | |
879 | IF rstn = '0' THEN |
|
905 | IF rstn = '0' THEN | |
880 | fifo_0_ready <= '0'; |
|
906 | fifo_0_ready <= '0'; | |
881 | fifo_1_ready <= '0'; |
|
907 | fifo_1_ready <= '0'; | |
882 | fifo_ongoing <= '0'; |
|
908 | fifo_ongoing <= '0'; | |
883 | ELSIF clk'EVENT AND clk = '1' THEN |
|
909 | ELSIF clk'EVENT AND clk = '1' THEN | |
884 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN |
|
910 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN | |
885 | fifo_ongoing <= '1'; |
|
911 | fifo_ongoing <= '1'; | |
886 | fifo_0_ready <= '0'; |
|
912 | fifo_0_ready <= '0'; | |
887 | ELSIF status_component_fifo_0_end = '1' THEN |
|
913 | ELSIF status_component_fifo_0_end = '1' THEN | |
888 | fifo_0_ready <= '1'; |
|
914 | fifo_0_ready <= '1'; | |
889 | END IF; |
|
915 | END IF; | |
890 |
|
916 | |||
891 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN |
|
917 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN | |
892 | fifo_ongoing <= '0'; |
|
918 | fifo_ongoing <= '0'; | |
893 | fifo_1_ready <= '0'; |
|
919 | fifo_1_ready <= '0'; | |
894 | ELSIF status_component_fifo_1_end = '1' THEN |
|
920 | ELSIF status_component_fifo_1_end = '1' THEN | |
895 | fifo_1_ready <= '1'; |
|
921 | fifo_1_ready <= '1'; | |
896 | END IF; |
|
922 | END IF; | |
897 |
|
923 | |||
898 | END IF; |
|
924 | END IF; | |
899 | END PROCESS; |
|
925 | END PROCESS; | |
900 |
|
926 | |||
901 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE |
|
927 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE | |
902 | '1' WHEN fifo_0_ready = '0' ELSE |
|
928 | '1' WHEN fifo_0_ready = '0' ELSE | |
903 | FSM_DMA_fifo_ren; |
|
929 | FSM_DMA_fifo_ren; | |
904 |
|
930 | |||
905 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE |
|
931 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE | |
906 | '1' WHEN fifo_1_ready = '0' ELSE |
|
932 | '1' WHEN fifo_1_ready = '0' ELSE | |
907 | FSM_DMA_fifo_ren; |
|
933 | FSM_DMA_fifo_ren; | |
908 |
|
934 | |||
909 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE |
|
935 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE | |
910 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE |
|
936 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE | |
911 | '1'; |
|
937 | '1'; | |
912 |
|
938 | |||
913 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE |
|
939 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE | |
914 | status_component_fifo_1; |
|
940 | status_component_fifo_1; | |
915 |
|
941 | |||
916 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE |
|
942 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE | |
917 | MEM_OUT_SM_Data_out(63 DOWNTO 32); |
|
943 | MEM_OUT_SM_Data_out(63 DOWNTO 32); | |
918 |
|
944 | |||
919 | ----------------------------------------------------------------------------- |
|
945 | ----------------------------------------------------------------------------- | |
920 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
|
946 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma | |
921 | PORT MAP ( |
|
947 | PORT MAP ( | |
922 | HCLK => clk, |
|
948 | HCLK => clk, | |
923 | HRESETn => rstn, |
|
949 | HRESETn => rstn, | |
924 |
|
950 | |||
925 | fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), |
|
951 | fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), | |
926 | fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), |
|
952 | fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), | |
927 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
953 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), | |
928 | fifo_data => FSM_DMA_fifo_data, |
|
954 | fifo_data => FSM_DMA_fifo_data, | |
929 | fifo_empty => FSM_DMA_fifo_empty, |
|
955 | fifo_empty => FSM_DMA_fifo_empty, | |
930 | fifo_ren => FSM_DMA_fifo_ren, |
|
956 | fifo_ren => FSM_DMA_fifo_ren, | |
931 |
|
957 | |||
932 | dma_addr => dma_addr, |
|
958 | dma_addr => dma_addr, | |
933 | dma_data => dma_data, |
|
959 | dma_data => dma_data, | |
934 | dma_valid => dma_valid, |
|
960 | dma_valid => dma_valid, | |
935 | dma_valid_burst => dma_valid_burst, |
|
961 | dma_valid_burst => dma_valid_burst, | |
936 | dma_ren => dma_ren, |
|
962 | dma_ren => dma_ren, | |
937 | dma_done => dma_done, |
|
963 | dma_done => dma_done, | |
938 |
|
964 | |||
939 | ready_matrix_f0 => ready_matrix_f0, |
|
965 | ready_matrix_f0 => ready_matrix_f0, | |
940 | ready_matrix_f1 => ready_matrix_f1, |
|
966 | ready_matrix_f1 => ready_matrix_f1, | |
941 | ready_matrix_f2 => ready_matrix_f2, |
|
967 | ready_matrix_f2 => ready_matrix_f2, | |
942 |
|
968 | |||
943 | error_bad_component_error => error_bad_component_error, |
|
969 | error_bad_component_error => error_bad_component_error, | |
944 | error_buffer_full => error_buffer_full, |
|
970 | error_buffer_full => error_buffer_full, | |
945 |
|
971 | |||
946 | debug_reg => debug_reg, |
|
972 | debug_reg => debug_reg, | |
947 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
973 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
948 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
974 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
949 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
975 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
950 |
|
976 | |||
951 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
977 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
952 | config_active_interruption_onError => config_active_interruption_onError, |
|
978 | config_active_interruption_onError => config_active_interruption_onError, | |
953 |
|
979 | |||
954 | addr_matrix_f0 => addr_matrix_f0, |
|
980 | addr_matrix_f0 => addr_matrix_f0, | |
955 | addr_matrix_f1 => addr_matrix_f1, |
|
981 | addr_matrix_f1 => addr_matrix_f1, | |
956 | addr_matrix_f2 => addr_matrix_f2, |
|
982 | addr_matrix_f2 => addr_matrix_f2, | |
957 |
|
983 | |||
958 | matrix_time_f0 => matrix_time_f0, |
|
984 | matrix_time_f0 => matrix_time_f0, | |
959 | matrix_time_f1 => matrix_time_f1, |
|
985 | matrix_time_f1 => matrix_time_f1, | |
960 | matrix_time_f2 => matrix_time_f2 |
|
986 | matrix_time_f2 => matrix_time_f2 | |
961 | ); |
|
987 | ); | |
962 | ----------------------------------------------------------------------------- |
|
988 | ----------------------------------------------------------------------------- | |
963 |
|
989 | |||
964 |
|
990 | |||
965 |
|
991 | |||
966 |
|
992 | |||
967 |
|
993 | |||
968 | ----------------------------------------------------------------------------- |
|
994 | ----------------------------------------------------------------------------- | |
969 | -- TIME MANAGMENT |
|
995 | -- TIME MANAGMENT | |
970 | ----------------------------------------------------------------------------- |
|
996 | ----------------------------------------------------------------------------- | |
971 | all_time <= coarse_time & fine_time; |
|
997 | all_time <= coarse_time & fine_time; | |
972 | -- |
|
998 | -- | |
973 | f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; |
|
999 | f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; | |
974 | f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; |
|
1000 | f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; | |
975 | f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; |
|
1001 | f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; | |
976 | f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; |
|
1002 | f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; | |
977 |
|
1003 | |||
978 | all_time_reg: FOR I IN 0 TO 3 GENERATE |
|
1004 | all_time_reg: FOR I IN 0 TO 3 GENERATE | |
979 |
|
1005 | |||
980 | PROCESS (clk, rstn) |
|
1006 | PROCESS (clk, rstn) | |
981 | BEGIN |
|
1007 | BEGIN | |
982 | IF rstn = '0' THEN |
|
1008 | IF rstn = '0' THEN | |
983 | f_empty_reg(I) <= '1'; |
|
1009 | f_empty_reg(I) <= '1'; | |
984 | ELSIF clk'event AND clk = '1' THEN |
|
1010 | ELSIF clk'event AND clk = '1' THEN | |
985 | f_empty_reg(I) <= f_empty(I); |
|
1011 | f_empty_reg(I) <= f_empty(I); | |
986 | END IF; |
|
1012 | END IF; | |
987 | END PROCESS; |
|
1013 | END PROCESS; | |
988 |
|
1014 | |||
989 | time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; |
|
1015 | time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; | |
990 |
|
1016 | |||
991 | s_m_t_m_f0_A : spectral_matrix_time_managment |
|
1017 | s_m_t_m_f0_A : spectral_matrix_time_managment | |
992 | PORT MAP ( |
|
1018 | PORT MAP ( | |
993 | clk => clk, |
|
1019 | clk => clk, | |
994 | rstn => rstn, |
|
1020 | rstn => rstn, | |
995 | time_in => all_time, |
|
1021 | time_in => all_time, | |
996 | update_1 => time_update_f(I), |
|
1022 | update_1 => time_update_f(I), | |
997 | time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) |
|
1023 | time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) | |
998 | ); |
|
1024 | ); | |
999 |
|
1025 | |||
1000 | END GENERATE all_time_reg; |
|
1026 | END GENERATE all_time_reg; | |
1001 |
|
1027 | |||
1002 | time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); |
|
1028 | time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); | |
1003 | time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); |
|
1029 | time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); | |
1004 | time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); |
|
1030 | time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); | |
1005 | time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); |
|
1031 | time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); | |
1006 |
|
1032 | |||
1007 | ----------------------------------------------------------------------------- |
|
1033 | ----------------------------------------------------------------------------- | |
1008 |
|
1034 | |||
1009 | END Behavioral; |
|
1035 | END Behavioral; |
@@ -1,416 +1,429 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
|
5 | USE grlib.amba.ALL; | |
6 |
|
6 | |||
7 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
8 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
9 | USE lpp.iir_filter.ALL; |
|
9 | USE lpp.iir_filter.ALL; | |
10 | USE lpp.FILTERcfg.ALL; |
|
10 | USE lpp.FILTERcfg.ALL; | |
11 | USE lpp.lpp_memory.ALL; |
|
11 | USE lpp.lpp_memory.ALL; | |
12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
14 |
|
14 | |||
15 | PACKAGE lpp_lfr_pkg IS |
|
15 | PACKAGE lpp_lfr_pkg IS | |
16 | ----------------------------------------------------------------------------- |
|
16 | ----------------------------------------------------------------------------- | |
17 | -- TEMP |
|
17 | -- TEMP | |
18 | ----------------------------------------------------------------------------- |
|
18 | ----------------------------------------------------------------------------- | |
19 | COMPONENT lpp_lfr_ms_test |
|
19 | COMPONENT lpp_lfr_ms_test | |
20 | GENERIC ( |
|
20 | GENERIC ( | |
21 | Mem_use : INTEGER); |
|
21 | Mem_use : INTEGER); | |
22 | PORT ( |
|
22 | PORT ( | |
23 | clk : IN STD_LOGIC; |
|
23 | clk : IN STD_LOGIC; | |
24 | rstn : IN STD_LOGIC; |
|
24 | rstn : IN STD_LOGIC; | |
25 |
|
25 | |||
26 | -- TIME |
|
26 | -- TIME | |
27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
29 | -- |
|
29 | -- | |
30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
32 | -- |
|
32 | -- | |
33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
35 | -- |
|
35 | -- | |
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
38 |
|
38 | |||
39 |
|
39 | |||
40 |
|
40 | |||
41 | --------------------------------------------------------------------------- |
|
41 | --------------------------------------------------------------------------- | |
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
43 |
|
43 | |||
44 | -- |
|
44 | -- | |
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
49 |
|
49 | |||
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); | |
51 |
|
51 | |||
52 | -- IN |
|
52 | -- IN | |
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
54 |
|
54 | |||
55 | ----------------------------------------------------------------------------- |
|
55 | ----------------------------------------------------------------------------- | |
56 |
|
56 | |||
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); | |
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
61 |
|
61 | |||
62 | SM_correlation_start : OUT STD_LOGIC; |
|
62 | SM_correlation_start : OUT STD_LOGIC; | |
63 | SM_correlation_auto : OUT STD_LOGIC; |
|
63 | SM_correlation_auto : OUT STD_LOGIC; | |
64 | SM_correlation_done : IN STD_LOGIC |
|
64 | SM_correlation_done : IN STD_LOGIC | |
65 | ); |
|
65 | ); | |
66 | END COMPONENT; |
|
66 | END COMPONENT; | |
67 |
|
67 | |||
68 |
|
68 | |||
69 | ----------------------------------------------------------------------------- |
|
69 | ----------------------------------------------------------------------------- | |
70 | COMPONENT lpp_lfr_ms |
|
70 | COMPONENT lpp_lfr_ms | |
71 | GENERIC ( |
|
71 | GENERIC ( | |
72 | Mem_use : INTEGER |
|
72 | Mem_use : INTEGER | |
73 | ); |
|
73 | ); | |
74 | PORT ( |
|
74 | PORT ( | |
75 | clk : IN STD_LOGIC; |
|
75 | clk : IN STD_LOGIC; | |
76 | rstn : IN STD_LOGIC; |
|
76 | rstn : IN STD_LOGIC; | |
77 |
|
77 | |||
78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
80 |
|
80 | |||
81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
83 |
|
83 | |||
84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
86 |
|
86 | |||
87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
89 |
|
89 | |||
90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | dma_valid : OUT STD_LOGIC; |
|
92 | dma_valid : OUT STD_LOGIC; | |
93 | dma_valid_burst : OUT STD_LOGIC; |
|
93 | dma_valid_burst : OUT STD_LOGIC; | |
94 | dma_ren : IN STD_LOGIC; |
|
94 | dma_ren : IN STD_LOGIC; | |
95 | dma_done : IN STD_LOGIC; |
|
95 | dma_done : IN STD_LOGIC; | |
96 |
|
96 | |||
97 | ready_matrix_f0 : OUT STD_LOGIC; |
|
97 | ready_matrix_f0 : OUT STD_LOGIC; | |
98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
99 | ready_matrix_f1 : OUT STD_LOGIC; |
|
99 | ready_matrix_f1 : OUT STD_LOGIC; | |
100 | ready_matrix_f2 : OUT STD_LOGIC; |
|
100 | ready_matrix_f2 : OUT STD_LOGIC; | |
101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
102 | error_bad_component_error : OUT STD_LOGIC; |
|
102 | error_bad_component_error : OUT STD_LOGIC; | |
103 | error_buffer_full : OUT STD_LOGIC; |
|
103 | error_buffer_full : OUT STD_LOGIC; | |
104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
106 | -- |
|
106 | -- | |
107 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
107 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
108 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
108 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
109 | ------------------------------------------------------------------------- |
|
109 | ------------------------------------------------------------------------- | |
110 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
110 | status_ready_matrix_f0 : IN STD_LOGIC; | |
111 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
111 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
112 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
112 | status_ready_matrix_f1 : IN STD_LOGIC; | |
113 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
113 | status_ready_matrix_f2 : IN STD_LOGIC; | |
114 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
114 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
115 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
115 | -- status_error_bad_component_error : IN STD_LOGIC; | |
116 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
116 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
117 | config_active_interruption_onError : IN STD_LOGIC; |
|
117 | config_active_interruption_onError : IN STD_LOGIC; | |
118 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
118 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
119 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
120 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
122 |
|
122 | |||
123 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
123 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
124 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
124 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
125 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
125 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
126 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
126 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
127 | END COMPONENT; |
|
127 | END COMPONENT; | |
128 |
|
128 | |||
129 | COMPONENT lpp_lfr_ms_fsmdma |
|
129 | COMPONENT lpp_lfr_ms_fsmdma | |
130 | PORT ( |
|
130 | PORT ( | |
131 | HCLK : IN STD_ULOGIC; |
|
131 | HCLK : IN STD_ULOGIC; | |
132 | HRESETn : IN STD_ULOGIC; |
|
132 | HRESETn : IN STD_ULOGIC; | |
133 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
133 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
134 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
134 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
135 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
135 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
136 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
136 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
137 | fifo_empty : IN STD_LOGIC; |
|
137 | fifo_empty : IN STD_LOGIC; | |
138 | fifo_ren : OUT STD_LOGIC; |
|
138 | fifo_ren : OUT STD_LOGIC; | |
139 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
139 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
140 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
141 | --fifo_empty : IN STD_LOGIC; |
|
141 | --fifo_empty : IN STD_LOGIC; | |
142 | --fifo_ren : OUT STD_LOGIC; |
|
142 | --fifo_ren : OUT STD_LOGIC; | |
143 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
144 | --header_val : IN STD_LOGIC; |
|
144 | --header_val : IN STD_LOGIC; | |
145 | --header_ack : OUT STD_LOGIC; |
|
145 | --header_ack : OUT STD_LOGIC; | |
146 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
146 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
147 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
147 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
148 | dma_valid : OUT STD_LOGIC; |
|
148 | dma_valid : OUT STD_LOGIC; | |
149 | dma_valid_burst : OUT STD_LOGIC; |
|
149 | dma_valid_burst : OUT STD_LOGIC; | |
150 | dma_ren : IN STD_LOGIC; |
|
150 | dma_ren : IN STD_LOGIC; | |
151 | dma_done : IN STD_LOGIC; |
|
151 | dma_done : IN STD_LOGIC; | |
152 | ready_matrix_f0 : OUT STD_LOGIC; |
|
152 | ready_matrix_f0 : OUT STD_LOGIC; | |
153 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
153 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
154 | ready_matrix_f1 : OUT STD_LOGIC; |
|
154 | ready_matrix_f1 : OUT STD_LOGIC; | |
155 | ready_matrix_f2 : OUT STD_LOGIC; |
|
155 | ready_matrix_f2 : OUT STD_LOGIC; | |
156 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
156 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
157 | error_bad_component_error : OUT STD_LOGIC; |
|
157 | error_bad_component_error : OUT STD_LOGIC; | |
158 | error_buffer_full : OUT STD_LOGIC; |
|
158 | error_buffer_full : OUT STD_LOGIC; | |
159 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
159 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
160 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
160 | status_ready_matrix_f0 : IN STD_LOGIC; | |
161 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
161 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
162 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
162 | status_ready_matrix_f1 : IN STD_LOGIC; | |
163 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
163 | status_ready_matrix_f2 : IN STD_LOGIC; | |
164 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
164 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
165 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
165 | -- status_error_bad_component_error : IN STD_LOGIC; | |
166 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
166 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
167 | config_active_interruption_onError : IN STD_LOGIC; |
|
167 | config_active_interruption_onError : IN STD_LOGIC; | |
168 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
168 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
169 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
169 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
170 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
170 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
171 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
171 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
172 |
|
172 | |||
173 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
173 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
174 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
174 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
175 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
175 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
176 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
176 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
177 | ); |
|
177 | ); | |
178 | END COMPONENT; |
|
178 | END COMPONENT; | |
179 |
|
179 | |||
180 | COMPONENT lpp_lfr_ms_FFT |
|
180 | COMPONENT lpp_lfr_ms_FFT | |
181 | PORT ( |
|
181 | PORT ( | |
182 | clk : IN STD_LOGIC; |
|
182 | clk : IN STD_LOGIC; | |
183 | rstn : IN STD_LOGIC; |
|
183 | rstn : IN STD_LOGIC; | |
184 | sample_valid : IN STD_LOGIC; |
|
184 | sample_valid : IN STD_LOGIC; | |
185 | fft_read : IN STD_LOGIC; |
|
185 | fft_read : IN STD_LOGIC; | |
186 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
186 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
187 | sample_load : OUT STD_LOGIC; |
|
187 | sample_load : OUT STD_LOGIC; | |
188 | fft_pong : OUT STD_LOGIC; |
|
188 | fft_pong : OUT STD_LOGIC; | |
189 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
189 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
190 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
190 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
191 | fft_data_valid : OUT STD_LOGIC; |
|
191 | fft_data_valid : OUT STD_LOGIC; | |
192 | fft_ready : OUT STD_LOGIC); |
|
192 | fft_ready : OUT STD_LOGIC); | |
193 | END COMPONENT; |
|
193 | END COMPONENT; | |
194 |
|
194 | |||
195 | COMPONENT lpp_lfr_filter |
|
195 | COMPONENT lpp_lfr_filter | |
196 | GENERIC ( |
|
196 | GENERIC ( | |
197 | Mem_use : INTEGER); |
|
197 | Mem_use : INTEGER); | |
198 | PORT ( |
|
198 | PORT ( | |
199 | sample : IN Samples(7 DOWNTO 0); |
|
199 | sample : IN Samples(7 DOWNTO 0); | |
200 | sample_val : IN STD_LOGIC; |
|
200 | sample_val : IN STD_LOGIC; | |
201 | clk : IN STD_LOGIC; |
|
201 | clk : IN STD_LOGIC; | |
202 | rstn : IN STD_LOGIC; |
|
202 | rstn : IN STD_LOGIC; | |
203 | data_shaping_SP0 : IN STD_LOGIC; |
|
203 | data_shaping_SP0 : IN STD_LOGIC; | |
204 | data_shaping_SP1 : IN STD_LOGIC; |
|
204 | data_shaping_SP1 : IN STD_LOGIC; | |
205 | data_shaping_R0 : IN STD_LOGIC; |
|
205 | data_shaping_R0 : IN STD_LOGIC; | |
206 | data_shaping_R1 : IN STD_LOGIC; |
|
206 | data_shaping_R1 : IN STD_LOGIC; | |
207 | sample_f0_val : OUT STD_LOGIC; |
|
207 | sample_f0_val : OUT STD_LOGIC; | |
208 | sample_f1_val : OUT STD_LOGIC; |
|
208 | sample_f1_val : OUT STD_LOGIC; | |
209 | sample_f2_val : OUT STD_LOGIC; |
|
209 | sample_f2_val : OUT STD_LOGIC; | |
210 | sample_f3_val : OUT STD_LOGIC; |
|
210 | sample_f3_val : OUT STD_LOGIC; | |
211 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
211 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
212 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
212 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
213 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
213 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
214 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
|
214 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); | |
215 | END COMPONENT; |
|
215 | END COMPONENT; | |
216 |
|
216 | |||
217 | COMPONENT lpp_lfr |
|
217 | COMPONENT lpp_lfr | |
218 | GENERIC ( |
|
218 | GENERIC ( | |
219 | Mem_use : INTEGER; |
|
219 | Mem_use : INTEGER; | |
220 | nb_data_by_buffer_size : INTEGER; |
|
220 | nb_data_by_buffer_size : INTEGER; | |
221 | nb_word_by_buffer_size : INTEGER; |
|
221 | nb_word_by_buffer_size : INTEGER; | |
222 | nb_snapshot_param_size : INTEGER; |
|
222 | nb_snapshot_param_size : INTEGER; | |
223 | delta_vector_size : INTEGER; |
|
223 | delta_vector_size : INTEGER; | |
224 | delta_vector_size_f0_2 : INTEGER; |
|
224 | delta_vector_size_f0_2 : INTEGER; | |
225 | pindex : INTEGER; |
|
225 | pindex : INTEGER; | |
226 | paddr : INTEGER; |
|
226 | paddr : INTEGER; | |
227 | pmask : INTEGER; |
|
227 | pmask : INTEGER; | |
228 | pirq_ms : INTEGER; |
|
228 | pirq_ms : INTEGER; | |
229 | pirq_wfp : INTEGER; |
|
229 | pirq_wfp : INTEGER; | |
230 | hindex : INTEGER; |
|
230 | hindex : INTEGER; | |
231 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
231 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
232 | ); |
|
232 | ); | |
233 | PORT ( |
|
233 | PORT ( | |
234 | clk : IN STD_LOGIC; |
|
234 | clk : IN STD_LOGIC; | |
235 | rstn : IN STD_LOGIC; |
|
235 | rstn : IN STD_LOGIC; | |
236 | sample_B : IN Samples(2 DOWNTO 0); |
|
236 | sample_B : IN Samples(2 DOWNTO 0); | |
237 | sample_E : IN Samples(4 DOWNTO 0); |
|
237 | sample_E : IN Samples(4 DOWNTO 0); | |
238 | sample_val : IN STD_LOGIC; |
|
238 | sample_val : IN STD_LOGIC; | |
239 | apbi : IN apb_slv_in_type; |
|
239 | apbi : IN apb_slv_in_type; | |
240 | apbo : OUT apb_slv_out_type; |
|
240 | apbo : OUT apb_slv_out_type; | |
241 | ahbi : IN AHB_Mst_In_Type; |
|
241 | ahbi : IN AHB_Mst_In_Type; | |
242 | ahbo : OUT AHB_Mst_Out_Type; |
|
242 | ahbo : OUT AHB_Mst_Out_Type; | |
243 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
243 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
244 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
244 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
245 | data_shaping_BW : OUT STD_LOGIC; |
|
245 | data_shaping_BW : OUT STD_LOGIC; | |
246 | -- |
|
246 | -- | |
247 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
247 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
248 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
248 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
249 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
249 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
250 | ); |
|
250 | ); | |
251 | END COMPONENT; |
|
251 | END COMPONENT; | |
252 |
|
252 | |||
253 | ----------------------------------------------------------------------------- |
|
253 | ----------------------------------------------------------------------------- | |
254 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
254 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) | |
255 | ----------------------------------------------------------------------------- |
|
255 | ----------------------------------------------------------------------------- | |
256 | COMPONENT lpp_lfr_WFP_nMS |
|
256 | COMPONENT lpp_lfr_WFP_nMS | |
257 | GENERIC ( |
|
257 | GENERIC ( | |
258 | Mem_use : INTEGER; |
|
258 | Mem_use : INTEGER; | |
259 | nb_data_by_buffer_size : INTEGER; |
|
259 | nb_data_by_buffer_size : INTEGER; | |
260 | nb_word_by_buffer_size : INTEGER; |
|
260 | nb_word_by_buffer_size : INTEGER; | |
261 | nb_snapshot_param_size : INTEGER; |
|
261 | nb_snapshot_param_size : INTEGER; | |
262 | delta_vector_size : INTEGER; |
|
262 | delta_vector_size : INTEGER; | |
263 | delta_vector_size_f0_2 : INTEGER; |
|
263 | delta_vector_size_f0_2 : INTEGER; | |
264 | pindex : INTEGER; |
|
264 | pindex : INTEGER; | |
265 | paddr : INTEGER; |
|
265 | paddr : INTEGER; | |
266 | pmask : INTEGER; |
|
266 | pmask : INTEGER; | |
267 | pirq_ms : INTEGER; |
|
267 | pirq_ms : INTEGER; | |
268 | pirq_wfp : INTEGER; |
|
268 | pirq_wfp : INTEGER; | |
269 | hindex : INTEGER; |
|
269 | hindex : INTEGER; | |
270 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
270 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
271 | PORT ( |
|
271 | PORT ( | |
272 | clk : IN STD_LOGIC; |
|
272 | clk : IN STD_LOGIC; | |
273 | rstn : IN STD_LOGIC; |
|
273 | rstn : IN STD_LOGIC; | |
274 | sample_B : IN Samples(2 DOWNTO 0); |
|
274 | sample_B : IN Samples(2 DOWNTO 0); | |
275 | sample_E : IN Samples(4 DOWNTO 0); |
|
275 | sample_E : IN Samples(4 DOWNTO 0); | |
276 | sample_val : IN STD_LOGIC; |
|
276 | sample_val : IN STD_LOGIC; | |
277 | apbi : IN apb_slv_in_type; |
|
277 | apbi : IN apb_slv_in_type; | |
278 | apbo : OUT apb_slv_out_type; |
|
278 | apbo : OUT apb_slv_out_type; | |
279 | ahbi : IN AHB_Mst_In_Type; |
|
279 | ahbi : IN AHB_Mst_In_Type; | |
280 | ahbo : OUT AHB_Mst_Out_Type; |
|
280 | ahbo : OUT AHB_Mst_Out_Type; | |
281 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
281 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
282 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
282 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
283 | data_shaping_BW : OUT STD_LOGIC; |
|
283 | data_shaping_BW : OUT STD_LOGIC; | |
284 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
284 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
285 | END COMPONENT; |
|
285 | END COMPONENT; | |
286 | ----------------------------------------------------------------------------- |
|
286 | ----------------------------------------------------------------------------- | |
287 | COMPONENT lpp_lfr_apbreg |
|
287 | COMPONENT lpp_lfr_apbreg | |
288 | GENERIC ( |
|
288 | GENERIC ( | |
289 | nb_data_by_buffer_size : INTEGER; |
|
289 | nb_data_by_buffer_size : INTEGER; | |
290 | nb_word_by_buffer_size : INTEGER; |
|
290 | nb_word_by_buffer_size : INTEGER; | |
291 | nb_snapshot_param_size : INTEGER; |
|
291 | nb_snapshot_param_size : INTEGER; | |
292 | delta_vector_size : INTEGER; |
|
292 | delta_vector_size : INTEGER; | |
293 | delta_vector_size_f0_2 : INTEGER; |
|
293 | delta_vector_size_f0_2 : INTEGER; | |
294 | pindex : INTEGER; |
|
294 | pindex : INTEGER; | |
295 | paddr : INTEGER; |
|
295 | paddr : INTEGER; | |
296 | pmask : INTEGER; |
|
296 | pmask : INTEGER; | |
297 | pirq_ms : INTEGER; |
|
297 | pirq_ms : INTEGER; | |
298 | pirq_wfp : INTEGER; |
|
298 | pirq_wfp : INTEGER; | |
299 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
299 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
300 | PORT ( |
|
300 | PORT ( | |
301 | HCLK : IN STD_ULOGIC; |
|
301 | HCLK : IN STD_ULOGIC; | |
302 | HRESETn : IN STD_ULOGIC; |
|
302 | HRESETn : IN STD_ULOGIC; | |
303 | apbi : IN apb_slv_in_type; |
|
303 | apbi : IN apb_slv_in_type; | |
304 | apbo : OUT apb_slv_out_type; |
|
304 | apbo : OUT apb_slv_out_type; | |
305 | run_ms : OUT STD_LOGIC; |
|
305 | run_ms : OUT STD_LOGIC; | |
306 | ready_matrix_f0 : IN STD_LOGIC; |
|
306 | ready_matrix_f0 : IN STD_LOGIC; | |
307 | ready_matrix_f1 : IN STD_LOGIC; |
|
307 | ready_matrix_f1 : IN STD_LOGIC; | |
308 | ready_matrix_f2 : IN STD_LOGIC; |
|
308 | ready_matrix_f2 : IN STD_LOGIC; | |
309 | error_bad_component_error : IN STD_LOGIC; |
|
309 | error_bad_component_error : IN STD_LOGIC; | |
310 | error_buffer_full : in STD_LOGIC; |
|
310 | error_buffer_full : in STD_LOGIC; | |
311 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
311 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); | |
312 | --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
312 | --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
313 | status_ready_matrix_f0 : OUT STD_LOGIC; |
|
313 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
314 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
314 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
315 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
315 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
316 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
316 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
317 | config_active_interruption_onError : OUT STD_LOGIC; |
|
317 | config_active_interruption_onError : OUT STD_LOGIC; | |
318 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
318 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
319 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
319 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
320 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
320 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
321 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
321 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
322 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
322 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
323 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
323 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
324 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
324 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
325 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
325 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
326 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
326 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
327 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
327 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
328 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
328 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
329 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
329 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
330 | data_shaping_BW : OUT STD_LOGIC; |
|
330 | data_shaping_BW : OUT STD_LOGIC; | |
331 | data_shaping_SP0 : OUT STD_LOGIC; |
|
331 | data_shaping_SP0 : OUT STD_LOGIC; | |
332 | data_shaping_SP1 : OUT STD_LOGIC; |
|
332 | data_shaping_SP1 : OUT STD_LOGIC; | |
333 | data_shaping_R0 : OUT STD_LOGIC; |
|
333 | data_shaping_R0 : OUT STD_LOGIC; | |
334 | data_shaping_R1 : OUT STD_LOGIC; |
|
334 | data_shaping_R1 : OUT STD_LOGIC; | |
335 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
335 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
336 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
336 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
337 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
337 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
338 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
338 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
339 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
339 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
340 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
340 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
341 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
341 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
342 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
342 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
343 | enable_f0 : OUT STD_LOGIC; |
|
343 | enable_f0 : OUT STD_LOGIC; | |
344 | enable_f1 : OUT STD_LOGIC; |
|
344 | enable_f1 : OUT STD_LOGIC; | |
345 | enable_f2 : OUT STD_LOGIC; |
|
345 | enable_f2 : OUT STD_LOGIC; | |
346 | enable_f3 : OUT STD_LOGIC; |
|
346 | enable_f3 : OUT STD_LOGIC; | |
347 | burst_f0 : OUT STD_LOGIC; |
|
347 | burst_f0 : OUT STD_LOGIC; | |
348 | burst_f1 : OUT STD_LOGIC; |
|
348 | burst_f1 : OUT STD_LOGIC; | |
349 | burst_f2 : OUT STD_LOGIC; |
|
349 | burst_f2 : OUT STD_LOGIC; | |
350 | run : OUT STD_LOGIC; |
|
350 | run : OUT STD_LOGIC; | |
351 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
351 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
352 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
352 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
353 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
353 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
354 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
354 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
355 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
355 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
356 |
|
356 | |||
357 | debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
357 | debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
358 |
|
358 | |||
359 | ); |
|
359 | ); | |
360 | END COMPONENT; |
|
360 | END COMPONENT; | |
361 |
|
361 | |||
362 |
|
362 | |||
363 |
|
363 | |||
364 | COMPONENT lpp_top_ms |
|
364 | COMPONENT lpp_top_ms | |
365 | GENERIC ( |
|
365 | GENERIC ( | |
366 | Mem_use : INTEGER; |
|
366 | Mem_use : INTEGER; | |
367 | nb_burst_available_size : INTEGER; |
|
367 | nb_burst_available_size : INTEGER; | |
368 | nb_snapshot_param_size : INTEGER; |
|
368 | nb_snapshot_param_size : INTEGER; | |
369 | delta_snapshot_size : INTEGER; |
|
369 | delta_snapshot_size : INTEGER; | |
370 | delta_f2_f0_size : INTEGER; |
|
370 | delta_f2_f0_size : INTEGER; | |
371 | delta_f2_f1_size : INTEGER; |
|
371 | delta_f2_f1_size : INTEGER; | |
372 | pindex : INTEGER; |
|
372 | pindex : INTEGER; | |
373 | paddr : INTEGER; |
|
373 | paddr : INTEGER; | |
374 | pmask : INTEGER; |
|
374 | pmask : INTEGER; | |
375 | pirq_ms : INTEGER; |
|
375 | pirq_ms : INTEGER; | |
376 | pirq_wfp : INTEGER; |
|
376 | pirq_wfp : INTEGER; | |
377 | hindex_wfp : INTEGER; |
|
377 | hindex_wfp : INTEGER; | |
378 | hindex_ms : INTEGER); |
|
378 | hindex_ms : INTEGER); | |
379 | PORT ( |
|
379 | PORT ( | |
380 | clk : IN STD_LOGIC; |
|
380 | clk : IN STD_LOGIC; | |
381 | rstn : IN STD_LOGIC; |
|
381 | rstn : IN STD_LOGIC; | |
382 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
382 | sample_B : IN Samples14v(2 DOWNTO 0); | |
383 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
383 | sample_E : IN Samples14v(4 DOWNTO 0); | |
384 | sample_val : IN STD_LOGIC; |
|
384 | sample_val : IN STD_LOGIC; | |
385 | apbi : IN apb_slv_in_type; |
|
385 | apbi : IN apb_slv_in_type; | |
386 | apbo : OUT apb_slv_out_type; |
|
386 | apbo : OUT apb_slv_out_type; | |
387 | ahbi_ms : IN AHB_Mst_In_Type; |
|
387 | ahbi_ms : IN AHB_Mst_In_Type; | |
388 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
388 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
389 | data_shaping_BW : OUT STD_LOGIC; |
|
389 | data_shaping_BW : OUT STD_LOGIC; | |
390 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
390 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
391 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
391 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
392 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
392 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
393 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
393 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
394 |
|
394 | |||
395 | ); |
|
395 | ); | |
396 | END COMPONENT; |
|
396 | END COMPONENT; | |
397 |
|
397 | |||
398 | COMPONENT lpp_apbreg_ms_pointer |
|
398 | COMPONENT lpp_apbreg_ms_pointer | |
399 | PORT ( |
|
399 | PORT ( | |
400 | clk : IN STD_LOGIC; |
|
400 | clk : IN STD_LOGIC; | |
401 | rstn : IN STD_LOGIC; |
|
401 | rstn : IN STD_LOGIC; | |
402 | reg0_status_ready_matrix : IN STD_LOGIC; |
|
402 | reg0_status_ready_matrix : IN STD_LOGIC; | |
403 | reg0_ready_matrix : OUT STD_LOGIC; |
|
403 | reg0_ready_matrix : OUT STD_LOGIC; | |
404 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
404 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
405 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
405 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
406 | reg1_status_ready_matrix : IN STD_LOGIC; |
|
406 | reg1_status_ready_matrix : IN STD_LOGIC; | |
407 | reg1_ready_matrix : OUT STD_LOGIC; |
|
407 | reg1_ready_matrix : OUT STD_LOGIC; | |
408 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
408 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
409 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
409 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
410 | ready_matrix : IN STD_LOGIC; |
|
410 | ready_matrix : IN STD_LOGIC; | |
411 | status_ready_matrix : OUT STD_LOGIC; |
|
411 | status_ready_matrix : OUT STD_LOGIC; | |
412 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
412 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
413 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
413 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
414 | END COMPONENT; |
|
414 | END COMPONENT; | |
|
415 | ||||
|
416 | COMPONENT lpp_lfr_ms_reg_head | |||
|
417 | PORT ( | |||
|
418 | clk : IN STD_LOGIC; | |||
|
419 | rstn : IN STD_LOGIC; | |||
|
420 | in_wen : IN STD_LOGIC; | |||
|
421 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |||
|
422 | in_full : IN STD_LOGIC; | |||
|
423 | in_empty : IN STD_LOGIC; | |||
|
424 | out_wen : OUT STD_LOGIC; | |||
|
425 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |||
|
426 | out_full : OUT STD_LOGIC); | |||
|
427 | END COMPONENT; | |||
415 |
|
428 | |||
416 | END lpp_lfr_pkg; |
|
429 | END lpp_lfr_pkg; |
@@ -1,9 +1,10 | |||||
1 | lpp_top_lfr_pkg.vhd |
|
1 | lpp_top_lfr_pkg.vhd | |
2 | lpp_lfr_pkg.vhd |
|
2 | lpp_lfr_pkg.vhd | |
3 | lpp_lfr_filter.vhd |
|
3 | lpp_lfr_filter.vhd | |
4 | lpp_lfr_apbreg.vhd |
|
4 | lpp_lfr_apbreg.vhd | |
5 | lpp_lfr_apbreg_ms_pointer.vhd |
|
5 | lpp_lfr_apbreg_ms_pointer.vhd | |
6 | lpp_lfr_ms_fsmdma.vhd |
|
6 | lpp_lfr_ms_fsmdma.vhd | |
7 | lpp_lfr_ms_FFT.vhd |
|
7 | lpp_lfr_ms_FFT.vhd | |
8 | lpp_lfr_ms.vhd |
|
8 | lpp_lfr_ms.vhd | |
|
9 | lpp_lfr_ms_reg_head.vhd | |||
9 | lpp_lfr.vhd |
|
10 | lpp_lfr.vhd |
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