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20 | 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
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21 | 21 | ---------------------------------------------------------------------------- |
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22 | 22 | |
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23 | library IEEE; | |
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24 |
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25 | library grlib; | |
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26 |
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27 |
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28 |
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23 | LIBRARY IEEE; | |
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24 | USE IEEE.STD_LOGIC_1164.ALL; | |
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25 | LIBRARY grlib; | |
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26 | USE grlib.amba.ALL; | |
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27 | USE grlib.stdlib.ALL; | |
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28 | USE grlib.devices.ALL; | |
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29 | 29 | |
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30 | 30 | |
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31 | package lpp_ad_conv is | |
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31 | PACKAGE lpp_ad_conv IS | |
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32 | 32 | |
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33 | 33 | |
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34 | constant AD7688 : integer := 0; | |
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35 | constant ADS7886 : integer := 1; | |
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34 | --CONSTANT AD7688 : INTEGER := 0; | |
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35 | --CONSTANT ADS7886 : INTEGER := 1; | |
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36 | 36 | |
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37 | 37 | |
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38 |
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39 | record | |
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40 | CNV : std_logic; | |
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41 | SCK : std_logic; | |
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42 | end record; | |
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38 | --TYPE AD7688_out IS | |
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39 | --RECORD | |
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40 | -- CNV : STD_LOGIC; | |
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41 | -- SCK : STD_LOGIC; | |
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42 | --END RECORD; | |
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43 | 43 | |
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44 |
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45 | record | |
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46 | SDI : std_logic; | |
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47 | end record; | |
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44 | --TYPE AD7688_in_element IS | |
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45 | --RECORD | |
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46 | -- SDI : STD_LOGIC; | |
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47 | --END RECORD; | |
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48 | 48 | |
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49 | type AD7688_in is array(natural range <>) of AD7688_in_element; | |
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49 | --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; | |
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50 | ||
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51 | TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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50 | 52 | |
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51 | type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0); | |
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53 | COMPONENT ADS7886_drvr | |
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54 | GENERIC ( | |
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55 | ChanelCount : INTEGER; | |
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56 | ncycle_cnv_high : INTEGER := 79; | |
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57 | ncycle_cnv : INTEGER := 500); | |
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58 | PORT ( | |
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59 | cnv_clk : IN STD_LOGIC; | |
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60 | cnv_rstn : IN STD_LOGIC; | |
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61 | cnv_run : IN STD_LOGIC; | |
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62 | cnv : OUT STD_LOGIC; | |
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63 | clk : IN STD_LOGIC; | |
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64 | rstn : IN STD_LOGIC; | |
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65 | sck : OUT STD_LOGIC; | |
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66 | sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
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67 | sample : OUT Samples(ChanelCount-1 DOWNTO 0); | |
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68 | sample_val : OUT STD_LOGIC); | |
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69 | END COMPONENT; | |
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52 | 70 | |
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53 | component AD7688_drvr is | |
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54 | generic(ChanelCount : integer; | |
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55 | clkkHz : integer); | |
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56 |
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57 |
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58 | enable : in std_logic; | |
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59 |
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60 | DataReady : out std_logic; | |
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61 |
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62 |
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63 |
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64 | end component; | |
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71 | --COMPONENT AD7688_drvr IS | |
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72 | -- GENERIC(ChanelCount : INTEGER; | |
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73 | -- clkkHz : INTEGER); | |
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74 | -- PORT (clk : IN STD_LOGIC; | |
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75 | -- rstn : IN STD_LOGIC; | |
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76 | -- enable : IN STD_LOGIC; | |
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77 | -- smplClk : IN STD_LOGIC; | |
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78 | -- DataReady : OUT STD_LOGIC; | |
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79 | -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0); | |
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80 | -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); | |
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81 | -- AD_out : OUT AD7688_out); | |
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82 | --END COMPONENT; | |
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65 | 83 | |
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66 | 84 | |
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67 | component AD7688_spi_if is | |
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68 | generic(ChanelCount : integer); | |
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69 |
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70 |
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71 |
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72 | DataReady: out std_logic; | |
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73 |
sdi |
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74 |
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75 | ); | |
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76 | end component; | |
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85 | --COMPONENT AD7688_spi_if IS | |
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86 | -- GENERIC(ChanelCount : INTEGER); | |
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87 | -- PORT(clk : IN STD_LOGIC; | |
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88 | -- reset : IN STD_LOGIC; | |
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89 | -- cnv : IN STD_LOGIC; | |
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90 | -- DataReady : OUT STD_LOGIC; | |
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91 | -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0); | |
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92 | -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0) | |
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93 | -- ); | |
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94 | --END COMPONENT; | |
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77 | 95 | |
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78 | 96 | |
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79 | component lpp_apb_ad_conv | |
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80 | generic( | |
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81 |
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82 |
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83 |
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84 |
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85 |
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86 |
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87 |
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88 |
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89 |
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90 |
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91 |
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92 |
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93 |
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94 |
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95 |
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96 |
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97 | end component; | |
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97 | --COMPONENT lpp_apb_ad_conv | |
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98 | -- GENERIC( | |
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99 | -- pindex : INTEGER := 0; | |
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100 | -- paddr : INTEGER := 0; | |
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101 | -- pmask : INTEGER := 16#fff#; | |
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102 | -- pirq : INTEGER := 0; | |
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103 | -- abits : INTEGER := 8; | |
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104 | -- ChanelCount : INTEGER := 1; | |
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105 | -- clkkHz : INTEGER := 50000; | |
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106 | -- smpClkHz : INTEGER := 100; | |
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107 | -- ADCref : INTEGER := AD7688); | |
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108 | -- PORT ( | |
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109 | -- clk : IN STD_LOGIC; | |
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110 | -- reset : IN STD_LOGIC; | |
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111 | -- apbi : IN apb_slv_in_type; | |
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112 | -- apbo : OUT apb_slv_out_type; | |
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113 | -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); | |
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114 | -- AD_out : OUT AD7688_out); | |
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115 | --END COMPONENT; | |
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98 | 116 | |
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99 | component ADS7886_drvr is | |
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100 | generic(ChanelCount : integer; | |
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101 |
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102 |
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103 |
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104 |
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105 |
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106 | DataReady : out std_logic; | |
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107 |
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108 |
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109 |
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110 |
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111 | end component; | |
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117 | --COMPONENT ADS7886_drvr IS | |
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118 | -- GENERIC(ChanelCount : INTEGER; | |
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119 | -- clkkHz : INTEGER); | |
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120 | -- PORT ( | |
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121 | -- clk : IN STD_LOGIC; | |
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122 | -- reset : IN STD_LOGIC; | |
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123 | -- smplClk : IN STD_LOGIC; | |
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124 | -- DataReady : OUT STD_LOGIC; | |
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125 | -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0); | |
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126 | -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); | |
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127 | -- AD_out : OUT AD7688_out | |
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128 | -- ); | |
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129 | --END COMPONENT; | |
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112 | 130 | |
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113 | component WriteGen_ADC is | |
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114 | port( | |
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115 | clk : in std_logic; | |
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116 | rstn : in std_logic; | |
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117 | SmplCLK : in std_logic; | |
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118 | DataReady : in std_logic; | |
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119 | Full : in std_logic_vector(4 downto 0); | |
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120 | ReUse : out std_logic_vector(4 downto 0); | |
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121 | Write : out std_logic_vector(4 downto 0) | |
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122 | ); | |
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123 | end component; | |
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131 | --COMPONENT WriteGen_ADC IS | |
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132 | -- PORT( | |
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133 | -- clk : IN STD_LOGIC; | |
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134 | -- rstn : IN STD_LOGIC; | |
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135 | -- SmplCLK : IN STD_LOGIC; | |
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136 | -- DataReady : IN STD_LOGIC; | |
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137 | -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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138 | -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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139 | -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) | |
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140 | -- ); | |
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141 | --END COMPONENT; | |
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124 | 142 | |
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125 |
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143 | END lpp_ad_conv; | |
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126 | 144 | |
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127 | 145 |
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