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1 1
2 2 --=================================================================================
3 3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 4 --
5 5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 6 --=================================================================================
7 7
8 8
9 9 library ieee;
10 10 use ieee.std_logic_1164.all;
11 11 library grlib;
12 12 use grlib.amba.all;
13 13 use std.textio.all;
14 14
15 15
16 package lpp_apb_devices is
16 package apb_devices_list is
17 17
18 18
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 /*-- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------*/
1 22 #include "stdio.h"
2 23 #include "lpp_apb_functions.h"
3 24 #include "apb_lcd_driver.h"
4 25
5 26
6 27
7 28 int main()
8 29 {
9 30 lcd_device* lcd0;
10 31 struct apbdevinfo lcd0info;
11 32 lcd0 = lcdopen(0);
12 33 char message[lcdCharCnt+1];
13 34 if(lcd0!= NULL)
14 35 {
15 36 apbgetdeviceinfofromid(LPP_LCD_CTRLR,VENDOR_LPP,0,&lcd0info);
16 37 printf("find lcd device @ %8x\n",(int)lcd0);
17 38 apbprintdeviceinfo(lcd0info);
18 39 }
19 40
20 41 printf("hello\n");
21 42 lcdclear(lcd0);
22 43 int d=0;
23 44 while(d!=10)
24 45 {
25 46 scanf("%d",&d);
26 47 switch(d)
27 48 {
28 49 case 0:
29 50 lcdsendcmd(lcd0,CursorOFF&lcd_100us);
30 51 printf("cursor OFF \n");
31 52 sprintf(message,"cursor OFF %d",d);
32 53 lcdprint(lcd0,0,message);
33 54 break;
34 55 case 1:
35 56 lcdsendcmd(lcd0,CursorON&lcd_100us);
36 57 printf("cursor ON \n");
37 58 sprintf(message,"cursor ON %d ",d);
38 59 lcdprint(lcd0,0,message);
39 60 break;
40 61 case 2:
41 62 sprintf(message,"Test line 2_%d\nline2",d);
42 63 lcdprint(lcd0,0,message);
43 64 break;
44 65 case 3:
45 66 apbprintdeviceslist();
46 67 break;
47 68 case 10:
48 69 sprintf(message,"QUIT %d ",d);
49 70 lcdprint(lcd0,0,message);
50 71 return 0;
51 72 break;
52 73 default:
53 74 sprintf(message,"Not a CMD %d ",d);
54 75 lcdprint(lcd0,0,message);
55 76 break;
56 77 }
57 78 }
58 79 return 0;
59 80 }
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
1 19 #include "stdio.h"
2 20 #include "lpp_apb_functions.h"
3 21
4 22
5 23
6 24 int main()
7 25 {
8 26 int d=0;
9 27 while(d!=10)
10 28 {
11 29 scanf("%d",&d);
12 30 switch(d)
13 31 {
14 32 case 0:
15 33 printf("cursor OFF \n");
16 34 break;
17 35 case 1:
18 36 printf("cursor ON \n");
19 37 break;
20 38 case 2:
21 39 break;
22 40 case 3:
23 41 apbprintdeviceslist();
24 42 break;
25 43 case 10:
26 44 return 0;
27 45 break;
28 46 default:
29 47 break;
30 48 }
31 49 }
32 50 return 0;
33 51 }
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
1 19 #ifndef APB_CNA_DRIVER_H
2 20 #define APB_CNA_DRIVER_H
3 21
4 22 #define DAC_ready 3
5 23 #define DAC_enable 1
6 24 #define DAC_disable 0
7 25
8 26
9 27 /*===================================================
10 28 T Y P E S D E F
11 29 ====================================================*/
12 30
13 31 struct DAC_Driver
14 32 {
15 33 int configReg;
16 34 int dataReg;
17 35 };
18 36
19 37 typedef struct DAC_Driver DAC_Device;
20 38
21 39 /*===================================================
22 40 F U N C T I O N S
23 41 ====================================================*/
24 42
25 43 DAC_Device* DacOpen(int count);
26 44
27 45 //DAC_Device* DacClose(int count);
28 46
29 47 int DacTable();
30 48
31 49 int DacConst();
32 50
33 51
34 52
35 53 #endif
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1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------*/
19 19 #ifndef LPP_APB_FUNCTIONS_H
20 20 #define LPP_APB_FUNCTIONS_H
21 21
22 22 #define APB_TBL_HEAD 0x800FF000
23 23 #define APB_BASE_ADDRS 0x80000000
24 24 #define APB_MAX_DEVICES 256
25 25
26 #define VENDOR_LPP 0x19
27
28 #define ROCKET_TM 0x001
29 #define otherCore 0x002
30 #define LPP_SIMPLE_DIODE 0x003
31 #define LPP_MULTI_DIODE 0x004
32 #define LPP_LCD_CTRLR 0x005
33 #define LPP_UART_CTRLR 0x006
34 #define LPP_DAC_CTRLR 0x007
26 #include "apb_devices_list.h"
35 27
36 28 /** @todo implemente a descriptor structure for any APB device */
37 29
38 30
39 31 /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */
40 32 struct apbPnPreg
41 33 {
42 34 int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */
43 35 int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */
44 36 };
45 37
46 38 struct apbdevinfo
47 39 {
48 40 int vendorID;
49 41 int productID;
50 42 int version;
51 43 int irq;
52 44 int address;
53 45 int mask;
54 46 };
55 47
56 48 /** This Function scans APB devices table and returns counth device according to VID and PID */
57 49 int* apbgetdevice(int PID,int VID,int count);
58 50 /** This Function scans APB devices table and returns counth device informations according VID and PID */
59 51 void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo);
60 52
61 53 void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo);
62 54
63 55
64 56 void apbprintdeviceinfo(struct apbdevinfo devinfo);
65 57
66 58 void apbprintdeviceslist();
67 59 #endif // LPP_APB_FUNCTIONS_H
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1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------*/
19 /*-- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------*/
19 22 #include "lpp_apb_functions.h"
20 23 #include <stdio.h>
21 24
22 25
23 26
24 27 int* apbgetdevice(int PID,int VID,int count)
25 28 {
26 29 struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD + sizeof(struct apbPnPreg));
27 30 int id;
28 31 id = (PID<<12) | (VID<<24);
29 32 while(dev != (struct apbPnPreg*)(APB_TBL_HEAD|0xFFF))
30 33 {
31 34 if((dev->idReg & 0xFFFFF000) == id)
32 35 {
33 36 if(count == 0)
34 37 {
35 38 return (int*) (APB_BASE_ADDRS | (dev->bar&0xFFF00000)>>12);
36 39 }
37 40 count-=1;
38 41 }
39 42 dev += 1;
40 43 }
41 44 return NULL;
42 45 }
43 46
44 47
45 48 void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo)
46 49 {
47 50
48 51 devinfo->productID = (dev->idReg>>12) & 0xFFF;
49 52 devinfo->vendorID = (dev->idReg>>24) & 0xFF;
50 53 devinfo->address = ((dev->bar>>12) & 0xFFF00)|APB_BASE_ADDRS;
51 54 devinfo->irq = dev->idReg & 0x1F;
52 55 devinfo->mask = (dev->bar>>4)&0xFFF;
53 56 devinfo->version = (dev->idReg>>5)&0x1F;
54 57 }
55 58
56 59 void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo)
57 60 {
58 61 struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD + sizeof(struct apbPnPreg));
59 62 int id;
60 63 id = (PID<<12) | (VID<<24);
61 64 while(dev != (struct apbPnPreg*)(APB_TBL_HEAD|0xFFF))
62 65 {
63 66 if((dev->idReg & 0xFFFFF000) == id)
64 67 {
65 68 if(count == 0)
66 69 {
67 70 devinfo->productID = PID;
68 71 devinfo->vendorID = VID;
69 72 devinfo->address = ((dev->bar>>12) & 0xFFF00)|APB_BASE_ADDRS;
70 73 devinfo->irq = dev->idReg & 0x1F;
71 74 devinfo->mask = (dev->bar>>4)&0xFFF;
72 75 devinfo->version = (dev->idReg>>5)&0x1F;
73 76 return;
74 77 }
75 78 count-=1;
76 79 }
77 80 dev += 1;
78 81 }
79 82 }
80 83
81 84
82 85
83 86 void apbprintdeviceinfo(struct apbdevinfo devinfo)
84 87 {
85 88 printf("Vendor ID = 0x%x\n",devinfo.vendorID);
86 89 printf("Product ID = 0x%x\n",devinfo.productID);
87 90 printf("Device address = 0x%x\n",devinfo.address);
88 91 printf("Device Irq = %d\n",devinfo.irq);
89 92 printf("Device mask = 0x%x\n",devinfo.mask);
90 93 printf("Device Version = %d\n",devinfo.version);
91 94 }
92 95
93 96
94 97 void apbprintdeviceslist()
95 98 {
96 99 struct apbdevinfo devinfo;
97 100 struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD );//+ sizeof(struct apbPnPreg));
98 101 int i =0;
99 102 int fisrtBAR;
100 103 while((dev->idReg == 0) && (i<APB_MAX_DEVICES))
101 104 {
102 105 dev += 1;
103 106 i+=1;
104 107 }
105 108 fisrtBAR = dev->bar;
106 109 for(i=i;i<APB_MAX_DEVICES;i++)
107 110 {
108 111 if((dev->idReg != 0 ))
109 112 {
110 113 apbgetdeviceinfofromdevptr(dev,&devinfo);
111 114 printf("\n\n======= new device found========\n");
112 115 apbprintdeviceinfo(devinfo);
113 116 }
114 117 dev += 1;
115 118 if(dev->bar == fisrtBAR)
116 119 break;
117 120 }
118 121 }
119 122
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@@ -1,59 +1,62
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------*/
19 /*-- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------*/
19 22 #ifndef LPP_APB_FUNCTIONS_H
20 23 #define LPP_APB_FUNCTIONS_H
21 24
22 25 #define APB_TBL_HEAD 0x800FF000
23 26 #define APB_BASE_ADDRS 0x80000000
24 27 #define APB_MAX_DEVICES 256
25 28
26 29 #include "apb_devices_list.h"
27 30
28 31 /** @todo implemente a descriptor structure for any APB device */
29 32
30 33
31 34 /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */
32 35 struct apbPnPreg
33 36 {
34 37 int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */
35 38 int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */
36 39 };
37 40
38 41 struct apbdevinfo
39 42 {
40 43 int vendorID;
41 44 int productID;
42 45 int version;
43 46 int irq;
44 47 int address;
45 48 int mask;
46 49 };
47 50
48 51 /** This Function scans APB devices table and returns counth device according to VID and PID */
49 52 int* apbgetdevice(int PID,int VID,int count);
50 53 /** This Function scans APB devices table and returns counth device informations according VID and PID */
51 54 void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo);
52 55
53 56 void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo);
54 57
55 58
56 59 void apbprintdeviceinfo(struct apbdevinfo devinfo);
57 60
58 61 void apbprintdeviceslist();
59 62 #endif // LPP_APB_FUNCTIONS_H
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@@ -1,68 +1,86
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
1 19 #include "apb_dac_Driver.h"
2 20 #include "lpp_apb_functions.h"
3 21 #include <stdio.h>
4 22
5 23
6 24 DAC_Device* DacOpen(int count)
7 25 {
8 26 DAC_Device* dac0;
9 27 dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
10 28 dac0->configReg = DAC_enable;
11 29 return dac0;
12 30 }
13 31
14 32 /*
15 33 DAC_Device* DacClose(int count)
16 34 {
17 35 DAC_Device* dac1;
18 36 dac1 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
19 37 dac1->configReg = DAC_disable;
20 38 return dac1;
21 39 }
22 40 */
23 41
24 42
25 43 int DacTable()
26 44 {
27 45 int i;
28 46 DAC_Device* dac2;
29 47 int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,
30 48 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,
31 49 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,
32 50 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,
33 51 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,
34 52 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,
35 53 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
36 54 dac2 = (DAC_Device*)0x80000800;
37 55 dac2->configReg = DAC_enable;
38 56 dac2->dataReg = tablo[0];
39 57
40 58 while(1)
41 59 {
42 60 for (i = 0 ; i < 251 ; i++)
43 61 {
44 62 while(!((dac2->configReg & DAC_ready) == DAC_ready));
45 63 dac2->dataReg = tablo[i];
46 64 while((dac2->configReg & DAC_ready) == DAC_ready);
47 65 }
48 66 }
49 67 return 0;
50 68 }
51 69
52 70
53 71
54 72 int DacConst()
55 73 {
56 74 DAC_Device* dac3;
57 75 int Value = 0x1FFF;
58 76 dac3 = (DAC_Device*)0x80000800;
59 77 dac3->configReg = DAC_enable;
60 78 while(1)
61 79 {
62 80 printf("\nEntrer une valeur entre 4096 et 8191 : ");
63 81 scanf("%d",&Value);
64 82 dac3->dataReg = Value;
65 83 }
66 84 return 0;
67 85 }
68 86
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@@ -1,35 +1,53
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
1 19 #ifndef APB_CNA_DRIVER_H
2 20 #define APB_CNA_DRIVER_H
3 21
4 22 #define DAC_ready 3
5 23 #define DAC_enable 1
6 24 #define DAC_disable 0
7 25
8 26
9 27 /*===================================================
10 28 T Y P E S D E F
11 29 ====================================================*/
12 30
13 31 struct DAC_Driver
14 32 {
15 33 int configReg;
16 34 int dataReg;
17 35 };
18 36
19 37 typedef struct DAC_Driver DAC_Device;
20 38
21 39 /*===================================================
22 40 F U N C T I O N S
23 41 ====================================================*/
24 42
25 43 DAC_Device* DacOpen(int count);
26 44
27 45 //DAC_Device* DacClose(int count);
28 46
29 47 int DacTable();
30 48
31 49 int DacConst();
32 50
33 51
34 52
35 53 #endif
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@@ -1,115 +1,118
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------*/
19 /*-- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------*/
19 22 #include "apb_lcd_driver.h"
20 23 #include "lpp_apb_functions.h"
21 24 #include "lpp_apb_functions.h"
22 25 #include <stdio.h>
23 26
24 27 int lcdbusy(lcd_device* lcd)
25 28 {
26 29 return (!(lcd->cfg_reg&readyFlag)==readyFlag);
27 30 }
28 31
29 32
30 33 lcd_device* lcdopen(int count)
31 34 {
32 35 lcd_device* dev;
33 36 dev = (lcd_device*) apbgetdevice(LPP_LCD_CTRLR,VENDOR_LPP,count);
34 37 return dev;
35 38 //* scan APB bus an return the count(th) lcd controler */
36 39
37 40 }
38 41
39 42
40 43
41 44 lcd_err lcdsendcmd(lcd_device* lcd,int cmd)
42 45 {
43 46 lcd_err err;
44 47 err = lcd_error_no_error;
45 48 if (lcd!=NULL)
46 49 {
47 50 while(lcdbusy(lcd));
48 51 lcd->cfg_reg = cmd;
49 52 return err;
50 53 }
51 54 else
52 55 {
53 56 err = lcd_error_not_openned ;
54 57 return err;
55 58 }
56 59 }
57 60
58 61
59 62
60 63 lcd_err lcdsetchar(lcd_device* lcd,int position,const char value)
61 64 {
62 65 lcd_err err;
63 66 err = lcd_error_no_error;
64 67 return err;
65 68 }
66 69
67 70
68 71
69 72 lcd_err lcdprint(lcd_device* lcd,int position,const char* value)
70 73 {
71 74 lcd_err err;
72 75 err = lcd_error_no_error;
73 76 if (lcd!=NULL)
74 77 {
75 78 int i = position;
76 79 int n = 0;
77 80 while(value[n]!= '\0' && i<lcdCharCnt)
78 81 {
79 82 if(value[n] == '\n')
80 83 {
81 84 i=40;n++;
82 85 }
83 86 lcd->Frame_buff[i++] = value[n++];
84 87 }
85 88 return err;
86 89 }
87 90 else
88 91 {
89 92 err = lcd_error_not_openned ;
90 93 return err;
91 94 }
92 95 }
93 96
94 97
95 98
96 99 lcd_err lcdclear(lcd_device* lcd)
97 100 {
98 101 lcd_err err;
99 102 err = lcd_error_no_error;
100 103 if (lcd!=NULL)
101 104 {
102 105 int i=0;
103 106 for(i=0;i<lcdCharCnt;i++)
104 107 {
105 108 lcd->Frame_buff[i] = ' ';
106 109 }
107 110 return err;
108 111 }
109 112 err = lcd_error_not_openned ;
110 113 return err;
111 114 }
112 115
113 116
114 117
115 118
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@@ -1,95 +1,98
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------*/
19 /*-- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------*/
19 22 #ifndef APB_LCD_DRIVER_H
20 23 #define APB_LCD_DRIVER_H
21 24
22 25 #define readyFlag 1024
23 26 #define lcdCharCnt 80
24 27
25 28
26 29 /** @todo implemente some shift functions */
27 30
28 31
29 32 /*===================================================
30 33 T Y P E S D E F
31 34 ====================================================*/
32 35
33 36
34 37
35 38 /** error type used for most of lcd functions */
36 39 typedef int lcd_err;
37 40
38 41 /** lcd error ennum for higher abstraction level when error decoding */
39 42 enum lcd_error
40 43 {
41 44 lcd_error_no_error, /**< no error append while function execution */
42 45 lcd_error_not_ready, /**< the lcd isn't available*/
43 46 lcd_error_not_openned, /**< the device guiven to the function isn't opened*/
44 47 lcd_error_too_long /**< the string guiven to the lcd is bigger than the lcd frame buffer memory */
45 48 };
46 49
47 50
48 51 /** for each command sended to the lcd driver a time should be guiven according to the lcd datasheet */
49 52 enum lcd_CMD_time
50 53 {
51 54 lcd_4us = 0x0FF,
52 55 lcd_100us = 0x1FF,
53 56 lcd_4ms = 0x2FF,
54 57 lcd_20ms = 0x3FF
55 58 };
56 59
57 60 /** list of availiable lcd commands use whith an AND mask whith cmd time */
58 61 enum lcd_CMD
59 62 {
60 63 CursorON = 0xF0E,
61 64 CursorOFF = 0xF0C
62 65 };
63 66
64 67 /** structure representing the lcd registers */
65 68 struct lcd_driver
66 69 {
67 70 int cfg_reg; /**< Configuration register composed of Ready flag [10], CMD time Value [9:8], CMD to send [7:0]*/
68 71 int Frame_buff[lcdCharCnt]; /**< Frame Buffer space each address corresponds to a char on the lcd screen */
69 72 };
70 73
71 74 typedef struct lcd_driver lcd_device;
72 75
73 76 /*===================================================
74 77 F U N C T I O N S
75 78 ====================================================*/
76 79
77 80 /** says if the lcd is busy */
78 81 int lcdbusy(lcd_device * lcd);
79 82
80 83 /** Opens and returns the counth lcd found on APB bus else NULL */
81 84 lcd_device* lcdopen(int count);
82 85
83 86 /** Sends a command to the given device, don't forget to guive the time of the cmd */
84 87 lcd_err lcdsendcmd(lcd_device* lcd,int cmd);
85 88
86 89 /** Sets a char on the given device at given position */
87 90 lcd_err lcdsetchar(lcd_device* lcd,int position,const char value);
88 91
89 92 /** Prints a message on the given device at given position, "\n" is understood but for others use sprintf before */
90 93 lcd_err lcdprint(lcd_device* lcd,int position,const char* value);
91 94
92 95 /** Writes space character on each adress of the lcd screen */
93 96 lcd_err lcdclear(lcd_device* lcd);
94 97
95 98 #endif
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@@ -1,68 +1,71
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24 use IEEE.NUMERIC_STD.ALL;
22 25 library lpp;
23 26 use lpp.amba_lcd_16x2_ctrlr.all;
24 27
25 28 entity FRAME_CLK_GEN is
26 29 generic(OSC_freqKHz : integer := 50000);
27 30 Port ( clk : in STD_LOGIC;
28 31 reset : in STD_LOGIC;
29 32 FRAME_CLK : out STD_LOGIC);
30 33 end FRAME_CLK_GEN;
31 34
32 35 architecture Behavioral of FRAME_CLK_GEN is
33 36
34 37 Constant Goal_FRAME_CLK_FREQ : integer := 25;
35 38
36 39 Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;
37 40
38 41 signal CPT : integer := 0;
39 42 signal FRAME_CLK_reg : std_logic :='0';
40 43
41 44 begin
42 45
43 46 FRAME_CLK <= FRAME_CLK_reg;
44 47
45 48 process(reset,clk)
46 49 begin
47 50 if reset = '0' then
48 51 CPT <= 0;
49 52 FRAME_CLK_reg <= '0';
50 53 elsif clk'event and clk = '1' then
51 54 if CPT = FRAME_CLK_TRIG then
52 55 CPT <= 0;
53 56 FRAME_CLK_reg <= not FRAME_CLK_reg;
54 57 else
55 58 CPT <= CPT + 1;
56 59 end if;
57 60 end if;
58 61 end process;
59 62 end Behavioral;
60 63
61 64
62 65
63 66
64 67
65 68
66 69
67 70
68 71
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@@ -1,50 +1,53
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.all;
21 24 library lpp;
22 25 use lpp.amba_lcd_16x2_ctrlr.all;
23 26
24 27
25 28
26 29 package LCD_16x2_CFG is
27 30
28 31
29 32 constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01";
30 33 constant FunctionSet : std_logic_vector(7 downto 0):= X"38";
31 34 constant RetHome : std_logic_vector(7 downto 0):= X"02";
32 35 constant SetEntryMode : std_logic_vector(7 downto 0):= X"06";
33 36 constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0E";
34 37
35 38 constant CursorON : std_logic_vector(7 downto 0):= X"0E";
36 39 constant CursorOFF : std_logic_vector(7 downto 0):= X"0C";
37 40
38 41 --===========================================================|
39 42 --======L C D D R I V E R T I M I N G C O D E=====|
40 43 --===========================================================|
41 44
42 45 constant Duration_4us : std_logic_vector(1 downto 0) := "00";
43 46 constant Duration_100us : std_logic_vector(1 downto 0) := "01";
44 47 constant Duration_4ms : std_logic_vector(1 downto 0) := "10";
45 48 constant Duration_20ms : std_logic_vector(1 downto 0) := "11";
46 49
47 50
48 51
49 52 end LCD_16x2_CFG;
50 53
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@@ -1,168 +1,171
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22
20 23 ---TDODO => Clean Enable pulse FSM
21 24 library IEEE;
22 25 use IEEE.STD_LOGIC_1164.ALL;
23 26 use IEEE.NUMERIC_STD.all;
24 27 library lpp;
25 28 use lpp.amba_lcd_16x2_ctrlr.all;
26 29 use lpp.lcd_16x2_cfg.all;
27 30
28 31 entity LCD_16x2_DRIVER is
29 32 generic(
30 33 OSC_Freq_KHz : integer:=50000
31 34 );
32 35 Port(
33 36 reset : in STD_LOGIC;
34 37 clk : in STD_LOGIC;
35 38 LCD_CTRL : out LCD_DRVR_CTRL_BUSS;
36 39 SYNCH : out LCD_DRVR_SYNCH_BUSS;
37 40 DRIVER_CMD : in LCD_DRVR_CMD_BUSS
38 41 );
39 42 end LCD_16x2_DRIVER;
40 43
41 44 architecture Behavioral of LCD_16x2_DRIVER is
42 45
43 46 type stateT is (idle,Enable0,Enable1,Enable2,tempo);
44 47 signal state : stateT;
45 48
46 49
47 50 constant trigger_4us : integer := 5;
48 51 constant trigger_100us : integer := 100;
49 52 constant trigger_4ms : integer := 4200;
50 53 constant trigger_20ms : integer := 20000;
51 54
52 55
53 56 signal i : integer :=0;
54 57 signal reset_i : std_logic := '0';
55 58 signal tempoTRIG : integer :=0;
56 59
57 60 signal clk_1us : std_logic;
58 61 signal clk_1us_reg : std_logic;
59 62
60 63 begin
61 64
62 65
63 66 CLK0: LCD_CLK_GENERATOR
64 67 generic map(OSC_Freq_KHz)
65 68 Port map( clk,reset,clk_1us);
66 69
67 70
68 71
69 72 process(clk_1us,reset_i)
70 73 begin
71 74 if reset_i = '0' then
72 75 i <= 0;
73 76 elsif clk_1us'event and clk_1us ='1' then
74 77 i <= i+1;
75 78 end if;
76 79 end process;
77 80
78 81 LCD_CTRL.LCD_RW <= '0';
79 82
80 83 process(clk,reset)
81 84 begin
82 85 if reset = '0' then
83 86 state <= idle;
84 87 LCD_CTRL.LCD_E <= '0';
85 88 SYNCH.DRVR_READY <= '0';
86 89 SYNCH.LCD_INITIALISED <= '0';
87 90 reset_i <= '0';
88 91 elsif clk'event and clk = '1' then
89 92 case state is
90 93 when idle =>
91 94 SYNCH.LCD_INITIALISED <= '1';
92 95 LCD_CTRL.LCD_E <= '0';
93 96 if DRIVER_CMD.Exec = '1' then
94 97 state <= Enable0;
95 98 reset_i <= '1';
96 99 SYNCH.DRVR_READY <= '0';
97 100 LCD_CTRL.LCD_DATA <= DRIVER_CMD.Word;
98 101 LCD_CTRL.LCD_RS <= DRIVER_CMD.CMD_Data;
99 102 case DRIVER_CMD.Duration is
100 103 when Duration_4us =>
101 104 tempoTRIG <= trigger_4us;
102 105 when Duration_100us =>
103 106 tempoTRIG <= trigger_100us;
104 107 when Duration_4ms =>
105 108 tempoTRIG <= trigger_4ms;
106 109 when Duration_20ms =>
107 110 tempoTRIG <= trigger_20ms;
108 111 when others =>
109 112 tempoTRIG <= trigger_20ms;
110 113 end case;
111 114 else
112 115 SYNCH.DRVR_READY <= '1';
113 116 reset_i <= '0';
114 117 end if;
115 118 when Enable0 =>
116 119 if i = 1 then
117 120 reset_i <= '0';
118 121 LCD_CTRL.LCD_E <= '1';
119 122 state <= Enable1;
120 123 else
121 124 reset_i <= '1';
122 125 LCD_CTRL.LCD_E <= '0';
123 126 end if;
124 127 when Enable1 =>
125 128 if i = 2 then
126 129 reset_i <= '0';
127 130 LCD_CTRL.LCD_E <= '0';
128 131 state <= Enable2;
129 132 else
130 133 reset_i <= '1';
131 134 LCD_CTRL.LCD_E <= '1';
132 135 end if;
133 136 when Enable2 =>
134 137 if i = 1 then
135 138 reset_i <= '0';
136 139 LCD_CTRL.LCD_E <= '0';
137 140 state <= tempo;
138 141 else
139 142 reset_i <= '1';
140 143 LCD_CTRL.LCD_E <= '0';
141 144 end if;
142 145 when tempo =>
143 146 if i = tempoTRIG then
144 147 reset_i <= '0';
145 148 state <= idle;
146 149 else
147 150 reset_i <= '1';
148 151 end if;
149 152 end case;
150 153 end if;
151 154 end process;
152 155
153 156 end Behavioral;
154 157
155 158
156 159
157 160
158 161
159 162
160 163
161 164
162 165
163 166
164 167
165 168
166 169
167 170
168 171
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@@ -1,210 +1,213
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24 use IEEE.NUMERIC_STD.ALL;
22 25
23 26 library lpp;
24 27 use lpp.amba_lcd_16x2_ctrlr.all;
25 28 use lpp.LCD_16x2_CFG.all;
26 29
27 30
28 31 entity LCD_16x2_ENGINE is
29 32 generic(OSC_freqKHz : integer := 50000);
30 33 Port ( clk : in STD_LOGIC;
31 34 reset : in STD_LOGIC;
32 35 DATA : in FRM_Buff_Space;
33 36 CMD : in std_logic_vector(10 downto 0);
34 37 Exec : in std_logic;
35 38 Ready : out std_logic;
36 39 LCD_CTRL : out LCD_DRVR_CTRL_BUSS
37 40 );
38 41 end LCD_16x2_ENGINE;
39 42
40 43 architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is
41 44
42 45 constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome);
43 46
44 47
45 48
46 49 signal SYNCH : LCD_DRVR_SYNCH_BUSS;
47 50 signal DRIVER_CMD : LCD_DRVR_CMD_BUSS;
48 51 signal FRAME_CLK : std_logic;
49 52
50 53 signal FRAME_CLK_reg : std_logic;
51 54 signal RefreshFlag : std_logic;
52 55 signal CMD_Flag : std_logic;
53 56 signal Exec_Reg : std_logic;
54 57
55 58 type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1);
56 59 signal state : state_t;
57 60 signal i : integer range 0 to lcd_space_size := 0;
58 61
59 62
60 63
61 64 begin
62 65
63 66 Driver0 : LCD_16x2_DRIVER
64 67 generic map(OSC_freqKHz)
65 68 Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD);
66 69
67 70 FRAME_CLK_GEN0 : FRAME_CLK_GEN
68 71 generic map(OSC_freqKHz)
69 72 Port map( clk,reset,FRAME_CLK);
70 73
71 74
72 75
73 76 process(reset,clk)
74 77 begin
75 78 if reset = '0' then
76 79 state <= INIT0;
77 80 Ready <= '0';
78 81 RefreshFlag <= '0';
79 82 i <= 0;
80 83 elsif clk'event and clk ='1' then
81 84 FRAME_CLK_reg <= FRAME_CLK;
82 85 Exec_Reg <= Exec;
83 86
84 87 if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then
85 88 RefreshFlag <= '1';
86 89 elsif state = Refresh or state = Refresh0 or state = Refresh1 then
87 90 RefreshFlag <= '0';
88 91 end if;
89 92
90 93 if Exec_Reg = '0' and Exec = '1' then
91 94 CMD_Flag <= '1';
92 95 elsif state = ExecCMD0 or state = ExecCMD1 then
93 96 CMD_Flag <= '0';
94 97 end if;
95 98
96 99 case state is
97 100 when INIT0 =>
98 101 if SYNCH.DRVR_READY = '1' then
99 102 DRIVER_CMD.Exec <= '1';
100 103 DRIVER_CMD.Duration <= Duration_20ms;
101 104 DRIVER_CMD.CMD_Data <= '0';
102 105 DRIVER_CMD.Word <= ConfigTbl(i);
103 106 i <= i + 1;
104 107 state <= INIT1;
105 108 else
106 109 DRIVER_CMD.Exec <= '0';
107 110 end if;
108 111 when INIT1 =>
109 112 state <= INIT2;
110 113 DRIVER_CMD.Exec <= '0';
111 114 when INIT2 =>
112 115 if SYNCH.DRVR_READY = '1' then
113 116 if i = 5 then
114 117 state <= Idle;
115 118 else
116 119 state <= INIT0;
117 120 end if;
118 121 end if;
119 122 when Idle=>
120 123 DRIVER_CMD.Exec <= '0';
121 124 if RefreshFlag = '1' then
122 125 Ready <= '0';
123 126 state <= Refresh;
124 127 elsif CMD_Flag = '1' then
125 128 Ready <= '0';
126 129 state <= ExecCMD0;
127 130 else
128 131 Ready <= '1';
129 132 end if;
130 133 i <= 0;
131 134 when Refresh=>
132 135 if SYNCH.DRVR_READY = '1' then
133 136 DRIVER_CMD.Exec <= '1';
134 137 DRIVER_CMD.Duration <= Duration_100us;
135 138 DRIVER_CMD.CMD_Data <= '1';
136 139 DRIVER_CMD.Word <= DATA(i);
137 140 state <= Refresh0;
138 141 else
139 142 DRIVER_CMD.Exec <= '0';
140 143 end if;
141 144 when Refresh0=>
142 145 i <= i + 1;
143 146 state <= Refresh1;
144 147 DRIVER_CMD.Exec <= '0';
145 148 when Refresh1=>
146 149 if SYNCH.DRVR_READY = '1' then
147 150 if i = lcd_space_size then
148 151 -- state <= ReturnHome;
149 152 state <= Idle;
150 153 -- elsif i = 16 then
151 154 -- state <= GoLine2;
152 155 else
153 156 state <= Refresh;
154 157 end if;
155 158 end if;
156 159
157 160 when ExecCMD0=>
158 161 if SYNCH.DRVR_READY = '1' then
159 162 DRIVER_CMD.Exec <= '1';
160 163 DRIVER_CMD.Duration <= CMD(9 downto 8);
161 164 DRIVER_CMD.CMD_Data <= '0';
162 165 DRIVER_CMD.Word <= CMD(7 downto 0);
163 166 state <= ExecCMD1;
164 167 else
165 168 DRIVER_CMD.Exec <= '0';
166 169 end if;
167 170
168 171 when ExecCMD1=>
169 172 state <= Idle;
170 173 DRIVER_CMD.Exec <= '0';
171 174
172 175 when GoLine2=>
173 176 if SYNCH.DRVR_READY = '1' then
174 177 DRIVER_CMD.Exec <= '1';
175 178 DRIVER_CMD.Duration <= Duration_4ms;
176 179 DRIVER_CMD.CMD_Data <= '0';
177 180 DRIVER_CMD.Word <= X"C0";
178 181 state <= GoLine2_0;
179 182 else
180 183 DRIVER_CMD.Exec <= '0';
181 184 end if;
182 185 when GoLine2_0=>
183 186 state <= Refresh;
184 187 DRIVER_CMD.Exec <= '0';
185 188 when ReturnHome=>
186 189 if SYNCH.DRVR_READY = '1' then
187 190 DRIVER_CMD.Exec <= '1';
188 191 DRIVER_CMD.Duration <= Duration_4ms;
189 192 DRIVER_CMD.CMD_Data <= '0';
190 193 DRIVER_CMD.Word <= RetHome;
191 194 state <= Idle;
192 195 else
193 196 DRIVER_CMD.Exec <= '0';
194 197 end if;
195 198 end case;
196 199 end if;
197 200 end process;
198 201
199 202
200 203 end ar_LCD_16x2_ENGINE;
201 204
202 205
203 206
204 207
205 208
206 209
207 210
208 211
209 212
210 213
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@@ -1,156 +1,159
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24 use IEEE.NUMERIC_STD.all;
22 25 library lpp;
23 26 use lpp.amba_lcd_16x2_ctrlr.all;
24 27
25 28 entity LCD_2x16_DRIVER is
26 29 generic(
27 30 OSC_Freq_MHz : integer:=60;
28 31 Refresh_RateHz : integer:=5
29 32 );
30 33 Port ( clk : in STD_LOGIC;
31 34 reset : in STD_LOGIC;
32 35 FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
33 36 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
34 37 LCD_RS : out STD_LOGIC;
35 38 LCD_RW : out STD_LOGIC;
36 39 LCD_E : out STD_LOGIC;
37 40 LCD_RET : out STD_LOGIC;
38 41 LCD_CS1 : out STD_LOGIC;
39 42 LCD_CS2 : out STD_LOGIC;
40 43 STATEOUT: out std_logic_vector(3 downto 0);
41 44 refreshPulse : out std_logic
42 45 );
43 46 end LCD_2x16_DRIVER;
44 47
45 48 architecture Behavioral of LCD_2x16_DRIVER is
46 49
47 50 type stateT is(Rst,Configure,IDLE,RefreshScreen);
48 51 signal state : stateT;
49 52
50 53 signal ShortTimePulse : std_logic;
51 54 signal MidleTimePulse : std_logic;
52 55 signal Refresh_RatePulse : std_logic;
53 56 signal Start : STD_LOGIC;
54 57
55 58 signal CFGM_LCD_RS : std_logic;
56 59 signal CFGM_LCD_RW : std_logic;
57 60 signal CFGM_LCD_E : std_logic;
58 61 signal CFGM_LCD_DATA : std_logic_vector(7 downto 0);
59 62 signal CFGM_Enable : std_logic;
60 63 signal CFGM_completed : std_logic;
61 64
62 65
63 66 signal FRMW_LCD_RS : std_logic;
64 67 signal FRMW_LCD_RW : std_logic;
65 68 signal FRMW_LCD_E : std_logic;
66 69 signal FRMW_LCD_DATA : std_logic_vector(7 downto 0);
67 70 signal FRMW_Enable : std_logic;
68 71 signal FRMW_completed : std_logic;
69 72
70 73 begin
71 74
72 75
73 76 Counter : LCD_Counter
74 77 generic map(OSC_Freq_MHz,Refresh_RateHz)
75 78 port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start);
76 79
77 80 ConfigModule : Config_Module
78 81 port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse);
79 82
80 83
81 84 FrameWriter : FRAME_WRITER
82 85 port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse);
83 86
84 87
85 88 STATEOUT(0) <= '1' when state = Rst else '0';
86 89 STATEOUT(1) <= '1' when state = Configure else '0';
87 90 STATEOUT(2) <= '1' when state = IDLE else '0';
88 91 STATEOUT(3) <= '1' when state = RefreshScreen else '0';
89 92
90 93
91 94
92 95 refreshPulse <= Refresh_RatePulse;
93 96
94 97 Start <= '1';
95 98
96 99 process(reset,clk)
97 100 begin
98 101 if reset = '0' then
99 102 LCD_data <= (others=>'0');
100 103 LCD_RS <= '0';
101 104 LCD_RW <= '0';
102 105 LCD_RET <= '0';
103 106 LCD_CS1 <= '0';
104 107 LCD_CS2 <= '0';
105 108 LCD_E <= '0';
106 109 state <= Rst;
107 110 CFGM_Enable <= '0';
108 111 FRMW_Enable <= '0';
109 112 elsif clk'event and clk ='1' then
110 113 case state is
111 114 when Rst =>
112 115 LCD_data <= (others=>'0');
113 116 LCD_RS <= '0';
114 117 LCD_RW <= '0';
115 118 LCD_E <= '0';
116 119 CFGM_Enable <= '1';
117 120 FRMW_Enable <= '0';
118 121 if Refresh_RatePulse = '1' then
119 122 state <= Configure;
120 123 end if;
121 124 when Configure =>
122 125 LCD_data <= CFGM_LCD_data;
123 126 LCD_RS <= CFGM_LCD_RS;
124 127 LCD_RW <= CFGM_LCD_RW;
125 128 LCD_E <= CFGM_LCD_E;
126 129 CFGM_Enable <= '0';
127 130 if CFGM_completed = '1' then
128 131 state <= IDLE;
129 132 end if;
130 133 when IDLE =>
131 134 if Refresh_RatePulse = '1' then
132 135 state <= RefreshScreen;
133 136 FRMW_Enable <= '1';
134 137 end if;
135 138 LCD_RS <= '0';
136 139 LCD_RW <= '0';
137 140 LCD_E <= '0';
138 141 LCD_data <= (others=>'0');
139 142 when RefreshScreen =>
140 143 LCD_data <= FRMW_LCD_data;
141 144 LCD_RS <= FRMW_LCD_RS;
142 145 LCD_RW <= FRMW_LCD_RW;
143 146 LCD_E <= FRMW_LCD_E;
144 147 FRMW_Enable <= '0';
145 148 if FRMW_completed = '1' then
146 149 state <= IDLE;
147 150 end if;
148 151 end case;
149 152 end if;
150 153 end process;
151 154 end Behavioral;
152 155
153 156
154 157
155 158
156 159
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@@ -1,72 +1,75
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24 use IEEE.NUMERIC_STD.ALL;
22 25 library lpp;
23 26 use lpp.amba_lcd_16x2_ctrlr.all;
24 27
25 28 entity LCD_CLK_GENERATOR is
26 29 generic(OSC_freqKHz : integer := 50000);
27 30 Port ( clk : in STD_LOGIC;
28 31 reset : in STD_LOGIC;
29 32 clk_1us : out STD_LOGIC);
30 33 end LCD_CLK_GENERATOR;
31 34
32 35 architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is
33 36
34 37 Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1;
35 38
36 39
37 40 signal cpt1 : integer;
38 41
39 42 signal clk_1us_int : std_logic := '0';
40 43
41 44
42 45 begin
43 46
44 47 clk_1us <= clk_1us_int;
45 48
46 49
47 50 process(reset,clk)
48 51 begin
49 52 if reset = '0' then
50 53 cpt1 <= 0;
51 54 clk_1us_int <= '0';
52 55 elsif clk'event and clk = '1' then
53 56 if cpt1 = clk_1usTRIGER then
54 57 clk_1us_int <= not clk_1us_int;
55 58 cpt1 <= 0;
56 59 else
57 60 cpt1 <= cpt1 + 1;
58 61 end if;
59 62 end if;
60 63 end process;
61 64
62 65
63 66 end ar_LCD_CLK_GENERATOR;
64 67
65 68
66 69
67 70
68 71
69 72
70 73
71 74
72 75
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@@ -1,105 +1,107
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.STD_LOGIC_1164.ALL;
22 24
23 25 library lpp;
24 26 use lpp.amba_lcd_16x2_ctrlr.all;
25 27 use lpp.LCD_16x2_CFG.all;
26 28
27 29
28 30 entity AMBA_LCD_16x2_DRIVER is
29 31 Port ( reset : in STD_LOGIC;
30 32 clk : in STD_LOGIC;
31 33 Bp0 : in STD_LOGIC;
32 34 Bp1 : in STD_LOGIC;
33 35 Bp2 : in STD_LOGIC;
34 36 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
35 37 LCD_RS : out STD_LOGIC;
36 38 LCD_RW : out STD_LOGIC;
37 39 LCD_E : out STD_LOGIC;
38 40 LCD_RET : out STD_LOGIC;
39 41 LCD_CS1 : out STD_LOGIC;
40 42 LCD_CS2 : out STD_LOGIC;
41 43 SF_CE0 : out std_logic
42 44 );
43 45 end AMBA_LCD_16x2_DRIVER;
44 46
45 47 architecture Behavioral of AMBA_LCD_16x2_DRIVER is
46 48
47 49 signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0);
48 50 signal CMD : std_logic_vector(10 downto 0);
49 51 signal Exec : std_logic;
50 52 signal Ready : std_logic;
51 53 signal rst : std_logic;
52 54 signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
53 55
54 56 begin
55 57
56 58 LCD_data <= LCD_CTRL.LCD_DATA;
57 59 LCD_RS <= LCD_CTRL.LCD_RS;
58 60 LCD_RW <= LCD_CTRL.LCD_RW;
59 61 LCD_E <= LCD_CTRL.LCD_E;
60 62
61 63
62 64 LCD_RET <= '0';
63 65 LCD_CS1 <= '0';
64 66 LCD_CS2 <= '0';
65 67
66 68 SF_CE0 <= '1';
67 69
68 70
69 71
70 72
71 73 Driver0 : LCD_16x2_ENGINE
72 74 generic map(50000)
73 75 Port map(clk,reset,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
74 76
75 77 FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else
76 78 X"42" when Bp1 = '1' else
77 79 X"43" when Bp2 = '1' else
78 80 X"44";
79 81
80 82 FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else
81 83 X"47" when Bp1 = '1' else
82 84 X"48" when Bp2 = '1' else
83 85 X"49";
84 86
85 87
86 88 CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else
87 89 Duration_100us & CursorOFF;
88 90
89 91
90 92 Exec <= Bp1;
91 93
92 94 FramBUFF(2*8+7 downto 2*8) <= X"23";
93 95 FramBUFF(3*8+7 downto 3*8) <= X"66";
94 96 FramBUFF(4*8+7 downto 4*8) <= X"67";
95 97 FramBUFF(5*8+7 downto 5*8) <= X"68";
96 98 FramBUFF(17*8+7 downto 17*8) <= X"69";
97 99 --FramBUFF(16*2*8-1 downto 16) <= (others => '0');
98 100
99 101 end Behavioral;
100 102
101 103
102 104
103 105
104 106
105 107
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@@ -1,170 +1,173
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 library grlib;
22 25 use grlib.amba.all;
23 26 use grlib.stdlib.all;
24 27 use grlib.devices.all;
25 28
26 29
27 30 package amba_lcd_16x2_ctrlr is
28 31
29 32 constant lcd_space_size : integer := 80;
30 33
31 34 type FRM_Buff_Space is array(lcd_space_size-1 downto 0) of std_logic_vector(7 downto 0);
32 35
33 36
34 37 type LCD_DRVR_CTRL_BUSS is
35 38 record
36 39 LCD_RW : std_logic;
37 40 LCD_RS : std_logic;
38 41 LCD_E : std_logic;
39 42 LCD_DATA : std_logic_vector(7 downto 0);
40 43 end record;
41 44
42 45 type LCD_DRVR_SYNCH_BUSS is
43 46 record
44 47 DRVR_READY : std_logic;
45 48 LCD_INITIALISED : std_logic;
46 49 end record;
47 50
48 51
49 52 type LCD_DRVR_CMD_BUSS is
50 53 record
51 54 Word : std_logic_vector(7 downto 0);
52 55 CMD_Data : std_logic; --CMD = '0' and data = '1'
53 56 Exec : std_logic;
54 57 Duration : std_logic_vector(1 downto 0);
55 58 end record;
56 59 type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0);
57 60
58 61
59 62
60 63 component LCD_16x2_DRIVER is
61 64 generic(
62 65 OSC_Freq_MHz : integer:=60
63 66 );
64 67 Port ( reset : in STD_LOGIC;
65 68 clk : in STD_LOGIC;
66 69 LCD_CTRL : out LCD_DRVR_CTRL_BUSS;
67 70 SYNCH : out LCD_DRVR_SYNCH_BUSS;
68 71 DRIVER_CMD : in LCD_DRVR_CMD_BUSS
69 72 );
70 73 end component;
71 74
72 75
73 76
74 77 component amba_lcd_16x2_driver is
75 78 Port ( reset : in STD_LOGIC;
76 79 clk : in STD_LOGIC;
77 80 Bp0 : in STD_LOGIC;
78 81 Bp1 : in STD_LOGIC;
79 82 Bp2 : in STD_LOGIC;
80 83 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
81 84 LCD_RS : out STD_LOGIC;
82 85 LCD_RW : out STD_LOGIC;
83 86 LCD_E : out STD_LOGIC;
84 87 LCD_RET : out STD_LOGIC;
85 88 LCD_CS1 : out STD_LOGIC;
86 89 LCD_CS2 : out STD_LOGIC;
87 90 SF_CE0 : out std_logic
88 91 );
89 92 end component;
90 93
91 94
92 95
93 96 component FRAME_CLK_GEN is
94 97 generic(OSC_freqKHz : integer := 50000);
95 98 Port ( clk : in STD_LOGIC;
96 99 reset : in STD_LOGIC;
97 100 FRAME_CLK : out STD_LOGIC);
98 101 end component;
99 102
100 103
101 104
102 105 component LCD_2x16_DRIVER is
103 106 generic(
104 107 OSC_Freq_MHz : integer:=60;
105 108 Refresh_RateHz : integer:=5
106 109 );
107 110 Port ( clk : in STD_LOGIC;
108 111 reset : in STD_LOGIC;
109 112 FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
110 113 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
111 114 LCD_RS : out STD_LOGIC;
112 115 LCD_RW : out STD_LOGIC;
113 116 LCD_E : out STD_LOGIC;
114 117 LCD_RET : out STD_LOGIC;
115 118 LCD_CS1 : out STD_LOGIC;
116 119 LCD_CS2 : out STD_LOGIC;
117 120 STATEOUT: out std_logic_vector(3 downto 0);
118 121 refreshPulse : out std_logic
119 122 );
120 123 end component;
121 124
122 125
123 126 component LCD_CLK_GENERATOR is
124 127 generic(OSC_freqKHz : integer := 50000);
125 128 Port ( clk : in STD_LOGIC;
126 129 reset : in STD_LOGIC;
127 130 clk_1us : out STD_LOGIC);
128 131 end component;
129 132
130 133 component LCD_16x2_ENGINE is
131 134 generic(OSC_freqKHz : integer := 50000);
132 135 Port ( clk : in STD_LOGIC;
133 136 reset : in STD_LOGIC;
134 137 DATA : in FRM_Buff_Space;
135 138 CMD : in std_logic_vector(10 downto 0);
136 139 Exec : in std_logic;
137 140 Ready : out std_logic;
138 141 LCD_CTRL : out LCD_DRVR_CTRL_BUSS
139 142 );
140 143 end component;
141 144
142 145
143 146
144 147 component apb_lcd_ctrlr is
145 148 generic (
146 149 pindex : integer := 0;
147 150 paddr : integer := 0;
148 151 pmask : integer := 16#fff#;
149 152 pirq : integer := 0;
150 153 abits : integer := 8);
151 154 port (
152 155 rst : in std_ulogic;
153 156 clk : in std_ulogic;
154 157 apbi : in apb_slv_in_type;
155 158 apbo : out apb_slv_out_type;
156 159 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
157 160 LCD_RS : out STD_LOGIC;
158 161 LCD_RW : out STD_LOGIC;
159 162 LCD_E : out STD_LOGIC;
160 163 LCD_RET : out STD_LOGIC;
161 164 LCD_CS1 : out STD_LOGIC;
162 165 LCD_CS2 : out STD_LOGIC;
163 166 SF_CE0 : out std_logic
164 167 );
165 168 end component;
166 169
167 170
168 171
169 172
170 173 end;
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@@ -1,164 +1,167
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 --------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24 use ieee.numeric_std.all;
22 25 library grlib;
23 26 use grlib.amba.all;
24 27 use grlib.stdlib.all;
25 28 use grlib.devices.all;
26 29 library lpp;
27 30 use lpp.amba_lcd_16x2_ctrlr.all;
28 31 use lpp.LCD_16x2_CFG.all;
29 32 use lpp.lpp_amba.all;
30 33 use lpp.apb_devices_list.all;
31 34
32 35 entity apb_lcd_ctrlr is
33 36 generic (
34 37 pindex : integer := 0;
35 38 paddr : integer := 0;
36 39 pmask : integer := 16#fff#;
37 40 pirq : integer := 0;
38 41 abits : integer := 8);
39 42 port (
40 43 rst : in std_ulogic;
41 44 clk : in std_ulogic;
42 45 apbi : in apb_slv_in_type;
43 46 apbo : out apb_slv_out_type;
44 47 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
45 48 LCD_RS : out STD_LOGIC;
46 49 LCD_RW : out STD_LOGIC;
47 50 LCD_E : out STD_LOGIC;
48 51 LCD_RET : out STD_LOGIC;
49 52 LCD_CS1 : out STD_LOGIC;
50 53 LCD_CS2 : out STD_LOGIC;
51 54 SF_CE0 : out std_logic
52 55 );
53 56 end apb_lcd_ctrlr;
54 57
55 58 architecture Behavioral of apb_lcd_ctrlr is
56 59
57 60 signal FramBUFF : FRM_Buff_Space;
58 61 signal CMD : std_logic_vector(10 downto 0);
59 62 signal Exec : std_logic;
60 63 signal Ready : std_logic;
61 64 signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
62 65
63 66
64 67
65 68 constant REVISION : integer := 1;
66 69
67 70 constant pconfig : apb_config_type := (
68 71 0 => ahb_device_reg (VENDOR_LPP, LPP_LCD_CTRLR, 0, REVISION, 0),
69 72 1 => apb_iobar(paddr, pmask));
70 73
71 74
72 75 --type FRM_Buff_El is std_logic_vector(31 downto 0);
73 76 type FRM_Buff_Reg is array(lcd_space_size-1 downto 0) of std_logic_vector(31 downto 0);
74 77
75 78
76 79 type LCD_ctrlr_Reg is record
77 80 CTRL_Reg : std_logic_vector(31 downto 0);
78 81 FRAME_BUFF : FRM_Buff_Reg;
79 82 end record;
80 83
81 84 signal r : LCD_ctrlr_Reg;
82 85
83 86 signal Rdata : std_logic_vector(31 downto 0);
84 87
85 88 begin
86 89
87 90 LCD_data <= LCD_CTRL.LCD_DATA;
88 91 LCD_RS <= LCD_CTRL.LCD_RS;
89 92 LCD_RW <= LCD_CTRL.LCD_RW;
90 93 LCD_E <= LCD_CTRL.LCD_E;
91 94
92 95
93 96 LCD_RET <= '0';
94 97 LCD_CS1 <= '0';
95 98 LCD_CS2 <= '0';
96 99
97 100 SF_CE0 <= '1';
98 101
99 102 CMD(7 downto 0) <= r.CTRL_Reg(7 downto 0); --CMD value
100 103 CMD(9 downto 8) <= r.CTRL_Reg(9 downto 8); --CMD tempo value
101 104
102 105 r.CTRL_Reg(10) <= Ready;
103 106
104 107 Driver0 : LCD_16x2_ENGINE
105 108 generic map(50000)
106 109 Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
107 110
108 111 FRM_BF : for i in 0 to lcd_space_size-1 generate
109 112 FramBUFF(i) <= r.FRAME_BUFF(i)(7 downto 0);
110 113 end generate;
111 114
112 115
113 116 process(rst,clk)
114 117 begin
115 118 if rst = '0' then
116 119 r.CTRL_Reg(9 downto 0) <= (others => '0');
117 120 Exec <= '0';
118 121 elsif clk'event and clk = '1' then
119 122
120 123 --APB Write OP
121 124 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
122 125 case apbi.paddr(7 downto 2) is
123 126 when "000000" =>
124 127 r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0);
125 128 Exec <= '1';
126 129 when others =>
127 130 writeC: for i in 1 to lcd_space_size loop
128 131 if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
129 132 r.FRAME_BUFF(i-1) <= apbi.pwdata;
130 133 end if;
131 134 Exec <= '0';
132 135 end loop;
133 136 end case;
134 137 else
135 138 Exec <= '0';
136 139 end if;
137 140
138 141 --APB READ OP
139 142 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
140 143 case apbi.paddr(7 downto 2) is
141 144 when "000000" =>
142 145 Rdata <= r.CTRL_Reg;
143 146 when others =>
144 147 readC: for i in 1 to lcd_space_size loop
145 148 if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
146 149 Rdata(7 downto 0) <= r.FRAME_BUFF(i-1)(7 downto 0);
147 150 end if;
148 151 end loop;
149 152 end case;
150 153 end if;
151 154
152 155 end if;
153 156 apbo.pconfig <= pconfig;
154 157 end process;
155 158
156 159 apbo.prdata <= Rdata when apbi.penable = '1' ;
157 160
158 161 end Behavioral;
159 162
160 163
161 164
162 165
163 166
164 167
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@@ -1,209 +1,212
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 use ieee.numeric_std.all;
22 25 library grlib;
23 26 use grlib.amba.all;
24 27 use grlib.stdlib.all;
25 28 use grlib.devices.all;
26 29 library lpp;
27 30 use lpp.iir_filter.all;
28 31 use lpp.general_purpose.all;
29 32 use lpp.lpp_amba.all;
30 33 use lpp.apb_devices_list.all;
31 34
32 35 entity APB_IIR_CEL is
33 36 generic (
34 37 pindex : integer := 0;
35 38 paddr : integer := 0;
36 39 pmask : integer := 16#fff#;
37 40 pirq : integer := 0;
38 41 abits : integer := 8;
39 42 Sample_SZ : integer := 16;
40 43 ChanelsCount : integer := 1;
41 44 Coef_SZ : integer := 9;
42 45 CoefCntPerCel: integer := 3;
43 46 Cels_count : integer := 5;
44 47 virgPos : integer := 3;
45 48 Mem_use : integer := use_RAM
46 49 );
47 50 port (
48 51 rst : in std_logic;
49 52 clk : in std_logic;
50 53 apbi : in apb_slv_in_type;
51 54 apbo : out apb_slv_out_type;
52 55 sample_clk : in std_logic;
53 56 sample_clk_out : out std_logic;
54 57 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
55 58 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
56 59 );
57 60 end;
58 61
59 62
60 63 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
61 64
62 65 constant REVISION : integer := 1;
63 66
64 67 constant pconfig : apb_config_type := (
65 68 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
66 69 1 => apb_iobar(paddr, pmask));
67 70
68 71
69 72
70 73 type FILTERreg is record
71 74 regin : in_IIR_CEL_reg;
72 75 regout : out_IIR_CEL_reg;
73 76 end record;
74 77
75 78 signal Rdata : std_logic_vector(31 downto 0);
76 79 signal r : FILTERreg;
77 80 signal filter_reset : std_logic:='0';
78 81 signal smp_cnt : integer :=0;
79 82 signal sample_clk_out_R : std_logic;
80 83
81 84
82 85 type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
83 86 type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT;
84 87
85 88 type CoefsRegT is record
86 89 numCoefs : CoefTblT;
87 90 denCoefs : CoefTblT;
88 91 end record;
89 92
90 93 signal CoefsReg : CoefsRegT;
91 94
92 95 begin
93 96
94 97 filter_reset <= rst and r.regin.config(0);
95 98 sample_clk_out <= sample_clk_out_R;
96 99
97 100 filter : IIR_CEL_FILTER
98 101 generic map(Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
99 102 port map(
100 103 reset => filter_reset,
101 104 clk => clk,
102 105 sample_clk => sample_clk,
103 106 regs_in => r.regin,
104 107 regs_out => r.regout,
105 108 sample_in => sample_in,
106 109 sample_out => sample_out
107 110 );
108 111
109 112 process(rst,sample_clk)
110 113 begin
111 114 if rst = '0' then
112 115 smp_cnt <= 0;
113 116 sample_clk_out_R <= '0';
114 117 elsif sample_clk'event and sample_clk = '1' then
115 118 if smp_cnt = 1 then
116 119 smp_cnt <= 0;
117 120 sample_clk_out_R <= not sample_clk_out_R;
118 121 else
119 122 smp_cnt <= smp_cnt +1;
120 123 end if;
121 124 end if;
122 125 end process;
123 126
124 127
125 128 process(rst,clk)
126 129 begin
127 130 if rst = '0' then
128 131 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
129 132
130 133 elsif clk'event and clk = '1' then
131 134
132 135
133 136 --APB Write OP
134 137 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
135 138 case apbi.paddr(7 downto 2) is
136 139 when "000000" =>
137 140 r.regin.config(0) <= apbi.pwdata(0);
138 141 when "000001" =>
139 142 r.regin.virgPos <= apbi.pwdata(4 downto 0);
140 143 when others =>
141 144 for i in 0 to Cels_count-1 loop
142 145 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
143 146 case apbi.paddr(4 downto 2) is
144 147 when "000" =>
145 148 CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
146 149 when "001" =>
147 150 CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
148 151 when "010" =>
149 152 CoefsReg.numCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0));
150 153 when "011" =>
151 154 CoefsReg.denCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
152 155 when "100" =>
153 156 CoefsReg.denCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
154 157 when "101" =>
155 158 CoefsReg.denCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0));
156 159 when others =>
157 160 end case;
158 161 end if;
159 162 end loop;
160 163 end case;
161 164 end if;
162 165
163 166 --APB READ OP
164 167 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
165 168 case apbi.paddr(7 downto 2) is
166 169 when "000000" =>
167 170
168 171 when "000001" =>
169 172 Rdata(4 downto 0) <= r.regin.virgPos;
170 173 when others =>
171 174 for i in 0 to Cels_count-1 loop
172 175 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
173 176 case apbi.paddr(4 downto 2) is
174 177 when "000" =>
175 178 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(0));
176 179 when "001" =>
177 180 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(1));
178 181 when "010" =>
179 182 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(2));
180 183 when "011" =>
181 184 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(0));
182 185 when "100" =>
183 186 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(1));
184 187 when "101" =>
185 188 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(2));
186 189 when others =>
187 190 end case;
188 191 end if;
189 192 end loop;
190 193 end case;
191 194 end if;
192 195
193 196 end if;
194 197 apbo.pconfig <= pconfig;
195 198 end process;
196 199
197 200 apbo.prdata <= Rdata when apbi.penable = '1' ;
198 201
199 202 -- pragma translate_off
200 203 bootmsg : report_version
201 204 generic map ("apbuart" & tost(pindex) &
202 205 ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
203 206 ", irq " & tost(pirq));
204 207 -- pragma translate_on
205 208
206 209
207 210
208 211 end ar_APB_IIR_CEL;
209 212
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@@ -1,104 +1,107
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.iir_filter.all;
24 27 use lpp.FILTERcfg.all;
25 28 use lpp.general_purpose.all;
26 29 --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
27 30 --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
28 31 --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
29 32
30 33 entity FILTER is
31 34 generic(Smpl_SZ : integer := 16;
32 35 ChanelsCNT : integer := 3
33 36 );
34 37 port(
35 38
36 39 reset : in std_logic;
37 40 clk : in std_logic;
38 41 sample_clk : in std_logic;
39 42 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
40 43 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
41 44 );
42 45 end entity;
43 46
44 47
45 48
46 49
47 50
48 51 architecture ar_FILTER of FILTER is
49 52
50 53
51 54
52 55
53 56 signal ALU_ctrl : std_logic_vector(3 downto 0);
54 57 signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
55 58 signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
56 59 signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
57 60
58 61 begin
59 62
60 63 --==============================================================
61 64 --=========================A L U================================
62 65 --==============================================================
63 66 ALU1 : entity ALU
64 67 generic map(
65 68 Arith_en => 1,
66 69 Logic_en => 0,
67 70 Input_SZ_1 => Smpl_SZ,
68 71 Input_SZ_2 => Coef_SZ
69 72
70 73 )
71 74 port map(
72 75 clk => clk,
73 76 reset => reset,
74 77 ctrl => ALU_ctrl,
75 78 OP1 => Sample,
76 79 OP2 => Coef,
77 80 RES => ALU_OUT
78 81 );
79 82 --==============================================================
80 83
81 84 --==============================================================
82 85 --===============F I L T E R C O N T R O L E R================
83 86 --==============================================================
84 87 filterctrlr1 : FilterCTRLR
85 88 port map(
86 89 reset => reset,
87 90 clk => clk,
88 91 sample_clk => sample_clk,
89 92 ALU_Ctrl => ALU_ctrl,
90 93 sample_in => sample_Tbl,
91 94 coef => Coef,
92 95 sample => Sample
93 96 );
94 97 --==============================================================
95 98
96 99 chanelCut : for i in 0 to ChanelsCNT-1 generate
97 100 sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ);
98 101 end generate;
99 102
100 103
101 104
102 105
103 106 end ar_FILTER;
104 107
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@@ -1,225 +1,228
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.iir_filter.all;
24 27 use lpp.FILTERcfg.all;
25 28 use lpp.general_purpose.all;
26 29
27 30 --TODO am�liorer la flexibilit� de la config de la RAM.
28 31
29 32 entity FILTER_RAM_CTRLR is
30 33 port(
31 34 reset : in std_logic;
32 35 clk : in std_logic;
33 36 run : in std_logic;
34 37 GO_0 : in std_logic;
35 38 B_A : in std_logic;
36 39 writeForce : in std_logic;
37 40 next_blk : in std_logic;
38 41 sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
39 42 sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
40 43 );
41 44 end FILTER_RAM_CTRLR;
42 45
43 46
44 47 architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is
45 48
46 49 signal WD : std_logic_vector(35 downto 0);
47 50 signal WD_D : std_logic_vector(35 downto 0);
48 51 signal RD : std_logic_vector(35 downto 0);
49 52 signal WEN, REN : std_logic;
50 53 signal WADDR_back : std_logic_vector(7 downto 0);
51 54 signal WADDR_back_D: std_logic_vector(7 downto 0);
52 55 signal RADDR : std_logic_vector(7 downto 0);
53 56 signal WADDR : std_logic_vector(7 downto 0);
54 57 signal WADDR_D : std_logic_vector(7 downto 0);
55 58 signal run_D : std_logic;
56 59 signal run_D_inv : std_logic;
57 60 signal run_inv : std_logic;
58 61 signal next_blk_D : std_logic;
59 62 signal MUX2_inst1_sel : std_logic;
60 63
61 64
62 65 begin
63 66
64 67 sample_out <= RD(Smpl_SZ-1 downto 0);
65 68
66 69 MUX2_inst1_sel <= run_D and not next_blk;
67 70 run_D_inv <= not run_D;
68 71 run_inv <= not run;
69 72 WEN <= run_D_inv and not writeForce;
70 73 REN <= run_inv ;--and not next_blk;
71 74
72 75
73 76 --==============================================================
74 77 --=========================R A M================================
75 78 --==============================================================
76 79 memRAM : if Mem_use = use_RAM generate
77 80 RAMblk :RAM
78 81 port map(
79 82 WD => WD_D,
80 83 RD => RD,
81 84 WEN => WEN,
82 85 REN => REN,
83 86 WADDR => WADDR,
84 87 RADDR => RADDR,
85 88 RWCLK => clk,
86 89 RESET => reset
87 90 ) ;
88 91 end generate;
89 92
90 93 memCEL : if Mem_use = use_CEL generate
91 94 RAMblk :RAM_CEL
92 95 port map(
93 96 WD => WD_D,
94 97 RD => RD,
95 98 WEN => WEN,
96 99 REN => REN,
97 100 WADDR => WADDR,
98 101 RADDR => RADDR,
99 102 RWCLK => clk,
100 103 RESET => reset
101 104 ) ;
102 105 end generate;
103 106 --==============================================================
104 107 --==============================================================
105 108
106 109
107 110 ADDRcntr_inst : ADDRcntr
108 111 port map(
109 112 clk => clk,
110 113 reset => reset,
111 114 count => run,
112 115 clr => GO_0,
113 116 Q => RADDR
114 117 );
115 118
116 119
117 120
118 121 MUX2_inst1 :MUX2
119 122 generic map(Input_SZ => Smpl_SZ)
120 123 port map(
121 124 sel => MUX2_inst1_sel,
122 125 IN1 => sample_in,
123 126 IN2 => RD(Smpl_SZ-1 downto 0),
124 127 RES => WD(Smpl_SZ-1 downto 0)
125 128 );
126 129
127 130
128 131 MUX2_inst2 :MUX2
129 132 generic map(Input_SZ => 8)
130 133 port map(
131 134 sel => next_blk_D,
132 135 IN1 => WADDR_D,
133 136 IN2 => WADDR_back_D,
134 137 RES => WADDR
135 138 );
136 139
137 140
138 141 next_blkRreg :REG
139 142 generic map(size => 1)
140 143 port map(
141 144 reset => reset,
142 145 clk => clk,
143 146 D(0) => next_blk,
144 147 Q(0) => next_blk_D
145 148 );
146 149
147 150 WADDR_backreg :REG
148 151 generic map(size => 8)
149 152 port map(
150 153 reset => reset,
151 154 clk => B_A,
152 155 D => RADDR,
153 156 Q => WADDR_back
154 157 );
155 158
156 159 WADDR_backreg2 :REG
157 160 generic map(size => 8)
158 161 port map(
159 162 reset => reset,
160 163 clk => B_A,
161 164 D => WADDR_back,
162 165 Q => WADDR_back_D
163 166 );
164 167
165 168 WDRreg :REG
166 169 generic map(size => Smpl_SZ)
167 170 port map(
168 171 reset => reset,
169 172 clk => clk,
170 173 D => WD(Smpl_SZ-1 downto 0),
171 174 Q => WD_D(Smpl_SZ-1 downto 0)
172 175 );
173 176
174 177 RunRreg :REG
175 178 generic map(size => 1)
176 179 port map(
177 180 reset => reset,
178 181 clk => clk,
179 182 D(0) => run,
180 183 Q(0) => run_D
181 184 );
182 185
183 186
184 187
185 188 ADDRreg :REG
186 189 generic map(size => 8)
187 190 port map(
188 191 reset => reset,
189 192 clk => clk,
190 193 D => RADDR,
191 194 Q => WADDR_D
192 195 );
193 196
194 197
195 198
196 199 end ar_FILTER_RAM_CTRLR;
197 200
198 201
199 202
200 203
201 204
202 205
203 206
204 207
205 208
206 209
207 210
208 211
209 212
210 213
211 214
212 215
213 216
214 217
215 218
216 219
217 220
218 221
219 222
220 223
221 224
222 225
223 226
224 227
225 228
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@@ -1,193 +1,196
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25
23 26
24 27 package FILTERcfg is
25 28
26 29
27 30
28 31
29 32 --===========================================================|
30 33 --========F I L T E R C O N F I G V A L U E S=============|
31 34 --===========================================================|
32 35 --____________________________
33 36 --Bus Width and chanels number|
34 37 --____________________________|
35 38 constant ChanelsCNT : integer := 6;
36 39 constant Smpl_SZ : integer := 16;
37 40 constant Coef_SZ : integer := 9;
38 41 constant Scalefac_SZ: integer := 3;
39 42 constant Cels_count : integer := 5;
40 43
41 44 constant Mem_use : integer := 1;
42 45
43 46
44 47
45 48 --============================================================
46 49 -- create each initial values for each coefs ============
47 50 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
48 51 --============================================================
49 52 --constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ));
50 53 --constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
51 54 --constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
52 55 --constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
53 56 --constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
54 57 --constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
55 58 --constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
56 59 --
57 60 --constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
58 61 --constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
59 62 --constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ));
60 63 --constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
61 64 --constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ));
62 65 --
63 66 --
64 67 --constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
65 68 --constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ));
66 69 --constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
67 70 --
68 71 --constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
69 72 --constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ));
70 73 --constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
71 74 --
72 75 --constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
73 76 --constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ));
74 77 --constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
75 78 --
76 79 --constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
77 80 --constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ));
78 81 --constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
79 82 --
80 83 --constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
81 84 --constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ));
82 85 --constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
83 86 --
84 87 --constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
85 88 --constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
86 89 --constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
87 90 --
88 91 --constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
89 92 --constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
90 93 --constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
91 94 --
92 95 --
93 96 --constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
94 97 --constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ));
95 98 --constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ));
96 99 --
97 100 --constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
98 101 --constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ));
99 102 --constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
100 103 --
101 104 --constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
102 105 --constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ));
103 106 --constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ));
104 107 --
105 108 --constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
106 109 --constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ));
107 110 --constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ));
108 111 --
109 112 --constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
110 113 --constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ));
111 114 --constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ));
112 115 --
113 116 --constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
114 117 --constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
115 118 --constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
116 119 --constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
117 120 --constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
118 121 --constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
119 122 --
120 123 --
121 124 --constant celb0 : coef_celT := (b0_0,b0_1,b0_2);
122 125 --constant celb1 : coef_celT := (b1_0,b1_1,b1_2);
123 126 --constant celb2 : coef_celT := (b2_0,b2_1,b2_2);
124 127 --constant celb3 : coef_celT := (b3_0,b3_1,b3_2);
125 128 --constant celb4 : coef_celT := (b4_0,b4_1,b4_2);
126 129 --constant celb5 : coef_celT := (b5_0,b5_1,b5_2);
127 130 --constant celb6 : coef_celT := (b6_0,b6_1,b6_2);
128 131 --
129 132 --constant cela0 : coef_celT := (a0_0,a0_1,a0_2);
130 133 --constant cela1 : coef_celT := (a1_0,a1_1,a1_2);
131 134 --constant cela2 : coef_celT := (a2_0,a2_1,a2_2);
132 135 --constant cela3 : coef_celT := (a3_0,a3_1,a3_2);
133 136 --constant cela4 : coef_celT := (a4_0,a4_1,a4_2);
134 137 --constant cela5 : coef_celT := (a5_0,a5_1,a5_2);
135 138 --constant cela6 : coef_celT := (a6_0,a6_1,a6_2);
136 139 --
137 140 --
138 141 --
139 142 --constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4);
140 143 --constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4);
141 144 --constant virgPos : integer := 7;
142 145 --
143 146 --
144 147 --
145 148 --
146 149 --
147 150 --
148 151 --
149 152 --signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6);
150 153 --signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4);
151 154 --
152 155 --
153 156 --signal sample_Tbl : samplT;
154 157
155 158
156 159 end;
157 160
158 161
159 162
160 163
161 164
162 165
163 166
164 167
165 168
166 169
167 170
168 171
169 172
170 173
171 174
172 175
173 176
174 177
175 178
176 179
177 180
178 181
179 182
180 183
181 184
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183 186
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186 189
187 190
188 191
189 192
190 193
191 194
192 195
193 196
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@@ -1,262 +1,265
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.iir_filter.all;
24 27 use lpp.FILTERcfg.all;
25 28 use lpp.general_purpose.all;
26 29
27 30 --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
28 31
29 32 entity FilterCTRLR is
30 33 port(
31 34 reset : in std_logic;
32 35 clk : in std_logic;
33 36 sample_clk : in std_logic;
34 37 ALU_Ctrl : out std_logic_vector(3 downto 0);
35 38 sample_in : in samplT;
36 39 coef : out std_logic_vector(Coef_SZ-1 downto 0);
37 40 sample : out std_logic_vector(Smpl_SZ-1 downto 0)
38 41 );
39 42 end FilterCTRLR;
40 43
41 44
42 45 architecture ar_FilterCTRLR of FilterCTRLR is
43 46
44 47 constant NUMCoefsCnt : integer:= NumeratorCoefs'high;
45 48 constant DENCoefsCnt : integer:= DenominatorCoefs'high;
46 49
47 50 signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0;
48 51 signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0;
49 52
50 53 signal chanelCnt : integer range 0 to 15:=0;
51 54
52 55 signal WD : std_logic_vector(35 downto 0);
53 56 signal WD_D : std_logic_vector(35 downto 0);
54 57 signal RD : std_logic_vector(35 downto 0);
55 58 signal WEN, REN,WEN_D : std_logic;
56 59 signal WADDR_back : std_logic_vector(7 downto 0);
57 60 signal ADDR : std_logic_vector(7 downto 0);
58 61 signal ADDR_D : std_logic_vector(7 downto 0);
59 62 signal clk_inv : std_logic;
60 63
61 64 type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
62 65 signal in_Rotate_Buff : Rotate_BuffT;
63 66 signal out_Rotate_Buff : Rotate_BuffT;
64 67
65 68 signal sample_clk_old : std_logic;
66 69
67 70 type stateT is (waiting,computeNUM,computeDEN,NextChanel);
68 71 signal state : stateT;
69 72
70 73 begin
71 74 clk_inv <= not clk;
72 75
73 76 process(clk,reset)
74 77 begin
75 78 if reset = '0' then
76 79 state <= waiting;
77 80 WEN <= '1';
78 81 REN <= '1';
79 82 ADDR <= (others => '0');
80 83 WD <= (others => '0');
81 84 NcoefCnt <= 0;
82 85 DcoefCnt <= 0;
83 86 chanelCnt <= 0;
84 87 ALU_Ctrl <= clr_mac;
85 88 sample_clk_old <= '0';
86 89 coef <= (others => '0');
87 90 sample <= (others => '0');
88 91 rst:for i in 0 to ChanelsCNT-1 loop
89 92 in_Rotate_Buff(i) <= (others => '0');
90 93 end loop;
91 94 elsif clk'event and clk = '1' then
92 95
93 96 sample_clk_old <= sample_clk;
94 97
95 98 --=================================================================
96 99 --===============DATA processing===================================
97 100 --=================================================================
98 101 case state is
99 102 when waiting=>
100 103
101 104 if sample_clk_old = '0' and sample_clk = '1' then
102 105 ALU_Ctrl <= MAC_op;
103 106 sample <= in_Rotate_Buff(0);
104 107 coef <= std_logic_vector(NumeratorCoefs(0));
105 108 else
106 109 ALU_Ctrl <= clr_mac;
107 110 loadinput: for i in 0 to ChanelsCNT-1 loop
108 111 in_Rotate_Buff(i) <= sample_in(i);
109 112 end loop;
110 113 end if;
111 114
112 115 when computeNUM=>
113 116 ALU_Ctrl <= MAC_op;
114 117 sample <= RD(Smpl_SZ-1 downto 0);
115 118 coef <= std_logic_vector(NumeratorCoefs(NcoefCnt));
116 119
117 120 when computeDEN=>
118 121 ALU_Ctrl <= MAC_op;
119 122 sample <= RD(Smpl_SZ-1 downto 0);
120 123 coef <= std_logic_vector(DenominatorCoefs(DcoefCnt));
121 124
122 125 when NextChanel=>
123 126 rotate : for i in 0 to ChanelsCNT-2 loop
124 127 in_Rotate_Buff(i) <= in_Rotate_Buff(i+1);
125 128 end loop;
126 129 rotatetoo: if ChanelsCNT > 1 then
127 130 sample <= in_Rotate_Buff(1);
128 131 coef <= std_logic_vector(NumeratorCoefs(0));
129 132 end if;
130 133 end case;
131 134
132 135 --=================================================================
133 136 --===============RAM read write====================================
134 137 --=================================================================
135 138 case state is
136 139 when waiting=>
137 140 if sample_clk_old = '0' and sample_clk = '1' then
138 141 REN <= '0';
139 142 else
140 143 REN <= '1';
141 144 end if;
142 145 ADDR <= (others => '0');
143 146 WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0);
144 147 WEN <= '1';
145 148
146 149 when computeNUM=>
147 150 WD <= RD;
148 151 REN <= '0';
149 152 WEN <= '0';
150 153 ADDR <= std_logic_vector(unsigned(ADDR)+1);
151 154 when computeDEN=>
152 155 WD <= RD;
153 156 REN <= '0';
154 157 WEN <= '0';
155 158 ADDR <= std_logic_vector(unsigned(ADDR)+1);
156 159 when NextChanel=>
157 160 REN <= '1';
158 161 WEN <= '1';
159 162 end case;
160 163 --=================================================================
161 164
162 165
163 166 --=================================================================
164 167 --===============FSM Management====================================
165 168 --=================================================================
166 169 case state is
167 170 when waiting=>
168 171 if sample_clk_old = '0' and sample_clk = '1' then
169 172 state <= computeNUM;
170 173 end if;
171 174 DcoefCnt <= 0;
172 175 NcoefCnt <= 1;
173 176 chanelCnt<= 0;
174 177 when computeNUM=>
175 178 if NcoefCnt = NumCoefsCnt then
176 179 state <= computeDEN;
177 180 NcoefCnt <= 1;
178 181 else
179 182 NcoefCnt <= NcoefCnt+1;
180 183 end if;
181 184 when computeDEN=>
182 185 if DcoefCnt = DENCoefsCnt then
183 186 state <= NextChanel;
184 187 DcoefCnt <= 0;
185 188 else
186 189 DcoefCnt <= DcoefCnt+1;
187 190 end if;
188 191 when NextChanel=>
189 192 if chanelCnt = (ChanelsCNT-1) then
190 193 state <= waiting;
191 194 else
192 195 chanelCnt<= chanelCnt+1;
193 196 state <= computeNUM;
194 197 end if;
195 198 end case;
196 199 --=================================================================
197 200
198 201 end if;
199 202 end process;
200 203
201 204 ADDRreg : REG
202 205 generic map(size => 8)
203 206 port map(
204 207 reset => reset,
205 208 clk => clk,
206 209 D => ADDR,
207 210 Q => ADDR_D
208 211 );
209 212
210 213 WDreg :REG
211 214 generic map(size => 36)
212 215 port map(
213 216 reset => reset,
214 217 clk => clk,
215 218 D => WD,
216 219 Q => WD_D
217 220 );
218 221
219 222 WRreg :REG
220 223 generic map(size => 1)
221 224 port map(
222 225 reset => reset,
223 226 clk => clk,
224 227 D(0) => WEN,
225 228 Q(0) => WEN_D
226 229 );
227 230 --==============================================================
228 231 --=========================R A M================================
229 232 --==============================================================
230 233 memRAM : if Mem_use = use_RAM generate
231 234 RAMblk :RAM
232 235 port map(
233 236 WD => WD_D,
234 237 RD => RD,
235 238 WEN => WEN_D,
236 239 REN => REN,
237 240 WADDR => ADDR_D,
238 241 RADDR => ADDR,
239 242 RWCLK => clk_inv,
240 243 RESET => reset
241 244 ) ;
242 245 end generate;
243 246
244 247 memCEL : if Mem_use = use_CEL generate
245 248 RAMblk :RAM
246 249 port map(
247 250 WD => WD_D,
248 251 RD => RD,
249 252 WEN => WEN_D,
250 253 REN => REN,
251 254 WADDR => ADDR_D,
252 255 RADDR => ADDR,
253 256 RWCLK => clk_inv,
254 257 RESET => reset
255 258 ) ;
256 259 end generate;
257 260
258 261 --==============================================================
259 262
260 263
261 264
262 265 end ar_FilterCTRLR;
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@@ -1,327 +1,326
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 ------------------------------------------------------------------------------
20 -- This file is a part of the LPP VHDL IP LIBRARY
21 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
22 --
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
23 22
24 23 library IEEE;
25 24 use IEEE.numeric_std.all;
26 25 use IEEE.std_logic_1164.all;
27 26 library lpp;
28 27 use lpp.iir_filter.all;
29 28 use lpp.general_purpose.all;
30 29
31 30 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
32 31
33 32 entity IIR_CEL_CTRLR is
34 33 generic(Sample_SZ : integer := 16;
35 34 ChanelsCount : integer := 1;
36 35 Coef_SZ : integer := 9;
37 36 CoefCntPerCel: integer := 3;
38 37 Cels_count : integer := 5;
39 38 Mem_use : integer := use_RAM
40 39 );
41 40 port(
42 41 reset : in std_logic;
43 42 clk : in std_logic;
44 43 sample_clk : in std_logic;
45 44 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
46 45 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
47 46 virg_pos : in integer;
48 47 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
49 48 );
50 49 end IIR_CEL_CTRLR;
51 50
52 51
53 52
54 53
55 54 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
56 55
57 56 subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0);
58 57
59 58 signal smpl_clk_old : std_logic := '0';
60 59 signal WD_sel : std_logic := '0';
61 60 signal Read : std_logic := '0';
62 61 signal SVG_ADDR : std_logic := '0';
63 62 signal count : std_logic := '0';
64 63 signal Write : std_logic := '0';
65 64 signal WADDR_sel : std_logic := '0';
66 65 signal GO_0 : std_logic := '0';
67 66
68 67 signal RAM_sample_in : sampleVect;
69 68 signal RAM_sample_in_bk: sampleVect;
70 69 signal RAM_sample_out : sampleVect;
71 70 signal ALU_ctrl : std_logic_vector(3 downto 0);
72 71 signal ALU_sample_in : sampleVect;
73 72 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
74 73 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
75 74 signal curentCel : integer range 0 to Cels_count-1 := 0;
76 75 signal curentChan : integer range 0 to ChanelsCount-1 := 0;
77 76
78 77
79 78 type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect;
80 79
81 80 signal sample_in_BUFF : sampleBuffT;
82 81 signal sample_out_BUFF : sampleBuffT;
83 82
84 83 type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
85 84 type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT;
86 85
87 86 type CoefsRegT is record
88 87 numCoefs : CoefTblT;
89 88 denCoefs : CoefTblT;
90 89 end record;
91 90
92 91 signal CoefsReg : CoefsRegT;
93 92
94 93 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
95 94
96 95 signal IIR_CEL_STATE : fsmIIR_CEL_T;
97 96
98 97 begin
99 98
100 99
101 100 coefsConnectL0: for z in 0 to Cels_count-1 generate
102 101 coefsConnectL1: for y in 0 to CoefCntPerCel-1 generate
103 102 coefsConnectL2: for x in 0 to Coef_SZ-1 generate
104 103 CoefsReg.numCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
105 104 CoefsReg.denCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
106 105 end generate;
107 106 end generate;
108 107 end generate;
109 108
110 109
111 110 RAM_CTRLR2inst : RAM_CTRLR2
112 111 generic map(Sample_SZ,Mem_use)
113 112 port map(
114 113 reset => reset,
115 114 clk => clk,
116 115 WD_sel => WD_sel,
117 116 Read => Read,
118 117 WADDR_sel => WADDR_sel,
119 118 count => count,
120 119 SVG_ADDR => SVG_ADDR,
121 120 Write => Write,
122 121 GO_0 => GO_0,
123 122 sample_in => RAM_sample_in,
124 123 sample_out => RAM_sample_out
125 124 );
126 125
127 126
128 127
129 128 ALU_inst :ALU
130 129 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
131 130 port map(
132 131 clk => clk,
133 132 reset => reset,
134 133 ctrl => ALU_ctrl,
135 134 OP1 => ALU_sample_in,
136 135 OP2 => ALU_coef_in,
137 136 RES => ALU_out
138 137 );
139 138
140 139
141 140
142 141
143 142
144 143
145 144 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
146 145 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
147 146 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
148 147 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
149 148 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
150 149 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
151 150 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
152 151
153 152 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
154 153
155 154
156 155
157 156
158 157
159 158
160 159
161 160 process(clk,reset)
162 161 variable result : std_logic_vector(Sample_SZ-1 downto 0);
163 162
164 163 begin
165 164
166 165 if reset = '0' then
167 166
168 167 smpl_clk_old <= '0';
169 168 RAM_sample_in <= (others=> '0');
170 169 ALU_ctrl <= IDLE;
171 170 ALU_sample_in <= (others=> '0');
172 171 ALU_Coef_in <= (others=> '0');
173 172 RAM_sample_in_bk<= (others=> '0');
174 173 curentCel <= 0;
175 174 curentChan <= 0;
176 175 IIR_CEL_STATE <= waiting;
177 176 resetL0 : for i in 0 to ChanelsCount-1 loop
178 177 sample_in_BUFF(i) <= (others => '0');
179 178 sample_out_BUFF(i) <= (others => '0');
180 179 resetL1: for j in 0 to Sample_SZ-1 loop
181 180 sample_out(i,j) <= '0';
182 181 end loop;
183 182 end loop;
184 183
185 184 elsif clk'event and clk = '1' then
186 185
187 186 smpl_clk_old <= sample_clk;
188 187
189 188 case IIR_CEL_STATE is
190 189
191 190 when waiting =>
192 191 if sample_clk = '1' and smpl_clk_old = '0' then
193 192 IIR_CEL_STATE <= pipe1;
194 193 RAM_sample_in <= std_logic_vector(sample_in_BUFF(0));
195 194 ALU_sample_in <= std_logic_vector(sample_in_BUFF(0));
196 195
197 196 else
198 197 ALU_ctrl <= IDLE;
199 198 smplConnectL0: for i in 0 to ChanelsCount-1 loop
200 199 smplConnectL1: for j in 0 to Sample_SZ-1 loop
201 200 sample_in_BUFF(i)(j) <= sample_in(i,j);
202 201 sample_out(i,j) <= sample_out_BUFF(i)(j);
203 202 end loop;
204 203 end loop;
205 204 end if;
206 205 curentCel <= 0;
207 206 curentChan <= 0;
208 207
209 208 when pipe1 =>
210 209 IIR_CEL_STATE <= computeb1;
211 210 ALU_ctrl <= MAC_op;
212 211 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0));
213 212
214 213 when computeb1 =>
215 214
216 215 ALU_ctrl <= MAC_op;
217 216 ALU_sample_in <= RAM_sample_out;
218 217 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1));
219 218 IIR_CEL_STATE <= computeb2;
220 219 RAM_sample_in <= RAM_sample_in_bk;
221 220 when computeb2 =>
222 221 ALU_sample_in <= RAM_sample_out;
223 222 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2));
224 223 IIR_CEL_STATE <= computea1;
225 224
226 225
227 226 when computea1 =>
228 227 ALU_sample_in <= RAM_sample_out;
229 228 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1));
230 229 IIR_CEL_STATE <= computea2;
231 230
232 231
233 232 when computea2 =>
234 233 ALU_sample_in <= RAM_sample_out;
235 234 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2));
236 235 IIR_CEL_STATE <= next_cel;
237 236
238 237
239 238 when next_cel =>
240 239 ALU_ctrl <= clr_mac;
241 240 IIR_CEL_STATE <= pipe2;
242 241
243 242 when pipe2 =>
244 243 IIR_CEL_STATE <= pipe3;
245 244
246 245
247 246 when pipe3 =>
248 247
249 248 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
250 249
251 250 sample_out_BUFF(0) <= result;
252 251 RAM_sample_in_bk <= result;
253 252 RAM_sample_in <= result;
254 253 if curentCel = Cels_count-1 then
255 254 IIR_CEL_STATE <= next_chan;
256 255 curentCel <= 0;
257 256 else
258 257 curentCel <= curentCel + 1;
259 258 IIR_CEL_STATE <= pipe1;
260 259 ALU_sample_in <= result;
261 260 end if;
262 261 when next_chan =>
263 262
264 263 rotate : for i in 1 to ChanelsCount-1 loop
265 264 sample_in_BUFF(i-1) <= sample_in_BUFF(i);
266 265 sample_out_BUFF(i-1) <= sample_out_BUFF(i);
267 266 end loop;
268 267 sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0);
269 268 sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0);
270 269
271 270 if curentChan = (ChanelsCount-1) then
272 271 IIR_CEL_STATE <= waiting;
273 272 ALU_ctrl <= clr_mac;
274 273 elsif ChanelsCount>1 then
275 274 curentChan <= curentChan + 1;
276 275 IIR_CEL_STATE <= pipe1;
277 276 ALU_sample_in <= sample_in_BUFF(1);
278 277 RAM_sample_in <= sample_in_BUFF(1);
279 278 end if;
280 279 end case;
281 280
282 281 end if;
283 282 end process;
284 283
285 284
286 285
287 286
288 287
289 288
290 289 end ar_IIR_CEL_CTRLR;
291 290
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@@ -1,92 +1,95
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.iir_filter.all;
24 27 use lpp.general_purpose.all;
25 28
26 29 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
27 30
28 31 entity IIR_CEL_FILTER is
29 32 generic(Sample_SZ : integer := 16;
30 33 ChanelsCount : integer := 1;
31 34 Coef_SZ : integer := 9;
32 35 CoefCntPerCel: integer := 3;
33 36 Cels_count : integer := 5;
34 37 Mem_use : integer := use_RAM);
35 38 port(
36 39 reset : in std_logic;
37 40 clk : in std_logic;
38 41 sample_clk : in std_logic;
39 42 regs_in : in in_IIR_CEL_reg;
40 43 regs_out : in out_IIR_CEL_reg;
41 44 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
42 45 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
43 46 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
44 47
45 48 );
46 49 end IIR_CEL_FILTER;
47 50
48 51
49 52
50 53
51 54 architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
52 55
53 56 signal virg_pos : integer;
54 57 begin
55 58
56 59 virg_pos <= to_integer(unsigned(regs_in.virgPos));
57 60
58 61 CTRLR : IIR_CEL_CTRLR
59 62 generic map (Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
60 63 port map(
61 64 reset => reset,
62 65 clk => clk,
63 66 sample_clk => sample_clk,
64 67 sample_in => sample_in,
65 68 sample_out => sample_out,
66 69 virg_pos => virg_pos,
67 70 coefs => coefs
68 71 );
69 72
70 73
71 74
72 75
73 76
74 77 end ar_IIR_CEL_FILTER;
75 78
76 79
77 80
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79 82
80 83
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@@ -1,61 +1,64
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 use IEEE.numeric_std.all;
22 25
23 26 entity RAM is
24 27 port( WD : in std_logic_vector(35 downto 0); RD : out
25 28 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
26 29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
27 30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
28 31 ) ;
29 32 end RAM;
30 33
31 34
32 35 architecture DEF_ARCH of RAM is
33 36 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
34 37 signal RAMarray : RAMarrayT:=(others => X"000000000");
35 38 signal RD_int : std_logic_vector(35 downto 0);
36 39
37 40 begin
38 41
39 42 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
40 43
41 44
42 45 process(RWclk,reset)
43 46 begin
44 47 if reset = '0' then
45 48 RD <= (X"000000000");
46 49 rst:for i in 0 to 255 loop
47 50 RAMarray(i) <= (others => '0');
48 51 end loop;
49 52
50 53 elsif RWclk'event and RWclk = '1' then
51 54 if REN = '0' then
52 55 RD <= RD_int;
53 56 end if;
54 57
55 58 if WEN = '0' then
56 59 RAMarray(to_integer(unsigned(WADDR))) <= WD;
57 60 end if;
58 61
59 62 end if;
60 63 end process;
61 64 end DEF_ARCH;
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@@ -1,90 +1,93
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 use IEEE.numeric_std.all;
22 25
23 26 entity RAM_CEL is
24 27 port( WD : in std_logic_vector(35 downto 0); RD : out
25 28 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
26 29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
27 30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
28 31 ) ;
29 32 end RAM_CEL;
30 33
31 34
32 35
33 36 architecture ar_RAM_CEL of RAM_CEL is
34 37 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
35 38 signal RAMarray : RAMarrayT:=(others => X"000000000");
36 39 signal RD_int : std_logic_vector(35 downto 0);
37 40
38 41 begin
39 42
40 43 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
41 44
42 45
43 46 process(RWclk,reset)
44 47 begin
45 48 if reset = '0' then
46 49 RD <= (X"000000000");
47 50 rst:for i in 0 to 255 loop
48 51 RAMarray(i) <= (others => '0');
49 52 end loop;
50 53
51 54 elsif RWclk'event and RWclk = '1' then
52 55 if REN = '0' then
53 56 RD <= RD_int;
54 57 end if;
55 58
56 59 if WEN = '0' then
57 60 RAMarray(to_integer(unsigned(WADDR))) <= WD;
58 61 end if;
59 62
60 63 end if;
61 64 end process;
62 65 end ar_RAM_CEL;
63 66
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@@ -1,210 +1,213
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.iir_filter.all;
24 27 use lpp.FILTERcfg.all;
25 28 use lpp.general_purpose.all;
26 29
27 30 --TODO amliorer la flexibilit de la config de la RAM.
28 31
29 32 entity RAM_CTRLR2 is
30 33 generic(
31 34 Input_SZ_1 : integer := 16;
32 35 Mem_use : integer := use_RAM
33 36 );
34 37 port(
35 38 reset : in std_logic;
36 39 clk : in std_logic;
37 40 WD_sel : in std_logic;
38 41 Read : in std_logic;
39 42 WADDR_sel : in std_logic;
40 43 count : in std_logic;
41 44 SVG_ADDR : in std_logic;
42 45 Write : in std_logic;
43 46 GO_0 : in std_logic;
44 47 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
45 48 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
46 49 );
47 50 end RAM_CTRLR2;
48 51
49 52
50 53 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
51 54
52 55 signal WD : std_logic_vector(35 downto 0);
53 56 signal WD_D : std_logic_vector(35 downto 0);
54 57 signal RD : std_logic_vector(35 downto 0);
55 58 signal WEN, REN : std_logic;
56 59 signal WADDR_back : std_logic_vector(7 downto 0);
57 60 signal WADDR_back_D: std_logic_vector(7 downto 0);
58 61 signal RADDR : std_logic_vector(7 downto 0);
59 62 signal WADDR : std_logic_vector(7 downto 0);
60 63 signal WADDR_D : std_logic_vector(7 downto 0);
61 64
62 65
63 66
64 67 begin
65 68
66 69 sample_out <= RD(Input_SZ_1-1 downto 0);
67 70
68 71
69 72 WEN <= not Write;
70 73 REN <= not read;
71 74
72 75
73 76 --==============================================================
74 77 --=========================R A M================================
75 78 --==============================================================
76 79 memRAM : if Mem_use = use_RAM generate
77 80 RAMblk :RAM
78 81 port map(
79 82 WD => WD_D,
80 83 RD => RD,
81 84 WEN => WEN,
82 85 REN => REN,
83 86 WADDR => WADDR,
84 87 RADDR => RADDR,
85 88 RWCLK => clk,
86 89 RESET => reset
87 90 ) ;
88 91 end generate;
89 92
90 93 memCEL : if Mem_use = use_CEL generate
91 94 RAMblk :RAM_CEL
92 95 port map(
93 96 WD => WD_D,
94 97 RD => RD,
95 98 WEN => WEN,
96 99 REN => REN,
97 100 WADDR => WADDR,
98 101 RADDR => RADDR,
99 102 RWCLK => clk,
100 103 RESET => reset
101 104 ) ;
102 105 end generate;
103 106 --==============================================================
104 107 --==============================================================
105 108
106 109
107 110 ADDRcntr_inst : ADDRcntr
108 111 port map(
109 112 clk => clk,
110 113 reset => reset,
111 114 count => count,
112 115 clr => GO_0,
113 116 Q => RADDR
114 117 );
115 118
116 119
117 120
118 121 MUX2_inst1 :MUX2
119 122 generic map(Input_SZ => Input_SZ_1)
120 123 port map(
121 124 sel => WD_sel,
122 125 IN1 => sample_in,
123 126 IN2 => RD(Input_SZ_1-1 downto 0),
124 127 RES => WD(Input_SZ_1-1 downto 0)
125 128 );
126 129
127 130
128 131 MUX2_inst2 :MUX2
129 132 generic map(Input_SZ => 8)
130 133 port map(
131 134 sel => WADDR_sel,
132 135 IN1 => WADDR_D,
133 136 IN2 => WADDR_back_D,
134 137 RES => WADDR
135 138 );
136 139
137 140
138 141
139 142
140 143 WADDR_backreg :REG
141 144 generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2)
142 145 port map(
143 146 reset => reset,
144 147 clk => SVG_ADDR,
145 148 D => RADDR,
146 149 Q => WADDR_back
147 150 );
148 151
149 152 WADDR_backreg2 :REG
150 153 generic map(size => 8)
151 154 port map(
152 155 reset => reset,
153 156 clk => SVG_ADDR,
154 157 D => WADDR_back,
155 158 Q => WADDR_back_D
156 159 );
157 160
158 161 WDRreg :REG
159 162 generic map(size => Input_SZ_1)
160 163 port map(
161 164 reset => reset,
162 165 clk => clk,
163 166 D => WD(Input_SZ_1-1 downto 0),
164 167 Q => WD_D(Input_SZ_1-1 downto 0)
165 168 );
166 169
167 170
168 171
169 172
170 173 ADDRreg :REG
171 174 generic map(size => 8)
172 175 port map(
173 176 reset => reset,
174 177 clk => clk,
175 178 D => RADDR,
176 179 Q => WADDR_D
177 180 );
178 181
179 182
180 183
181 184 end ar_RAM_CTRLR2;
182 185
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@@ -1,113 +1,116
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25
23 26
24 27
25 28 entity TestbenshMAC is
26 29 end TestbenshMAC;
27 30
28 31
29 32
30 33
31 34 architecture ar_TestbenshMAC of TestbenshMAC is
32 35
33 36
34 37
35 38 constant OP1sz : integer := 16;
36 39 constant OP2sz : integer := 12;
37 40 --IDLE =00 MAC =01 MULT =10 ADD =11
38 41 constant IDLE : std_logic_vector(1 downto 0) := "00";
39 42 constant MAC : std_logic_vector(1 downto 0) := "01";
40 43 constant MULT : std_logic_vector(1 downto 0) := "10";
41 44 constant ADD : std_logic_vector(1 downto 0) := "11";
42 45
43 46 signal clk : std_logic:='0';
44 47 signal reset : std_logic:='0';
45 48 signal clrMAC : std_logic:='0';
46 49 signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE;
47 50 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
48 51 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
49 52 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
50 53
51 54
52 55
53 56
54 57 begin
55 58
56 59
57 60 MAC1 : entity LPP_IIR_FILTER.MAC
58 61 generic map(
59 62 Input_SZ_A => OP1sz,
60 63 Input_SZ_B => OP2sz
61 64
62 65 )
63 66 port map(
64 67 clk => clk,
65 68 reset => reset,
66 69 clr_MAC => clrMAC,
67 70 MAC_MUL_ADD => MAC_MUL_ADD,
68 71 OP1 => Operand1,
69 72 OP2 => Operand2,
70 73 RES => Resultat
71 74 );
72 75
73 76 clk <= not clk after 25 ns;
74 77
75 78 process
76 79 begin
77 80 wait for 40 ns;
78 81 reset <= '1';
79 82 wait for 11 ns;
80 83 Operand1 <= X"0001";
81 84 Operand2 <= X"001";
82 85 MAC_MUL_ADD <= ADD;
83 86 wait for 50 ns;
84 87 Operand1 <= X"0001";
85 88 Operand2 <= X"100";
86 89 wait for 50 ns;
87 90 Operand1 <= X"0001";
88 91 Operand2 <= X"001";
89 92 MAC_MUL_ADD <= MULT;
90 93 wait for 50 ns;
91 94 Operand1 <= X"0002";
92 95 Operand2 <= X"002";
93 96 wait for 50 ns;
94 97 clrMAC <= '1';
95 98 wait for 50 ns;
96 99 clrMAC <= '0';
97 100 Operand1 <= X"0001";
98 101 Operand2 <= X"003";
99 102 MAC_MUL_ADD <= MAC;
100 103 wait;
101 104 end process;
102 105 end ar_TestbenshMAC;
103 106
104 107
105 108
106 109
107 110
108 111
109 112
110 113
111 114
112 115
113 116
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@@ -1,223 +1,225
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
20 22 library ieee;
21 23 use ieee.std_logic_1164.all;
22 24 library grlib;
23 25 use grlib.amba.all;
24 26 use grlib.stdlib.all;
25 27 use grlib.devices.all;
26 28 library lpp;
27 29
28 30
29 31
30 32
31 33 package iir_filter is
32 34
33 35
34 36 --===========================================================|
35 37 --================A L U C O N T R O L======================|
36 38 --===========================================================|
37 39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
38 40 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
39 41 constant MULT : std_logic_vector(3 downto 0) := "0010";
40 42 constant ADD : std_logic_vector(3 downto 0) := "0011";
41 43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
42 44
43 45 --____
44 46 --RAM |
45 47 --____|
46 48 constant use_RAM : integer := 1;
47 49 constant use_CEL : integer := 0;
48 50
49 51
50 52 --===========================================================|
51 53 --=============C O E F S ====================================|
52 54 --===========================================================|
53 55 -- create a specific type of data for coefs to avoid errors |
54 56 --===========================================================|
55 57
56 58 type scaleValT is array(natural range <>) of integer;
57 59
58 60 type samplT is array(natural range <>,natural range <>) of std_logic;
59 61
60 62 type in_IIR_CEL_reg is record
61 63 config : std_logic_vector(31 downto 0);
62 64 virgPos : std_logic_vector(4 downto 0);
63 65 end record;
64 66
65 67 type out_IIR_CEL_reg is record
66 68 config : std_logic_vector(31 downto 0);
67 69 status : std_logic_vector(31 downto 0);
68 70 end record;
69 71
70 72
71 73
72 74 component APB_IIR_CEL is
73 75 generic (
74 76 pindex : integer := 0;
75 77 paddr : integer := 0;
76 78 pmask : integer := 16#fff#;
77 79 pirq : integer := 0;
78 80 abits : integer := 8;
79 81 Sample_SZ : integer := 16;
80 82 ChanelsCount : integer := 1;
81 83 Coef_SZ : integer := 9;
82 84 CoefCntPerCel: integer := 3;
83 85 Cels_count : integer := 5;
84 86 virgPos : integer := 3;
85 87 Mem_use : integer := use_RAM
86 88 );
87 89 port (
88 90 rst : in std_logic;
89 91 clk : in std_logic;
90 92 apbi : in apb_slv_in_type;
91 93 apbo : out apb_slv_out_type;
92 94 sample_clk : in std_logic;
93 95 sample_clk_out : out std_logic;
94 96 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
95 97 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
96 98 );
97 99 end component;
98 100
99 101
100 102 --component FILTER is
101 103 --generic(Smpl_SZ : integer := 16;
102 104 -- ChanelsCNT : integer := 3
103 105 --);
104 106 --port(
105 107 --
106 108 -- reset : in std_logic;
107 109 -- clk : in std_logic;
108 110 -- sample_clk : in std_logic;
109 111 -- Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
110 112 -- Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
111 113 --);
112 114 --end component;
113 115
114 116
115 117
116 118 --component FilterCTRLR is
117 119 --port(
118 120 -- reset : in std_logic;
119 121 -- clk : in std_logic;
120 122 -- sample_clk : in std_logic;
121 123 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
122 124 -- sample_in : in samplT;
123 125 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
124 126 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
125 127 --);
126 128 --end component;
127 129
128 130
129 131 --component FILTER_RAM_CTRLR is
130 132 --port(
131 133 -- reset : in std_logic;
132 134 -- clk : in std_logic;
133 135 -- run : in std_logic;
134 136 -- GO_0 : in std_logic;
135 137 -- B_A : in std_logic;
136 138 -- writeForce : in std_logic;
137 139 -- next_blk : in std_logic;
138 140 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
139 141 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
140 142 --);
141 143 --end component;
142 144
143 145
144 146 component IIR_CEL_CTRLR is
145 147 generic(Sample_SZ : integer := 16;
146 148 ChanelsCount : integer := 1;
147 149 Coef_SZ : integer := 9;
148 150 CoefCntPerCel: integer := 3;
149 151 Cels_count : integer := 5;
150 152 Mem_use : integer := use_RAM
151 153 );
152 154 port(
153 155 reset : in std_logic;
154 156 clk : in std_logic;
155 157 sample_clk : in std_logic;
156 158 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
157 159 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
158 160 virg_pos : in integer;
159 161 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
160 162 );
161 163 end component;
162 164
163 165
164 166 component RAM is
165 167 port( WD : in std_logic_vector(35 downto 0); RD : out
166 168 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
167 169 WADDR : in std_logic_vector(7 downto 0); RADDR : in
168 170 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
169 171 ) ;
170 172 end component;
171 173
172 174
173 175 component RAM_CEL is
174 176 port( WD : in std_logic_vector(35 downto 0); RD : out
175 177 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
176 178 WADDR : in std_logic_vector(7 downto 0); RADDR : in
177 179 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
178 180 ) ;
179 181 end component;
180 182
181 183 component IIR_CEL_FILTER is
182 184 generic(Sample_SZ : integer := 16;
183 185 ChanelsCount : integer := 1;
184 186 Coef_SZ : integer := 9;
185 187 CoefCntPerCel: integer := 3;
186 188 Cels_count : integer := 5;
187 189 Mem_use : integer := use_RAM);
188 190 port(
189 191 reset : in std_logic;
190 192 clk : in std_logic;
191 193 sample_clk : in std_logic;
192 194 regs_in : in in_IIR_CEL_reg;
193 195 regs_out : in out_IIR_CEL_reg;
194 196 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
195 197 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
196 198 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
197 199
198 200 );
199 201 end component;
200 202
201 203
202 204 component RAM_CTRLR2 is
203 205 generic(
204 206 Input_SZ_1 : integer := 16;
205 207 Mem_use : integer := use_RAM
206 208 );
207 209 port(
208 210 reset : in std_logic;
209 211 clk : in std_logic;
210 212 WD_sel : in std_logic;
211 213 Read : in std_logic;
212 214 WADDR_sel : in std_logic;
213 215 count : in std_logic;
214 216 SVG_ADDR : in std_logic;
215 217 Write : in std_logic;
216 218 GO_0 : in std_logic;
217 219 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
218 220 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
219 221 );
220 222 end component;
221 223
222 224
223 225 end;
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@@ -1,61 +1,64
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.general_purpose.all;
24 27
25 28
26 29
27 30 entity ADDRcntr is
28 31 port(
29 32 clk : in std_logic;
30 33 reset : in std_logic;
31 34 count : in std_logic;
32 35 clr : in std_logic;
33 36 Q : out std_logic_vector(7 downto 0)
34 37 );
35 38 end entity;
36 39
37 40
38 41
39 42
40 43 architecture ar_ADDRcntr of ADDRcntr is
41 44
42 45 signal reg : std_logic_vector(7 downto 0);
43 46
44 47 begin
45 48
46 49 Q <= REG;
47 50
48 51 process(clk,reset)
49 52 begin
50 53 if reset = '0' then
51 54 REG <= (others => '0');
52 55 elsif clk'event and clk ='1' then
53 56 if clr = '1' then
54 57 REG <= (others => '0');
55 58 elsif count ='1' then
56 59 REG <= std_logic_vector(unsigned(REG)+1);
57 60 end if;
58 61 end if;
59 62 end process;
60 63
61 64 end ar_ADDRcntr;
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@@ -1,81 +1,81
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 ------------------------------------------------------------------------------
20 -- This file is a part of the LPP VHDL IP LIBRARY
21 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25 library lpp;
26 26 use lpp.general_purpose.all;
27 27 --IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100
28 28 --NOT =0101 AND =0110 OR =0111 XOR =1000
29 29 --SHIFTleft =1001 SHIFTright =1010
30 30
31 31 entity ALU is
32 32 generic(
33 33 Arith_en : integer := 1;
34 34 Logic_en : integer := 1;
35 35 Input_SZ_1 : integer := 16;
36 36 Input_SZ_2 : integer := 9
37 37
38 38 );
39 39 port(
40 40 clk : in std_logic;
41 41 reset : in std_logic;
42 42 ctrl : in std_logic_vector(3 downto 0);
43 43 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
44 44 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
45 45 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
46 46 );
47 47 end entity;
48 48
49 49
50 50
51 51 architecture ar_ALU of ALU is
52 52
53 53
54 54
55 55 signal clr_MAC : std_logic:='1';
56 56
57 57
58 58 begin
59 59
60 60 clr_MAC <= '1' when ctrl = "0100" else '0';
61 61
62 62
63 63 arith : if Arith_en = 1 generate
64 64 MACinst : MAC
65 65 generic map(Input_SZ_1,Input_SZ_2)
66 66 port map(clk,reset,clr_MAC,ctrl(1 downto 0),OP1,OP2,RES);
67 67 end generate;
68 68
69 69 end architecture;
70 70
71 71
72 72
73 73
74 74
75 75
76 76
77 77
78 78
79 79
80 80
81 81
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@@ -1,69 +1,72
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.general_purpose.all;
24 27
25 28
26 29
27 30 entity Adder is
28 31 generic(
29 32 Input_SZ_A : integer := 16;
30 33 Input_SZ_B : integer := 16
31 34
32 35 );
33 36 port(
34 37 clk : in std_logic;
35 38 reset : in std_logic;
36 39 clr : in std_logic;
37 40 add : in std_logic;
38 41 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
39 42 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
40 43 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
41 44 );
42 45 end entity;
43 46
44 47
45 48
46 49
47 50 architecture ar_Adder of Adder is
48 51
49 52 signal REG : std_logic_vector(Input_SZ_A-1 downto 0);
50 53 signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0);
51 54
52 55 begin
53 56
54 57 RES <= REG;
55 58 RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
56 59
57 60 process(clk,reset)
58 61 begin
59 62 if reset = '0' then
60 63 REG <= (others => '0');
61 64 elsif clk'event and clk ='1' then
62 65 if clr = '1' then
63 66 REG <= (others => '0');
64 67 elsif add = '1' then
65 68 REG <= RESADD;
66 69 end if;
67 70 end if;
68 71 end process;
69 72 end ar_Adder;
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@@ -1,64 +1,67
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24
22 25
23 26 entity Clk_divider is
24 27 generic(OSC_freqHz : integer := 50000000;
25 28 TargetFreq_Hz : integer := 50000);
26 29 Port ( clk : in STD_LOGIC;
27 30 reset : in STD_LOGIC;
28 31 clk_divided : out STD_LOGIC);
29 32 end Clk_divider;
30 33
31 34 architecture ar_Clk_divider of Clk_divider is
32 35
33 36 Constant clk_TRIGER : integer := (OSC_freqHz/(2*TargetFreq_Hz))+1;
34 37
35 38
36 39 signal cpt1 : integer;
37 40
38 41 signal clk_int : std_logic := '0';
39 42
40 43
41 44 begin
42 45
43 46 clk_divided <= clk_int;
44 47
45 48
46 49 process(reset,clk)
47 50 begin
48 51 if reset = '0' then
49 52 cpt1 <= 0;
50 53 clk_int <= '0';
51 54 elsif clk'event and clk = '1' then
52 55 if cpt1 = clk_TRIGER then
53 56 clk_int <= not clk_int;
54 57 cpt1 <= 0;
55 58 else
56 59 cpt1 <= cpt1 + 1;
57 60 end if;
58 61 end if;
59 62 end process;
60 63
61 64
62 65 end ar_Clk_divider;
63 66
64 67
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@@ -1,262 +1,278
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
6 22 library IEEE;
7 23 use IEEE.numeric_std.all;
8 24 use IEEE.std_logic_1164.all;
9 25 library lpp;
10 26 use lpp.general_purpose.all;
11 27 --TODO
12 28 --terminer le testbensh puis changer le resize dans les instanciations
13 29 --par un resize sur un vecteur en combi
14 30
15 31
16 32
17 33
18 34
19 35 entity MAC is
20 36 generic(
21 37 Input_SZ_A : integer := 8;
22 38 Input_SZ_B : integer := 8
23 39
24 40 );
25 41 port(
26 42 clk : in std_logic;
27 43 reset : in std_logic;
28 44 clr_MAC : in std_logic;
29 45 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
30 46 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
31 47 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
32 48 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
33 49 );
34 50 end MAC;
35 51
36 52
37 53
38 54
39 55 architecture ar_MAC of MAC is
40 56
41 57
42 58
43 59
44 60
45 61 signal add,mult : std_logic;
46 62 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
47 63
48 64 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
49 65 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
50 66 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
51 67
52 68
53 69 signal MACMUXsel : std_logic;
54 70 signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
55 71 signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
56 72
57 73
58 74
59 75 signal MACMUX2sel : std_logic;
60 76
61 77 signal add_D : std_logic;
62 78 signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0);
63 79 signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0);
64 80 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
65 81 signal MACMUXsel_D : std_logic;
66 82 signal MACMUX2sel_D : std_logic;
67 83 signal MACMUX2sel_D_D : std_logic;
68 84 signal clr_MAC_D : std_logic;
69 85 signal clr_MAC_D_D : std_logic;
70 86
71 87
72 88
73 89
74 90
75 91 begin
76 92
77 93
78 94
79 95
80 96 --==============================================================
81 97 --=============M A C C O N T R O L E R=========================
82 98 --==============================================================
83 99 MAC_CONTROLER1 : MAC_CONTROLER
84 100 port map(
85 101 ctrl => MAC_MUL_ADD,
86 102 MULT => mult,
87 103 ADD => add,
88 104 MACMUX_sel => MACMUXsel,
89 105 MACMUX2_sel => MACMUX2sel
90 106
91 107 );
92 108 --==============================================================
93 109
94 110
95 111
96 112
97 113 --==============================================================
98 114 --=============M U L T I P L I E R==============================
99 115 --==============================================================
100 116 Multiplieri_nst : Multiplier
101 117 generic map(
102 118 Input_SZ_A => Input_SZ_A,
103 119 Input_SZ_B => Input_SZ_B
104 120 )
105 121 port map(
106 122 clk => clk,
107 123 reset => reset,
108 124 mult => mult,
109 125 OP1 => OP1,
110 126 OP2 => OP2,
111 127 RES => MULTout
112 128 );
113 129
114 130 --==============================================================
115 131
116 132
117 133
118 134
119 135 --==============================================================
120 136 --======================A D D E R ==============================
121 137 --==============================================================
122 138 adder_inst : Adder
123 139 generic map(
124 140 Input_SZ_A => Input_SZ_A+Input_SZ_B,
125 141 Input_SZ_B => Input_SZ_A+Input_SZ_B
126 142 )
127 143 port map(
128 144 clk => clk,
129 145 reset => reset,
130 146 clr => clr_MAC_D,
131 147 add => add_D,
132 148 OP1 => ADDERinA,
133 149 OP2 => ADDERinB,
134 150 RES => ADDERout
135 151 );
136 152
137 153 --==============================================================
138 154
139 155
140 156 clr_MACREG1 : MAC_REG
141 157 generic map(size => 1)
142 158 port map(
143 159 reset => reset,
144 160 clk => clk,
145 161 D(0) => clr_MAC,
146 162 Q(0) => clr_MAC_D
147 163 );
148 164
149 165 clr_MACREG2 : MAC_REG
150 166 generic map(size => 1)
151 167 port map(
152 168 reset => reset,
153 169 clk => clk,
154 170 D(0) => clr_MAC_D,
155 171 Q(0) => clr_MAC_D_D
156 172 );
157 173
158 174 addREG : MAC_REG
159 175 generic map(size => 1)
160 176 port map(
161 177 reset => reset,
162 178 clk => clk,
163 179 D(0) => add,
164 180 Q(0) => add_D
165 181 );
166 182
167 183 OP1REG : MAC_REG
168 184 generic map(size => Input_SZ_A)
169 185 port map(
170 186 reset => reset,
171 187 clk => clk,
172 188 D => OP1,
173 189 Q => OP1_D
174 190 );
175 191
176 192
177 193 OP2REG : MAC_REG
178 194 generic map(size => Input_SZ_B)
179 195 port map(
180 196 reset => reset,
181 197 clk => clk,
182 198 D => OP2,
183 199 Q => OP2_D
184 200 );
185 201
186 202
187 203 MULToutREG : MAC_REG
188 204 generic map(size => Input_SZ_A+Input_SZ_B)
189 205 port map(
190 206 reset => reset,
191 207 clk => clk,
192 208 D => MULTout,
193 209 Q => MULTout_D
194 210 );
195 211
196 212
197 213 MACMUXselREG : MAC_REG
198 214 generic map(size => 1)
199 215 port map(
200 216 reset => reset,
201 217 clk => clk,
202 218 D(0) => MACMUXsel,
203 219 Q(0) => MACMUXsel_D
204 220 );
205 221
206 222 MACMUX2selREG : MAC_REG
207 223 generic map(size => 1)
208 224 port map(
209 225 reset => reset,
210 226 clk => clk,
211 227 D(0) => MACMUX2sel,
212 228 Q(0) => MACMUX2sel_D
213 229 );
214 230
215 231 MACMUX2selREG2 : MAC_REG
216 232 generic map(size => 1)
217 233 port map(
218 234 reset => reset,
219 235 clk => clk,
220 236 D(0) => MACMUX2sel_D,
221 237 Q(0) => MACMUX2sel_D_D
222 238 );
223 239
224 240 --==============================================================
225 241 --======================M A C M U X ===========================
226 242 --==============================================================
227 243 MACMUX_inst : MAC_MUX
228 244 generic map(
229 245 Input_SZ_A => Input_SZ_A+Input_SZ_B,
230 246 Input_SZ_B => Input_SZ_A+Input_SZ_B
231 247
232 248 )
233 249 port map(
234 250 sel => MACMUXsel_D,
235 251 INA1 => ADDERout,
236 252 INA2 => OP2_D_Resz,
237 253 INB1 => MULTout,
238 254 INB2 => OP1_D_Resz,
239 255 OUTA => ADDERinA,
240 256 OUTB => ADDERinB
241 257 );
242 258 OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B));
243 259 OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B));
244 260 --==============================================================
245 261
246 262
247 263 --==============================================================
248 264 --======================M A C M U X2 ==========================
249 265 --==============================================================
250 266 MAC_MUX2_inst : MAC_MUX2
251 267 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
252 268 port map(
253 269 sel => MACMUX2sel_D_D,
254 270 RES2 => MULTout_D,
255 271 RES1 => ADDERout,
256 272 RES => RES
257 273 );
258 274
259 275
260 276 --==============================================================
261 277
262 278 end ar_MAC;
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@@ -1,67 +1,69
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.numeric_std.all;
22 24 use IEEE.std_logic_1164.all;
23 25 library lpp;
24 26 use lpp.general_purpose.all;
25 27
26 28
27 29 --IDLE =00 MAC =01 MULT =10 ADD =11
28 30
29 31
30 32 entity MAC_CONTROLER is
31 33 port(
32 34 ctrl : in std_logic_vector(1 downto 0);
33 35 MULT : out std_logic;
34 36 ADD : out std_logic;
35 37 MACMUX_sel : out std_logic;
36 38 MACMUX2_sel : out std_logic
37 39
38 40 );
39 41 end MAC_CONTROLER;
40 42
41 43
42 44
43 45
44 46
45 47 architecture ar_MAC_CONTROLER of MAC_CONTROLER is
46 48
47 49 begin
48 50
49 51
50 52
51 53 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
52 54 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
53 55 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
54 56 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01"or ctrl = "11") else '1';
55 57
56 58
57 59 end ar_MAC_CONTROLER;
58 60
59 61
60 62
61 63
62 64
63 65
64 66
65 67
66 68
67 69
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@@ -1,54 +1,57
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.general_purpose.all;
24 27
25 28
26 29
27 30 entity MAC_MUX is
28 31 generic(
29 32 Input_SZ_A : integer := 16;
30 33 Input_SZ_B : integer := 16
31 34
32 35 );
33 36 port(
34 37 sel : in std_logic;
35 38 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
36 39 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
37 40 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
38 41 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
39 42 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
40 43 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
41 44 );
42 45 end entity;
43 46
44 47
45 48
46 49
47 50 architecture ar_MAC_MUX of MAC_MUX is
48 51
49 52 begin
50 53
51 54 OUTA <= INA1 when sel = '0' else INA2;
52 55 OUTB <= INB1 when sel = '0' else INB2;
53 56
54 57 end ar_MAC_MUX;
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@@ -1,46 +1,49
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.general_purpose.all;
24 27
25 28
26 29
27 30 entity MAC_MUX2 is
28 31 generic(Input_SZ : integer := 16);
29 32 port(
30 33 sel : in std_logic;
31 34 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
32 35 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
33 36 RES : out std_logic_vector(Input_SZ-1 downto 0)
34 37 );
35 38 end entity;
36 39
37 40
38 41
39 42
40 43 architecture ar_MAC_MUX2 of MAC_MUX2 is
41 44
42 45 begin
43 46
44 47 RES <= RES1 when sel = '0' else RES2;
45 48
46 49 end ar_MAC_MUX2;
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@@ -1,59 +1,62
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.general_purpose.all;
24 27
25 28
26 29
27 30 entity MAC_REG is
28 31 generic(size : integer := 16);
29 32 port(
30 33 reset : in std_logic;
31 34 clk : in std_logic;
32 35 D : in std_logic_vector(size-1 downto 0);
33 36 Q : out std_logic_vector(size-1 downto 0)
34 37 );
35 38 end entity;
36 39
37 40
38 41
39 42 architecture ar_MAC_REG of MAC_REG is
40 43 begin
41 44 process(clk,reset)
42 45 begin
43 46 if reset = '0' then
44 47 Q <= (others => '0');
45 48 elsif clk'event and clk ='1' then
46 49 Q <= D;
47 50 end if;
48 51 end process;
49 52 end ar_MAC_REG;
50 53
51 54
52 55
53 56
54 57
55 58
56 59
57 60
58 61
59 62
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@@ -1,46 +1,49
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.general_purpose.all;
24 27
25 28
26 29
27 30 entity MUX2 is
28 31 generic(Input_SZ : integer := 16);
29 32 port(
30 33 sel : in std_logic;
31 34 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
32 35 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
33 36 RES : out std_logic_vector(Input_SZ-1 downto 0)
34 37 );
35 38 end entity;
36 39
37 40
38 41
39 42
40 43 architecture ar_MUX2 of MUX2 is
41 44
42 45 begin
43 46
44 47 RES <= IN1 when sel = '0' else IN2;
45 48
46 49 end ar_MUX2;
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@@ -1,77 +1,80
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25
23 26 library lpp;
24 27 use lpp.general_purpose.all;
25 28
26 29
27 30
28 31 entity Multiplier is
29 32 generic(
30 33 Input_SZ_A : integer := 16;
31 34 Input_SZ_B : integer := 16
32 35
33 36 );
34 37 port(
35 38 clk : in std_logic;
36 39 reset : in std_logic;
37 40 mult : in std_logic;
38 41 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
39 42 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
40 43 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
41 44 );
42 45 end Multiplier;
43 46
44 47
45 48
46 49
47 50
48 51 architecture ar_Multiplier of Multiplier is
49 52
50 53 signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
51 54 signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
52 55
53 56
54 57 begin
55 58
56 59 RES <= REG;
57 60 RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
58 61 process(clk,reset)
59 62 begin
60 63 if reset = '0' then
61 64 REG <= (others => '0');
62 65 elsif clk'event and clk ='1' then
63 66 if mult = '1' then
64 67 REG <= RESMULT;
65 68 end if;
66 69 end if;
67 70 end process;
68 71
69 72 end ar_Multiplier;
70 73
71 74
72 75
73 76
74 77
75 78
76 79
77 80
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@@ -1,47 +1,50
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.general_purpose.all;
24 27
25 28 entity REG is
26 29 generic(size : integer := 16 ; initial_VALUE : integer := 0);
27 30 port(
28 31 reset : in std_logic;
29 32 clk : in std_logic;
30 33 D : in std_logic_vector(size-1 downto 0);
31 34 Q : out std_logic_vector(size-1 downto 0)
32 35 );
33 36 end entity;
34 37
35 38
36 39
37 40 architecture ar_REG of REG is
38 41 begin
39 42 process(clk,reset)
40 43 begin
41 44 if reset = '0' then
42 45 Q <= std_logic_vector(to_unsigned(initial_VALUE,size));
43 46 elsif clk'event and clk ='1' then
44 47 Q <= D;
45 48 end if;
46 49 end process;
47 50 end ar_REG;
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@@ -1,65 +1,68
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.general_purpose.all;
24 27
25 28
26 29
27 30 entity RShifter is
28 31 generic(
29 32 Input_SZ : integer := 16;
30 33 shift_SZ : integer := 4
31 34 );
32 35 port(
33 36 clk : in std_logic;
34 37 reset : in std_logic;
35 38 shift : in std_logic;
36 39 OP : in std_logic_vector(Input_SZ-1 downto 0);
37 40 cnt : in std_logic_vector(shift_SZ-1 downto 0);
38 41 RES : out std_logic_vector(Input_SZ-1 downto 0)
39 42 );
40 43 end entity;
41 44
42 45
43 46
44 47
45 48 architecture ar_RShifter of RShifter is
46 49
47 50 signal REG : std_logic_vector(Input_SZ-1 downto 0);
48 51 signal RESSHIFT: std_logic_vector(Input_SZ-1 downto 0);
49 52
50 53 begin
51 54
52 55 RES <= REG;
53 56 RESSHIFT <= std_logic_vector(SHIFT_RIGHT(signed(OP),to_integer(unsigned(cnt))));
54 57
55 58 process(clk,reset)
56 59 begin
57 60 if reset = '0' then
58 61 REG <= (others => '0');
59 62 elsif clk'event and clk ='1' then
60 63 if shift = '1' then
61 64 REG <= RESSHIFT;
62 65 end if;
63 66 end if;
64 67 end process;
65 68 end ar_RShifter;
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@@ -1,135 +1,138
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25
23 26
24 27
25 28 entity TestbenshALU is
26 29 end TestbenshALU;
27 30
28 31
29 32
30 33
31 34 architecture ar_TestbenshALU of TestbenshALU is
32 35
33 36
34 37
35 38 constant OP1sz : integer := 16;
36 39 constant OP2sz : integer := 12;
37 40 --IDLE =00 MAC =01 MULT =10 ADD =11
38 41 constant IDLE : std_logic_vector(3 downto 0) := "0000";
39 42 constant MAC : std_logic_vector(3 downto 0) := "0001";
40 43 constant MULT : std_logic_vector(3 downto 0) := "0010";
41 44 constant ADD : std_logic_vector(3 downto 0) := "0011";
42 45 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
43 46
44 47 signal clk : std_logic:='0';
45 48 signal reset : std_logic:='0';
46 49 signal ctrl : std_logic_vector(3 downto 0):=IDLE;
47 50 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
48 51 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
49 52 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
50 53
51 54
52 55
53 56
54 57 begin
55 58
56 59 ALU1 : entity LPP_IIR_FILTER.ALU
57 60 generic map(
58 61 Arith_en => 1,
59 62 Logic_en => 0,
60 63 Input_SZ_1 => OP1sz,
61 64 Input_SZ_2 => OP2sz
62 65
63 66 )
64 67 port map(
65 68 clk => clk,
66 69 reset => reset,
67 70 ctrl => ctrl,
68 71 OP1 => Operand1,
69 72 OP2 => Operand2,
70 73 RES => Resultat
71 74 );
72 75
73 76
74 77
75 78
76 79 clk <= not clk after 25 ns;
77 80
78 81 process
79 82 begin
80 83 wait for 40 ns;
81 84 reset <= '1';
82 85 wait for 11 ns;
83 86 Operand1 <= X"0001";
84 87 Operand2 <= X"001";
85 88 ctrl <= ADD;
86 89 wait for 50 ns;
87 90 Operand1 <= X"0001";
88 91 Operand2 <= X"100";
89 92 wait for 50 ns;
90 93 Operand1 <= X"0001";
91 94 Operand2 <= X"001";
92 95 ctrl <= MULT;
93 96 wait for 50 ns;
94 97 Operand1 <= X"0002";
95 98 Operand2 <= X"002";
96 99 wait for 50 ns;
97 100 ctrl <= clr_mac;
98 101 wait for 50 ns;
99 102 Operand1 <= X"0001";
100 103 Operand2 <= X"003";
101 104 ctrl <= MAC;
102 105 wait for 50 ns;
103 106 Operand1 <= X"0001";
104 107 Operand2 <= X"001";
105 108 wait for 50 ns;
106 109 Operand1 <= X"0011";
107 110 Operand2 <= X"003";
108 111 wait for 50 ns;
109 112 Operand1 <= X"1001";
110 113 Operand2 <= X"003";
111 114 wait for 50 ns;
112 115 Operand1 <= X"0001";
113 116 Operand2 <= X"000";
114 117 wait for 50 ns;
115 118 Operand1 <= X"0001";
116 119 Operand2 <= X"003";
117 120 wait for 50 ns;
118 121 Operand1 <= X"0101";
119 122 Operand2 <= X"053";
120 123 wait for 50 ns;
121 124 ctrl <= clr_mac;
122 125 wait;
123 126 end process;
124 127 end ar_TestbenshALU;
125 128
126 129
127 130
128 131
129 132
130 133
131 134
132 135
133 136
134 137
135 138
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@@ -1,208 +1,208
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24
22 25
23 26
24 27 package general_purpose is
25 28
26 29
27 30
28 31 component Clk_divider is
29 32 generic(OSC_freqHz : integer := 50000000;
30 33 TargetFreq_Hz : integer := 50000);
31 34 Port ( clk : in STD_LOGIC;
32 35 reset : in STD_LOGIC;
33 36 clk_divided : out STD_LOGIC);
34 37 end component;
35 38
36 39
37
38
39
40 40 component Adder is
41 41 generic(
42 42 Input_SZ_A : integer := 16;
43 43 Input_SZ_B : integer := 16
44 44
45 45 );
46 46 port(
47 47 clk : in std_logic;
48 48 reset : in std_logic;
49 49 clr : in std_logic;
50 50 add : in std_logic;
51 51 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
52 52 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
53 53 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
54 54 );
55 55 end component;
56 56
57 57 component ADDRcntr is
58 58 port(
59 59 clk : in std_logic;
60 60 reset : in std_logic;
61 61 count : in std_logic;
62 62 clr : in std_logic;
63 63 Q : out std_logic_vector(7 downto 0)
64 64 );
65 65 end component;
66 66
67 67 component ALU is
68 68 generic(
69 69 Arith_en : integer := 1;
70 70 Logic_en : integer := 1;
71 71 Input_SZ_1 : integer := 16;
72 72 Input_SZ_2 : integer := 9
73 73
74 74 );
75 75 port(
76 76 clk : in std_logic;
77 77 reset : in std_logic;
78 78 ctrl : in std_logic_vector(3 downto 0);
79 79 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
80 80 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
81 81 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
82 82 );
83 83 end component;
84 84
85 85
86 86 component MAC is
87 87 generic(
88 88 Input_SZ_A : integer := 8;
89 89 Input_SZ_B : integer := 8
90 90
91 91 );
92 92 port(
93 93 clk : in std_logic;
94 94 reset : in std_logic;
95 95 clr_MAC : in std_logic;
96 96 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
97 97 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
98 98 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
99 99 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
100 100 );
101 101 end component;
102 102
103 103
104 104 component MAC_CONTROLER is
105 105 port(
106 106 ctrl : in std_logic_vector(1 downto 0);
107 107 MULT : out std_logic;
108 108 ADD : out std_logic;
109 109 MACMUX_sel : out std_logic;
110 110 MACMUX2_sel : out std_logic
111 111
112 112 );
113 113 end component;
114 114
115 115 component MAC_MUX is
116 116 generic(
117 117 Input_SZ_A : integer := 16;
118 118 Input_SZ_B : integer := 16
119 119
120 120 );
121 121 port(
122 122 sel : in std_logic;
123 123 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
124 124 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
125 125 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
126 126 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
127 127 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
128 128 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
129 129 );
130 130 end component;
131 131
132 132
133 133 component MAC_MUX2 is
134 134 generic(Input_SZ : integer := 16);
135 135 port(
136 136 sel : in std_logic;
137 137 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
138 138 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
139 139 RES : out std_logic_vector(Input_SZ-1 downto 0)
140 140 );
141 141 end component;
142 142
143 143
144 144 component MAC_REG is
145 145 generic(size : integer := 16);
146 146 port(
147 147 reset : in std_logic;
148 148 clk : in std_logic;
149 149 D : in std_logic_vector(size-1 downto 0);
150 150 Q : out std_logic_vector(size-1 downto 0)
151 151 );
152 152 end component;
153 153
154 154
155 155 component MUX2 is
156 156 generic(Input_SZ : integer := 16);
157 157 port(
158 158 sel : in std_logic;
159 159 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
160 160 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
161 161 RES : out std_logic_vector(Input_SZ-1 downto 0)
162 162 );
163 163 end component;
164 164
165 165 component Multiplier is
166 166 generic(
167 167 Input_SZ_A : integer := 16;
168 168 Input_SZ_B : integer := 16
169 169
170 170 );
171 171 port(
172 172 clk : in std_logic;
173 173 reset : in std_logic;
174 174 mult : in std_logic;
175 175 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
176 176 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
177 177 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
178 178 );
179 179 end component;
180 180
181 181 component REG is
182 182 generic(size : integer := 16 ; initial_VALUE : integer := 0);
183 183 port(
184 184 reset : in std_logic;
185 185 clk : in std_logic;
186 186 D : in std_logic_vector(size-1 downto 0);
187 187 Q : out std_logic_vector(size-1 downto 0)
188 188 );
189 189 end component;
190 190
191 191
192 192
193 193 component RShifter is
194 194 generic(
195 195 Input_SZ : integer := 16;
196 196 shift_SZ : integer := 4
197 197 );
198 198 port(
199 199 clk : in std_logic;
200 200 reset : in std_logic;
201 201 shift : in std_logic;
202 202 OP : in std_logic_vector(Input_SZ-1 downto 0);
203 203 cnt : in std_logic_vector(shift_SZ-1 downto 0);
204 204 RES : out std_logic_vector(Input_SZ-1 downto 0)
205 205 );
206 206 end component;
207 207
208 208 end;
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@@ -1,98 +1,101
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24 library lpp;
22 25 use lpp.lpp_ad_conv.all;
23 26 use lpp.general_purpose.Clk_divider;
24 27
25 28 entity AD7688_drvr is
26 29 generic(ChanelCount : integer;
27 30 clkkHz : integer);
28 31 Port ( clk : in STD_LOGIC;
29 32 reset : in STD_LOGIC;
30 33 smplClk: in STD_LOGIC;
31 34 DataReady : out std_logic;
32 35 smpout : out Samples_out(ChanelCount-1 downto 0);
33 36 AD_in : in AD7688_in(ChanelCount-1 downto 0);
34 37 AD_out : out AD7688_out);
35 38 end AD7688_drvr;
36 39
37 40 architecture ar_AD7688_drvr of AD7688_drvr is
38 41
39 42 constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs
40 43
41 44 signal i : integer range 0 to convTrigger :=0;
42 45 signal clk_int : std_logic;
43 46 signal smplClk_reg : std_logic;
44 47 signal cnv_int : std_logic;
45 48
46 49 begin
47 50
48 51 clkdiv: if clkkHz>=66000 generate
49 52 clkdivider: Clk_divider
50 53 generic map(clkkHz*1000,60000000)
51 54 Port map( clk ,reset,clk_int);
52 55 end generate;
53 56
54 57 clknodiv: if clkkHz<66000 generate
55 58 nodiv: clk_int <= clk;
56 59 end generate;
57 60
58 61 AD_out.CNV <= cnv_int;
59 62 AD_out.SCK <= clk_int;
60 63
61 64
62 65 sckgen: process(clk,reset)
63 66 begin
64 67 if reset = '0' then
65 68 i <= 0;
66 69 cnv_int <= '0';
67 70 smplClk_reg <= '0';
68 71 elsif clk'event and clk = '1' then
69 72 if smplClk = '1' and smplClk_reg = '0' then
70 73 if i = convTrigger then
71 74 smplClk_reg <= '1';
72 75 i <= 0;
73 76 cnv_int <= '0';
74 77 else
75 78 i <= i+1;
76 79 cnv_int <= '1';
77 80 end if;
78 81 elsif smplClk = '0' and smplClk_reg = '1' then
79 82 smplClk_reg <= '0';
80 83 end if;
81 84 end if;
82 85 end process;
83 86
84 87
85 88
86 89 spidrvr: AD7688_spi_if
87 90 generic map(ChanelCount)
88 91 Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout);
89 92
90 93
91 94
92 95 end ar_AD7688_drvr;
93 96
94 97
95 98
96 99
97 100
98 101
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@@ -1,75 +1,78
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24 library lpp;
22 25 use lpp.lpp_ad_conv.all;
23 26 use lpp.general_purpose.Clk_divider;
24 27
25 28 entity AD7688_spi_if is
26 29 generic(ChanelCount : integer);
27 30 Port( clk : in STD_LOGIC;
28 31 reset : in STD_LOGIC;
29 32 cnv : in STD_LOGIC;
30 33 DataReady: out std_logic;
31 34 sdi : in AD7688_in(ChanelCount-1 downto 0);
32 35 smpout : out Samples_out(ChanelCount-1 downto 0)
33 36 );
34 37 end AD7688_spi_if;
35 38
36 39 architecture ar_AD7688_spi_if of AD7688_spi_if is
37 40
38 41 signal shift_reg : Samples_out(ChanelCount-1 downto 0);
39 42 signal i : integer range 0 to 15 :=0;
40 43 signal cnv_reg : std_logic := '0';
41 44
42 45 begin
43 46
44 47
45 48
46 49 process(clk,reset)
47 50 begin
48 51 if reset = '0' then
49 52 for l in 0 to ChanelCount-1 loop
50 53 shift_reg(l) <= (others => '0');
51 54 end loop;
52 55 i <= 0;
53 56 cnv_reg <= '0';
54 57 elsif clk'event and clk = '1' then
55 58 if cnv = '0' and cnv_reg = '0' then
56 59 if i = 15 then
57 60 i <= 0;
58 61 cnv_reg <= '1';
59 62 else
60 63 DataReady <= '0';
61 64 i <= i+1;
62 65 for l in 0 to ChanelCount-1 loop
63 66 shift_reg(l)(0) <= sdi(l).SDI;
64 67 shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0);
65 68 end loop;
66 69 end if;
67 70 else
68 71 cnv_reg <= not cnv;
69 72 smpout <= shift_reg;
70 73 DataReady <= '1';
71 74 end if;
72 75 end if;
73 76 end process;
74 77
75 78 end ar_AD7688_spi_if;
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@@ -1,102 +1,105
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24 library lpp;
22 25 use lpp.lpp_ad_conv.all;
23 26 use lpp.general_purpose.Clk_divider;
24 27
25 28 entity ADS7886_drvr is
26 29 generic(ChanelCount : integer;
27 30 clkkHz : integer);
28 31 Port ( clk : in STD_LOGIC;
29 32 reset : in STD_LOGIC;
30 33 smplClk: in STD_LOGIC;
31 34 DataReady : out std_logic;
32 35 smpout : out Samples_out(ChanelCount-1 downto 0);
33 36 AD_in : in AD7688_in(ChanelCount-1 downto 0);
34 37 AD_out : out AD7688_out);
35 38 end ADS7886_drvr;
36 39
37 40 architecture ar_ADS7886_drvr of ADS7886_drvr is
38 41
39 42 constant convTrigger : integer:= clkkHz*1/1000; --tconv = 1.6µs
40 43
41 44 signal i : integer range 0 to convTrigger :=0;
42 45 signal clk_int : std_logic;
43 46 signal smplClk_reg : std_logic;
44 47 signal cnv_int : std_logic;
45 48 signal smpout_int : Samples_out(ChanelCount-1 downto 0);
46 49
47 50
48 51 begin
49 52
50 53
51 54 clkdiv: if clkkHz>=20000 generate
52 55 clkdivider: Clk_divider
53 56 generic map(clkkHz*1000,19000000)
54 57 Port map( clk ,reset,clk_int);
55 58 end generate;
56 59
57 60
58 61 clknodiv: if clkkHz<20000 generate
59 62 nodiv: clk_int <= clk;
60 63 end generate;
61 64
62 65 AD_out.CNV <= cnv_int;
63 66 AD_out.SCK <= clk_int;
64 67
65 68
66 69 sckgen: process(clk,reset)
67 70 begin
68 71 if reset = '0' then
69 72 i <= 0;
70 73 cnv_int <= '0';
71 74 smplClk_reg <= '0';
72 75 elsif clk'event and clk = '1' then
73 76 if smplClk = '1' and smplClk_reg = '0' then
74 77 if i = convTrigger then
75 78 smplClk_reg <= '1';
76 79 i <= 0;
77 80 cnv_int <= '0';
78 81 else
79 82 i <= i+1;
80 83 cnv_int <= '1';
81 84 end if;
82 85 elsif smplClk = '0' and smplClk_reg = '1' then
83 86 smplClk_reg <= '0';
84 87 end if;
85 88 end if;
86 89 end process;
87 90
88 91
89 92 NDMSK: for i in 0 to ChanelCount-1
90 93 generate
91 94 smpout(i) <= smpout_int(i) and X"0FFF";
92 95 end generate;
93 96
94 97
95 98 spidrvr: AD7688_spi_if
96 99 generic map(ChanelCount)
97 100 Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout_int);
98 101
99 102
100 103
101 104 end ar_ADS7886_drvr;
102 105
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@@ -1,112 +1,115
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22
20 23 library IEEE;
21 24 use IEEE.STD_LOGIC_1164.all;
22 25 library grlib;
23 26 use grlib.amba.all;
24 27 use grlib.stdlib.all;
25 28 use grlib.devices.all;
26 29
27 30
28 31 package lpp_ad_conv is
29 32
30 33
31 34 constant AD7688 : integer := 0;
32 35 constant ADS7886 : integer := 1;
33 36
34 37
35 38 type AD7688_out is
36 39 record
37 40 CNV : std_logic;
38 41 SCK : std_logic;
39 42 end record;
40 43
41 44 type AD7688_in_element is
42 45 record
43 46 SDI : std_logic;
44 47 end record;
45 48
46 49 type AD7688_in is array(natural range <>) of AD7688_in_element;
47 50
48 51 type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);
49 52
50 53 component AD7688_drvr is
51 54 generic(ChanelCount : integer;
52 55 clkkHz : integer);
53 56 Port ( clk : in STD_LOGIC;
54 57 reset : in STD_LOGIC;
55 58 smplClk: in STD_LOGIC;
56 59 DataReady : out std_logic;
57 60 smpout : out Samples_out(ChanelCount-1 downto 0);
58 61 AD_in : in AD7688_in(ChanelCount-1 downto 0);
59 62 AD_out : out AD7688_out);
60 63 end component;
61 64
62 65
63 66 component AD7688_spi_if is
64 67 generic(ChanelCount : integer);
65 68 Port( clk : in STD_LOGIC;
66 69 reset : in STD_LOGIC;
67 70 cnv : in STD_LOGIC;
68 71 DataReady: out std_logic;
69 72 sdi : in AD7688_in(ChanelCount-1 downto 0);
70 73 smpout : out Samples_out(ChanelCount-1 downto 0)
71 74 );
72 75 end component;
73 76
74 77
75 78 component lpp_apb_ad_conv
76 79 generic(
77 80 pindex : integer := 0;
78 81 paddr : integer := 0;
79 82 pmask : integer := 16#fff#;
80 83 pirq : integer := 0;
81 84 abits : integer := 8;
82 85 ChanelCount : integer := 1;
83 86 clkkHz : integer := 50000;
84 87 smpClkHz : integer := 100;
85 88 ADCref : integer := AD7688);
86 89 Port (
87 90 clk : in STD_LOGIC;
88 91 reset : in STD_LOGIC;
89 92 apbi : in apb_slv_in_type;
90 93 apbo : out apb_slv_out_type;
91 94 AD_in : in AD7688_in(ChanelCount-1 downto 0);
92 95 AD_out : out AD7688_out);
93 96 end component;
94 97
95 98 component ADS7886_drvr is
96 99 generic(ChanelCount : integer;
97 100 clkkHz : integer);
98 101 Port (
99 102 clk : in STD_LOGIC;
100 103 reset : in STD_LOGIC;
101 104 smplClk : in STD_LOGIC;
102 105 DataReady : out std_logic;
103 106 smpout : out Samples_out(ChanelCount-1 downto 0);
104 107 AD_in : in AD7688_in(ChanelCount-1 downto 0);
105 108 AD_out : out AD7688_out
106 109 );
107 110 end component;
108 111
109 112
110 113 end lpp_ad_conv;
111 114
112 115
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@@ -1,143 +1,146
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.STD_LOGIC_1164.ALL;
21 24 use ieee.numeric_std.all;
22 25 library grlib;
23 26 use grlib.amba.all;
24 27 use grlib.stdlib.all;
25 28 use grlib.devices.all;
26 29 library lpp;
27 30 use lpp.lpp_ad_conv.all;
28 31 use lpp.lpp_amba.all;
29 32 use lpp.apb_devices_list.all;
30 33 use lpp.general_purpose.Clk_divider;
31 34
32 35 entity lpp_apb_ad_conv is
33 36 generic(
34 37 pindex : integer := 0;
35 38 paddr : integer := 0;
36 39 pmask : integer := 16#fff#;
37 40 pirq : integer := 0;
38 41 abits : integer := 8;
39 42 ChanelCount : integer := 1;
40 43 clkkHz : integer := 50000;
41 44 smpClkHz : integer := 100;
42 45 ADCref : integer := AD7688);
43 46 Port (
44 47 clk : in STD_LOGIC;
45 48 reset : in STD_LOGIC;
46 49 apbi : in apb_slv_in_type;
47 50 apbo : out apb_slv_out_type;
48 51 AD_in : in AD7688_in(ChanelCount-1 downto 0);
49 52 AD_out : out AD7688_out);
50 53 end lpp_apb_ad_conv;
51 54
52 55
53 56 architecture ar_lpp_apb_ad_conv of lpp_apb_ad_conv is
54 57 constant REVISION : integer := 1;
55 58
56 59 constant pconfig : apb_config_type := (
57 60 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADC, 0, REVISION, 0),
58 61 1 => apb_iobar(paddr, pmask));
59 62
60 63 signal Rdata : std_logic_vector(31 downto 0);
61 64 signal smpout : Samples_out(ChanelCount-1 downto 0);
62 65 signal smplClk : STD_LOGIC;
63 66 signal DataReady : STD_LOGIC;
64 67
65 68 type lpp_apb_ad_conv_Reg is record
66 69 CTRL_Reg : std_logic_vector(31 downto 0);
67 70 sample : Samples_out(ChanelCount-1 downto 0);
68 71 end record;
69 72
70 73 signal r : lpp_apb_ad_conv_Reg;
71 74
72 75 begin
73 76
74 77
75 78 caseAD7688: if ADCref = AD7688 generate
76 79 AD7688: AD7688_drvr
77 80 generic map(ChanelCount,clkkHz)
78 81 Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out);
79 82 end generate;
80 83
81 84 caseADS786: if ADCref = ADS7886 generate
82 85 ADS7886: ADS7886_drvr
83 86 generic map(ChanelCount,clkkHz)
84 87 Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out);
85 88 end generate;
86 89
87 90
88 91 clkdivider: Clk_divider
89 92 generic map(clkkHz*1000,smpClkHz)
90 93 Port map( clk ,reset,smplClk);
91 94
92 95
93 96
94 97 r.CTRL_Reg(0) <= DataReady;
95 98
96 99 r.sample <= smpout;
97 100
98 101
99 102 process(reset,clk)
100 103 begin
101 104 if reset = '0' then
102 105 --r.CTRL_Reg(9 downto 0) <= (others => '0');
103 106 elsif clk'event and clk = '1' then
104 107
105 108 --APB Write OP
106 109 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
107 110 case apbi.paddr(7 downto 2) is
108 111 when "000000" =>
109 112 --r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0);
110 113 when others =>
111 114 end case;
112 115 end if;
113 116
114 117 --APB READ OP
115 118 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
116 119 case apbi.paddr(7 downto 2) is
117 120 when "000000" =>
118 121 Rdata <= r.CTRL_Reg;
119 122 when others =>
120 123 readC: for i in 1 to ChanelCount loop
121 124 if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
122 125 Rdata(15 downto 0) <= r.sample(i-1)(15 downto 0);
123 126 end if;
124 127 end loop;
125 128 end case;
126 129 end if;
127 130 end if;
128 131 apbo.pconfig <= pconfig;
129 132 end process;
130 133
131 134 apbo.prdata <= Rdata when apbi.penable = '1' ;
132 135
133 136
134 137 end ar_lpp_apb_ad_conv;
135 138
136 139
137 140
138 141
139 142
140 143
141 144
142 145
143 146
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@@ -1,127 +1,130
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 --use ieee.numeric_std.all;
22 25 library grlib;
23 26 use grlib.amba.all;
24 27 use grlib.stdlib.all;
25 28 use grlib.devices.all;
26 29 library lpp;
27 30 use lpp.lpp_amba.all;
28 31
29 32
30 33 entity APB_SIMPLE_DIODE is
31 34 generic (
32 35 pindex : integer := 0;
33 36 paddr : integer := 0;
34 37 pmask : integer := 16#fff#;
35 38 pirq : integer := 0;
36 39 abits : integer := 8);
37 40 port (
38 41 rst : in std_ulogic;
39 42 clk : in std_ulogic;
40 43 apbi : in apb_slv_in_type;
41 44 apbo : out apb_slv_out_type;
42 45 LED : out std_ulogic
43 46 );
44 47 end;
45 48
46 49
47 50 architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
48 51
49 52 constant REVISION : integer := 1;
50 53
51 54 constant pconfig : apb_config_type := (
52 55 0 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0),
53 56 1 => apb_iobar(paddr, pmask));
54 57
55 58
56 59
57 60 type LEDregs is record
58 61 DATAin : std_logic_vector(31 downto 0);
59 62 DATAout : std_logic_vector(31 downto 0);
60 63 end record;
61 64
62 65 signal r : LEDregs;
63 66 signal Rdata : std_logic_vector(31 downto 0);
64 67
65 68 begin
66 69
67 70 r.DATAout <= r.DATAin xor X"FFFFFFFF";
68 71
69 72 process(rst,clk)
70 73 begin
71 74 if rst = '0' then
72 75 LED <= '0';
73 76 r.DATAin <= (others => '0');
74 77
75 78 elsif clk'event and clk = '1' then
76 79
77 80 LED <= r.DATAin(0);
78 81
79 82 --APB Write OP
80 83 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
81 84 case apbi.paddr(abits-1 downto 2) is
82 85 when "000000" =>
83 86 r.DATAin <= apbi.pwdata;
84 87 when others =>
85 88 null;
86 89 end case;
87 90 end if;
88 91
89 92 --APB READ OP
90 93 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
91 94 case apbi.paddr(abits-1 downto 2) is
92 95 when "000000" =>
93 96 Rdata <= r.DATAin;
94 97 when others =>
95 98 Rdata <= r.DATAout;
96 99 end case;
97 100 end if;
98 101
99 102 end if;
100 103 apbo.pconfig <= pconfig;
101 104 end process;
102 105
103 106 apbo.prdata <= Rdata when apbi.penable = '1';
104 107
105 108 -- pragma translate_off
106 109 -- bootmsg : report_version
107 110 -- generic map ("apbuart" & tost(pindex) &
108 111 -- ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
109 112 -- ", irq " & tost(pirq));
110 113 -- pragma translate_on
111 114
112 115
113 116
114 117 end ar_APB_SIMPLE_DIODE;
115 118
116 119
117 120
118 121
119 122
120 123
121 124
122 125
123 126
124 127
125 128
126 129
127 130
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@@ -1,79 +1,82
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 library grlib;
22 25 use grlib.amba.all;
23 26 use std.textio.all;
24 27
25 28
26 29
27 30 package lpp_amba is
28 31
29 32 component APB_CHENILLARD is
30 33 generic (
31 34 pindex : integer := 0;
32 35 paddr : integer := 0;
33 36 pmask : integer := 16#fff#;
34 37 pirq : integer := 0;
35 38 abits : integer := 8);
36 39 port (
37 40 rst : in std_ulogic;
38 41 clk : in std_ulogic;
39 42 RegLed : in std_logic_vector (7 downto 0);
40 43 apbi : in apb_slv_in_type;
41 44 apbo : out apb_slv_out_type;
42 45 Leds : out std_logic_vector (7 downto 0)
43 46 );
44 47 end component;
45 48
46 49 component APB_SIMPLE_DIODE is
47 50 generic (
48 51 pindex : integer := 0;
49 52 paddr : integer := 0;
50 53 pmask : integer := 16#fff#;
51 54 pirq : integer := 0;
52 55 abits : integer := 8);
53 56 port (
54 57 rst : in std_ulogic;
55 58 clk : in std_ulogic;
56 59 apbi : in apb_slv_in_type;
57 60 apbo : out apb_slv_out_type;
58 61 LED : out std_ulogic
59 62 );
60 63 end component;
61 64
62 65
63 66 component APB_MULTI_DIODE is
64 67 generic (
65 68 pindex : integer := 0;
66 69 paddr : integer := 0;
67 70 pmask : integer := 16#fff#;
68 71 pirq : integer := 0;
69 72 abits : integer := 8);
70 73 port (
71 74 rst : in std_ulogic;
72 75 clk : in std_ulogic;
73 76 apbi : in apb_slv_in_type;
74 77 apbo : out apb_slv_out_type;
75 78 LED : out std_logic_vector(2 downto 0)
76 79 );
77 80 end component;
78 81
79 82 end;
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@@ -1,5 +1,6
1 apb_devices_list.vhd
1 2 APB_MULTI_DIODE.vhd
2 3 APB_MULTI_DIODE.vhd.orig
3 4 APB_SIMPLE_DIODE.vhd
4 5 APB_SIMPLE_DIODE.vhd.orig
5 6 lpp_amba.vhd
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@@ -1,101 +1,119
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
1 19 -- APB_CNA.vhd
2 20
3 21 library ieee;
4 22 use ieee.std_logic_1164.all;
5 23 library grlib;
6 24 use grlib.amba.all;
7 25 use grlib.stdlib.all;
8 26 use grlib.devices.all;
9 27 library lpp;
10 28 use lpp.lpp_amba.all;
11 29 use lpp.apb_devices_list.all;
12 30 use lpp.lpp_cna.all;
13 31
14 32
15 33 entity APB_CNA is
16 34 generic (
17 35 pindex : integer := 0;
18 36 paddr : integer := 0;
19 37 pmask : integer := 16#fff#;
20 38 pirq : integer := 0;
21 39 abits : integer := 8);
22 40 port (
23 41 clk : in std_logic;
24 42 rst : in std_logic;
25 43 apbi : in apb_slv_in_type;
26 44 apbo : out apb_slv_out_type;
27 45 SYNC : out std_logic;
28 46 SCLK : out std_logic;
29 47 DATA : out std_logic
30 48 );
31 49 end APB_CNA;
32 50
33 51
34 52 architecture ar_APB_CNA of APB_CNA is
35 53
36 54 constant REVISION : integer := 1;
37 55
38 56 constant pconfig : apb_config_type := (
39 57 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
40 58 1 => apb_iobar(paddr, pmask));
41 59
42 60 signal enable : std_logic;
43 61 signal flag_sd : std_logic;
44 62
45 63 type CNA_ctrlr_Reg is record
46 64 CNA_Cfg : std_logic_vector(1 downto 0);
47 65 CNA_Data : std_logic_vector(15 downto 0);
48 66 end record;
49 67
50 68 signal Rec : CNA_ctrlr_Reg;
51 69 signal Rdata : std_logic_vector(31 downto 0);
52 70
53 71 begin
54 72
55 73 enable <= Rec.CNA_Cfg(0);
56 74 Rec.CNA_Cfg(1) <= flag_sd;
57 75
58 76 CONVERTER : entity Work.CNA_TabloC
59 77 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
60 78
61 79
62 80 process(rst,clk)
63 81 begin
64 82 if(rst='0')then
65 83 Rec.CNA_Data <= (others => '0');
66 84
67 85 elsif(clk'event and clk='1')then
68 86
69 87
70 88 --APB Write OP
71 89 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
72 90 case apbi.paddr(abits-1 downto 2) is
73 91 when "000000" =>
74 92 Rec.CNA_Cfg(0) <= apbi.pwdata(0);
75 93 when "000001" =>
76 94 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
77 95 when others =>
78 96 null;
79 97 end case;
80 98 end if;
81 99
82 100 --APB READ OP
83 101 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
84 102 case apbi.paddr(abits-1 downto 2) is
85 103 when "000000" =>
86 104 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
87 105 Rdata(1 downto 0) <= Rec.CNA_Cfg;
88 106 when "000001" =>
89 107 Rdata(31 downto 16) <= X"FD18";
90 108 Rdata(15 downto 0) <= Rec.CNA_Data;
91 109 when others =>
92 110 Rdata <= (others => '0');
93 111 end case;
94 112 end if;
95 113
96 114 end if;
97 115 apbo.pconfig <= pconfig;
98 116 end process;
99 117
100 118 apbo.prdata <= Rdata when apbi.penable = '1';
101 119 end ar_APB_CNA;
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@@ -1,67 +1,85
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
1 19 -- CNA_TabloC.vhd
2 20 library IEEE;
3 21 use IEEE.std_logic_1164.all;
4 22 use IEEE.numeric_std.all;
5 23 use work.Convertisseur_config.all;
6 24
7 25 entity CNA_TabloC is
8 26 port(
9 27 clock : in std_logic;
10 28 rst : in std_logic;
11 29 enable : in std_logic;
12 30 --bp : in std_logic;
13 31 Data_C : in std_logic_vector(15 downto 0);
14 32 SYNC : out std_logic;
15 33 SCLK : out std_logic;
16 34 --Rz : out std_logic;
17 35 flag_sd : out std_logic;
18 36 Data : out std_logic
19 37 );
20 38 end CNA_TabloC;
21 39
22 40
23 41 architecture ar_CNA_TabloC of CNA_TabloC is
24 42
25 43 component CLKINT
26 44 port( A : in std_logic := 'U';
27 45 Y : out std_logic);
28 46 end component;
29 47
30 48 signal clk : std_logic;
31 49
32 50 signal raz : std_logic;
33 51 signal s_SCLK : std_logic;
34 52 signal OKAI_send : std_logic;
35 53 --signal Data_int : std_logic_vector(15 downto 0);
36 54
37 55 begin
38 56
39 57
40 58 CLKINT_0 : CLKINT
41 59 port map(A => clock, Y => clk);
42 60
43 61 CLKINT_1 : CLKINT
44 62 port map(A => rst, Y => raz);
45 63
46 64
47 65 SystemCLK : entity work.Systeme_Clock
48 66 generic map (nb_serial)
49 67 port map (clk,raz,s_SCLK);
50 68
51 69
52 70 Signal_sync : entity work.Gene_SYNC
53 71 port map (s_SCLK,raz,enable,OKAI_send,SYNC);
54 72
55 73
56 74 Serial : entity work.serialize
57 75 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
58 76
59 77
60 78 --Rz <= raz;
61 79 SCLK <= s_SCLK;
62 80
63 81 --with bp select
64 82 -- Data_int <= X"9555" when '1',
65 83 -- Data_C when others;
66 84
67 85 end ar_CNA_TabloC; No newline at end of file
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@@ -1,24 +1,42
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
1 19 -- Convertisseur_config.vhd
2 20 library IEEE;
3 21 use IEEE.std_logic_1164.all;
4 22 use IEEE.numeric_std.all;
5 23
6 24 Package Convertisseur_config is
7 25
8 26
9 27 --===========================================================|
10 28 --================= Valeurs Sinus 1Khz ======================|
11 29 --===========================================================|
12 30 type Tbl is array(natural range <>) of std_logic_vector(11 downto 0);
13 31 constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF");
14 32
15 33 --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80");
16 34
17 35
18 36 --===========================================================|
19 37 --============= Fr�quence de s�rialisation ==================|
20 38 --===========================================================|
21 39 constant Freq_serial : integer := 5_000_000;
22 40 constant nb_serial : integer := 30_000_000 / Freq_serial;
23 41
24 42 end; No newline at end of file
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@@ -1,53 +1,71
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
1 19 -- Gene_SYNC.vhd
2 20 library IEEE;
3 21 use IEEE.std_logic_1164.all;
4 22 use IEEE.numeric_std.all;
5 23
6 24 entity Gene_SYNC is
7 25
8 26 port(
9 27 SCLK,raz : in std_logic;
10 28 enable : in std_logic;
11 29 -- Sysclk : in std_logic;
12 30 OKAI_send : out std_logic;
13 31 SYNC : out std_logic
14 32 );
15 33
16 34 end Gene_SYNC;
17 35
18 36
19 37 architecture ar_Gene_SYNC of Gene_SYNC is
20 38
21 39 --signal Sysclk_reg : std_logic;
22 40 signal count : integer;
23 41
24 42
25 43 begin
26 44 process (SCLK,raz)
27 45 begin
28 46 if(raz='0')then
29 47 SYNC <= '0';
30 48 -- Sysclk_reg <= '0';
31 49 count <= 14;
32 50 OKAI_send <= '0';
33 51
34 52 elsif(SCLK' event and SCLK='1')then
35 53 if(enable='1')then
36 54
37 55 -- Sysclk_reg <= Sysclk;
38 56 if(count=15)then
39 57 SYNC <= '1';
40 58 count <= count+1;
41 59 elsif(count=16)then
42 60 count <= 0;
43 61 SYNC <= '0';
44 62 OKAI_send <= '1';
45 63 else
46 64 count <= count+1;
47 65 OKAI_send <= '0';
48 66 end if;
49 67 end if;
50 68 end if;
51 69 end process;
52 70
53 71 end ar_Gene_SYNC; No newline at end of file
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@@ -1,86 +1,104
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
1 19 -- Serialize.vhd
2 20 library IEEE;
3 21 use IEEE.numeric_std.all;
4 22 use IEEE.std_logic_1164.all;
5 23
6 24 entity Serialize is
7 25
8 26 port(
9 27 clk,raz : in std_logic;
10 28 sclk : in std_logic;
11 29 vectin : in std_logic_vector(15 downto 0);
12 30 send : in std_logic;
13 31 sended : out std_logic;
14 32 Data : out std_logic);
15 33
16 34 end Serialize;
17 35
18 36
19 37 architecture ar_Serialize of Serialize is
20 38
21 39 type etat is (attente,serialize);
22 40 signal ect : etat;
23 41
24 42 signal vector_int : std_logic_vector(16 downto 0);
25 43 signal vectin_reg : std_logic_vector(15 downto 0);
26 44 signal load : std_logic;
27 45 signal N : integer range 0 to 16;
28 46 signal CPT_ended : std_logic:='0';
29 47
30 48 begin
31 49 process(clk,raz)
32 50 begin
33 51 if(raz='0')then
34 52 ect <= attente;
35 53 vectin_reg <= (others=> '0');
36 54 load <= '0';
37 55 sended <= '1';
38 56
39 57 elsif(clk'event and clk='1')then
40 58 vectin_reg <= vectin;
41 59
42 60 case ect is
43 61 when attente =>
44 62 if (send='1') then
45 63 sended <= '0';
46 64 load <= '1';
47 65 ect <= serialize;
48 66 else
49 67 ect <= attente;
50 68 end if;
51 69
52 70 when serialize =>
53 71 load <= '0';
54 72 if(CPT_ended='1')then
55 73 ect <= attente;
56 74 sended <= '1';
57 75 end if;
58 76
59 77 end case;
60 78 end if;
61 79 end process;
62 80
63 81 process(sclk,load,raz)
64 82 begin
65 83 if (raz='0')then
66 84 vector_int <= (others=> '0');
67 85 N <= 16;
68 86 elsif(load='1')then
69 87 vector_int <= vectin & '0';
70 88 N <= 0;
71 89 elsif(sclk'event and sclk='1')then
72 90 if (CPT_ended='0') then
73 91 vector_int <= vector_int(15 downto 0) & '0';
74 92 N <= N+1;
75 93 end if;
76 94 end if;
77 95 end process;
78 96
79 97 CPT_ended <= '1' when N = 16 else '0';
80 98
81 99 with ect select
82 100 Data <= vector_int(16) when serialize,
83 101 '0' when others;
84 102
85 103 end ar_Serialize;
86 104
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@@ -1,40 +1,58
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
1 19 -- Systeme_Clock.vhd
2 20 library IEEE;
3 21 use IEEE.std_logic_1164.all;
4 22 use IEEE.numeric_std.all;
5 23
6 24 --! Programme qui va permetre de g�n�rer l'horloge systeme (sclk)
7 25
8 26 entity Systeme_Clock is
9 27 generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk
10 28 port(
11 29 clk, raz : in std_logic; --! Horloge et Reset globale
12 30 sclk : out std_logic --! Horloge Systeme g�n�r�e
13 31 );
14 32 end Systeme_Clock;
15 33
16 34 --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
17 35 architecture ar_Systeme_Clock of Systeme_Clock is
18 36
19 37 signal clockint : std_logic;
20 38 signal countint : integer range 0 to N/2-1;
21 39
22 40 begin
23 41 process (clk,raz)
24 42 begin
25 43 if(raz = '0') then
26 44 countint <= 0;
27 45 clockint <= '0';
28 46 elsif (clk' event and clk='1') then
29 47 if (countint = N/2-1) then
30 48 countint <= 0;
31 49 clockint <= not clockint;
32 50 else
33 51 countint <= countint+1;
34 52 end if;
35 53 end if;
36 54 end process;
37 55
38 56 sclk <= clockint;
39 57
40 58 end ar_Systeme_Clock; No newline at end of file
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@@ -1,77 +1,95
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
1 19 library ieee;
2 20 use ieee.std_logic_1164.all;
3 21 library grlib;
4 22 use grlib.amba.all;
5 23 -- pragma translate_off
6 24 use std.textio.all;
7 25 -- pragma translate_on
8 26 library lpp;
9 27 use lpp.lpp_amba.all;
10 28
11 29
12 30 package lpp_cna is
13 31
14 32 component APB_CNA is
15 33 generic (
16 34 pindex : integer := 0;
17 35 paddr : integer := 0;
18 36 pmask : integer := 16#fff#;
19 37 pirq : integer := 0;
20 38 abits : integer := 8);
21 39 port (
22 40 clk : in std_logic;
23 41 rst : in std_logic;
24 42 apbi : in apb_slv_in_type;
25 43 apbo : out apb_slv_out_type;
26 44 SYNC : out std_logic;
27 45 SCLK : out std_logic;
28 46 DATA : out std_logic
29 47 );
30 48 end component;
31 49
32 50
33 51 component CNA_TabloC is
34 52 port(
35 53 clock : in std_logic;
36 54 rst : in std_logic;
37 55 flag_nw : in std_logic;
38 56 bp : in std_logic;
39 57 Data_C : in std_logic_vector(15 downto 0);
40 58 SYNC : out std_logic;
41 59 SCLK : out std_logic;
42 60 Rz : out std_logic;
43 61 flag_sd : out std_logic;
44 62 Data : out std_logic
45 63 );
46 64 end component;
47 65
48 66
49 67 component Systeme_Clock is
50 68 generic(N :integer := 695);
51 69 port(
52 70 clk, raz : in std_logic ;
53 71 clock : out std_logic);
54 72 end component;
55 73
56 74
57 75 component Gene_SYNC is
58 76 port(
59 77 clk,raz : in std_logic;
60 78 send : in std_logic;
61 79 Sysclk : in std_logic;
62 80 OKAI_send : out std_logic;
63 81 SYNC : out std_logic);
64 82 end component;
65 83
66 84
67 85 component Serialize is
68 86 port(
69 87 clk,raz : in std_logic;
70 88 sclk : in std_logic;
71 89 vectin : in std_logic_vector(15 downto 0);
72 90 send : in std_logic;
73 91 sended : out std_logic;
74 92 Data : out std_logic);
75 93 end component;
76 94
77 95 end;
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@@ -1,99 +1,102
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25
23 26 --! Generateur de Bauds
24 27
25 28 entity BaudGen is
26 29
27 30 port(
28 31 clk : in std_logic;
29 32 reset : in std_logic;
30 33 Capture : in std_logic;
31 34 Bclk : out std_logic;
32 35 RXD : in std_logic;
33 36 BTrigger : out std_logic_vector(11 downto 0)
34 37 );
35 38 end BaudGen;
36 39
37 40
38 41 architecture ar_BaudGen of BaudGen is
39 42 signal cpt : std_logic_vector(11 downto 0) := (others => '0');
40 43 signal errorFlag : std_logic;
41 44 signal triger : std_logic_vector(11 downto 0) := (others => '0');
42 45 signal RX_reg : std_logic:='1';
43 46
44 47 begin
45 48
46 49
47 50 BTrigger <= triger;
48 51
49 52
50 53 BaudGeneration:
51 54 process(clk,reset)
52 55 begin
53 56 if reset = '0' then
54 57 cpt <= (others => '0');
55 58 triger <= (others => '1');
56 59 errorFlag <= '0';
57 60 elsif clk'event and clk = '1'then
58 61 RX_reg <= RXD;
59 62 if capture = '1' then
60 63 cpt <= (others => '0');
61 64 triger <= (others => '1');
62 65 errorFlag <= '0';
63 66 else
64 67 if RX_reg /= RXD then
65 68 cpt <= (others => '0');
66 69 if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then
67 70 errorFlag <= '1';
68 71 elsif errorFlag = '1' then
69 72 triger <= cpt;
70 73 errorFlag <= '0';
71 74 else
72 75 errorFlag <= '1';
73 76 end if;
74 77 else
75 78 if cpt = triger then
76 79 cpt <= (others => '0');
77 80 errorFlag <= '0';
78 81 else
79 82 cpt <= std_logic_vector(unsigned(cpt) + 1);
80 83 end if;
81 84 end if;
82 85 end if;
83 86 end if;
84 87 end process;
85 88
86 89
87 90 process(clk)
88 91 begin
89 92 if clk'event and clk = '1' then
90 93 if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then
91 94 Bclk <= '0';
92 95 elsif cpt = '0' & triger(11 downto 1) then
93 96 Bclk <= '1';
94 97 end if;
95 98 end if;
96 99 end process;
97 100
98 101
99 102 end ar_BaudGen;
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@@ -1,109 +1,112
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25
23 26 --! Gestion Reception/Transmission
24 27
25 28 entity Shift_REG is
26 29 generic(Data_sz : integer := 10);
27 30 port(
28 31 clk : in std_logic;
29 32 Sclk : in std_logic;
30 33 reset : in std_logic;
31 34 SIN : in std_logic;
32 35 SOUT : out std_logic;
33 36 Serialize : in std_logic;
34 37 Serialized : out std_logic;
35 38 D : in std_logic_vector(Data_sz-1 downto 0);
36 39 Q : out std_logic_vector(Data_sz-1 downto 0)
37 40 );
38 41 end entity;
39 42
40 43
41 44 architecture ar_Shift_REG of Shift_REG is
42 45
43 46 signal REG : std_logic_vector(Data_sz-1 downto 0);
44 47 signal Serialized_int : std_logic;
45 48 signal Serialize_reg : std_logic;
46 49 signal CptBits : std_logic_vector(Data_sz-1 downto 0);
47 50 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
48 51 signal CptBits_flag : std_logic;
49 52 signal CptBits_flag_reg : std_logic;
50 53
51 54 begin
52 55
53 56 Serialized <= Serialized_int;
54 57 CptBits_flag <= '1' when CptBits = CptBits_trig else '0';
55 58
56 59 process(reset,clk)
57 60 begin
58 61 if reset = '0' then
59 62 Serialized_int <= '1';
60 63 CptBits_flag_reg <= '0';
61 64 Q <= (others => '0');
62 65 elsif clk'event and clk = '1' then
63 66 CptBits_flag_reg <= CptBits_flag;
64 67
65 68 if CptBits_flag = '1' and CptBits_flag_reg = '0' then
66 69 Serialized_int <= '1';
67 70 Q <= REG;
68 71 elsif Serialize = '1' then
69 72 Serialized_int <= '0';
70 73 end if;
71 74 end if;
72 75 end process;
73 76
74 77
75 78 process(reset,Sclk)
76 79 begin
77 80 if reset = '0' then
78 81 CptBits <= (others => '0');
79 82 REG <= (others => '0');
80 83 SOUT <= '1';
81 84 Serialize_reg <= '0';
82 85 elsif Sclk'event and Sclk = '1' then
83 86 Serialize_reg <= Serialized_int;
84 87 if (Serialized_int = '0' and Serialize_reg ='1') then
85 88 REG <= SIN & D(Data_sz-1 downto 1);
86 89 SOUT <= D(0);
87 90 elsif CptBits_flag ='1' then
88 91 REG <= SIN & D(Data_sz-1 downto 1);
89 92 SOUT <= D(0);
90 93 elsif Serialized_int = '0' then
91 94 REG <= SIN & REG(Data_sz-1 downto 1);
92 95 SOUT <= REG(0);
93 96 else
94 97 SOUT <= '1';
95 98 end if;
96 99 if Serialized_int = '0' then
97 100 if CptBits_flag = '1' then
98 101 CptBits <= (others => '0');
99 102 else
100 103 CptBits <= '1' & CptBits(Data_sz-1 downto 1);
101 104 end if;
102 105 else
103 106 CptBits <= (others => '0');
104 107 end if;
105 108
106 109 end if;
107 110 end process;
108 111
109 112 end ar_Shift_REG;
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@@ -1,103 +1,106
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
19 22 library IEEE;
20 23 use IEEE.numeric_std.all;
21 24 use IEEE.std_logic_1164.all;
22 25 library lpp;
23 26 use lpp.lpp_uart.all;
24 27
25 28 --! Programme qui va gerer toute la communication entre le PC et le FPGA
26 29
27 30 entity UART is
28 31 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
29 32 port(
30 33 clk : in std_logic; --! Horloge a 25Mhz du systeme
31 34 reset : in std_logic; --! Reset du systeme
32 35 TXD : out std_logic; --! Transmission, cote PC
33 36 RXD : in std_logic; --! Reception, cote PC
34 37 Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
35 38 NwDat : out std_logic; --! Flag, Nouvelle donnee presente
36 39 ACK : in std_logic; --! Flag, Reponse au flag precedent
37 40 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
38 41 Sended : out std_logic; --! Flag, Envoi termine
39 42 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
40 43 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
41 44 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
42 45 );
43 46 end entity;
44 47
45 48
46 49 --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
47 50 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
48 51 architecture ar_UART of UART is
49 52 signal Bclk : std_logic;
50 53
51 54 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
52 55 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
53 56
54 57 signal TXD_Dummy : std_logic;
55 58 signal NwDat_int : std_logic;
56 59 signal NwDat_int_reg : std_logic;
57 60 signal receive : std_logic;
58 61 constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0');
59 62
60 63 begin
61 64
62 65
63 66
64 67 WDATA_int <= '1' & WDATA & '0';
65 68
66 69 BaudGenerator : BaudGen
67 70 port map(clk,reset,Capture,Bclk,RXD,BTrigger);
68 71
69 72
70 73 RX_REG : Shift_REG
71 74 generic map(Data_sz+2)
72 75 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int);
73 76
74 77 TX_REG : Shift_REG
75 78 generic map(Data_sz+2)
76 79 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
77 80
78 81
79 82
80 83 process(clk,reset)
81 84 begin
82 85 if reset = '0' then
83 86 NwDat <= '0';
84 87 elsif clk'event and clk = '1' then
85 88 NwDat_int_reg <= NwDat_int;
86 89 if RXD = '1' and NwDat_int = '1' then
87 90 receive <= '0';
88 91 elsif RXD = '0' then
89 92 receive <= '1';
90 93 end if;
91 94 if NwDat_int_reg = '0' and NwDat_int = '1' then
92 95 NwDat <= '1';
93 96 RDATA <= RDATA_int(8 downto 1);
94 97 elsif ack = '1' then
95 98 NwDat <= '0';
96 99 end if;
97 100 end if;
98 101 end process;
99 102
100 103 end ar_UART;
101 104
102 105
103 106
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@@ -1,77 +1,77
1 1 echo "======================================================================================="
2 2 echo "---------------------------------------------------------------------------------------"
3 3 echo " LPP VHDL APB Devices List Updater "
4 4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 5 echo "======================================================================================="
6 6 echo '----------------------------------------------------------------------------------------
7 7 This file is a part of the LPP VHDL IP LIBRARY
8 8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9 9
10 10 This program is free software; you can redistribute it and/or modify
11 11 it under the terms of the GNU General Public License as published by
12 12 the Free Software Foundation; either version 3 of the License, or
13 13 (at your option) any later version.
14 14
15 15 This program is distributed in the hope that it will be useful,
16 16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 18 GNU General Public License for more details.
19 19
20 20 You should have received a copy of the GNU General Public License
21 21 along with this program; if not, write to the Free Software
22 22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 23 ----------------------------------------------------------------------------------------'
24 24 echo
25 25 echo
26 26 echo
27 27
28 28 LPP_PATCHPATH=`pwd -L`
29 29
30 30 cd $LPP_PATCHPATH/lib/lpp
31 31
32 32
33 33 VHDFileStart=$LPP_PATCHPATH/APB_DEVICES/VHDListSTART
34 34 VHDFileEnd=$LPP_PATCHPATH/APB_DEVICES/VHDListEND
35 35
36 36 CFileStart=$LPP_PATCHPATH/APB_DEVICES/CListSTART
37 37 CFileEnd=$LPP_PATCHPATH/APB_DEVICES/CListEND
38 38
39 39 ListFILE=$LPP_PATCHPATH/APB_DEVICES/apb_devices_list.txt
40 40
41 41 VHDListFILE=$LPP_PATCHPATH/lib/lpp/lpp_amba/apb_devices_list.vhd
42 42 CListFILE=$LPP_PATCHPATH/LPP_drivers/libsrc/AMBA/apb_devices_list.h
43 43
44 44
45 45 cat $VHDFileStart>$VHDListFILE
46 46 cat $CFileStart>$CListFILE
47 47
48 grep vendor $ListFILE | sed "s/vendor /constant /" | sed "s/.* /& : amba_vendor_type := 16#/" | sed "s/.*#*/&;/" >> $VHDListFILE
48 grep vendor $ListFILE | sed "s/vendor /constant /" | sed "s/.* /& : amba_vendor_type := 16#/" | sed "s/.*#*/&#;/" >> $VHDListFILE
49 49 grep vendor $ListFILE | sed "s/vendor /#define /" | sed "s/.* /& 0x/" >> $CListFILE
50 50
51 51 echo " ">>$VHDListFILE
52 52 echo " ">>$CListFILE
53 53
54 grep device $ListFILE | sed "s/device /constant /" | sed "s/.* /& : amba_device_type := 16#/" | sed "s/.*#*/&;/" >> $VHDListFILE
54 grep device $ListFILE | sed "s/device /constant /" | sed "s/.* /& : amba_device_type := 16#/" | sed "s/.*#*/&#;/" >> $VHDListFILE
55 55 grep device $ListFILE | sed "s/device /#define /" | sed "s/.* /& 0x/" >> $CListFILE
56 56
57 57 cat $VHDFileEnd>>$VHDListFILE
58 58 cat $CFileEnd>>$CListFILE
59 59
60 sh $(SCRIPTSDIR)/GPL_Patcher.sh vhd lib/lpp/lpp_amba/
61 sh $(SCRIPTSDIR)/GPL_Patcher.sh h LPP_drivers/libsrc/AMBA/
60 sh $LPP_PATCHPATH/scripts/GPL_Patcher.sh vhd $LPP_PATCHPATH/lib/lpp/lpp_amba/
61 sh $LPP_PATCHPATH/scripts/GPL_Patcher.sh h $LPP_PATCHPATH/LPP_drivers/libsrc/AMBA/
62 62
63 63 cd $LPP_PATCHPATH
64 64
65 65
66 66
67 67
68 68
69 69
70 70
71 71
72 72
73 73
74 74
75 75
76 76
77 77
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