HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_cna/Systeme_Clock.vhd

Fixed some files

martin - - Load All Authors

File last commit:

r29:4c437dd190b1 default


                r37:81e639333c9d

default

Download file

             Systeme_Clock.vhd
        
                    39 lines
            
             | 1.1 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / lib / lpp / lpp_cna / Systeme_Clock.vhd
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      -- Systeme_Clock.vhd

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      --! Programme qui va permetre de g�n�rer l'horloge systeme (sclk)

      entity Systeme_Clock is

      generic(N :integer := 695);   --! G�n�rique contenant le r�sultat de la division clk/sclk

      port( 

          clk, raz   : in std_logic;   --! Horloge et Reset globale

          sclk       : out std_logic   --! Horloge Systeme g�n�r�e

      );

      end Systeme_Clock;

      --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois

      architecture ar_Systeme_Clock of Systeme_Clock is

      signal clockint : std_logic;

      signal countint : integer range 0 to N/2-1;

      begin 

          process (clk,raz)

              begin

              if(raz = '0') then

                  countint <= 0;

                  clockint <= '0';

              elsif (clk' event and clk='1') then

                  if (countint = N/2-1) then 

                      countint <= 0;

                      clockint <= not clockint;

                  else 

                      countint <= countint+1;

                  end if;

              end if;

          end process;

      sclk <= clockint;

      end ar_Systeme_Clock;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

				-- Systeme_Clock.vhd
				library IEEE;
				use IEEE.std_logic_1164.all;
				use IEEE.numeric_std.all;

				--! Programme qui va permetre de g�n�rer l'horloge systeme (sclk)

				entity Systeme_Clock is
				generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk
				port(
				clk, raz : in std_logic; --! Horloge et Reset globale
				sclk : out std_logic --! Horloge Systeme g�n�r�e
				);
				end Systeme_Clock;

				--! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
				architecture ar_Systeme_Clock of Systeme_Clock is

				signal clockint : std_logic;
				signal countint : integer range 0 to N/2-1;

				begin
				process (clk,raz)
				begin
				if(raz = '0') then
				countint <= 0;
				clockint <= '0';
				elsif (clk' event and clk='1') then
				if (countint = N/2-1) then
				countint <= 0;
				clockint <= not clockint;
				else
				countint <= countint+1;
				end if;
				end if;
				end process;

				sclk <= clockint;

				end ar_Systeme_Clock;