1 | NO CONTENT: new file 100644, binary diff hidden |
|
NO CONTENT: new file 100644, binary diff hidden |
@@ -1,18 +1,18 | |||||
1 |
|
1 | |||
2 | --================================================================================= |
|
2 | --================================================================================= | |
3 | --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT |
|
3 | --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT | |
4 | -- |
|
4 | -- | |
5 | --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID |
|
5 | --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID | |
6 | --================================================================================= |
|
6 | --================================================================================= | |
7 |
|
7 | |||
8 |
|
8 | |||
9 | library ieee; |
|
9 | library ieee; | |
10 | use ieee.std_logic_1164.all; |
|
10 | use ieee.std_logic_1164.all; | |
11 | library grlib; |
|
11 | library grlib; | |
12 | use grlib.amba.all; |
|
12 | use grlib.amba.all; | |
13 | use std.textio.all; |
|
13 | use std.textio.all; | |
14 |
|
14 | |||
15 |
|
15 | |||
16 |
package |
|
16 | package apb_devices_list is | |
17 |
|
17 | |||
18 |
|
18 |
@@ -1,59 +1,80 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
|
19 | /*-- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ----------------------------------------------------------------------------*/ | |||
1 | #include "stdio.h" |
|
22 | #include "stdio.h" | |
2 | #include "lpp_apb_functions.h" |
|
23 | #include "lpp_apb_functions.h" | |
3 | #include "apb_lcd_driver.h" |
|
24 | #include "apb_lcd_driver.h" | |
4 |
|
25 | |||
5 |
|
26 | |||
6 |
|
27 | |||
7 | int main() |
|
28 | int main() | |
8 | { |
|
29 | { | |
9 | lcd_device* lcd0; |
|
30 | lcd_device* lcd0; | |
10 | struct apbdevinfo lcd0info; |
|
31 | struct apbdevinfo lcd0info; | |
11 | lcd0 = lcdopen(0); |
|
32 | lcd0 = lcdopen(0); | |
12 | char message[lcdCharCnt+1]; |
|
33 | char message[lcdCharCnt+1]; | |
13 | if(lcd0!= NULL) |
|
34 | if(lcd0!= NULL) | |
14 | { |
|
35 | { | |
15 | apbgetdeviceinfofromid(LPP_LCD_CTRLR,VENDOR_LPP,0,&lcd0info); |
|
36 | apbgetdeviceinfofromid(LPP_LCD_CTRLR,VENDOR_LPP,0,&lcd0info); | |
16 | printf("find lcd device @ %8x\n",(int)lcd0); |
|
37 | printf("find lcd device @ %8x\n",(int)lcd0); | |
17 | apbprintdeviceinfo(lcd0info); |
|
38 | apbprintdeviceinfo(lcd0info); | |
18 | } |
|
39 | } | |
19 |
|
40 | |||
20 | printf("hello\n"); |
|
41 | printf("hello\n"); | |
21 | lcdclear(lcd0); |
|
42 | lcdclear(lcd0); | |
22 | int d=0; |
|
43 | int d=0; | |
23 | while(d!=10) |
|
44 | while(d!=10) | |
24 | { |
|
45 | { | |
25 | scanf("%d",&d); |
|
46 | scanf("%d",&d); | |
26 | switch(d) |
|
47 | switch(d) | |
27 | { |
|
48 | { | |
28 | case 0: |
|
49 | case 0: | |
29 | lcdsendcmd(lcd0,CursorOFF&lcd_100us); |
|
50 | lcdsendcmd(lcd0,CursorOFF&lcd_100us); | |
30 | printf("cursor OFF \n"); |
|
51 | printf("cursor OFF \n"); | |
31 | sprintf(message,"cursor OFF %d",d); |
|
52 | sprintf(message,"cursor OFF %d",d); | |
32 | lcdprint(lcd0,0,message); |
|
53 | lcdprint(lcd0,0,message); | |
33 | break; |
|
54 | break; | |
34 | case 1: |
|
55 | case 1: | |
35 | lcdsendcmd(lcd0,CursorON&lcd_100us); |
|
56 | lcdsendcmd(lcd0,CursorON&lcd_100us); | |
36 | printf("cursor ON \n"); |
|
57 | printf("cursor ON \n"); | |
37 | sprintf(message,"cursor ON %d ",d); |
|
58 | sprintf(message,"cursor ON %d ",d); | |
38 | lcdprint(lcd0,0,message); |
|
59 | lcdprint(lcd0,0,message); | |
39 | break; |
|
60 | break; | |
40 | case 2: |
|
61 | case 2: | |
41 | sprintf(message,"Test line 2_%d\nline2",d); |
|
62 | sprintf(message,"Test line 2_%d\nline2",d); | |
42 | lcdprint(lcd0,0,message); |
|
63 | lcdprint(lcd0,0,message); | |
43 | break; |
|
64 | break; | |
44 | case 3: |
|
65 | case 3: | |
45 | apbprintdeviceslist(); |
|
66 | apbprintdeviceslist(); | |
46 | break; |
|
67 | break; | |
47 | case 10: |
|
68 | case 10: | |
48 | sprintf(message,"QUIT %d ",d); |
|
69 | sprintf(message,"QUIT %d ",d); | |
49 | lcdprint(lcd0,0,message); |
|
70 | lcdprint(lcd0,0,message); | |
50 | return 0; |
|
71 | return 0; | |
51 | break; |
|
72 | break; | |
52 | default: |
|
73 | default: | |
53 | sprintf(message,"Not a CMD %d ",d); |
|
74 | sprintf(message,"Not a CMD %d ",d); | |
54 | lcdprint(lcd0,0,message); |
|
75 | lcdprint(lcd0,0,message); | |
55 | break; |
|
76 | break; | |
56 | } |
|
77 | } | |
57 | } |
|
78 | } | |
58 | return 0; |
|
79 | return 0; | |
59 | } |
|
80 | } |
@@ -1,33 +1,51 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
1 | #include "stdio.h" |
|
19 | #include "stdio.h" | |
2 | #include "lpp_apb_functions.h" |
|
20 | #include "lpp_apb_functions.h" | |
3 |
|
21 | |||
4 |
|
22 | |||
5 |
|
23 | |||
6 | int main() |
|
24 | int main() | |
7 | { |
|
25 | { | |
8 | int d=0; |
|
26 | int d=0; | |
9 | while(d!=10) |
|
27 | while(d!=10) | |
10 | { |
|
28 | { | |
11 | scanf("%d",&d); |
|
29 | scanf("%d",&d); | |
12 | switch(d) |
|
30 | switch(d) | |
13 | { |
|
31 | { | |
14 | case 0: |
|
32 | case 0: | |
15 | printf("cursor OFF \n"); |
|
33 | printf("cursor OFF \n"); | |
16 | break; |
|
34 | break; | |
17 | case 1: |
|
35 | case 1: | |
18 | printf("cursor ON \n"); |
|
36 | printf("cursor ON \n"); | |
19 | break; |
|
37 | break; | |
20 | case 2: |
|
38 | case 2: | |
21 | break; |
|
39 | break; | |
22 | case 3: |
|
40 | case 3: | |
23 | apbprintdeviceslist(); |
|
41 | apbprintdeviceslist(); | |
24 | break; |
|
42 | break; | |
25 | case 10: |
|
43 | case 10: | |
26 | return 0; |
|
44 | return 0; | |
27 | break; |
|
45 | break; | |
28 | default: |
|
46 | default: | |
29 | break; |
|
47 | break; | |
30 | } |
|
48 | } | |
31 | } |
|
49 | } | |
32 | return 0; |
|
50 | return 0; | |
33 | } |
|
51 | } |
@@ -1,35 +1,53 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
1 | #ifndef APB_CNA_DRIVER_H |
|
19 | #ifndef APB_CNA_DRIVER_H | |
2 | #define APB_CNA_DRIVER_H |
|
20 | #define APB_CNA_DRIVER_H | |
3 |
|
21 | |||
4 | #define DAC_ready 3 |
|
22 | #define DAC_ready 3 | |
5 | #define DAC_enable 1 |
|
23 | #define DAC_enable 1 | |
6 | #define DAC_disable 0 |
|
24 | #define DAC_disable 0 | |
7 |
|
25 | |||
8 |
|
26 | |||
9 | /*=================================================== |
|
27 | /*=================================================== | |
10 | T Y P E S D E F |
|
28 | T Y P E S D E F | |
11 | ====================================================*/ |
|
29 | ====================================================*/ | |
12 |
|
30 | |||
13 | struct DAC_Driver |
|
31 | struct DAC_Driver | |
14 | { |
|
32 | { | |
15 | int configReg; |
|
33 | int configReg; | |
16 | int dataReg; |
|
34 | int dataReg; | |
17 | }; |
|
35 | }; | |
18 |
|
36 | |||
19 | typedef struct DAC_Driver DAC_Device; |
|
37 | typedef struct DAC_Driver DAC_Device; | |
20 |
|
38 | |||
21 | /*=================================================== |
|
39 | /*=================================================== | |
22 | F U N C T I O N S |
|
40 | F U N C T I O N S | |
23 | ====================================================*/ |
|
41 | ====================================================*/ | |
24 |
|
42 | |||
25 | DAC_Device* DacOpen(int count); |
|
43 | DAC_Device* DacOpen(int count); | |
26 |
|
44 | |||
27 | //DAC_Device* DacClose(int count); |
|
45 | //DAC_Device* DacClose(int count); | |
28 |
|
46 | |||
29 | int DacTable(); |
|
47 | int DacTable(); | |
30 |
|
48 | |||
31 | int DacConst(); |
|
49 | int DacConst(); | |
32 |
|
50 | |||
33 |
|
51 | |||
34 |
|
52 | |||
35 | #endif |
|
53 | #endif |
@@ -1,67 +1,59 | |||||
1 | /*------------------------------------------------------------------------------ |
|
1 | /*------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | -------------------------------------------------------------------------------*/ |
|
18 | -------------------------------------------------------------------------------*/ | |
19 | #ifndef LPP_APB_FUNCTIONS_H |
|
19 | #ifndef LPP_APB_FUNCTIONS_H | |
20 | #define LPP_APB_FUNCTIONS_H |
|
20 | #define LPP_APB_FUNCTIONS_H | |
21 |
|
21 | |||
22 | #define APB_TBL_HEAD 0x800FF000 |
|
22 | #define APB_TBL_HEAD 0x800FF000 | |
23 | #define APB_BASE_ADDRS 0x80000000 |
|
23 | #define APB_BASE_ADDRS 0x80000000 | |
24 | #define APB_MAX_DEVICES 256 |
|
24 | #define APB_MAX_DEVICES 256 | |
25 |
|
25 | |||
26 | #define VENDOR_LPP 0x19 |
|
26 | #include "apb_devices_list.h" | |
27 |
|
||||
28 | #define ROCKET_TM 0x001 |
|
|||
29 | #define otherCore 0x002 |
|
|||
30 | #define LPP_SIMPLE_DIODE 0x003 |
|
|||
31 | #define LPP_MULTI_DIODE 0x004 |
|
|||
32 | #define LPP_LCD_CTRLR 0x005 |
|
|||
33 | #define LPP_UART_CTRLR 0x006 |
|
|||
34 | #define LPP_DAC_CTRLR 0x007 |
|
|||
35 |
|
27 | |||
36 | /** @todo implemente a descriptor structure for any APB device */ |
|
28 | /** @todo implemente a descriptor structure for any APB device */ | |
37 |
|
29 | |||
38 |
|
30 | |||
39 | /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */ |
|
31 | /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */ | |
40 | struct apbPnPreg |
|
32 | struct apbPnPreg | |
41 | { |
|
33 | { | |
42 | int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */ |
|
34 | int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */ | |
43 | int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */ |
|
35 | int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */ | |
44 | }; |
|
36 | }; | |
45 |
|
37 | |||
46 | struct apbdevinfo |
|
38 | struct apbdevinfo | |
47 | { |
|
39 | { | |
48 | int vendorID; |
|
40 | int vendorID; | |
49 | int productID; |
|
41 | int productID; | |
50 | int version; |
|
42 | int version; | |
51 | int irq; |
|
43 | int irq; | |
52 | int address; |
|
44 | int address; | |
53 | int mask; |
|
45 | int mask; | |
54 | }; |
|
46 | }; | |
55 |
|
47 | |||
56 | /** This Function scans APB devices table and returns counth device according to VID and PID */ |
|
48 | /** This Function scans APB devices table and returns counth device according to VID and PID */ | |
57 | int* apbgetdevice(int PID,int VID,int count); |
|
49 | int* apbgetdevice(int PID,int VID,int count); | |
58 | /** This Function scans APB devices table and returns counth device informations according VID and PID */ |
|
50 | /** This Function scans APB devices table and returns counth device informations according VID and PID */ | |
59 | void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo); |
|
51 | void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo); | |
60 |
|
52 | |||
61 | void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo); |
|
53 | void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo); | |
62 |
|
54 | |||
63 |
|
55 | |||
64 | void apbprintdeviceinfo(struct apbdevinfo devinfo); |
|
56 | void apbprintdeviceinfo(struct apbdevinfo devinfo); | |
65 |
|
57 | |||
66 | void apbprintdeviceslist(); |
|
58 | void apbprintdeviceslist(); | |
67 | #endif // LPP_APB_FUNCTIONS_H |
|
59 | #endif // LPP_APB_FUNCTIONS_H |
@@ -1,119 +1,122 | |||||
1 | /*------------------------------------------------------------------------------ |
|
1 | /*------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | -------------------------------------------------------------------------------*/ |
|
18 | -------------------------------------------------------------------------------*/ | |
|
19 | /*-- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ----------------------------------------------------------------------------*/ | |||
19 | #include "lpp_apb_functions.h" |
|
22 | #include "lpp_apb_functions.h" | |
20 | #include <stdio.h> |
|
23 | #include <stdio.h> | |
21 |
|
24 | |||
22 |
|
25 | |||
23 |
|
26 | |||
24 | int* apbgetdevice(int PID,int VID,int count) |
|
27 | int* apbgetdevice(int PID,int VID,int count) | |
25 | { |
|
28 | { | |
26 | struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD + sizeof(struct apbPnPreg)); |
|
29 | struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD + sizeof(struct apbPnPreg)); | |
27 | int id; |
|
30 | int id; | |
28 | id = (PID<<12) | (VID<<24); |
|
31 | id = (PID<<12) | (VID<<24); | |
29 | while(dev != (struct apbPnPreg*)(APB_TBL_HEAD|0xFFF)) |
|
32 | while(dev != (struct apbPnPreg*)(APB_TBL_HEAD|0xFFF)) | |
30 | { |
|
33 | { | |
31 | if((dev->idReg & 0xFFFFF000) == id) |
|
34 | if((dev->idReg & 0xFFFFF000) == id) | |
32 | { |
|
35 | { | |
33 | if(count == 0) |
|
36 | if(count == 0) | |
34 | { |
|
37 | { | |
35 | return (int*) (APB_BASE_ADDRS | (dev->bar&0xFFF00000)>>12); |
|
38 | return (int*) (APB_BASE_ADDRS | (dev->bar&0xFFF00000)>>12); | |
36 | } |
|
39 | } | |
37 | count-=1; |
|
40 | count-=1; | |
38 | } |
|
41 | } | |
39 | dev += 1; |
|
42 | dev += 1; | |
40 | } |
|
43 | } | |
41 | return NULL; |
|
44 | return NULL; | |
42 | } |
|
45 | } | |
43 |
|
46 | |||
44 |
|
47 | |||
45 | void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo) |
|
48 | void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo) | |
46 | { |
|
49 | { | |
47 |
|
50 | |||
48 | devinfo->productID = (dev->idReg>>12) & 0xFFF; |
|
51 | devinfo->productID = (dev->idReg>>12) & 0xFFF; | |
49 | devinfo->vendorID = (dev->idReg>>24) & 0xFF; |
|
52 | devinfo->vendorID = (dev->idReg>>24) & 0xFF; | |
50 | devinfo->address = ((dev->bar>>12) & 0xFFF00)|APB_BASE_ADDRS; |
|
53 | devinfo->address = ((dev->bar>>12) & 0xFFF00)|APB_BASE_ADDRS; | |
51 | devinfo->irq = dev->idReg & 0x1F; |
|
54 | devinfo->irq = dev->idReg & 0x1F; | |
52 | devinfo->mask = (dev->bar>>4)&0xFFF; |
|
55 | devinfo->mask = (dev->bar>>4)&0xFFF; | |
53 | devinfo->version = (dev->idReg>>5)&0x1F; |
|
56 | devinfo->version = (dev->idReg>>5)&0x1F; | |
54 | } |
|
57 | } | |
55 |
|
58 | |||
56 | void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo) |
|
59 | void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo) | |
57 | { |
|
60 | { | |
58 | struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD + sizeof(struct apbPnPreg)); |
|
61 | struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD + sizeof(struct apbPnPreg)); | |
59 | int id; |
|
62 | int id; | |
60 | id = (PID<<12) | (VID<<24); |
|
63 | id = (PID<<12) | (VID<<24); | |
61 | while(dev != (struct apbPnPreg*)(APB_TBL_HEAD|0xFFF)) |
|
64 | while(dev != (struct apbPnPreg*)(APB_TBL_HEAD|0xFFF)) | |
62 | { |
|
65 | { | |
63 | if((dev->idReg & 0xFFFFF000) == id) |
|
66 | if((dev->idReg & 0xFFFFF000) == id) | |
64 | { |
|
67 | { | |
65 | if(count == 0) |
|
68 | if(count == 0) | |
66 | { |
|
69 | { | |
67 | devinfo->productID = PID; |
|
70 | devinfo->productID = PID; | |
68 | devinfo->vendorID = VID; |
|
71 | devinfo->vendorID = VID; | |
69 | devinfo->address = ((dev->bar>>12) & 0xFFF00)|APB_BASE_ADDRS; |
|
72 | devinfo->address = ((dev->bar>>12) & 0xFFF00)|APB_BASE_ADDRS; | |
70 | devinfo->irq = dev->idReg & 0x1F; |
|
73 | devinfo->irq = dev->idReg & 0x1F; | |
71 | devinfo->mask = (dev->bar>>4)&0xFFF; |
|
74 | devinfo->mask = (dev->bar>>4)&0xFFF; | |
72 | devinfo->version = (dev->idReg>>5)&0x1F; |
|
75 | devinfo->version = (dev->idReg>>5)&0x1F; | |
73 | return; |
|
76 | return; | |
74 | } |
|
77 | } | |
75 | count-=1; |
|
78 | count-=1; | |
76 | } |
|
79 | } | |
77 | dev += 1; |
|
80 | dev += 1; | |
78 | } |
|
81 | } | |
79 | } |
|
82 | } | |
80 |
|
83 | |||
81 |
|
84 | |||
82 |
|
85 | |||
83 | void apbprintdeviceinfo(struct apbdevinfo devinfo) |
|
86 | void apbprintdeviceinfo(struct apbdevinfo devinfo) | |
84 | { |
|
87 | { | |
85 | printf("Vendor ID = 0x%x\n",devinfo.vendorID); |
|
88 | printf("Vendor ID = 0x%x\n",devinfo.vendorID); | |
86 | printf("Product ID = 0x%x\n",devinfo.productID); |
|
89 | printf("Product ID = 0x%x\n",devinfo.productID); | |
87 | printf("Device address = 0x%x\n",devinfo.address); |
|
90 | printf("Device address = 0x%x\n",devinfo.address); | |
88 | printf("Device Irq = %d\n",devinfo.irq); |
|
91 | printf("Device Irq = %d\n",devinfo.irq); | |
89 | printf("Device mask = 0x%x\n",devinfo.mask); |
|
92 | printf("Device mask = 0x%x\n",devinfo.mask); | |
90 | printf("Device Version = %d\n",devinfo.version); |
|
93 | printf("Device Version = %d\n",devinfo.version); | |
91 | } |
|
94 | } | |
92 |
|
95 | |||
93 |
|
96 | |||
94 | void apbprintdeviceslist() |
|
97 | void apbprintdeviceslist() | |
95 | { |
|
98 | { | |
96 | struct apbdevinfo devinfo; |
|
99 | struct apbdevinfo devinfo; | |
97 | struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD );//+ sizeof(struct apbPnPreg)); |
|
100 | struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD );//+ sizeof(struct apbPnPreg)); | |
98 | int i =0; |
|
101 | int i =0; | |
99 | int fisrtBAR; |
|
102 | int fisrtBAR; | |
100 | while((dev->idReg == 0) && (i<APB_MAX_DEVICES)) |
|
103 | while((dev->idReg == 0) && (i<APB_MAX_DEVICES)) | |
101 | { |
|
104 | { | |
102 | dev += 1; |
|
105 | dev += 1; | |
103 | i+=1; |
|
106 | i+=1; | |
104 | } |
|
107 | } | |
105 | fisrtBAR = dev->bar; |
|
108 | fisrtBAR = dev->bar; | |
106 | for(i=i;i<APB_MAX_DEVICES;i++) |
|
109 | for(i=i;i<APB_MAX_DEVICES;i++) | |
107 | { |
|
110 | { | |
108 | if((dev->idReg != 0 )) |
|
111 | if((dev->idReg != 0 )) | |
109 | { |
|
112 | { | |
110 | apbgetdeviceinfofromdevptr(dev,&devinfo); |
|
113 | apbgetdeviceinfofromdevptr(dev,&devinfo); | |
111 | printf("\n\n======= new device found========\n"); |
|
114 | printf("\n\n======= new device found========\n"); | |
112 | apbprintdeviceinfo(devinfo); |
|
115 | apbprintdeviceinfo(devinfo); | |
113 | } |
|
116 | } | |
114 | dev += 1; |
|
117 | dev += 1; | |
115 | if(dev->bar == fisrtBAR) |
|
118 | if(dev->bar == fisrtBAR) | |
116 | break; |
|
119 | break; | |
117 | } |
|
120 | } | |
118 | } |
|
121 | } | |
119 |
|
122 |
@@ -1,59 +1,62 | |||||
1 | /*------------------------------------------------------------------------------ |
|
1 | /*------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | -------------------------------------------------------------------------------*/ |
|
18 | -------------------------------------------------------------------------------*/ | |
|
19 | /*-- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ----------------------------------------------------------------------------*/ | |||
19 | #ifndef LPP_APB_FUNCTIONS_H |
|
22 | #ifndef LPP_APB_FUNCTIONS_H | |
20 | #define LPP_APB_FUNCTIONS_H |
|
23 | #define LPP_APB_FUNCTIONS_H | |
21 |
|
24 | |||
22 | #define APB_TBL_HEAD 0x800FF000 |
|
25 | #define APB_TBL_HEAD 0x800FF000 | |
23 | #define APB_BASE_ADDRS 0x80000000 |
|
26 | #define APB_BASE_ADDRS 0x80000000 | |
24 | #define APB_MAX_DEVICES 256 |
|
27 | #define APB_MAX_DEVICES 256 | |
25 |
|
28 | |||
26 | #include "apb_devices_list.h" |
|
29 | #include "apb_devices_list.h" | |
27 |
|
30 | |||
28 | /** @todo implemente a descriptor structure for any APB device */ |
|
31 | /** @todo implemente a descriptor structure for any APB device */ | |
29 |
|
32 | |||
30 |
|
33 | |||
31 | /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */ |
|
34 | /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */ | |
32 | struct apbPnPreg |
|
35 | struct apbPnPreg | |
33 | { |
|
36 | { | |
34 | int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */ |
|
37 | int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */ | |
35 | int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */ |
|
38 | int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */ | |
36 | }; |
|
39 | }; | |
37 |
|
40 | |||
38 | struct apbdevinfo |
|
41 | struct apbdevinfo | |
39 | { |
|
42 | { | |
40 | int vendorID; |
|
43 | int vendorID; | |
41 | int productID; |
|
44 | int productID; | |
42 | int version; |
|
45 | int version; | |
43 | int irq; |
|
46 | int irq; | |
44 | int address; |
|
47 | int address; | |
45 | int mask; |
|
48 | int mask; | |
46 | }; |
|
49 | }; | |
47 |
|
50 | |||
48 | /** This Function scans APB devices table and returns counth device according to VID and PID */ |
|
51 | /** This Function scans APB devices table and returns counth device according to VID and PID */ | |
49 | int* apbgetdevice(int PID,int VID,int count); |
|
52 | int* apbgetdevice(int PID,int VID,int count); | |
50 | /** This Function scans APB devices table and returns counth device informations according VID and PID */ |
|
53 | /** This Function scans APB devices table and returns counth device informations according VID and PID */ | |
51 | void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo); |
|
54 | void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo); | |
52 |
|
55 | |||
53 | void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo); |
|
56 | void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo); | |
54 |
|
57 | |||
55 |
|
58 | |||
56 | void apbprintdeviceinfo(struct apbdevinfo devinfo); |
|
59 | void apbprintdeviceinfo(struct apbdevinfo devinfo); | |
57 |
|
60 | |||
58 | void apbprintdeviceslist(); |
|
61 | void apbprintdeviceslist(); | |
59 | #endif // LPP_APB_FUNCTIONS_H |
|
62 | #endif // LPP_APB_FUNCTIONS_H |
@@ -1,68 +1,86 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
1 | #include "apb_dac_Driver.h" |
|
19 | #include "apb_dac_Driver.h" | |
2 | #include "lpp_apb_functions.h" |
|
20 | #include "lpp_apb_functions.h" | |
3 | #include <stdio.h> |
|
21 | #include <stdio.h> | |
4 |
|
22 | |||
5 |
|
23 | |||
6 | DAC_Device* DacOpen(int count) |
|
24 | DAC_Device* DacOpen(int count) | |
7 | { |
|
25 | { | |
8 | DAC_Device* dac0; |
|
26 | DAC_Device* dac0; | |
9 | dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count); |
|
27 | dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count); | |
10 | dac0->configReg = DAC_enable; |
|
28 | dac0->configReg = DAC_enable; | |
11 | return dac0; |
|
29 | return dac0; | |
12 | } |
|
30 | } | |
13 |
|
31 | |||
14 | /* |
|
32 | /* | |
15 | DAC_Device* DacClose(int count) |
|
33 | DAC_Device* DacClose(int count) | |
16 | { |
|
34 | { | |
17 | DAC_Device* dac1; |
|
35 | DAC_Device* dac1; | |
18 | dac1 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count); |
|
36 | dac1 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count); | |
19 | dac1->configReg = DAC_disable; |
|
37 | dac1->configReg = DAC_disable; | |
20 | return dac1; |
|
38 | return dac1; | |
21 | } |
|
39 | } | |
22 | */ |
|
40 | */ | |
23 |
|
41 | |||
24 |
|
42 | |||
25 | int DacTable() |
|
43 | int DacTable() | |
26 | { |
|
44 | { | |
27 | int i; |
|
45 | int i; | |
28 | DAC_Device* dac2; |
|
46 | DAC_Device* dac2; | |
29 | int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13, |
|
47 | int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13, | |
30 | 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800, |
|
48 | 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800, | |
31 | 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14, |
|
49 | 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14, | |
32 | 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356, |
|
50 | 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356, | |
33 | 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492, |
|
51 | 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492, | |
34 | 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786, |
|
52 | 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786, | |
35 | 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656}; |
|
53 | 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656}; | |
36 | dac2 = (DAC_Device*)0x80000800; |
|
54 | dac2 = (DAC_Device*)0x80000800; | |
37 | dac2->configReg = DAC_enable; |
|
55 | dac2->configReg = DAC_enable; | |
38 | dac2->dataReg = tablo[0]; |
|
56 | dac2->dataReg = tablo[0]; | |
39 |
|
57 | |||
40 | while(1) |
|
58 | while(1) | |
41 | { |
|
59 | { | |
42 | for (i = 0 ; i < 251 ; i++) |
|
60 | for (i = 0 ; i < 251 ; i++) | |
43 | { |
|
61 | { | |
44 | while(!((dac2->configReg & DAC_ready) == DAC_ready)); |
|
62 | while(!((dac2->configReg & DAC_ready) == DAC_ready)); | |
45 | dac2->dataReg = tablo[i]; |
|
63 | dac2->dataReg = tablo[i]; | |
46 | while((dac2->configReg & DAC_ready) == DAC_ready); |
|
64 | while((dac2->configReg & DAC_ready) == DAC_ready); | |
47 | } |
|
65 | } | |
48 | } |
|
66 | } | |
49 | return 0; |
|
67 | return 0; | |
50 | } |
|
68 | } | |
51 |
|
69 | |||
52 |
|
70 | |||
53 |
|
71 | |||
54 | int DacConst() |
|
72 | int DacConst() | |
55 | { |
|
73 | { | |
56 | DAC_Device* dac3; |
|
74 | DAC_Device* dac3; | |
57 | int Value = 0x1FFF; |
|
75 | int Value = 0x1FFF; | |
58 | dac3 = (DAC_Device*)0x80000800; |
|
76 | dac3 = (DAC_Device*)0x80000800; | |
59 | dac3->configReg = DAC_enable; |
|
77 | dac3->configReg = DAC_enable; | |
60 | while(1) |
|
78 | while(1) | |
61 | { |
|
79 | { | |
62 | printf("\nEntrer une valeur entre 4096 et 8191 : "); |
|
80 | printf("\nEntrer une valeur entre 4096 et 8191 : "); | |
63 | scanf("%d",&Value); |
|
81 | scanf("%d",&Value); | |
64 | dac3->dataReg = Value; |
|
82 | dac3->dataReg = Value; | |
65 | } |
|
83 | } | |
66 | return 0; |
|
84 | return 0; | |
67 | } |
|
85 | } | |
68 |
|
86 |
@@ -1,35 +1,53 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
1 | #ifndef APB_CNA_DRIVER_H |
|
19 | #ifndef APB_CNA_DRIVER_H | |
2 | #define APB_CNA_DRIVER_H |
|
20 | #define APB_CNA_DRIVER_H | |
3 |
|
21 | |||
4 | #define DAC_ready 3 |
|
22 | #define DAC_ready 3 | |
5 | #define DAC_enable 1 |
|
23 | #define DAC_enable 1 | |
6 | #define DAC_disable 0 |
|
24 | #define DAC_disable 0 | |
7 |
|
25 | |||
8 |
|
26 | |||
9 | /*=================================================== |
|
27 | /*=================================================== | |
10 | T Y P E S D E F |
|
28 | T Y P E S D E F | |
11 | ====================================================*/ |
|
29 | ====================================================*/ | |
12 |
|
30 | |||
13 | struct DAC_Driver |
|
31 | struct DAC_Driver | |
14 | { |
|
32 | { | |
15 | int configReg; |
|
33 | int configReg; | |
16 | int dataReg; |
|
34 | int dataReg; | |
17 | }; |
|
35 | }; | |
18 |
|
36 | |||
19 | typedef struct DAC_Driver DAC_Device; |
|
37 | typedef struct DAC_Driver DAC_Device; | |
20 |
|
38 | |||
21 | /*=================================================== |
|
39 | /*=================================================== | |
22 | F U N C T I O N S |
|
40 | F U N C T I O N S | |
23 | ====================================================*/ |
|
41 | ====================================================*/ | |
24 |
|
42 | |||
25 | DAC_Device* DacOpen(int count); |
|
43 | DAC_Device* DacOpen(int count); | |
26 |
|
44 | |||
27 | //DAC_Device* DacClose(int count); |
|
45 | //DAC_Device* DacClose(int count); | |
28 |
|
46 | |||
29 | int DacTable(); |
|
47 | int DacTable(); | |
30 |
|
48 | |||
31 | int DacConst(); |
|
49 | int DacConst(); | |
32 |
|
50 | |||
33 |
|
51 | |||
34 |
|
52 | |||
35 | #endif |
|
53 | #endif |
@@ -1,115 +1,118 | |||||
1 | /*------------------------------------------------------------------------------ |
|
1 | /*------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | -------------------------------------------------------------------------------*/ |
|
18 | -------------------------------------------------------------------------------*/ | |
|
19 | /*-- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ----------------------------------------------------------------------------*/ | |||
19 | #include "apb_lcd_driver.h" |
|
22 | #include "apb_lcd_driver.h" | |
20 | #include "lpp_apb_functions.h" |
|
23 | #include "lpp_apb_functions.h" | |
21 | #include "lpp_apb_functions.h" |
|
24 | #include "lpp_apb_functions.h" | |
22 | #include <stdio.h> |
|
25 | #include <stdio.h> | |
23 |
|
26 | |||
24 | int lcdbusy(lcd_device* lcd) |
|
27 | int lcdbusy(lcd_device* lcd) | |
25 | { |
|
28 | { | |
26 | return (!(lcd->cfg_reg&readyFlag)==readyFlag); |
|
29 | return (!(lcd->cfg_reg&readyFlag)==readyFlag); | |
27 | } |
|
30 | } | |
28 |
|
31 | |||
29 |
|
32 | |||
30 | lcd_device* lcdopen(int count) |
|
33 | lcd_device* lcdopen(int count) | |
31 | { |
|
34 | { | |
32 | lcd_device* dev; |
|
35 | lcd_device* dev; | |
33 | dev = (lcd_device*) apbgetdevice(LPP_LCD_CTRLR,VENDOR_LPP,count); |
|
36 | dev = (lcd_device*) apbgetdevice(LPP_LCD_CTRLR,VENDOR_LPP,count); | |
34 | return dev; |
|
37 | return dev; | |
35 | //* scan APB bus an return the count(th) lcd controler */ |
|
38 | //* scan APB bus an return the count(th) lcd controler */ | |
36 |
|
39 | |||
37 | } |
|
40 | } | |
38 |
|
41 | |||
39 |
|
42 | |||
40 |
|
43 | |||
41 | lcd_err lcdsendcmd(lcd_device* lcd,int cmd) |
|
44 | lcd_err lcdsendcmd(lcd_device* lcd,int cmd) | |
42 | { |
|
45 | { | |
43 | lcd_err err; |
|
46 | lcd_err err; | |
44 | err = lcd_error_no_error; |
|
47 | err = lcd_error_no_error; | |
45 | if (lcd!=NULL) |
|
48 | if (lcd!=NULL) | |
46 | { |
|
49 | { | |
47 | while(lcdbusy(lcd)); |
|
50 | while(lcdbusy(lcd)); | |
48 | lcd->cfg_reg = cmd; |
|
51 | lcd->cfg_reg = cmd; | |
49 | return err; |
|
52 | return err; | |
50 | } |
|
53 | } | |
51 | else |
|
54 | else | |
52 | { |
|
55 | { | |
53 | err = lcd_error_not_openned ; |
|
56 | err = lcd_error_not_openned ; | |
54 | return err; |
|
57 | return err; | |
55 | } |
|
58 | } | |
56 | } |
|
59 | } | |
57 |
|
60 | |||
58 |
|
61 | |||
59 |
|
62 | |||
60 | lcd_err lcdsetchar(lcd_device* lcd,int position,const char value) |
|
63 | lcd_err lcdsetchar(lcd_device* lcd,int position,const char value) | |
61 | { |
|
64 | { | |
62 | lcd_err err; |
|
65 | lcd_err err; | |
63 | err = lcd_error_no_error; |
|
66 | err = lcd_error_no_error; | |
64 | return err; |
|
67 | return err; | |
65 | } |
|
68 | } | |
66 |
|
69 | |||
67 |
|
70 | |||
68 |
|
71 | |||
69 | lcd_err lcdprint(lcd_device* lcd,int position,const char* value) |
|
72 | lcd_err lcdprint(lcd_device* lcd,int position,const char* value) | |
70 | { |
|
73 | { | |
71 | lcd_err err; |
|
74 | lcd_err err; | |
72 | err = lcd_error_no_error; |
|
75 | err = lcd_error_no_error; | |
73 | if (lcd!=NULL) |
|
76 | if (lcd!=NULL) | |
74 | { |
|
77 | { | |
75 | int i = position; |
|
78 | int i = position; | |
76 | int n = 0; |
|
79 | int n = 0; | |
77 | while(value[n]!= '\0' && i<lcdCharCnt) |
|
80 | while(value[n]!= '\0' && i<lcdCharCnt) | |
78 | { |
|
81 | { | |
79 | if(value[n] == '\n') |
|
82 | if(value[n] == '\n') | |
80 | { |
|
83 | { | |
81 | i=40;n++; |
|
84 | i=40;n++; | |
82 | } |
|
85 | } | |
83 | lcd->Frame_buff[i++] = value[n++]; |
|
86 | lcd->Frame_buff[i++] = value[n++]; | |
84 | } |
|
87 | } | |
85 | return err; |
|
88 | return err; | |
86 | } |
|
89 | } | |
87 | else |
|
90 | else | |
88 | { |
|
91 | { | |
89 | err = lcd_error_not_openned ; |
|
92 | err = lcd_error_not_openned ; | |
90 | return err; |
|
93 | return err; | |
91 | } |
|
94 | } | |
92 | } |
|
95 | } | |
93 |
|
96 | |||
94 |
|
97 | |||
95 |
|
98 | |||
96 | lcd_err lcdclear(lcd_device* lcd) |
|
99 | lcd_err lcdclear(lcd_device* lcd) | |
97 | { |
|
100 | { | |
98 | lcd_err err; |
|
101 | lcd_err err; | |
99 | err = lcd_error_no_error; |
|
102 | err = lcd_error_no_error; | |
100 | if (lcd!=NULL) |
|
103 | if (lcd!=NULL) | |
101 | { |
|
104 | { | |
102 | int i=0; |
|
105 | int i=0; | |
103 | for(i=0;i<lcdCharCnt;i++) |
|
106 | for(i=0;i<lcdCharCnt;i++) | |
104 | { |
|
107 | { | |
105 | lcd->Frame_buff[i] = ' '; |
|
108 | lcd->Frame_buff[i] = ' '; | |
106 | } |
|
109 | } | |
107 | return err; |
|
110 | return err; | |
108 | } |
|
111 | } | |
109 | err = lcd_error_not_openned ; |
|
112 | err = lcd_error_not_openned ; | |
110 | return err; |
|
113 | return err; | |
111 | } |
|
114 | } | |
112 |
|
115 | |||
113 |
|
116 | |||
114 |
|
117 | |||
115 |
|
118 |
@@ -1,95 +1,98 | |||||
1 | /*------------------------------------------------------------------------------ |
|
1 | /*------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | -------------------------------------------------------------------------------*/ |
|
18 | -------------------------------------------------------------------------------*/ | |
|
19 | /*-- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ----------------------------------------------------------------------------*/ | |||
19 | #ifndef APB_LCD_DRIVER_H |
|
22 | #ifndef APB_LCD_DRIVER_H | |
20 | #define APB_LCD_DRIVER_H |
|
23 | #define APB_LCD_DRIVER_H | |
21 |
|
24 | |||
22 | #define readyFlag 1024 |
|
25 | #define readyFlag 1024 | |
23 | #define lcdCharCnt 80 |
|
26 | #define lcdCharCnt 80 | |
24 |
|
27 | |||
25 |
|
28 | |||
26 | /** @todo implemente some shift functions */ |
|
29 | /** @todo implemente some shift functions */ | |
27 |
|
30 | |||
28 |
|
31 | |||
29 | /*=================================================== |
|
32 | /*=================================================== | |
30 | T Y P E S D E F |
|
33 | T Y P E S D E F | |
31 | ====================================================*/ |
|
34 | ====================================================*/ | |
32 |
|
35 | |||
33 |
|
36 | |||
34 |
|
37 | |||
35 | /** error type used for most of lcd functions */ |
|
38 | /** error type used for most of lcd functions */ | |
36 | typedef int lcd_err; |
|
39 | typedef int lcd_err; | |
37 |
|
40 | |||
38 | /** lcd error ennum for higher abstraction level when error decoding */ |
|
41 | /** lcd error ennum for higher abstraction level when error decoding */ | |
39 | enum lcd_error |
|
42 | enum lcd_error | |
40 | { |
|
43 | { | |
41 | lcd_error_no_error, /**< no error append while function execution */ |
|
44 | lcd_error_no_error, /**< no error append while function execution */ | |
42 | lcd_error_not_ready, /**< the lcd isn't available*/ |
|
45 | lcd_error_not_ready, /**< the lcd isn't available*/ | |
43 | lcd_error_not_openned, /**< the device guiven to the function isn't opened*/ |
|
46 | lcd_error_not_openned, /**< the device guiven to the function isn't opened*/ | |
44 | lcd_error_too_long /**< the string guiven to the lcd is bigger than the lcd frame buffer memory */ |
|
47 | lcd_error_too_long /**< the string guiven to the lcd is bigger than the lcd frame buffer memory */ | |
45 | }; |
|
48 | }; | |
46 |
|
49 | |||
47 |
|
50 | |||
48 | /** for each command sended to the lcd driver a time should be guiven according to the lcd datasheet */ |
|
51 | /** for each command sended to the lcd driver a time should be guiven according to the lcd datasheet */ | |
49 | enum lcd_CMD_time |
|
52 | enum lcd_CMD_time | |
50 | { |
|
53 | { | |
51 | lcd_4us = 0x0FF, |
|
54 | lcd_4us = 0x0FF, | |
52 | lcd_100us = 0x1FF, |
|
55 | lcd_100us = 0x1FF, | |
53 | lcd_4ms = 0x2FF, |
|
56 | lcd_4ms = 0x2FF, | |
54 | lcd_20ms = 0x3FF |
|
57 | lcd_20ms = 0x3FF | |
55 | }; |
|
58 | }; | |
56 |
|
59 | |||
57 | /** list of availiable lcd commands use whith an AND mask whith cmd time */ |
|
60 | /** list of availiable lcd commands use whith an AND mask whith cmd time */ | |
58 | enum lcd_CMD |
|
61 | enum lcd_CMD | |
59 | { |
|
62 | { | |
60 | CursorON = 0xF0E, |
|
63 | CursorON = 0xF0E, | |
61 | CursorOFF = 0xF0C |
|
64 | CursorOFF = 0xF0C | |
62 | }; |
|
65 | }; | |
63 |
|
66 | |||
64 | /** structure representing the lcd registers */ |
|
67 | /** structure representing the lcd registers */ | |
65 | struct lcd_driver |
|
68 | struct lcd_driver | |
66 | { |
|
69 | { | |
67 | int cfg_reg; /**< Configuration register composed of Ready flag [10], CMD time Value [9:8], CMD to send [7:0]*/ |
|
70 | int cfg_reg; /**< Configuration register composed of Ready flag [10], CMD time Value [9:8], CMD to send [7:0]*/ | |
68 | int Frame_buff[lcdCharCnt]; /**< Frame Buffer space each address corresponds to a char on the lcd screen */ |
|
71 | int Frame_buff[lcdCharCnt]; /**< Frame Buffer space each address corresponds to a char on the lcd screen */ | |
69 | }; |
|
72 | }; | |
70 |
|
73 | |||
71 | typedef struct lcd_driver lcd_device; |
|
74 | typedef struct lcd_driver lcd_device; | |
72 |
|
75 | |||
73 | /*=================================================== |
|
76 | /*=================================================== | |
74 | F U N C T I O N S |
|
77 | F U N C T I O N S | |
75 | ====================================================*/ |
|
78 | ====================================================*/ | |
76 |
|
79 | |||
77 | /** says if the lcd is busy */ |
|
80 | /** says if the lcd is busy */ | |
78 | int lcdbusy(lcd_device * lcd); |
|
81 | int lcdbusy(lcd_device * lcd); | |
79 |
|
82 | |||
80 | /** Opens and returns the counth lcd found on APB bus else NULL */ |
|
83 | /** Opens and returns the counth lcd found on APB bus else NULL */ | |
81 | lcd_device* lcdopen(int count); |
|
84 | lcd_device* lcdopen(int count); | |
82 |
|
85 | |||
83 | /** Sends a command to the given device, don't forget to guive the time of the cmd */ |
|
86 | /** Sends a command to the given device, don't forget to guive the time of the cmd */ | |
84 | lcd_err lcdsendcmd(lcd_device* lcd,int cmd); |
|
87 | lcd_err lcdsendcmd(lcd_device* lcd,int cmd); | |
85 |
|
88 | |||
86 | /** Sets a char on the given device at given position */ |
|
89 | /** Sets a char on the given device at given position */ | |
87 | lcd_err lcdsetchar(lcd_device* lcd,int position,const char value); |
|
90 | lcd_err lcdsetchar(lcd_device* lcd,int position,const char value); | |
88 |
|
91 | |||
89 | /** Prints a message on the given device at given position, "\n" is understood but for others use sprintf before */ |
|
92 | /** Prints a message on the given device at given position, "\n" is understood but for others use sprintf before */ | |
90 | lcd_err lcdprint(lcd_device* lcd,int position,const char* value); |
|
93 | lcd_err lcdprint(lcd_device* lcd,int position,const char* value); | |
91 |
|
94 | |||
92 | /** Writes space character on each adress of the lcd screen */ |
|
95 | /** Writes space character on each adress of the lcd screen */ | |
93 | lcd_err lcdclear(lcd_device* lcd); |
|
96 | lcd_err lcdclear(lcd_device* lcd); | |
94 |
|
97 | |||
95 | #endif |
|
98 | #endif |
@@ -1,68 +1,71 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 | use IEEE.NUMERIC_STD.ALL; |
|
24 | use IEEE.NUMERIC_STD.ALL; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.amba_lcd_16x2_ctrlr.all; |
|
26 | use lpp.amba_lcd_16x2_ctrlr.all; | |
24 |
|
27 | |||
25 | entity FRAME_CLK_GEN is |
|
28 | entity FRAME_CLK_GEN is | |
26 | generic(OSC_freqKHz : integer := 50000); |
|
29 | generic(OSC_freqKHz : integer := 50000); | |
27 | Port ( clk : in STD_LOGIC; |
|
30 | Port ( clk : in STD_LOGIC; | |
28 | reset : in STD_LOGIC; |
|
31 | reset : in STD_LOGIC; | |
29 | FRAME_CLK : out STD_LOGIC); |
|
32 | FRAME_CLK : out STD_LOGIC); | |
30 | end FRAME_CLK_GEN; |
|
33 | end FRAME_CLK_GEN; | |
31 |
|
34 | |||
32 | architecture Behavioral of FRAME_CLK_GEN is |
|
35 | architecture Behavioral of FRAME_CLK_GEN is | |
33 |
|
36 | |||
34 | Constant Goal_FRAME_CLK_FREQ : integer := 25; |
|
37 | Constant Goal_FRAME_CLK_FREQ : integer := 25; | |
35 |
|
38 | |||
36 | Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1; |
|
39 | Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1; | |
37 |
|
40 | |||
38 | signal CPT : integer := 0; |
|
41 | signal CPT : integer := 0; | |
39 | signal FRAME_CLK_reg : std_logic :='0'; |
|
42 | signal FRAME_CLK_reg : std_logic :='0'; | |
40 |
|
43 | |||
41 | begin |
|
44 | begin | |
42 |
|
45 | |||
43 | FRAME_CLK <= FRAME_CLK_reg; |
|
46 | FRAME_CLK <= FRAME_CLK_reg; | |
44 |
|
47 | |||
45 | process(reset,clk) |
|
48 | process(reset,clk) | |
46 | begin |
|
49 | begin | |
47 | if reset = '0' then |
|
50 | if reset = '0' then | |
48 | CPT <= 0; |
|
51 | CPT <= 0; | |
49 | FRAME_CLK_reg <= '0'; |
|
52 | FRAME_CLK_reg <= '0'; | |
50 | elsif clk'event and clk = '1' then |
|
53 | elsif clk'event and clk = '1' then | |
51 | if CPT = FRAME_CLK_TRIG then |
|
54 | if CPT = FRAME_CLK_TRIG then | |
52 | CPT <= 0; |
|
55 | CPT <= 0; | |
53 | FRAME_CLK_reg <= not FRAME_CLK_reg; |
|
56 | FRAME_CLK_reg <= not FRAME_CLK_reg; | |
54 | else |
|
57 | else | |
55 | CPT <= CPT + 1; |
|
58 | CPT <= CPT + 1; | |
56 | end if; |
|
59 | end if; | |
57 | end if; |
|
60 | end if; | |
58 | end process; |
|
61 | end process; | |
59 | end Behavioral; |
|
62 | end Behavioral; | |
60 |
|
63 | |||
61 |
|
64 | |||
62 |
|
65 | |||
63 |
|
66 | |||
64 |
|
67 | |||
65 |
|
68 | |||
66 |
|
69 | |||
67 |
|
70 | |||
68 |
|
71 |
@@ -1,50 +1,53 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.all; |
|
23 | use IEEE.STD_LOGIC_1164.all; | |
21 | library lpp; |
|
24 | library lpp; | |
22 | use lpp.amba_lcd_16x2_ctrlr.all; |
|
25 | use lpp.amba_lcd_16x2_ctrlr.all; | |
23 |
|
26 | |||
24 |
|
27 | |||
25 |
|
28 | |||
26 | package LCD_16x2_CFG is |
|
29 | package LCD_16x2_CFG is | |
27 |
|
30 | |||
28 |
|
31 | |||
29 | constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01"; |
|
32 | constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01"; | |
30 | constant FunctionSet : std_logic_vector(7 downto 0):= X"38"; |
|
33 | constant FunctionSet : std_logic_vector(7 downto 0):= X"38"; | |
31 | constant RetHome : std_logic_vector(7 downto 0):= X"02"; |
|
34 | constant RetHome : std_logic_vector(7 downto 0):= X"02"; | |
32 | constant SetEntryMode : std_logic_vector(7 downto 0):= X"06"; |
|
35 | constant SetEntryMode : std_logic_vector(7 downto 0):= X"06"; | |
33 | constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0E"; |
|
36 | constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0E"; | |
34 |
|
37 | |||
35 | constant CursorON : std_logic_vector(7 downto 0):= X"0E"; |
|
38 | constant CursorON : std_logic_vector(7 downto 0):= X"0E"; | |
36 | constant CursorOFF : std_logic_vector(7 downto 0):= X"0C"; |
|
39 | constant CursorOFF : std_logic_vector(7 downto 0):= X"0C"; | |
37 |
|
40 | |||
38 | --===========================================================| |
|
41 | --===========================================================| | |
39 | --======L C D D R I V E R T I M I N G C O D E=====| |
|
42 | --======L C D D R I V E R T I M I N G C O D E=====| | |
40 | --===========================================================| |
|
43 | --===========================================================| | |
41 |
|
44 | |||
42 | constant Duration_4us : std_logic_vector(1 downto 0) := "00"; |
|
45 | constant Duration_4us : std_logic_vector(1 downto 0) := "00"; | |
43 | constant Duration_100us : std_logic_vector(1 downto 0) := "01"; |
|
46 | constant Duration_100us : std_logic_vector(1 downto 0) := "01"; | |
44 | constant Duration_4ms : std_logic_vector(1 downto 0) := "10"; |
|
47 | constant Duration_4ms : std_logic_vector(1 downto 0) := "10"; | |
45 | constant Duration_20ms : std_logic_vector(1 downto 0) := "11"; |
|
48 | constant Duration_20ms : std_logic_vector(1 downto 0) := "11"; | |
46 |
|
49 | |||
47 |
|
50 | |||
48 |
|
51 | |||
49 | end LCD_16x2_CFG; |
|
52 | end LCD_16x2_CFG; | |
50 |
|
53 |
@@ -1,168 +1,171 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 |
|
22 | |||
20 | ---TDODO => Clean Enable pulse FSM |
|
23 | ---TDODO => Clean Enable pulse FSM | |
21 | library IEEE; |
|
24 | library IEEE; | |
22 | use IEEE.STD_LOGIC_1164.ALL; |
|
25 | use IEEE.STD_LOGIC_1164.ALL; | |
23 | use IEEE.NUMERIC_STD.all; |
|
26 | use IEEE.NUMERIC_STD.all; | |
24 | library lpp; |
|
27 | library lpp; | |
25 | use lpp.amba_lcd_16x2_ctrlr.all; |
|
28 | use lpp.amba_lcd_16x2_ctrlr.all; | |
26 | use lpp.lcd_16x2_cfg.all; |
|
29 | use lpp.lcd_16x2_cfg.all; | |
27 |
|
30 | |||
28 | entity LCD_16x2_DRIVER is |
|
31 | entity LCD_16x2_DRIVER is | |
29 | generic( |
|
32 | generic( | |
30 | OSC_Freq_KHz : integer:=50000 |
|
33 | OSC_Freq_KHz : integer:=50000 | |
31 | ); |
|
34 | ); | |
32 | Port( |
|
35 | Port( | |
33 | reset : in STD_LOGIC; |
|
36 | reset : in STD_LOGIC; | |
34 | clk : in STD_LOGIC; |
|
37 | clk : in STD_LOGIC; | |
35 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS; |
|
38 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS; | |
36 | SYNCH : out LCD_DRVR_SYNCH_BUSS; |
|
39 | SYNCH : out LCD_DRVR_SYNCH_BUSS; | |
37 | DRIVER_CMD : in LCD_DRVR_CMD_BUSS |
|
40 | DRIVER_CMD : in LCD_DRVR_CMD_BUSS | |
38 | ); |
|
41 | ); | |
39 | end LCD_16x2_DRIVER; |
|
42 | end LCD_16x2_DRIVER; | |
40 |
|
43 | |||
41 | architecture Behavioral of LCD_16x2_DRIVER is |
|
44 | architecture Behavioral of LCD_16x2_DRIVER is | |
42 |
|
45 | |||
43 | type stateT is (idle,Enable0,Enable1,Enable2,tempo); |
|
46 | type stateT is (idle,Enable0,Enable1,Enable2,tempo); | |
44 | signal state : stateT; |
|
47 | signal state : stateT; | |
45 |
|
48 | |||
46 |
|
49 | |||
47 | constant trigger_4us : integer := 5; |
|
50 | constant trigger_4us : integer := 5; | |
48 | constant trigger_100us : integer := 100; |
|
51 | constant trigger_100us : integer := 100; | |
49 | constant trigger_4ms : integer := 4200; |
|
52 | constant trigger_4ms : integer := 4200; | |
50 | constant trigger_20ms : integer := 20000; |
|
53 | constant trigger_20ms : integer := 20000; | |
51 |
|
54 | |||
52 |
|
55 | |||
53 | signal i : integer :=0; |
|
56 | signal i : integer :=0; | |
54 | signal reset_i : std_logic := '0'; |
|
57 | signal reset_i : std_logic := '0'; | |
55 | signal tempoTRIG : integer :=0; |
|
58 | signal tempoTRIG : integer :=0; | |
56 |
|
59 | |||
57 | signal clk_1us : std_logic; |
|
60 | signal clk_1us : std_logic; | |
58 | signal clk_1us_reg : std_logic; |
|
61 | signal clk_1us_reg : std_logic; | |
59 |
|
62 | |||
60 | begin |
|
63 | begin | |
61 |
|
64 | |||
62 |
|
65 | |||
63 | CLK0: LCD_CLK_GENERATOR |
|
66 | CLK0: LCD_CLK_GENERATOR | |
64 | generic map(OSC_Freq_KHz) |
|
67 | generic map(OSC_Freq_KHz) | |
65 | Port map( clk,reset,clk_1us); |
|
68 | Port map( clk,reset,clk_1us); | |
66 |
|
69 | |||
67 |
|
70 | |||
68 |
|
71 | |||
69 | process(clk_1us,reset_i) |
|
72 | process(clk_1us,reset_i) | |
70 | begin |
|
73 | begin | |
71 | if reset_i = '0' then |
|
74 | if reset_i = '0' then | |
72 | i <= 0; |
|
75 | i <= 0; | |
73 | elsif clk_1us'event and clk_1us ='1' then |
|
76 | elsif clk_1us'event and clk_1us ='1' then | |
74 | i <= i+1; |
|
77 | i <= i+1; | |
75 | end if; |
|
78 | end if; | |
76 | end process; |
|
79 | end process; | |
77 |
|
80 | |||
78 | LCD_CTRL.LCD_RW <= '0'; |
|
81 | LCD_CTRL.LCD_RW <= '0'; | |
79 |
|
82 | |||
80 | process(clk,reset) |
|
83 | process(clk,reset) | |
81 | begin |
|
84 | begin | |
82 | if reset = '0' then |
|
85 | if reset = '0' then | |
83 | state <= idle; |
|
86 | state <= idle; | |
84 | LCD_CTRL.LCD_E <= '0'; |
|
87 | LCD_CTRL.LCD_E <= '0'; | |
85 | SYNCH.DRVR_READY <= '0'; |
|
88 | SYNCH.DRVR_READY <= '0'; | |
86 | SYNCH.LCD_INITIALISED <= '0'; |
|
89 | SYNCH.LCD_INITIALISED <= '0'; | |
87 | reset_i <= '0'; |
|
90 | reset_i <= '0'; | |
88 | elsif clk'event and clk = '1' then |
|
91 | elsif clk'event and clk = '1' then | |
89 | case state is |
|
92 | case state is | |
90 | when idle => |
|
93 | when idle => | |
91 | SYNCH.LCD_INITIALISED <= '1'; |
|
94 | SYNCH.LCD_INITIALISED <= '1'; | |
92 | LCD_CTRL.LCD_E <= '0'; |
|
95 | LCD_CTRL.LCD_E <= '0'; | |
93 | if DRIVER_CMD.Exec = '1' then |
|
96 | if DRIVER_CMD.Exec = '1' then | |
94 | state <= Enable0; |
|
97 | state <= Enable0; | |
95 | reset_i <= '1'; |
|
98 | reset_i <= '1'; | |
96 | SYNCH.DRVR_READY <= '0'; |
|
99 | SYNCH.DRVR_READY <= '0'; | |
97 | LCD_CTRL.LCD_DATA <= DRIVER_CMD.Word; |
|
100 | LCD_CTRL.LCD_DATA <= DRIVER_CMD.Word; | |
98 | LCD_CTRL.LCD_RS <= DRIVER_CMD.CMD_Data; |
|
101 | LCD_CTRL.LCD_RS <= DRIVER_CMD.CMD_Data; | |
99 | case DRIVER_CMD.Duration is |
|
102 | case DRIVER_CMD.Duration is | |
100 | when Duration_4us => |
|
103 | when Duration_4us => | |
101 | tempoTRIG <= trigger_4us; |
|
104 | tempoTRIG <= trigger_4us; | |
102 | when Duration_100us => |
|
105 | when Duration_100us => | |
103 | tempoTRIG <= trigger_100us; |
|
106 | tempoTRIG <= trigger_100us; | |
104 | when Duration_4ms => |
|
107 | when Duration_4ms => | |
105 | tempoTRIG <= trigger_4ms; |
|
108 | tempoTRIG <= trigger_4ms; | |
106 | when Duration_20ms => |
|
109 | when Duration_20ms => | |
107 | tempoTRIG <= trigger_20ms; |
|
110 | tempoTRIG <= trigger_20ms; | |
108 | when others => |
|
111 | when others => | |
109 | tempoTRIG <= trigger_20ms; |
|
112 | tempoTRIG <= trigger_20ms; | |
110 | end case; |
|
113 | end case; | |
111 | else |
|
114 | else | |
112 | SYNCH.DRVR_READY <= '1'; |
|
115 | SYNCH.DRVR_READY <= '1'; | |
113 | reset_i <= '0'; |
|
116 | reset_i <= '0'; | |
114 | end if; |
|
117 | end if; | |
115 | when Enable0 => |
|
118 | when Enable0 => | |
116 | if i = 1 then |
|
119 | if i = 1 then | |
117 | reset_i <= '0'; |
|
120 | reset_i <= '0'; | |
118 | LCD_CTRL.LCD_E <= '1'; |
|
121 | LCD_CTRL.LCD_E <= '1'; | |
119 | state <= Enable1; |
|
122 | state <= Enable1; | |
120 | else |
|
123 | else | |
121 | reset_i <= '1'; |
|
124 | reset_i <= '1'; | |
122 | LCD_CTRL.LCD_E <= '0'; |
|
125 | LCD_CTRL.LCD_E <= '0'; | |
123 | end if; |
|
126 | end if; | |
124 | when Enable1 => |
|
127 | when Enable1 => | |
125 | if i = 2 then |
|
128 | if i = 2 then | |
126 | reset_i <= '0'; |
|
129 | reset_i <= '0'; | |
127 | LCD_CTRL.LCD_E <= '0'; |
|
130 | LCD_CTRL.LCD_E <= '0'; | |
128 | state <= Enable2; |
|
131 | state <= Enable2; | |
129 | else |
|
132 | else | |
130 | reset_i <= '1'; |
|
133 | reset_i <= '1'; | |
131 | LCD_CTRL.LCD_E <= '1'; |
|
134 | LCD_CTRL.LCD_E <= '1'; | |
132 | end if; |
|
135 | end if; | |
133 | when Enable2 => |
|
136 | when Enable2 => | |
134 | if i = 1 then |
|
137 | if i = 1 then | |
135 | reset_i <= '0'; |
|
138 | reset_i <= '0'; | |
136 | LCD_CTRL.LCD_E <= '0'; |
|
139 | LCD_CTRL.LCD_E <= '0'; | |
137 | state <= tempo; |
|
140 | state <= tempo; | |
138 | else |
|
141 | else | |
139 | reset_i <= '1'; |
|
142 | reset_i <= '1'; | |
140 | LCD_CTRL.LCD_E <= '0'; |
|
143 | LCD_CTRL.LCD_E <= '0'; | |
141 | end if; |
|
144 | end if; | |
142 | when tempo => |
|
145 | when tempo => | |
143 | if i = tempoTRIG then |
|
146 | if i = tempoTRIG then | |
144 | reset_i <= '0'; |
|
147 | reset_i <= '0'; | |
145 | state <= idle; |
|
148 | state <= idle; | |
146 | else |
|
149 | else | |
147 | reset_i <= '1'; |
|
150 | reset_i <= '1'; | |
148 | end if; |
|
151 | end if; | |
149 | end case; |
|
152 | end case; | |
150 | end if; |
|
153 | end if; | |
151 | end process; |
|
154 | end process; | |
152 |
|
155 | |||
153 | end Behavioral; |
|
156 | end Behavioral; | |
154 |
|
157 | |||
155 |
|
158 | |||
156 |
|
159 | |||
157 |
|
160 | |||
158 |
|
161 | |||
159 |
|
162 | |||
160 |
|
163 | |||
161 |
|
164 | |||
162 |
|
165 | |||
163 |
|
166 | |||
164 |
|
167 | |||
165 |
|
168 | |||
166 |
|
169 | |||
167 |
|
170 | |||
168 |
|
171 |
@@ -1,210 +1,213 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 | use IEEE.NUMERIC_STD.ALL; |
|
24 | use IEEE.NUMERIC_STD.ALL; | |
22 |
|
25 | |||
23 | library lpp; |
|
26 | library lpp; | |
24 | use lpp.amba_lcd_16x2_ctrlr.all; |
|
27 | use lpp.amba_lcd_16x2_ctrlr.all; | |
25 | use lpp.LCD_16x2_CFG.all; |
|
28 | use lpp.LCD_16x2_CFG.all; | |
26 |
|
29 | |||
27 |
|
30 | |||
28 | entity LCD_16x2_ENGINE is |
|
31 | entity LCD_16x2_ENGINE is | |
29 | generic(OSC_freqKHz : integer := 50000); |
|
32 | generic(OSC_freqKHz : integer := 50000); | |
30 | Port ( clk : in STD_LOGIC; |
|
33 | Port ( clk : in STD_LOGIC; | |
31 | reset : in STD_LOGIC; |
|
34 | reset : in STD_LOGIC; | |
32 | DATA : in FRM_Buff_Space; |
|
35 | DATA : in FRM_Buff_Space; | |
33 | CMD : in std_logic_vector(10 downto 0); |
|
36 | CMD : in std_logic_vector(10 downto 0); | |
34 | Exec : in std_logic; |
|
37 | Exec : in std_logic; | |
35 | Ready : out std_logic; |
|
38 | Ready : out std_logic; | |
36 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS |
|
39 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS | |
37 | ); |
|
40 | ); | |
38 | end LCD_16x2_ENGINE; |
|
41 | end LCD_16x2_ENGINE; | |
39 |
|
42 | |||
40 | architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is |
|
43 | architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is | |
41 |
|
44 | |||
42 | constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome); |
|
45 | constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome); | |
43 |
|
46 | |||
44 |
|
47 | |||
45 |
|
48 | |||
46 | signal SYNCH : LCD_DRVR_SYNCH_BUSS; |
|
49 | signal SYNCH : LCD_DRVR_SYNCH_BUSS; | |
47 | signal DRIVER_CMD : LCD_DRVR_CMD_BUSS; |
|
50 | signal DRIVER_CMD : LCD_DRVR_CMD_BUSS; | |
48 | signal FRAME_CLK : std_logic; |
|
51 | signal FRAME_CLK : std_logic; | |
49 |
|
52 | |||
50 | signal FRAME_CLK_reg : std_logic; |
|
53 | signal FRAME_CLK_reg : std_logic; | |
51 | signal RefreshFlag : std_logic; |
|
54 | signal RefreshFlag : std_logic; | |
52 | signal CMD_Flag : std_logic; |
|
55 | signal CMD_Flag : std_logic; | |
53 | signal Exec_Reg : std_logic; |
|
56 | signal Exec_Reg : std_logic; | |
54 |
|
57 | |||
55 | type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1); |
|
58 | type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1); | |
56 | signal state : state_t; |
|
59 | signal state : state_t; | |
57 | signal i : integer range 0 to lcd_space_size := 0; |
|
60 | signal i : integer range 0 to lcd_space_size := 0; | |
58 |
|
61 | |||
59 |
|
62 | |||
60 |
|
63 | |||
61 | begin |
|
64 | begin | |
62 |
|
65 | |||
63 | Driver0 : LCD_16x2_DRIVER |
|
66 | Driver0 : LCD_16x2_DRIVER | |
64 | generic map(OSC_freqKHz) |
|
67 | generic map(OSC_freqKHz) | |
65 | Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD); |
|
68 | Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD); | |
66 |
|
69 | |||
67 | FRAME_CLK_GEN0 : FRAME_CLK_GEN |
|
70 | FRAME_CLK_GEN0 : FRAME_CLK_GEN | |
68 | generic map(OSC_freqKHz) |
|
71 | generic map(OSC_freqKHz) | |
69 | Port map( clk,reset,FRAME_CLK); |
|
72 | Port map( clk,reset,FRAME_CLK); | |
70 |
|
73 | |||
71 |
|
74 | |||
72 |
|
75 | |||
73 | process(reset,clk) |
|
76 | process(reset,clk) | |
74 | begin |
|
77 | begin | |
75 | if reset = '0' then |
|
78 | if reset = '0' then | |
76 | state <= INIT0; |
|
79 | state <= INIT0; | |
77 | Ready <= '0'; |
|
80 | Ready <= '0'; | |
78 | RefreshFlag <= '0'; |
|
81 | RefreshFlag <= '0'; | |
79 | i <= 0; |
|
82 | i <= 0; | |
80 | elsif clk'event and clk ='1' then |
|
83 | elsif clk'event and clk ='1' then | |
81 | FRAME_CLK_reg <= FRAME_CLK; |
|
84 | FRAME_CLK_reg <= FRAME_CLK; | |
82 | Exec_Reg <= Exec; |
|
85 | Exec_Reg <= Exec; | |
83 |
|
86 | |||
84 | if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then |
|
87 | if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then | |
85 | RefreshFlag <= '1'; |
|
88 | RefreshFlag <= '1'; | |
86 | elsif state = Refresh or state = Refresh0 or state = Refresh1 then |
|
89 | elsif state = Refresh or state = Refresh0 or state = Refresh1 then | |
87 | RefreshFlag <= '0'; |
|
90 | RefreshFlag <= '0'; | |
88 | end if; |
|
91 | end if; | |
89 |
|
92 | |||
90 | if Exec_Reg = '0' and Exec = '1' then |
|
93 | if Exec_Reg = '0' and Exec = '1' then | |
91 | CMD_Flag <= '1'; |
|
94 | CMD_Flag <= '1'; | |
92 | elsif state = ExecCMD0 or state = ExecCMD1 then |
|
95 | elsif state = ExecCMD0 or state = ExecCMD1 then | |
93 | CMD_Flag <= '0'; |
|
96 | CMD_Flag <= '0'; | |
94 | end if; |
|
97 | end if; | |
95 |
|
98 | |||
96 | case state is |
|
99 | case state is | |
97 | when INIT0 => |
|
100 | when INIT0 => | |
98 | if SYNCH.DRVR_READY = '1' then |
|
101 | if SYNCH.DRVR_READY = '1' then | |
99 | DRIVER_CMD.Exec <= '1'; |
|
102 | DRIVER_CMD.Exec <= '1'; | |
100 | DRIVER_CMD.Duration <= Duration_20ms; |
|
103 | DRIVER_CMD.Duration <= Duration_20ms; | |
101 | DRIVER_CMD.CMD_Data <= '0'; |
|
104 | DRIVER_CMD.CMD_Data <= '0'; | |
102 | DRIVER_CMD.Word <= ConfigTbl(i); |
|
105 | DRIVER_CMD.Word <= ConfigTbl(i); | |
103 | i <= i + 1; |
|
106 | i <= i + 1; | |
104 | state <= INIT1; |
|
107 | state <= INIT1; | |
105 | else |
|
108 | else | |
106 | DRIVER_CMD.Exec <= '0'; |
|
109 | DRIVER_CMD.Exec <= '0'; | |
107 | end if; |
|
110 | end if; | |
108 | when INIT1 => |
|
111 | when INIT1 => | |
109 | state <= INIT2; |
|
112 | state <= INIT2; | |
110 | DRIVER_CMD.Exec <= '0'; |
|
113 | DRIVER_CMD.Exec <= '0'; | |
111 | when INIT2 => |
|
114 | when INIT2 => | |
112 | if SYNCH.DRVR_READY = '1' then |
|
115 | if SYNCH.DRVR_READY = '1' then | |
113 | if i = 5 then |
|
116 | if i = 5 then | |
114 | state <= Idle; |
|
117 | state <= Idle; | |
115 | else |
|
118 | else | |
116 | state <= INIT0; |
|
119 | state <= INIT0; | |
117 | end if; |
|
120 | end if; | |
118 | end if; |
|
121 | end if; | |
119 | when Idle=> |
|
122 | when Idle=> | |
120 | DRIVER_CMD.Exec <= '0'; |
|
123 | DRIVER_CMD.Exec <= '0'; | |
121 | if RefreshFlag = '1' then |
|
124 | if RefreshFlag = '1' then | |
122 | Ready <= '0'; |
|
125 | Ready <= '0'; | |
123 | state <= Refresh; |
|
126 | state <= Refresh; | |
124 | elsif CMD_Flag = '1' then |
|
127 | elsif CMD_Flag = '1' then | |
125 | Ready <= '0'; |
|
128 | Ready <= '0'; | |
126 | state <= ExecCMD0; |
|
129 | state <= ExecCMD0; | |
127 | else |
|
130 | else | |
128 | Ready <= '1'; |
|
131 | Ready <= '1'; | |
129 | end if; |
|
132 | end if; | |
130 | i <= 0; |
|
133 | i <= 0; | |
131 | when Refresh=> |
|
134 | when Refresh=> | |
132 | if SYNCH.DRVR_READY = '1' then |
|
135 | if SYNCH.DRVR_READY = '1' then | |
133 | DRIVER_CMD.Exec <= '1'; |
|
136 | DRIVER_CMD.Exec <= '1'; | |
134 | DRIVER_CMD.Duration <= Duration_100us; |
|
137 | DRIVER_CMD.Duration <= Duration_100us; | |
135 | DRIVER_CMD.CMD_Data <= '1'; |
|
138 | DRIVER_CMD.CMD_Data <= '1'; | |
136 | DRIVER_CMD.Word <= DATA(i); |
|
139 | DRIVER_CMD.Word <= DATA(i); | |
137 | state <= Refresh0; |
|
140 | state <= Refresh0; | |
138 | else |
|
141 | else | |
139 | DRIVER_CMD.Exec <= '0'; |
|
142 | DRIVER_CMD.Exec <= '0'; | |
140 | end if; |
|
143 | end if; | |
141 | when Refresh0=> |
|
144 | when Refresh0=> | |
142 | i <= i + 1; |
|
145 | i <= i + 1; | |
143 | state <= Refresh1; |
|
146 | state <= Refresh1; | |
144 | DRIVER_CMD.Exec <= '0'; |
|
147 | DRIVER_CMD.Exec <= '0'; | |
145 | when Refresh1=> |
|
148 | when Refresh1=> | |
146 | if SYNCH.DRVR_READY = '1' then |
|
149 | if SYNCH.DRVR_READY = '1' then | |
147 | if i = lcd_space_size then |
|
150 | if i = lcd_space_size then | |
148 | -- state <= ReturnHome; |
|
151 | -- state <= ReturnHome; | |
149 | state <= Idle; |
|
152 | state <= Idle; | |
150 | -- elsif i = 16 then |
|
153 | -- elsif i = 16 then | |
151 | -- state <= GoLine2; |
|
154 | -- state <= GoLine2; | |
152 | else |
|
155 | else | |
153 | state <= Refresh; |
|
156 | state <= Refresh; | |
154 | end if; |
|
157 | end if; | |
155 | end if; |
|
158 | end if; | |
156 |
|
159 | |||
157 | when ExecCMD0=> |
|
160 | when ExecCMD0=> | |
158 | if SYNCH.DRVR_READY = '1' then |
|
161 | if SYNCH.DRVR_READY = '1' then | |
159 | DRIVER_CMD.Exec <= '1'; |
|
162 | DRIVER_CMD.Exec <= '1'; | |
160 | DRIVER_CMD.Duration <= CMD(9 downto 8); |
|
163 | DRIVER_CMD.Duration <= CMD(9 downto 8); | |
161 | DRIVER_CMD.CMD_Data <= '0'; |
|
164 | DRIVER_CMD.CMD_Data <= '0'; | |
162 | DRIVER_CMD.Word <= CMD(7 downto 0); |
|
165 | DRIVER_CMD.Word <= CMD(7 downto 0); | |
163 | state <= ExecCMD1; |
|
166 | state <= ExecCMD1; | |
164 | else |
|
167 | else | |
165 | DRIVER_CMD.Exec <= '0'; |
|
168 | DRIVER_CMD.Exec <= '0'; | |
166 | end if; |
|
169 | end if; | |
167 |
|
170 | |||
168 | when ExecCMD1=> |
|
171 | when ExecCMD1=> | |
169 | state <= Idle; |
|
172 | state <= Idle; | |
170 | DRIVER_CMD.Exec <= '0'; |
|
173 | DRIVER_CMD.Exec <= '0'; | |
171 |
|
174 | |||
172 | when GoLine2=> |
|
175 | when GoLine2=> | |
173 | if SYNCH.DRVR_READY = '1' then |
|
176 | if SYNCH.DRVR_READY = '1' then | |
174 | DRIVER_CMD.Exec <= '1'; |
|
177 | DRIVER_CMD.Exec <= '1'; | |
175 | DRIVER_CMD.Duration <= Duration_4ms; |
|
178 | DRIVER_CMD.Duration <= Duration_4ms; | |
176 | DRIVER_CMD.CMD_Data <= '0'; |
|
179 | DRIVER_CMD.CMD_Data <= '0'; | |
177 | DRIVER_CMD.Word <= X"C0"; |
|
180 | DRIVER_CMD.Word <= X"C0"; | |
178 | state <= GoLine2_0; |
|
181 | state <= GoLine2_0; | |
179 | else |
|
182 | else | |
180 | DRIVER_CMD.Exec <= '0'; |
|
183 | DRIVER_CMD.Exec <= '0'; | |
181 | end if; |
|
184 | end if; | |
182 | when GoLine2_0=> |
|
185 | when GoLine2_0=> | |
183 | state <= Refresh; |
|
186 | state <= Refresh; | |
184 | DRIVER_CMD.Exec <= '0'; |
|
187 | DRIVER_CMD.Exec <= '0'; | |
185 | when ReturnHome=> |
|
188 | when ReturnHome=> | |
186 | if SYNCH.DRVR_READY = '1' then |
|
189 | if SYNCH.DRVR_READY = '1' then | |
187 | DRIVER_CMD.Exec <= '1'; |
|
190 | DRIVER_CMD.Exec <= '1'; | |
188 | DRIVER_CMD.Duration <= Duration_4ms; |
|
191 | DRIVER_CMD.Duration <= Duration_4ms; | |
189 | DRIVER_CMD.CMD_Data <= '0'; |
|
192 | DRIVER_CMD.CMD_Data <= '0'; | |
190 | DRIVER_CMD.Word <= RetHome; |
|
193 | DRIVER_CMD.Word <= RetHome; | |
191 | state <= Idle; |
|
194 | state <= Idle; | |
192 | else |
|
195 | else | |
193 | DRIVER_CMD.Exec <= '0'; |
|
196 | DRIVER_CMD.Exec <= '0'; | |
194 | end if; |
|
197 | end if; | |
195 | end case; |
|
198 | end case; | |
196 | end if; |
|
199 | end if; | |
197 | end process; |
|
200 | end process; | |
198 |
|
201 | |||
199 |
|
202 | |||
200 | end ar_LCD_16x2_ENGINE; |
|
203 | end ar_LCD_16x2_ENGINE; | |
201 |
|
204 | |||
202 |
|
205 | |||
203 |
|
206 | |||
204 |
|
207 | |||
205 |
|
208 | |||
206 |
|
209 | |||
207 |
|
210 | |||
208 |
|
211 | |||
209 |
|
212 | |||
210 |
|
213 |
@@ -1,156 +1,159 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 | use IEEE.NUMERIC_STD.all; |
|
24 | use IEEE.NUMERIC_STD.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.amba_lcd_16x2_ctrlr.all; |
|
26 | use lpp.amba_lcd_16x2_ctrlr.all; | |
24 |
|
27 | |||
25 | entity LCD_2x16_DRIVER is |
|
28 | entity LCD_2x16_DRIVER is | |
26 | generic( |
|
29 | generic( | |
27 | OSC_Freq_MHz : integer:=60; |
|
30 | OSC_Freq_MHz : integer:=60; | |
28 | Refresh_RateHz : integer:=5 |
|
31 | Refresh_RateHz : integer:=5 | |
29 | ); |
|
32 | ); | |
30 | Port ( clk : in STD_LOGIC; |
|
33 | Port ( clk : in STD_LOGIC; | |
31 | reset : in STD_LOGIC; |
|
34 | reset : in STD_LOGIC; | |
32 | FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); |
|
35 | FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); | |
33 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); |
|
36 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
34 | LCD_RS : out STD_LOGIC; |
|
37 | LCD_RS : out STD_LOGIC; | |
35 | LCD_RW : out STD_LOGIC; |
|
38 | LCD_RW : out STD_LOGIC; | |
36 | LCD_E : out STD_LOGIC; |
|
39 | LCD_E : out STD_LOGIC; | |
37 | LCD_RET : out STD_LOGIC; |
|
40 | LCD_RET : out STD_LOGIC; | |
38 | LCD_CS1 : out STD_LOGIC; |
|
41 | LCD_CS1 : out STD_LOGIC; | |
39 | LCD_CS2 : out STD_LOGIC; |
|
42 | LCD_CS2 : out STD_LOGIC; | |
40 | STATEOUT: out std_logic_vector(3 downto 0); |
|
43 | STATEOUT: out std_logic_vector(3 downto 0); | |
41 | refreshPulse : out std_logic |
|
44 | refreshPulse : out std_logic | |
42 | ); |
|
45 | ); | |
43 | end LCD_2x16_DRIVER; |
|
46 | end LCD_2x16_DRIVER; | |
44 |
|
47 | |||
45 | architecture Behavioral of LCD_2x16_DRIVER is |
|
48 | architecture Behavioral of LCD_2x16_DRIVER is | |
46 |
|
49 | |||
47 | type stateT is(Rst,Configure,IDLE,RefreshScreen); |
|
50 | type stateT is(Rst,Configure,IDLE,RefreshScreen); | |
48 | signal state : stateT; |
|
51 | signal state : stateT; | |
49 |
|
52 | |||
50 | signal ShortTimePulse : std_logic; |
|
53 | signal ShortTimePulse : std_logic; | |
51 | signal MidleTimePulse : std_logic; |
|
54 | signal MidleTimePulse : std_logic; | |
52 | signal Refresh_RatePulse : std_logic; |
|
55 | signal Refresh_RatePulse : std_logic; | |
53 | signal Start : STD_LOGIC; |
|
56 | signal Start : STD_LOGIC; | |
54 |
|
57 | |||
55 | signal CFGM_LCD_RS : std_logic; |
|
58 | signal CFGM_LCD_RS : std_logic; | |
56 | signal CFGM_LCD_RW : std_logic; |
|
59 | signal CFGM_LCD_RW : std_logic; | |
57 | signal CFGM_LCD_E : std_logic; |
|
60 | signal CFGM_LCD_E : std_logic; | |
58 | signal CFGM_LCD_DATA : std_logic_vector(7 downto 0); |
|
61 | signal CFGM_LCD_DATA : std_logic_vector(7 downto 0); | |
59 | signal CFGM_Enable : std_logic; |
|
62 | signal CFGM_Enable : std_logic; | |
60 | signal CFGM_completed : std_logic; |
|
63 | signal CFGM_completed : std_logic; | |
61 |
|
64 | |||
62 |
|
65 | |||
63 | signal FRMW_LCD_RS : std_logic; |
|
66 | signal FRMW_LCD_RS : std_logic; | |
64 | signal FRMW_LCD_RW : std_logic; |
|
67 | signal FRMW_LCD_RW : std_logic; | |
65 | signal FRMW_LCD_E : std_logic; |
|
68 | signal FRMW_LCD_E : std_logic; | |
66 | signal FRMW_LCD_DATA : std_logic_vector(7 downto 0); |
|
69 | signal FRMW_LCD_DATA : std_logic_vector(7 downto 0); | |
67 | signal FRMW_Enable : std_logic; |
|
70 | signal FRMW_Enable : std_logic; | |
68 | signal FRMW_completed : std_logic; |
|
71 | signal FRMW_completed : std_logic; | |
69 |
|
72 | |||
70 | begin |
|
73 | begin | |
71 |
|
74 | |||
72 |
|
75 | |||
73 | Counter : LCD_Counter |
|
76 | Counter : LCD_Counter | |
74 | generic map(OSC_Freq_MHz,Refresh_RateHz) |
|
77 | generic map(OSC_Freq_MHz,Refresh_RateHz) | |
75 | port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start); |
|
78 | port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start); | |
76 |
|
79 | |||
77 | ConfigModule : Config_Module |
|
80 | ConfigModule : Config_Module | |
78 | port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse); |
|
81 | port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse); | |
79 |
|
82 | |||
80 |
|
83 | |||
81 | FrameWriter : FRAME_WRITER |
|
84 | FrameWriter : FRAME_WRITER | |
82 | port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse); |
|
85 | port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse); | |
83 |
|
86 | |||
84 |
|
87 | |||
85 | STATEOUT(0) <= '1' when state = Rst else '0'; |
|
88 | STATEOUT(0) <= '1' when state = Rst else '0'; | |
86 | STATEOUT(1) <= '1' when state = Configure else '0'; |
|
89 | STATEOUT(1) <= '1' when state = Configure else '0'; | |
87 | STATEOUT(2) <= '1' when state = IDLE else '0'; |
|
90 | STATEOUT(2) <= '1' when state = IDLE else '0'; | |
88 | STATEOUT(3) <= '1' when state = RefreshScreen else '0'; |
|
91 | STATEOUT(3) <= '1' when state = RefreshScreen else '0'; | |
89 |
|
92 | |||
90 |
|
93 | |||
91 |
|
94 | |||
92 | refreshPulse <= Refresh_RatePulse; |
|
95 | refreshPulse <= Refresh_RatePulse; | |
93 |
|
96 | |||
94 | Start <= '1'; |
|
97 | Start <= '1'; | |
95 |
|
98 | |||
96 | process(reset,clk) |
|
99 | process(reset,clk) | |
97 | begin |
|
100 | begin | |
98 | if reset = '0' then |
|
101 | if reset = '0' then | |
99 | LCD_data <= (others=>'0'); |
|
102 | LCD_data <= (others=>'0'); | |
100 | LCD_RS <= '0'; |
|
103 | LCD_RS <= '0'; | |
101 | LCD_RW <= '0'; |
|
104 | LCD_RW <= '0'; | |
102 | LCD_RET <= '0'; |
|
105 | LCD_RET <= '0'; | |
103 | LCD_CS1 <= '0'; |
|
106 | LCD_CS1 <= '0'; | |
104 | LCD_CS2 <= '0'; |
|
107 | LCD_CS2 <= '0'; | |
105 | LCD_E <= '0'; |
|
108 | LCD_E <= '0'; | |
106 | state <= Rst; |
|
109 | state <= Rst; | |
107 | CFGM_Enable <= '0'; |
|
110 | CFGM_Enable <= '0'; | |
108 | FRMW_Enable <= '0'; |
|
111 | FRMW_Enable <= '0'; | |
109 | elsif clk'event and clk ='1' then |
|
112 | elsif clk'event and clk ='1' then | |
110 | case state is |
|
113 | case state is | |
111 | when Rst => |
|
114 | when Rst => | |
112 | LCD_data <= (others=>'0'); |
|
115 | LCD_data <= (others=>'0'); | |
113 | LCD_RS <= '0'; |
|
116 | LCD_RS <= '0'; | |
114 | LCD_RW <= '0'; |
|
117 | LCD_RW <= '0'; | |
115 | LCD_E <= '0'; |
|
118 | LCD_E <= '0'; | |
116 | CFGM_Enable <= '1'; |
|
119 | CFGM_Enable <= '1'; | |
117 | FRMW_Enable <= '0'; |
|
120 | FRMW_Enable <= '0'; | |
118 | if Refresh_RatePulse = '1' then |
|
121 | if Refresh_RatePulse = '1' then | |
119 | state <= Configure; |
|
122 | state <= Configure; | |
120 | end if; |
|
123 | end if; | |
121 | when Configure => |
|
124 | when Configure => | |
122 | LCD_data <= CFGM_LCD_data; |
|
125 | LCD_data <= CFGM_LCD_data; | |
123 | LCD_RS <= CFGM_LCD_RS; |
|
126 | LCD_RS <= CFGM_LCD_RS; | |
124 | LCD_RW <= CFGM_LCD_RW; |
|
127 | LCD_RW <= CFGM_LCD_RW; | |
125 | LCD_E <= CFGM_LCD_E; |
|
128 | LCD_E <= CFGM_LCD_E; | |
126 | CFGM_Enable <= '0'; |
|
129 | CFGM_Enable <= '0'; | |
127 | if CFGM_completed = '1' then |
|
130 | if CFGM_completed = '1' then | |
128 | state <= IDLE; |
|
131 | state <= IDLE; | |
129 | end if; |
|
132 | end if; | |
130 | when IDLE => |
|
133 | when IDLE => | |
131 | if Refresh_RatePulse = '1' then |
|
134 | if Refresh_RatePulse = '1' then | |
132 | state <= RefreshScreen; |
|
135 | state <= RefreshScreen; | |
133 | FRMW_Enable <= '1'; |
|
136 | FRMW_Enable <= '1'; | |
134 | end if; |
|
137 | end if; | |
135 | LCD_RS <= '0'; |
|
138 | LCD_RS <= '0'; | |
136 | LCD_RW <= '0'; |
|
139 | LCD_RW <= '0'; | |
137 | LCD_E <= '0'; |
|
140 | LCD_E <= '0'; | |
138 | LCD_data <= (others=>'0'); |
|
141 | LCD_data <= (others=>'0'); | |
139 | when RefreshScreen => |
|
142 | when RefreshScreen => | |
140 | LCD_data <= FRMW_LCD_data; |
|
143 | LCD_data <= FRMW_LCD_data; | |
141 | LCD_RS <= FRMW_LCD_RS; |
|
144 | LCD_RS <= FRMW_LCD_RS; | |
142 | LCD_RW <= FRMW_LCD_RW; |
|
145 | LCD_RW <= FRMW_LCD_RW; | |
143 | LCD_E <= FRMW_LCD_E; |
|
146 | LCD_E <= FRMW_LCD_E; | |
144 | FRMW_Enable <= '0'; |
|
147 | FRMW_Enable <= '0'; | |
145 | if FRMW_completed = '1' then |
|
148 | if FRMW_completed = '1' then | |
146 | state <= IDLE; |
|
149 | state <= IDLE; | |
147 | end if; |
|
150 | end if; | |
148 | end case; |
|
151 | end case; | |
149 | end if; |
|
152 | end if; | |
150 | end process; |
|
153 | end process; | |
151 | end Behavioral; |
|
154 | end Behavioral; | |
152 |
|
155 | |||
153 |
|
156 | |||
154 |
|
157 | |||
155 |
|
158 | |||
156 |
|
159 |
@@ -1,72 +1,75 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 | use IEEE.NUMERIC_STD.ALL; |
|
24 | use IEEE.NUMERIC_STD.ALL; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.amba_lcd_16x2_ctrlr.all; |
|
26 | use lpp.amba_lcd_16x2_ctrlr.all; | |
24 |
|
27 | |||
25 | entity LCD_CLK_GENERATOR is |
|
28 | entity LCD_CLK_GENERATOR is | |
26 | generic(OSC_freqKHz : integer := 50000); |
|
29 | generic(OSC_freqKHz : integer := 50000); | |
27 | Port ( clk : in STD_LOGIC; |
|
30 | Port ( clk : in STD_LOGIC; | |
28 | reset : in STD_LOGIC; |
|
31 | reset : in STD_LOGIC; | |
29 | clk_1us : out STD_LOGIC); |
|
32 | clk_1us : out STD_LOGIC); | |
30 | end LCD_CLK_GENERATOR; |
|
33 | end LCD_CLK_GENERATOR; | |
31 |
|
34 | |||
32 | architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is |
|
35 | architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is | |
33 |
|
36 | |||
34 | Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1; |
|
37 | Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1; | |
35 |
|
38 | |||
36 |
|
39 | |||
37 | signal cpt1 : integer; |
|
40 | signal cpt1 : integer; | |
38 |
|
41 | |||
39 | signal clk_1us_int : std_logic := '0'; |
|
42 | signal clk_1us_int : std_logic := '0'; | |
40 |
|
43 | |||
41 |
|
44 | |||
42 | begin |
|
45 | begin | |
43 |
|
46 | |||
44 | clk_1us <= clk_1us_int; |
|
47 | clk_1us <= clk_1us_int; | |
45 |
|
48 | |||
46 |
|
49 | |||
47 | process(reset,clk) |
|
50 | process(reset,clk) | |
48 | begin |
|
51 | begin | |
49 | if reset = '0' then |
|
52 | if reset = '0' then | |
50 | cpt1 <= 0; |
|
53 | cpt1 <= 0; | |
51 | clk_1us_int <= '0'; |
|
54 | clk_1us_int <= '0'; | |
52 | elsif clk'event and clk = '1' then |
|
55 | elsif clk'event and clk = '1' then | |
53 | if cpt1 = clk_1usTRIGER then |
|
56 | if cpt1 = clk_1usTRIGER then | |
54 | clk_1us_int <= not clk_1us_int; |
|
57 | clk_1us_int <= not clk_1us_int; | |
55 | cpt1 <= 0; |
|
58 | cpt1 <= 0; | |
56 | else |
|
59 | else | |
57 | cpt1 <= cpt1 + 1; |
|
60 | cpt1 <= cpt1 + 1; | |
58 | end if; |
|
61 | end if; | |
59 | end if; |
|
62 | end if; | |
60 | end process; |
|
63 | end process; | |
61 |
|
64 | |||
62 |
|
65 | |||
63 | end ar_LCD_CLK_GENERATOR; |
|
66 | end ar_LCD_CLK_GENERATOR; | |
64 |
|
67 | |||
65 |
|
68 | |||
66 |
|
69 | |||
67 |
|
70 | |||
68 |
|
71 | |||
69 |
|
72 | |||
70 |
|
73 | |||
71 |
|
74 | |||
72 |
|
75 |
@@ -1,105 +1,107 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | ------------------------------------------------------------------------------ |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
20 | library IEEE; |
|
22 | library IEEE; | |
21 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
22 |
|
24 | |||
23 | library lpp; |
|
25 | library lpp; | |
24 | use lpp.amba_lcd_16x2_ctrlr.all; |
|
26 | use lpp.amba_lcd_16x2_ctrlr.all; | |
25 | use lpp.LCD_16x2_CFG.all; |
|
27 | use lpp.LCD_16x2_CFG.all; | |
26 |
|
28 | |||
27 |
|
29 | |||
28 | entity AMBA_LCD_16x2_DRIVER is |
|
30 | entity AMBA_LCD_16x2_DRIVER is | |
29 | Port ( reset : in STD_LOGIC; |
|
31 | Port ( reset : in STD_LOGIC; | |
30 | clk : in STD_LOGIC; |
|
32 | clk : in STD_LOGIC; | |
31 | Bp0 : in STD_LOGIC; |
|
33 | Bp0 : in STD_LOGIC; | |
32 | Bp1 : in STD_LOGIC; |
|
34 | Bp1 : in STD_LOGIC; | |
33 | Bp2 : in STD_LOGIC; |
|
35 | Bp2 : in STD_LOGIC; | |
34 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); |
|
36 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
35 | LCD_RS : out STD_LOGIC; |
|
37 | LCD_RS : out STD_LOGIC; | |
36 | LCD_RW : out STD_LOGIC; |
|
38 | LCD_RW : out STD_LOGIC; | |
37 | LCD_E : out STD_LOGIC; |
|
39 | LCD_E : out STD_LOGIC; | |
38 | LCD_RET : out STD_LOGIC; |
|
40 | LCD_RET : out STD_LOGIC; | |
39 | LCD_CS1 : out STD_LOGIC; |
|
41 | LCD_CS1 : out STD_LOGIC; | |
40 | LCD_CS2 : out STD_LOGIC; |
|
42 | LCD_CS2 : out STD_LOGIC; | |
41 | SF_CE0 : out std_logic |
|
43 | SF_CE0 : out std_logic | |
42 | ); |
|
44 | ); | |
43 | end AMBA_LCD_16x2_DRIVER; |
|
45 | end AMBA_LCD_16x2_DRIVER; | |
44 |
|
46 | |||
45 | architecture Behavioral of AMBA_LCD_16x2_DRIVER is |
|
47 | architecture Behavioral of AMBA_LCD_16x2_DRIVER is | |
46 |
|
48 | |||
47 | signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0); |
|
49 | signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0); | |
48 | signal CMD : std_logic_vector(10 downto 0); |
|
50 | signal CMD : std_logic_vector(10 downto 0); | |
49 | signal Exec : std_logic; |
|
51 | signal Exec : std_logic; | |
50 | signal Ready : std_logic; |
|
52 | signal Ready : std_logic; | |
51 | signal rst : std_logic; |
|
53 | signal rst : std_logic; | |
52 | signal LCD_CTRL : LCD_DRVR_CTRL_BUSS; |
|
54 | signal LCD_CTRL : LCD_DRVR_CTRL_BUSS; | |
53 |
|
55 | |||
54 | begin |
|
56 | begin | |
55 |
|
57 | |||
56 | LCD_data <= LCD_CTRL.LCD_DATA; |
|
58 | LCD_data <= LCD_CTRL.LCD_DATA; | |
57 | LCD_RS <= LCD_CTRL.LCD_RS; |
|
59 | LCD_RS <= LCD_CTRL.LCD_RS; | |
58 | LCD_RW <= LCD_CTRL.LCD_RW; |
|
60 | LCD_RW <= LCD_CTRL.LCD_RW; | |
59 | LCD_E <= LCD_CTRL.LCD_E; |
|
61 | LCD_E <= LCD_CTRL.LCD_E; | |
60 |
|
62 | |||
61 |
|
63 | |||
62 | LCD_RET <= '0'; |
|
64 | LCD_RET <= '0'; | |
63 | LCD_CS1 <= '0'; |
|
65 | LCD_CS1 <= '0'; | |
64 | LCD_CS2 <= '0'; |
|
66 | LCD_CS2 <= '0'; | |
65 |
|
67 | |||
66 | SF_CE0 <= '1'; |
|
68 | SF_CE0 <= '1'; | |
67 |
|
69 | |||
68 |
|
70 | |||
69 |
|
71 | |||
70 |
|
72 | |||
71 | Driver0 : LCD_16x2_ENGINE |
|
73 | Driver0 : LCD_16x2_ENGINE | |
72 | generic map(50000) |
|
74 | generic map(50000) | |
73 | Port map(clk,reset,FramBUFF,CMD,Exec,Ready,LCD_CTRL); |
|
75 | Port map(clk,reset,FramBUFF,CMD,Exec,Ready,LCD_CTRL); | |
74 |
|
76 | |||
75 | FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else |
|
77 | FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else | |
76 | X"42" when Bp1 = '1' else |
|
78 | X"42" when Bp1 = '1' else | |
77 | X"43" when Bp2 = '1' else |
|
79 | X"43" when Bp2 = '1' else | |
78 | X"44"; |
|
80 | X"44"; | |
79 |
|
81 | |||
80 | FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else |
|
82 | FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else | |
81 | X"47" when Bp1 = '1' else |
|
83 | X"47" when Bp1 = '1' else | |
82 | X"48" when Bp2 = '1' else |
|
84 | X"48" when Bp2 = '1' else | |
83 | X"49"; |
|
85 | X"49"; | |
84 |
|
86 | |||
85 |
|
87 | |||
86 | CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else |
|
88 | CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else | |
87 | Duration_100us & CursorOFF; |
|
89 | Duration_100us & CursorOFF; | |
88 |
|
90 | |||
89 |
|
91 | |||
90 | Exec <= Bp1; |
|
92 | Exec <= Bp1; | |
91 |
|
93 | |||
92 | FramBUFF(2*8+7 downto 2*8) <= X"23"; |
|
94 | FramBUFF(2*8+7 downto 2*8) <= X"23"; | |
93 | FramBUFF(3*8+7 downto 3*8) <= X"66"; |
|
95 | FramBUFF(3*8+7 downto 3*8) <= X"66"; | |
94 | FramBUFF(4*8+7 downto 4*8) <= X"67"; |
|
96 | FramBUFF(4*8+7 downto 4*8) <= X"67"; | |
95 | FramBUFF(5*8+7 downto 5*8) <= X"68"; |
|
97 | FramBUFF(5*8+7 downto 5*8) <= X"68"; | |
96 | FramBUFF(17*8+7 downto 17*8) <= X"69"; |
|
98 | FramBUFF(17*8+7 downto 17*8) <= X"69"; | |
97 | --FramBUFF(16*2*8-1 downto 16) <= (others => '0'); |
|
99 | --FramBUFF(16*2*8-1 downto 16) <= (others => '0'); | |
98 |
|
100 | |||
99 | end Behavioral; |
|
101 | end Behavioral; | |
100 |
|
102 | |||
101 |
|
103 | |||
102 |
|
104 | |||
103 |
|
105 | |||
104 |
|
106 | |||
105 |
|
107 |
@@ -1,170 +1,173 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library ieee; |
|
22 | library ieee; | |
20 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
21 | library grlib; |
|
24 | library grlib; | |
22 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
23 | use grlib.stdlib.all; |
|
26 | use grlib.stdlib.all; | |
24 | use grlib.devices.all; |
|
27 | use grlib.devices.all; | |
25 |
|
28 | |||
26 |
|
29 | |||
27 | package amba_lcd_16x2_ctrlr is |
|
30 | package amba_lcd_16x2_ctrlr is | |
28 |
|
31 | |||
29 | constant lcd_space_size : integer := 80; |
|
32 | constant lcd_space_size : integer := 80; | |
30 |
|
33 | |||
31 | type FRM_Buff_Space is array(lcd_space_size-1 downto 0) of std_logic_vector(7 downto 0); |
|
34 | type FRM_Buff_Space is array(lcd_space_size-1 downto 0) of std_logic_vector(7 downto 0); | |
32 |
|
35 | |||
33 |
|
36 | |||
34 | type LCD_DRVR_CTRL_BUSS is |
|
37 | type LCD_DRVR_CTRL_BUSS is | |
35 | record |
|
38 | record | |
36 | LCD_RW : std_logic; |
|
39 | LCD_RW : std_logic; | |
37 | LCD_RS : std_logic; |
|
40 | LCD_RS : std_logic; | |
38 | LCD_E : std_logic; |
|
41 | LCD_E : std_logic; | |
39 | LCD_DATA : std_logic_vector(7 downto 0); |
|
42 | LCD_DATA : std_logic_vector(7 downto 0); | |
40 | end record; |
|
43 | end record; | |
41 |
|
44 | |||
42 | type LCD_DRVR_SYNCH_BUSS is |
|
45 | type LCD_DRVR_SYNCH_BUSS is | |
43 | record |
|
46 | record | |
44 | DRVR_READY : std_logic; |
|
47 | DRVR_READY : std_logic; | |
45 | LCD_INITIALISED : std_logic; |
|
48 | LCD_INITIALISED : std_logic; | |
46 | end record; |
|
49 | end record; | |
47 |
|
50 | |||
48 |
|
51 | |||
49 | type LCD_DRVR_CMD_BUSS is |
|
52 | type LCD_DRVR_CMD_BUSS is | |
50 | record |
|
53 | record | |
51 | Word : std_logic_vector(7 downto 0); |
|
54 | Word : std_logic_vector(7 downto 0); | |
52 | CMD_Data : std_logic; --CMD = '0' and data = '1' |
|
55 | CMD_Data : std_logic; --CMD = '0' and data = '1' | |
53 | Exec : std_logic; |
|
56 | Exec : std_logic; | |
54 | Duration : std_logic_vector(1 downto 0); |
|
57 | Duration : std_logic_vector(1 downto 0); | |
55 | end record; |
|
58 | end record; | |
56 | type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0); |
|
59 | type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0); | |
57 |
|
60 | |||
58 |
|
61 | |||
59 |
|
62 | |||
60 | component LCD_16x2_DRIVER is |
|
63 | component LCD_16x2_DRIVER is | |
61 | generic( |
|
64 | generic( | |
62 | OSC_Freq_MHz : integer:=60 |
|
65 | OSC_Freq_MHz : integer:=60 | |
63 | ); |
|
66 | ); | |
64 | Port ( reset : in STD_LOGIC; |
|
67 | Port ( reset : in STD_LOGIC; | |
65 | clk : in STD_LOGIC; |
|
68 | clk : in STD_LOGIC; | |
66 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS; |
|
69 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS; | |
67 | SYNCH : out LCD_DRVR_SYNCH_BUSS; |
|
70 | SYNCH : out LCD_DRVR_SYNCH_BUSS; | |
68 | DRIVER_CMD : in LCD_DRVR_CMD_BUSS |
|
71 | DRIVER_CMD : in LCD_DRVR_CMD_BUSS | |
69 | ); |
|
72 | ); | |
70 | end component; |
|
73 | end component; | |
71 |
|
74 | |||
72 |
|
75 | |||
73 |
|
76 | |||
74 | component amba_lcd_16x2_driver is |
|
77 | component amba_lcd_16x2_driver is | |
75 | Port ( reset : in STD_LOGIC; |
|
78 | Port ( reset : in STD_LOGIC; | |
76 | clk : in STD_LOGIC; |
|
79 | clk : in STD_LOGIC; | |
77 | Bp0 : in STD_LOGIC; |
|
80 | Bp0 : in STD_LOGIC; | |
78 | Bp1 : in STD_LOGIC; |
|
81 | Bp1 : in STD_LOGIC; | |
79 | Bp2 : in STD_LOGIC; |
|
82 | Bp2 : in STD_LOGIC; | |
80 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); |
|
83 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
81 | LCD_RS : out STD_LOGIC; |
|
84 | LCD_RS : out STD_LOGIC; | |
82 | LCD_RW : out STD_LOGIC; |
|
85 | LCD_RW : out STD_LOGIC; | |
83 | LCD_E : out STD_LOGIC; |
|
86 | LCD_E : out STD_LOGIC; | |
84 | LCD_RET : out STD_LOGIC; |
|
87 | LCD_RET : out STD_LOGIC; | |
85 | LCD_CS1 : out STD_LOGIC; |
|
88 | LCD_CS1 : out STD_LOGIC; | |
86 | LCD_CS2 : out STD_LOGIC; |
|
89 | LCD_CS2 : out STD_LOGIC; | |
87 | SF_CE0 : out std_logic |
|
90 | SF_CE0 : out std_logic | |
88 | ); |
|
91 | ); | |
89 | end component; |
|
92 | end component; | |
90 |
|
93 | |||
91 |
|
94 | |||
92 |
|
95 | |||
93 | component FRAME_CLK_GEN is |
|
96 | component FRAME_CLK_GEN is | |
94 | generic(OSC_freqKHz : integer := 50000); |
|
97 | generic(OSC_freqKHz : integer := 50000); | |
95 | Port ( clk : in STD_LOGIC; |
|
98 | Port ( clk : in STD_LOGIC; | |
96 | reset : in STD_LOGIC; |
|
99 | reset : in STD_LOGIC; | |
97 | FRAME_CLK : out STD_LOGIC); |
|
100 | FRAME_CLK : out STD_LOGIC); | |
98 | end component; |
|
101 | end component; | |
99 |
|
102 | |||
100 |
|
103 | |||
101 |
|
104 | |||
102 | component LCD_2x16_DRIVER is |
|
105 | component LCD_2x16_DRIVER is | |
103 | generic( |
|
106 | generic( | |
104 | OSC_Freq_MHz : integer:=60; |
|
107 | OSC_Freq_MHz : integer:=60; | |
105 | Refresh_RateHz : integer:=5 |
|
108 | Refresh_RateHz : integer:=5 | |
106 | ); |
|
109 | ); | |
107 | Port ( clk : in STD_LOGIC; |
|
110 | Port ( clk : in STD_LOGIC; | |
108 | reset : in STD_LOGIC; |
|
111 | reset : in STD_LOGIC; | |
109 | FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); |
|
112 | FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); | |
110 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); |
|
113 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
111 | LCD_RS : out STD_LOGIC; |
|
114 | LCD_RS : out STD_LOGIC; | |
112 | LCD_RW : out STD_LOGIC; |
|
115 | LCD_RW : out STD_LOGIC; | |
113 | LCD_E : out STD_LOGIC; |
|
116 | LCD_E : out STD_LOGIC; | |
114 | LCD_RET : out STD_LOGIC; |
|
117 | LCD_RET : out STD_LOGIC; | |
115 | LCD_CS1 : out STD_LOGIC; |
|
118 | LCD_CS1 : out STD_LOGIC; | |
116 | LCD_CS2 : out STD_LOGIC; |
|
119 | LCD_CS2 : out STD_LOGIC; | |
117 | STATEOUT: out std_logic_vector(3 downto 0); |
|
120 | STATEOUT: out std_logic_vector(3 downto 0); | |
118 | refreshPulse : out std_logic |
|
121 | refreshPulse : out std_logic | |
119 | ); |
|
122 | ); | |
120 | end component; |
|
123 | end component; | |
121 |
|
124 | |||
122 |
|
125 | |||
123 | component LCD_CLK_GENERATOR is |
|
126 | component LCD_CLK_GENERATOR is | |
124 | generic(OSC_freqKHz : integer := 50000); |
|
127 | generic(OSC_freqKHz : integer := 50000); | |
125 | Port ( clk : in STD_LOGIC; |
|
128 | Port ( clk : in STD_LOGIC; | |
126 | reset : in STD_LOGIC; |
|
129 | reset : in STD_LOGIC; | |
127 | clk_1us : out STD_LOGIC); |
|
130 | clk_1us : out STD_LOGIC); | |
128 | end component; |
|
131 | end component; | |
129 |
|
132 | |||
130 | component LCD_16x2_ENGINE is |
|
133 | component LCD_16x2_ENGINE is | |
131 | generic(OSC_freqKHz : integer := 50000); |
|
134 | generic(OSC_freqKHz : integer := 50000); | |
132 | Port ( clk : in STD_LOGIC; |
|
135 | Port ( clk : in STD_LOGIC; | |
133 | reset : in STD_LOGIC; |
|
136 | reset : in STD_LOGIC; | |
134 | DATA : in FRM_Buff_Space; |
|
137 | DATA : in FRM_Buff_Space; | |
135 | CMD : in std_logic_vector(10 downto 0); |
|
138 | CMD : in std_logic_vector(10 downto 0); | |
136 | Exec : in std_logic; |
|
139 | Exec : in std_logic; | |
137 | Ready : out std_logic; |
|
140 | Ready : out std_logic; | |
138 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS |
|
141 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS | |
139 | ); |
|
142 | ); | |
140 | end component; |
|
143 | end component; | |
141 |
|
144 | |||
142 |
|
145 | |||
143 |
|
146 | |||
144 | component apb_lcd_ctrlr is |
|
147 | component apb_lcd_ctrlr is | |
145 | generic ( |
|
148 | generic ( | |
146 | pindex : integer := 0; |
|
149 | pindex : integer := 0; | |
147 | paddr : integer := 0; |
|
150 | paddr : integer := 0; | |
148 | pmask : integer := 16#fff#; |
|
151 | pmask : integer := 16#fff#; | |
149 | pirq : integer := 0; |
|
152 | pirq : integer := 0; | |
150 | abits : integer := 8); |
|
153 | abits : integer := 8); | |
151 | port ( |
|
154 | port ( | |
152 | rst : in std_ulogic; |
|
155 | rst : in std_ulogic; | |
153 | clk : in std_ulogic; |
|
156 | clk : in std_ulogic; | |
154 | apbi : in apb_slv_in_type; |
|
157 | apbi : in apb_slv_in_type; | |
155 | apbo : out apb_slv_out_type; |
|
158 | apbo : out apb_slv_out_type; | |
156 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); |
|
159 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
157 | LCD_RS : out STD_LOGIC; |
|
160 | LCD_RS : out STD_LOGIC; | |
158 | LCD_RW : out STD_LOGIC; |
|
161 | LCD_RW : out STD_LOGIC; | |
159 | LCD_E : out STD_LOGIC; |
|
162 | LCD_E : out STD_LOGIC; | |
160 | LCD_RET : out STD_LOGIC; |
|
163 | LCD_RET : out STD_LOGIC; | |
161 | LCD_CS1 : out STD_LOGIC; |
|
164 | LCD_CS1 : out STD_LOGIC; | |
162 | LCD_CS2 : out STD_LOGIC; |
|
165 | LCD_CS2 : out STD_LOGIC; | |
163 | SF_CE0 : out std_logic |
|
166 | SF_CE0 : out std_logic | |
164 | ); |
|
167 | ); | |
165 | end component; |
|
168 | end component; | |
166 |
|
169 | |||
167 |
|
170 | |||
168 |
|
171 | |||
169 |
|
172 | |||
170 | end; |
|
173 | end; |
@@ -1,164 +1,167 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | -------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 | use ieee.numeric_std.all; |
|
24 | use ieee.numeric_std.all; | |
22 | library grlib; |
|
25 | library grlib; | |
23 | use grlib.amba.all; |
|
26 | use grlib.amba.all; | |
24 | use grlib.stdlib.all; |
|
27 | use grlib.stdlib.all; | |
25 | use grlib.devices.all; |
|
28 | use grlib.devices.all; | |
26 | library lpp; |
|
29 | library lpp; | |
27 | use lpp.amba_lcd_16x2_ctrlr.all; |
|
30 | use lpp.amba_lcd_16x2_ctrlr.all; | |
28 | use lpp.LCD_16x2_CFG.all; |
|
31 | use lpp.LCD_16x2_CFG.all; | |
29 | use lpp.lpp_amba.all; |
|
32 | use lpp.lpp_amba.all; | |
30 | use lpp.apb_devices_list.all; |
|
33 | use lpp.apb_devices_list.all; | |
31 |
|
34 | |||
32 | entity apb_lcd_ctrlr is |
|
35 | entity apb_lcd_ctrlr is | |
33 | generic ( |
|
36 | generic ( | |
34 | pindex : integer := 0; |
|
37 | pindex : integer := 0; | |
35 | paddr : integer := 0; |
|
38 | paddr : integer := 0; | |
36 | pmask : integer := 16#fff#; |
|
39 | pmask : integer := 16#fff#; | |
37 | pirq : integer := 0; |
|
40 | pirq : integer := 0; | |
38 | abits : integer := 8); |
|
41 | abits : integer := 8); | |
39 | port ( |
|
42 | port ( | |
40 | rst : in std_ulogic; |
|
43 | rst : in std_ulogic; | |
41 | clk : in std_ulogic; |
|
44 | clk : in std_ulogic; | |
42 | apbi : in apb_slv_in_type; |
|
45 | apbi : in apb_slv_in_type; | |
43 | apbo : out apb_slv_out_type; |
|
46 | apbo : out apb_slv_out_type; | |
44 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); |
|
47 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
45 | LCD_RS : out STD_LOGIC; |
|
48 | LCD_RS : out STD_LOGIC; | |
46 | LCD_RW : out STD_LOGIC; |
|
49 | LCD_RW : out STD_LOGIC; | |
47 | LCD_E : out STD_LOGIC; |
|
50 | LCD_E : out STD_LOGIC; | |
48 | LCD_RET : out STD_LOGIC; |
|
51 | LCD_RET : out STD_LOGIC; | |
49 | LCD_CS1 : out STD_LOGIC; |
|
52 | LCD_CS1 : out STD_LOGIC; | |
50 | LCD_CS2 : out STD_LOGIC; |
|
53 | LCD_CS2 : out STD_LOGIC; | |
51 | SF_CE0 : out std_logic |
|
54 | SF_CE0 : out std_logic | |
52 | ); |
|
55 | ); | |
53 | end apb_lcd_ctrlr; |
|
56 | end apb_lcd_ctrlr; | |
54 |
|
57 | |||
55 | architecture Behavioral of apb_lcd_ctrlr is |
|
58 | architecture Behavioral of apb_lcd_ctrlr is | |
56 |
|
59 | |||
57 | signal FramBUFF : FRM_Buff_Space; |
|
60 | signal FramBUFF : FRM_Buff_Space; | |
58 | signal CMD : std_logic_vector(10 downto 0); |
|
61 | signal CMD : std_logic_vector(10 downto 0); | |
59 | signal Exec : std_logic; |
|
62 | signal Exec : std_logic; | |
60 | signal Ready : std_logic; |
|
63 | signal Ready : std_logic; | |
61 | signal LCD_CTRL : LCD_DRVR_CTRL_BUSS; |
|
64 | signal LCD_CTRL : LCD_DRVR_CTRL_BUSS; | |
62 |
|
65 | |||
63 |
|
66 | |||
64 |
|
67 | |||
65 | constant REVISION : integer := 1; |
|
68 | constant REVISION : integer := 1; | |
66 |
|
69 | |||
67 | constant pconfig : apb_config_type := ( |
|
70 | constant pconfig : apb_config_type := ( | |
68 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LCD_CTRLR, 0, REVISION, 0), |
|
71 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LCD_CTRLR, 0, REVISION, 0), | |
69 | 1 => apb_iobar(paddr, pmask)); |
|
72 | 1 => apb_iobar(paddr, pmask)); | |
70 |
|
73 | |||
71 |
|
74 | |||
72 | --type FRM_Buff_El is std_logic_vector(31 downto 0); |
|
75 | --type FRM_Buff_El is std_logic_vector(31 downto 0); | |
73 | type FRM_Buff_Reg is array(lcd_space_size-1 downto 0) of std_logic_vector(31 downto 0); |
|
76 | type FRM_Buff_Reg is array(lcd_space_size-1 downto 0) of std_logic_vector(31 downto 0); | |
74 |
|
77 | |||
75 |
|
78 | |||
76 | type LCD_ctrlr_Reg is record |
|
79 | type LCD_ctrlr_Reg is record | |
77 | CTRL_Reg : std_logic_vector(31 downto 0); |
|
80 | CTRL_Reg : std_logic_vector(31 downto 0); | |
78 | FRAME_BUFF : FRM_Buff_Reg; |
|
81 | FRAME_BUFF : FRM_Buff_Reg; | |
79 | end record; |
|
82 | end record; | |
80 |
|
83 | |||
81 | signal r : LCD_ctrlr_Reg; |
|
84 | signal r : LCD_ctrlr_Reg; | |
82 |
|
85 | |||
83 | signal Rdata : std_logic_vector(31 downto 0); |
|
86 | signal Rdata : std_logic_vector(31 downto 0); | |
84 |
|
87 | |||
85 | begin |
|
88 | begin | |
86 |
|
89 | |||
87 | LCD_data <= LCD_CTRL.LCD_DATA; |
|
90 | LCD_data <= LCD_CTRL.LCD_DATA; | |
88 | LCD_RS <= LCD_CTRL.LCD_RS; |
|
91 | LCD_RS <= LCD_CTRL.LCD_RS; | |
89 | LCD_RW <= LCD_CTRL.LCD_RW; |
|
92 | LCD_RW <= LCD_CTRL.LCD_RW; | |
90 | LCD_E <= LCD_CTRL.LCD_E; |
|
93 | LCD_E <= LCD_CTRL.LCD_E; | |
91 |
|
94 | |||
92 |
|
95 | |||
93 | LCD_RET <= '0'; |
|
96 | LCD_RET <= '0'; | |
94 | LCD_CS1 <= '0'; |
|
97 | LCD_CS1 <= '0'; | |
95 | LCD_CS2 <= '0'; |
|
98 | LCD_CS2 <= '0'; | |
96 |
|
99 | |||
97 | SF_CE0 <= '1'; |
|
100 | SF_CE0 <= '1'; | |
98 |
|
101 | |||
99 | CMD(7 downto 0) <= r.CTRL_Reg(7 downto 0); --CMD value |
|
102 | CMD(7 downto 0) <= r.CTRL_Reg(7 downto 0); --CMD value | |
100 | CMD(9 downto 8) <= r.CTRL_Reg(9 downto 8); --CMD tempo value |
|
103 | CMD(9 downto 8) <= r.CTRL_Reg(9 downto 8); --CMD tempo value | |
101 |
|
104 | |||
102 | r.CTRL_Reg(10) <= Ready; |
|
105 | r.CTRL_Reg(10) <= Ready; | |
103 |
|
106 | |||
104 | Driver0 : LCD_16x2_ENGINE |
|
107 | Driver0 : LCD_16x2_ENGINE | |
105 | generic map(50000) |
|
108 | generic map(50000) | |
106 | Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL); |
|
109 | Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL); | |
107 |
|
110 | |||
108 | FRM_BF : for i in 0 to lcd_space_size-1 generate |
|
111 | FRM_BF : for i in 0 to lcd_space_size-1 generate | |
109 | FramBUFF(i) <= r.FRAME_BUFF(i)(7 downto 0); |
|
112 | FramBUFF(i) <= r.FRAME_BUFF(i)(7 downto 0); | |
110 | end generate; |
|
113 | end generate; | |
111 |
|
114 | |||
112 |
|
115 | |||
113 | process(rst,clk) |
|
116 | process(rst,clk) | |
114 | begin |
|
117 | begin | |
115 | if rst = '0' then |
|
118 | if rst = '0' then | |
116 | r.CTRL_Reg(9 downto 0) <= (others => '0'); |
|
119 | r.CTRL_Reg(9 downto 0) <= (others => '0'); | |
117 | Exec <= '0'; |
|
120 | Exec <= '0'; | |
118 | elsif clk'event and clk = '1' then |
|
121 | elsif clk'event and clk = '1' then | |
119 |
|
122 | |||
120 | --APB Write OP |
|
123 | --APB Write OP | |
121 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
124 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
122 | case apbi.paddr(7 downto 2) is |
|
125 | case apbi.paddr(7 downto 2) is | |
123 | when "000000" => |
|
126 | when "000000" => | |
124 | r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0); |
|
127 | r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0); | |
125 | Exec <= '1'; |
|
128 | Exec <= '1'; | |
126 | when others => |
|
129 | when others => | |
127 | writeC: for i in 1 to lcd_space_size loop |
|
130 | writeC: for i in 1 to lcd_space_size loop | |
128 | if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then |
|
131 | if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then | |
129 | r.FRAME_BUFF(i-1) <= apbi.pwdata; |
|
132 | r.FRAME_BUFF(i-1) <= apbi.pwdata; | |
130 | end if; |
|
133 | end if; | |
131 | Exec <= '0'; |
|
134 | Exec <= '0'; | |
132 | end loop; |
|
135 | end loop; | |
133 | end case; |
|
136 | end case; | |
134 | else |
|
137 | else | |
135 | Exec <= '0'; |
|
138 | Exec <= '0'; | |
136 | end if; |
|
139 | end if; | |
137 |
|
140 | |||
138 | --APB READ OP |
|
141 | --APB READ OP | |
139 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
142 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
140 | case apbi.paddr(7 downto 2) is |
|
143 | case apbi.paddr(7 downto 2) is | |
141 | when "000000" => |
|
144 | when "000000" => | |
142 | Rdata <= r.CTRL_Reg; |
|
145 | Rdata <= r.CTRL_Reg; | |
143 | when others => |
|
146 | when others => | |
144 | readC: for i in 1 to lcd_space_size loop |
|
147 | readC: for i in 1 to lcd_space_size loop | |
145 | if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then |
|
148 | if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then | |
146 | Rdata(7 downto 0) <= r.FRAME_BUFF(i-1)(7 downto 0); |
|
149 | Rdata(7 downto 0) <= r.FRAME_BUFF(i-1)(7 downto 0); | |
147 | end if; |
|
150 | end if; | |
148 | end loop; |
|
151 | end loop; | |
149 | end case; |
|
152 | end case; | |
150 | end if; |
|
153 | end if; | |
151 |
|
154 | |||
152 | end if; |
|
155 | end if; | |
153 | apbo.pconfig <= pconfig; |
|
156 | apbo.pconfig <= pconfig; | |
154 | end process; |
|
157 | end process; | |
155 |
|
158 | |||
156 | apbo.prdata <= Rdata when apbi.penable = '1' ; |
|
159 | apbo.prdata <= Rdata when apbi.penable = '1' ; | |
157 |
|
160 | |||
158 | end Behavioral; |
|
161 | end Behavioral; | |
159 |
|
162 | |||
160 |
|
163 | |||
161 |
|
164 | |||
162 |
|
165 | |||
163 |
|
166 | |||
164 |
|
167 |
@@ -1,209 +1,212 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library ieee; |
|
22 | library ieee; | |
20 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
21 | use ieee.numeric_std.all; |
|
24 | use ieee.numeric_std.all; | |
22 | library grlib; |
|
25 | library grlib; | |
23 | use grlib.amba.all; |
|
26 | use grlib.amba.all; | |
24 | use grlib.stdlib.all; |
|
27 | use grlib.stdlib.all; | |
25 | use grlib.devices.all; |
|
28 | use grlib.devices.all; | |
26 | library lpp; |
|
29 | library lpp; | |
27 | use lpp.iir_filter.all; |
|
30 | use lpp.iir_filter.all; | |
28 | use lpp.general_purpose.all; |
|
31 | use lpp.general_purpose.all; | |
29 | use lpp.lpp_amba.all; |
|
32 | use lpp.lpp_amba.all; | |
30 | use lpp.apb_devices_list.all; |
|
33 | use lpp.apb_devices_list.all; | |
31 |
|
34 | |||
32 | entity APB_IIR_CEL is |
|
35 | entity APB_IIR_CEL is | |
33 | generic ( |
|
36 | generic ( | |
34 | pindex : integer := 0; |
|
37 | pindex : integer := 0; | |
35 | paddr : integer := 0; |
|
38 | paddr : integer := 0; | |
36 | pmask : integer := 16#fff#; |
|
39 | pmask : integer := 16#fff#; | |
37 | pirq : integer := 0; |
|
40 | pirq : integer := 0; | |
38 | abits : integer := 8; |
|
41 | abits : integer := 8; | |
39 | Sample_SZ : integer := 16; |
|
42 | Sample_SZ : integer := 16; | |
40 | ChanelsCount : integer := 1; |
|
43 | ChanelsCount : integer := 1; | |
41 | Coef_SZ : integer := 9; |
|
44 | Coef_SZ : integer := 9; | |
42 | CoefCntPerCel: integer := 3; |
|
45 | CoefCntPerCel: integer := 3; | |
43 | Cels_count : integer := 5; |
|
46 | Cels_count : integer := 5; | |
44 | virgPos : integer := 3; |
|
47 | virgPos : integer := 3; | |
45 | Mem_use : integer := use_RAM |
|
48 | Mem_use : integer := use_RAM | |
46 | ); |
|
49 | ); | |
47 | port ( |
|
50 | port ( | |
48 | rst : in std_logic; |
|
51 | rst : in std_logic; | |
49 | clk : in std_logic; |
|
52 | clk : in std_logic; | |
50 | apbi : in apb_slv_in_type; |
|
53 | apbi : in apb_slv_in_type; | |
51 | apbo : out apb_slv_out_type; |
|
54 | apbo : out apb_slv_out_type; | |
52 | sample_clk : in std_logic; |
|
55 | sample_clk : in std_logic; | |
53 | sample_clk_out : out std_logic; |
|
56 | sample_clk_out : out std_logic; | |
54 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
57 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
55 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0) |
|
58 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0) | |
56 | ); |
|
59 | ); | |
57 | end; |
|
60 | end; | |
58 |
|
61 | |||
59 |
|
62 | |||
60 | architecture AR_APB_IIR_CEL of APB_IIR_CEL is |
|
63 | architecture AR_APB_IIR_CEL of APB_IIR_CEL is | |
61 |
|
64 | |||
62 | constant REVISION : integer := 1; |
|
65 | constant REVISION : integer := 1; | |
63 |
|
66 | |||
64 | constant pconfig : apb_config_type := ( |
|
67 | constant pconfig : apb_config_type := ( | |
65 | 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0), |
|
68 | 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0), | |
66 | 1 => apb_iobar(paddr, pmask)); |
|
69 | 1 => apb_iobar(paddr, pmask)); | |
67 |
|
70 | |||
68 |
|
71 | |||
69 |
|
72 | |||
70 | type FILTERreg is record |
|
73 | type FILTERreg is record | |
71 | regin : in_IIR_CEL_reg; |
|
74 | regin : in_IIR_CEL_reg; | |
72 | regout : out_IIR_CEL_reg; |
|
75 | regout : out_IIR_CEL_reg; | |
73 | end record; |
|
76 | end record; | |
74 |
|
77 | |||
75 | signal Rdata : std_logic_vector(31 downto 0); |
|
78 | signal Rdata : std_logic_vector(31 downto 0); | |
76 | signal r : FILTERreg; |
|
79 | signal r : FILTERreg; | |
77 | signal filter_reset : std_logic:='0'; |
|
80 | signal filter_reset : std_logic:='0'; | |
78 | signal smp_cnt : integer :=0; |
|
81 | signal smp_cnt : integer :=0; | |
79 | signal sample_clk_out_R : std_logic; |
|
82 | signal sample_clk_out_R : std_logic; | |
80 |
|
83 | |||
81 |
|
84 | |||
82 | type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0); |
|
85 | type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0); | |
83 | type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT; |
|
86 | type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT; | |
84 |
|
87 | |||
85 | type CoefsRegT is record |
|
88 | type CoefsRegT is record | |
86 | numCoefs : CoefTblT; |
|
89 | numCoefs : CoefTblT; | |
87 | denCoefs : CoefTblT; |
|
90 | denCoefs : CoefTblT; | |
88 | end record; |
|
91 | end record; | |
89 |
|
92 | |||
90 | signal CoefsReg : CoefsRegT; |
|
93 | signal CoefsReg : CoefsRegT; | |
91 |
|
94 | |||
92 | begin |
|
95 | begin | |
93 |
|
96 | |||
94 | filter_reset <= rst and r.regin.config(0); |
|
97 | filter_reset <= rst and r.regin.config(0); | |
95 | sample_clk_out <= sample_clk_out_R; |
|
98 | sample_clk_out <= sample_clk_out_R; | |
96 |
|
99 | |||
97 | filter : IIR_CEL_FILTER |
|
100 | filter : IIR_CEL_FILTER | |
98 | generic map(Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) |
|
101 | generic map(Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) | |
99 | port map( |
|
102 | port map( | |
100 | reset => filter_reset, |
|
103 | reset => filter_reset, | |
101 | clk => clk, |
|
104 | clk => clk, | |
102 | sample_clk => sample_clk, |
|
105 | sample_clk => sample_clk, | |
103 | regs_in => r.regin, |
|
106 | regs_in => r.regin, | |
104 | regs_out => r.regout, |
|
107 | regs_out => r.regout, | |
105 | sample_in => sample_in, |
|
108 | sample_in => sample_in, | |
106 | sample_out => sample_out |
|
109 | sample_out => sample_out | |
107 | ); |
|
110 | ); | |
108 |
|
111 | |||
109 | process(rst,sample_clk) |
|
112 | process(rst,sample_clk) | |
110 | begin |
|
113 | begin | |
111 | if rst = '0' then |
|
114 | if rst = '0' then | |
112 | smp_cnt <= 0; |
|
115 | smp_cnt <= 0; | |
113 | sample_clk_out_R <= '0'; |
|
116 | sample_clk_out_R <= '0'; | |
114 | elsif sample_clk'event and sample_clk = '1' then |
|
117 | elsif sample_clk'event and sample_clk = '1' then | |
115 | if smp_cnt = 1 then |
|
118 | if smp_cnt = 1 then | |
116 | smp_cnt <= 0; |
|
119 | smp_cnt <= 0; | |
117 | sample_clk_out_R <= not sample_clk_out_R; |
|
120 | sample_clk_out_R <= not sample_clk_out_R; | |
118 | else |
|
121 | else | |
119 | smp_cnt <= smp_cnt +1; |
|
122 | smp_cnt <= smp_cnt +1; | |
120 | end if; |
|
123 | end if; | |
121 | end if; |
|
124 | end if; | |
122 | end process; |
|
125 | end process; | |
123 |
|
126 | |||
124 |
|
127 | |||
125 | process(rst,clk) |
|
128 | process(rst,clk) | |
126 | begin |
|
129 | begin | |
127 | if rst = '0' then |
|
130 | if rst = '0' then | |
128 | r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5)); |
|
131 | r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5)); | |
129 |
|
132 | |||
130 | elsif clk'event and clk = '1' then |
|
133 | elsif clk'event and clk = '1' then | |
131 |
|
134 | |||
132 |
|
135 | |||
133 | --APB Write OP |
|
136 | --APB Write OP | |
134 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
137 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
135 | case apbi.paddr(7 downto 2) is |
|
138 | case apbi.paddr(7 downto 2) is | |
136 | when "000000" => |
|
139 | when "000000" => | |
137 | r.regin.config(0) <= apbi.pwdata(0); |
|
140 | r.regin.config(0) <= apbi.pwdata(0); | |
138 | when "000001" => |
|
141 | when "000001" => | |
139 | r.regin.virgPos <= apbi.pwdata(4 downto 0); |
|
142 | r.regin.virgPos <= apbi.pwdata(4 downto 0); | |
140 | when others => |
|
143 | when others => | |
141 | for i in 0 to Cels_count-1 loop |
|
144 | for i in 0 to Cels_count-1 loop | |
142 | if conv_integer(apbi.paddr(7 downto 5)) = i+1 then |
|
145 | if conv_integer(apbi.paddr(7 downto 5)) = i+1 then | |
143 | case apbi.paddr(4 downto 2) is |
|
146 | case apbi.paddr(4 downto 2) is | |
144 | when "000" => |
|
147 | when "000" => | |
145 | CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); |
|
148 | CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); | |
146 | when "001" => |
|
149 | when "001" => | |
147 | CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); |
|
150 | CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); | |
148 | when "010" => |
|
151 | when "010" => | |
149 | CoefsReg.numCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0)); |
|
152 | CoefsReg.numCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0)); | |
150 | when "011" => |
|
153 | when "011" => | |
151 | CoefsReg.denCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); |
|
154 | CoefsReg.denCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); | |
152 | when "100" => |
|
155 | when "100" => | |
153 | CoefsReg.denCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); |
|
156 | CoefsReg.denCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); | |
154 | when "101" => |
|
157 | when "101" => | |
155 | CoefsReg.denCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0)); |
|
158 | CoefsReg.denCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0)); | |
156 | when others => |
|
159 | when others => | |
157 | end case; |
|
160 | end case; | |
158 | end if; |
|
161 | end if; | |
159 | end loop; |
|
162 | end loop; | |
160 | end case; |
|
163 | end case; | |
161 | end if; |
|
164 | end if; | |
162 |
|
165 | |||
163 | --APB READ OP |
|
166 | --APB READ OP | |
164 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
167 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
165 | case apbi.paddr(7 downto 2) is |
|
168 | case apbi.paddr(7 downto 2) is | |
166 | when "000000" => |
|
169 | when "000000" => | |
167 |
|
170 | |||
168 | when "000001" => |
|
171 | when "000001" => | |
169 | Rdata(4 downto 0) <= r.regin.virgPos; |
|
172 | Rdata(4 downto 0) <= r.regin.virgPos; | |
170 | when others => |
|
173 | when others => | |
171 | for i in 0 to Cels_count-1 loop |
|
174 | for i in 0 to Cels_count-1 loop | |
172 | if conv_integer(apbi.paddr(7 downto 5)) = i+1 then |
|
175 | if conv_integer(apbi.paddr(7 downto 5)) = i+1 then | |
173 | case apbi.paddr(4 downto 2) is |
|
176 | case apbi.paddr(4 downto 2) is | |
174 | when "000" => |
|
177 | when "000" => | |
175 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(0)); |
|
178 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(0)); | |
176 | when "001" => |
|
179 | when "001" => | |
177 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(1)); |
|
180 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(1)); | |
178 | when "010" => |
|
181 | when "010" => | |
179 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(2)); |
|
182 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(2)); | |
180 | when "011" => |
|
183 | when "011" => | |
181 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(0)); |
|
184 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(0)); | |
182 | when "100" => |
|
185 | when "100" => | |
183 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(1)); |
|
186 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(1)); | |
184 | when "101" => |
|
187 | when "101" => | |
185 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(2)); |
|
188 | Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(2)); | |
186 | when others => |
|
189 | when others => | |
187 | end case; |
|
190 | end case; | |
188 | end if; |
|
191 | end if; | |
189 | end loop; |
|
192 | end loop; | |
190 | end case; |
|
193 | end case; | |
191 | end if; |
|
194 | end if; | |
192 |
|
195 | |||
193 | end if; |
|
196 | end if; | |
194 | apbo.pconfig <= pconfig; |
|
197 | apbo.pconfig <= pconfig; | |
195 | end process; |
|
198 | end process; | |
196 |
|
199 | |||
197 | apbo.prdata <= Rdata when apbi.penable = '1' ; |
|
200 | apbo.prdata <= Rdata when apbi.penable = '1' ; | |
198 |
|
201 | |||
199 | -- pragma translate_off |
|
202 | -- pragma translate_off | |
200 | bootmsg : report_version |
|
203 | bootmsg : report_version | |
201 | generic map ("apbuart" & tost(pindex) & |
|
204 | generic map ("apbuart" & tost(pindex) & | |
202 | ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) & |
|
205 | ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) & | |
203 | ", irq " & tost(pirq)); |
|
206 | ", irq " & tost(pirq)); | |
204 | -- pragma translate_on |
|
207 | -- pragma translate_on | |
205 |
|
208 | |||
206 |
|
209 | |||
207 |
|
210 | |||
208 | end ar_APB_IIR_CEL; |
|
211 | end ar_APB_IIR_CEL; | |
209 |
|
212 |
@@ -1,104 +1,107 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.iir_filter.all; |
|
26 | use lpp.iir_filter.all; | |
24 | use lpp.FILTERcfg.all; |
|
27 | use lpp.FILTERcfg.all; | |
25 | use lpp.general_purpose.all; |
|
28 | use lpp.general_purpose.all; | |
26 | --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs) |
|
29 | --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs) | |
27 | --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s |
|
30 | --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s | |
28 | --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs |
|
31 | --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs | |
29 |
|
32 | |||
30 | entity FILTER is |
|
33 | entity FILTER is | |
31 | generic(Smpl_SZ : integer := 16; |
|
34 | generic(Smpl_SZ : integer := 16; | |
32 | ChanelsCNT : integer := 3 |
|
35 | ChanelsCNT : integer := 3 | |
33 | ); |
|
36 | ); | |
34 | port( |
|
37 | port( | |
35 |
|
38 | |||
36 | reset : in std_logic; |
|
39 | reset : in std_logic; | |
37 | clk : in std_logic; |
|
40 | clk : in std_logic; | |
38 | sample_clk : in std_logic; |
|
41 | sample_clk : in std_logic; | |
39 | Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0); |
|
42 | Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0); | |
40 | Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0) |
|
43 | Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0) | |
41 | ); |
|
44 | ); | |
42 | end entity; |
|
45 | end entity; | |
43 |
|
46 | |||
44 |
|
47 | |||
45 |
|
48 | |||
46 |
|
49 | |||
47 |
|
50 | |||
48 | architecture ar_FILTER of FILTER is |
|
51 | architecture ar_FILTER of FILTER is | |
49 |
|
52 | |||
50 |
|
53 | |||
51 |
|
54 | |||
52 |
|
55 | |||
53 | signal ALU_ctrl : std_logic_vector(3 downto 0); |
|
56 | signal ALU_ctrl : std_logic_vector(3 downto 0); | |
54 | signal Sample : std_logic_vector(Smpl_SZ-1 downto 0); |
|
57 | signal Sample : std_logic_vector(Smpl_SZ-1 downto 0); | |
55 | signal Coef : std_logic_vector(Coef_SZ-1 downto 0); |
|
58 | signal Coef : std_logic_vector(Coef_SZ-1 downto 0); | |
56 | signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0); |
|
59 | signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0); | |
57 |
|
60 | |||
58 | begin |
|
61 | begin | |
59 |
|
62 | |||
60 | --============================================================== |
|
63 | --============================================================== | |
61 | --=========================A L U================================ |
|
64 | --=========================A L U================================ | |
62 | --============================================================== |
|
65 | --============================================================== | |
63 | ALU1 : entity ALU |
|
66 | ALU1 : entity ALU | |
64 | generic map( |
|
67 | generic map( | |
65 | Arith_en => 1, |
|
68 | Arith_en => 1, | |
66 | Logic_en => 0, |
|
69 | Logic_en => 0, | |
67 | Input_SZ_1 => Smpl_SZ, |
|
70 | Input_SZ_1 => Smpl_SZ, | |
68 | Input_SZ_2 => Coef_SZ |
|
71 | Input_SZ_2 => Coef_SZ | |
69 |
|
72 | |||
70 | ) |
|
73 | ) | |
71 | port map( |
|
74 | port map( | |
72 | clk => clk, |
|
75 | clk => clk, | |
73 | reset => reset, |
|
76 | reset => reset, | |
74 | ctrl => ALU_ctrl, |
|
77 | ctrl => ALU_ctrl, | |
75 | OP1 => Sample, |
|
78 | OP1 => Sample, | |
76 | OP2 => Coef, |
|
79 | OP2 => Coef, | |
77 | RES => ALU_OUT |
|
80 | RES => ALU_OUT | |
78 | ); |
|
81 | ); | |
79 | --============================================================== |
|
82 | --============================================================== | |
80 |
|
83 | |||
81 | --============================================================== |
|
84 | --============================================================== | |
82 | --===============F I L T E R C O N T R O L E R================ |
|
85 | --===============F I L T E R C O N T R O L E R================ | |
83 | --============================================================== |
|
86 | --============================================================== | |
84 | filterctrlr1 : FilterCTRLR |
|
87 | filterctrlr1 : FilterCTRLR | |
85 | port map( |
|
88 | port map( | |
86 | reset => reset, |
|
89 | reset => reset, | |
87 | clk => clk, |
|
90 | clk => clk, | |
88 | sample_clk => sample_clk, |
|
91 | sample_clk => sample_clk, | |
89 | ALU_Ctrl => ALU_ctrl, |
|
92 | ALU_Ctrl => ALU_ctrl, | |
90 | sample_in => sample_Tbl, |
|
93 | sample_in => sample_Tbl, | |
91 | coef => Coef, |
|
94 | coef => Coef, | |
92 | sample => Sample |
|
95 | sample => Sample | |
93 | ); |
|
96 | ); | |
94 | --============================================================== |
|
97 | --============================================================== | |
95 |
|
98 | |||
96 | chanelCut : for i in 0 to ChanelsCNT-1 generate |
|
99 | chanelCut : for i in 0 to ChanelsCNT-1 generate | |
97 | sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ); |
|
100 | sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ); | |
98 | end generate; |
|
101 | end generate; | |
99 |
|
102 | |||
100 |
|
103 | |||
101 |
|
104 | |||
102 |
|
105 | |||
103 | end ar_FILTER; |
|
106 | end ar_FILTER; | |
104 |
|
107 |
@@ -1,225 +1,228 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.iir_filter.all; |
|
26 | use lpp.iir_filter.all; | |
24 | use lpp.FILTERcfg.all; |
|
27 | use lpp.FILTERcfg.all; | |
25 | use lpp.general_purpose.all; |
|
28 | use lpp.general_purpose.all; | |
26 |
|
29 | |||
27 | --TODO am�liorer la flexibilit� de la config de la RAM. |
|
30 | --TODO am�liorer la flexibilit� de la config de la RAM. | |
28 |
|
31 | |||
29 | entity FILTER_RAM_CTRLR is |
|
32 | entity FILTER_RAM_CTRLR is | |
30 | port( |
|
33 | port( | |
31 | reset : in std_logic; |
|
34 | reset : in std_logic; | |
32 | clk : in std_logic; |
|
35 | clk : in std_logic; | |
33 | run : in std_logic; |
|
36 | run : in std_logic; | |
34 | GO_0 : in std_logic; |
|
37 | GO_0 : in std_logic; | |
35 | B_A : in std_logic; |
|
38 | B_A : in std_logic; | |
36 | writeForce : in std_logic; |
|
39 | writeForce : in std_logic; | |
37 | next_blk : in std_logic; |
|
40 | next_blk : in std_logic; | |
38 | sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); |
|
41 | sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); | |
39 | sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
42 | sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) | |
40 | ); |
|
43 | ); | |
41 | end FILTER_RAM_CTRLR; |
|
44 | end FILTER_RAM_CTRLR; | |
42 |
|
45 | |||
43 |
|
46 | |||
44 | architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is |
|
47 | architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is | |
45 |
|
48 | |||
46 | signal WD : std_logic_vector(35 downto 0); |
|
49 | signal WD : std_logic_vector(35 downto 0); | |
47 | signal WD_D : std_logic_vector(35 downto 0); |
|
50 | signal WD_D : std_logic_vector(35 downto 0); | |
48 | signal RD : std_logic_vector(35 downto 0); |
|
51 | signal RD : std_logic_vector(35 downto 0); | |
49 | signal WEN, REN : std_logic; |
|
52 | signal WEN, REN : std_logic; | |
50 | signal WADDR_back : std_logic_vector(7 downto 0); |
|
53 | signal WADDR_back : std_logic_vector(7 downto 0); | |
51 | signal WADDR_back_D: std_logic_vector(7 downto 0); |
|
54 | signal WADDR_back_D: std_logic_vector(7 downto 0); | |
52 | signal RADDR : std_logic_vector(7 downto 0); |
|
55 | signal RADDR : std_logic_vector(7 downto 0); | |
53 | signal WADDR : std_logic_vector(7 downto 0); |
|
56 | signal WADDR : std_logic_vector(7 downto 0); | |
54 | signal WADDR_D : std_logic_vector(7 downto 0); |
|
57 | signal WADDR_D : std_logic_vector(7 downto 0); | |
55 | signal run_D : std_logic; |
|
58 | signal run_D : std_logic; | |
56 | signal run_D_inv : std_logic; |
|
59 | signal run_D_inv : std_logic; | |
57 | signal run_inv : std_logic; |
|
60 | signal run_inv : std_logic; | |
58 | signal next_blk_D : std_logic; |
|
61 | signal next_blk_D : std_logic; | |
59 | signal MUX2_inst1_sel : std_logic; |
|
62 | signal MUX2_inst1_sel : std_logic; | |
60 |
|
63 | |||
61 |
|
64 | |||
62 | begin |
|
65 | begin | |
63 |
|
66 | |||
64 | sample_out <= RD(Smpl_SZ-1 downto 0); |
|
67 | sample_out <= RD(Smpl_SZ-1 downto 0); | |
65 |
|
68 | |||
66 | MUX2_inst1_sel <= run_D and not next_blk; |
|
69 | MUX2_inst1_sel <= run_D and not next_blk; | |
67 | run_D_inv <= not run_D; |
|
70 | run_D_inv <= not run_D; | |
68 | run_inv <= not run; |
|
71 | run_inv <= not run; | |
69 | WEN <= run_D_inv and not writeForce; |
|
72 | WEN <= run_D_inv and not writeForce; | |
70 | REN <= run_inv ;--and not next_blk; |
|
73 | REN <= run_inv ;--and not next_blk; | |
71 |
|
74 | |||
72 |
|
75 | |||
73 | --============================================================== |
|
76 | --============================================================== | |
74 | --=========================R A M================================ |
|
77 | --=========================R A M================================ | |
75 | --============================================================== |
|
78 | --============================================================== | |
76 | memRAM : if Mem_use = use_RAM generate |
|
79 | memRAM : if Mem_use = use_RAM generate | |
77 | RAMblk :RAM |
|
80 | RAMblk :RAM | |
78 | port map( |
|
81 | port map( | |
79 | WD => WD_D, |
|
82 | WD => WD_D, | |
80 | RD => RD, |
|
83 | RD => RD, | |
81 | WEN => WEN, |
|
84 | WEN => WEN, | |
82 | REN => REN, |
|
85 | REN => REN, | |
83 | WADDR => WADDR, |
|
86 | WADDR => WADDR, | |
84 | RADDR => RADDR, |
|
87 | RADDR => RADDR, | |
85 | RWCLK => clk, |
|
88 | RWCLK => clk, | |
86 | RESET => reset |
|
89 | RESET => reset | |
87 | ) ; |
|
90 | ) ; | |
88 | end generate; |
|
91 | end generate; | |
89 |
|
92 | |||
90 | memCEL : if Mem_use = use_CEL generate |
|
93 | memCEL : if Mem_use = use_CEL generate | |
91 | RAMblk :RAM_CEL |
|
94 | RAMblk :RAM_CEL | |
92 | port map( |
|
95 | port map( | |
93 | WD => WD_D, |
|
96 | WD => WD_D, | |
94 | RD => RD, |
|
97 | RD => RD, | |
95 | WEN => WEN, |
|
98 | WEN => WEN, | |
96 | REN => REN, |
|
99 | REN => REN, | |
97 | WADDR => WADDR, |
|
100 | WADDR => WADDR, | |
98 | RADDR => RADDR, |
|
101 | RADDR => RADDR, | |
99 | RWCLK => clk, |
|
102 | RWCLK => clk, | |
100 | RESET => reset |
|
103 | RESET => reset | |
101 | ) ; |
|
104 | ) ; | |
102 | end generate; |
|
105 | end generate; | |
103 | --============================================================== |
|
106 | --============================================================== | |
104 | --============================================================== |
|
107 | --============================================================== | |
105 |
|
108 | |||
106 |
|
109 | |||
107 | ADDRcntr_inst : ADDRcntr |
|
110 | ADDRcntr_inst : ADDRcntr | |
108 | port map( |
|
111 | port map( | |
109 | clk => clk, |
|
112 | clk => clk, | |
110 | reset => reset, |
|
113 | reset => reset, | |
111 | count => run, |
|
114 | count => run, | |
112 | clr => GO_0, |
|
115 | clr => GO_0, | |
113 | Q => RADDR |
|
116 | Q => RADDR | |
114 | ); |
|
117 | ); | |
115 |
|
118 | |||
116 |
|
119 | |||
117 |
|
120 | |||
118 | MUX2_inst1 :MUX2 |
|
121 | MUX2_inst1 :MUX2 | |
119 | generic map(Input_SZ => Smpl_SZ) |
|
122 | generic map(Input_SZ => Smpl_SZ) | |
120 | port map( |
|
123 | port map( | |
121 | sel => MUX2_inst1_sel, |
|
124 | sel => MUX2_inst1_sel, | |
122 | IN1 => sample_in, |
|
125 | IN1 => sample_in, | |
123 | IN2 => RD(Smpl_SZ-1 downto 0), |
|
126 | IN2 => RD(Smpl_SZ-1 downto 0), | |
124 | RES => WD(Smpl_SZ-1 downto 0) |
|
127 | RES => WD(Smpl_SZ-1 downto 0) | |
125 | ); |
|
128 | ); | |
126 |
|
129 | |||
127 |
|
130 | |||
128 | MUX2_inst2 :MUX2 |
|
131 | MUX2_inst2 :MUX2 | |
129 | generic map(Input_SZ => 8) |
|
132 | generic map(Input_SZ => 8) | |
130 | port map( |
|
133 | port map( | |
131 | sel => next_blk_D, |
|
134 | sel => next_blk_D, | |
132 | IN1 => WADDR_D, |
|
135 | IN1 => WADDR_D, | |
133 | IN2 => WADDR_back_D, |
|
136 | IN2 => WADDR_back_D, | |
134 | RES => WADDR |
|
137 | RES => WADDR | |
135 | ); |
|
138 | ); | |
136 |
|
139 | |||
137 |
|
140 | |||
138 | next_blkRreg :REG |
|
141 | next_blkRreg :REG | |
139 | generic map(size => 1) |
|
142 | generic map(size => 1) | |
140 | port map( |
|
143 | port map( | |
141 | reset => reset, |
|
144 | reset => reset, | |
142 | clk => clk, |
|
145 | clk => clk, | |
143 | D(0) => next_blk, |
|
146 | D(0) => next_blk, | |
144 | Q(0) => next_blk_D |
|
147 | Q(0) => next_blk_D | |
145 | ); |
|
148 | ); | |
146 |
|
149 | |||
147 | WADDR_backreg :REG |
|
150 | WADDR_backreg :REG | |
148 | generic map(size => 8) |
|
151 | generic map(size => 8) | |
149 | port map( |
|
152 | port map( | |
150 | reset => reset, |
|
153 | reset => reset, | |
151 | clk => B_A, |
|
154 | clk => B_A, | |
152 | D => RADDR, |
|
155 | D => RADDR, | |
153 | Q => WADDR_back |
|
156 | Q => WADDR_back | |
154 | ); |
|
157 | ); | |
155 |
|
158 | |||
156 | WADDR_backreg2 :REG |
|
159 | WADDR_backreg2 :REG | |
157 | generic map(size => 8) |
|
160 | generic map(size => 8) | |
158 | port map( |
|
161 | port map( | |
159 | reset => reset, |
|
162 | reset => reset, | |
160 | clk => B_A, |
|
163 | clk => B_A, | |
161 | D => WADDR_back, |
|
164 | D => WADDR_back, | |
162 | Q => WADDR_back_D |
|
165 | Q => WADDR_back_D | |
163 | ); |
|
166 | ); | |
164 |
|
167 | |||
165 | WDRreg :REG |
|
168 | WDRreg :REG | |
166 | generic map(size => Smpl_SZ) |
|
169 | generic map(size => Smpl_SZ) | |
167 | port map( |
|
170 | port map( | |
168 | reset => reset, |
|
171 | reset => reset, | |
169 | clk => clk, |
|
172 | clk => clk, | |
170 | D => WD(Smpl_SZ-1 downto 0), |
|
173 | D => WD(Smpl_SZ-1 downto 0), | |
171 | Q => WD_D(Smpl_SZ-1 downto 0) |
|
174 | Q => WD_D(Smpl_SZ-1 downto 0) | |
172 | ); |
|
175 | ); | |
173 |
|
176 | |||
174 | RunRreg :REG |
|
177 | RunRreg :REG | |
175 | generic map(size => 1) |
|
178 | generic map(size => 1) | |
176 | port map( |
|
179 | port map( | |
177 | reset => reset, |
|
180 | reset => reset, | |
178 | clk => clk, |
|
181 | clk => clk, | |
179 | D(0) => run, |
|
182 | D(0) => run, | |
180 | Q(0) => run_D |
|
183 | Q(0) => run_D | |
181 | ); |
|
184 | ); | |
182 |
|
185 | |||
183 |
|
186 | |||
184 |
|
187 | |||
185 | ADDRreg :REG |
|
188 | ADDRreg :REG | |
186 | generic map(size => 8) |
|
189 | generic map(size => 8) | |
187 | port map( |
|
190 | port map( | |
188 | reset => reset, |
|
191 | reset => reset, | |
189 | clk => clk, |
|
192 | clk => clk, | |
190 | D => RADDR, |
|
193 | D => RADDR, | |
191 | Q => WADDR_D |
|
194 | Q => WADDR_D | |
192 | ); |
|
195 | ); | |
193 |
|
196 | |||
194 |
|
197 | |||
195 |
|
198 | |||
196 | end ar_FILTER_RAM_CTRLR; |
|
199 | end ar_FILTER_RAM_CTRLR; | |
197 |
|
200 | |||
198 |
|
201 | |||
199 |
|
202 | |||
200 |
|
203 | |||
201 |
|
204 | |||
202 |
|
205 | |||
203 |
|
206 | |||
204 |
|
207 | |||
205 |
|
208 | |||
206 |
|
209 | |||
207 |
|
210 | |||
208 |
|
211 | |||
209 |
|
212 | |||
210 |
|
213 | |||
211 |
|
214 | |||
212 |
|
215 | |||
213 |
|
216 | |||
214 |
|
217 | |||
215 |
|
218 | |||
216 |
|
219 | |||
217 |
|
220 | |||
218 |
|
221 | |||
219 |
|
222 | |||
220 |
|
223 | |||
221 |
|
224 | |||
222 |
|
225 | |||
223 |
|
226 | |||
224 |
|
227 | |||
225 |
|
228 |
@@ -1,193 +1,196 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 |
|
25 | |||
23 |
|
26 | |||
24 | package FILTERcfg is |
|
27 | package FILTERcfg is | |
25 |
|
28 | |||
26 |
|
29 | |||
27 |
|
30 | |||
28 |
|
31 | |||
29 | --===========================================================| |
|
32 | --===========================================================| | |
30 | --========F I L T E R C O N F I G V A L U E S=============| |
|
33 | --========F I L T E R C O N F I G V A L U E S=============| | |
31 | --===========================================================| |
|
34 | --===========================================================| | |
32 | --____________________________ |
|
35 | --____________________________ | |
33 | --Bus Width and chanels number| |
|
36 | --Bus Width and chanels number| | |
34 | --____________________________| |
|
37 | --____________________________| | |
35 | constant ChanelsCNT : integer := 6; |
|
38 | constant ChanelsCNT : integer := 6; | |
36 | constant Smpl_SZ : integer := 16; |
|
39 | constant Smpl_SZ : integer := 16; | |
37 | constant Coef_SZ : integer := 9; |
|
40 | constant Coef_SZ : integer := 9; | |
38 | constant Scalefac_SZ: integer := 3; |
|
41 | constant Scalefac_SZ: integer := 3; | |
39 | constant Cels_count : integer := 5; |
|
42 | constant Cels_count : integer := 5; | |
40 |
|
43 | |||
41 | constant Mem_use : integer := 1; |
|
44 | constant Mem_use : integer := 1; | |
42 |
|
45 | |||
43 |
|
46 | |||
44 |
|
47 | |||
45 | --============================================================ |
|
48 | --============================================================ | |
46 | -- create each initial values for each coefs ============ |
|
49 | -- create each initial values for each coefs ============ | |
47 | --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!! |
|
50 | --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!! | |
48 | --============================================================ |
|
51 | --============================================================ | |
49 | --constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ)); |
|
52 | --constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ)); | |
50 | --constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); |
|
53 | --constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); | |
51 | --constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ)); |
|
54 | --constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ)); | |
52 | --constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ)); |
|
55 | --constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ)); | |
53 | --constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ)); |
|
56 | --constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ)); | |
54 | --constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ)); |
|
57 | --constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ)); | |
55 | --constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ)); |
|
58 | --constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ)); | |
56 | -- |
|
59 | -- | |
57 | --constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); |
|
60 | --constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); | |
58 | --constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); |
|
61 | --constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); | |
59 | --constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ)); |
|
62 | --constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ)); | |
60 | --constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); |
|
63 | --constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); | |
61 | --constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ)); |
|
64 | --constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ)); | |
62 | -- |
|
65 | -- | |
63 | -- |
|
66 | -- | |
64 | --constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); |
|
67 | --constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); | |
65 | --constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ)); |
|
68 | --constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ)); | |
66 | --constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); |
|
69 | --constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); | |
67 | -- |
|
70 | -- | |
68 | --constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); |
|
71 | --constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); | |
69 | --constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ)); |
|
72 | --constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ)); | |
70 | --constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); |
|
73 | --constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); | |
71 | -- |
|
74 | -- | |
72 | --constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ)); |
|
75 | --constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ)); | |
73 | --constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ)); |
|
76 | --constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ)); | |
74 | --constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ)); |
|
77 | --constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ)); | |
75 | -- |
|
78 | -- | |
76 | --constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); |
|
79 | --constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); | |
77 | --constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ)); |
|
80 | --constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ)); | |
78 | --constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); |
|
81 | --constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); | |
79 | -- |
|
82 | -- | |
80 | --constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); |
|
83 | --constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); | |
81 | --constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ)); |
|
84 | --constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ)); | |
82 | --constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); |
|
85 | --constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); | |
83 | -- |
|
86 | -- | |
84 | --constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); |
|
87 | --constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); | |
85 | --constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ)); |
|
88 | --constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ)); | |
86 | --constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ)); |
|
89 | --constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ)); | |
87 | -- |
|
90 | -- | |
88 | --constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ)); |
|
91 | --constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ)); | |
89 | --constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ)); |
|
92 | --constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ)); | |
90 | --constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ)); |
|
93 | --constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ)); | |
91 | -- |
|
94 | -- | |
92 | -- |
|
95 | -- | |
93 | --constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); |
|
96 | --constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); | |
94 | --constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ)); |
|
97 | --constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ)); | |
95 | --constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ)); |
|
98 | --constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ)); | |
96 | -- |
|
99 | -- | |
97 | --constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); |
|
100 | --constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); | |
98 | --constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ)); |
|
101 | --constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ)); | |
99 | --constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); |
|
102 | --constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); | |
100 | -- |
|
103 | -- | |
101 | --constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); |
|
104 | --constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); | |
102 | --constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ)); |
|
105 | --constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ)); | |
103 | --constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ)); |
|
106 | --constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ)); | |
104 | -- |
|
107 | -- | |
105 | --constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); |
|
108 | --constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); | |
106 | --constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ)); |
|
109 | --constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ)); | |
107 | --constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ)); |
|
110 | --constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ)); | |
108 | -- |
|
111 | -- | |
109 | --constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); |
|
112 | --constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); | |
110 | --constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ)); |
|
113 | --constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ)); | |
111 | --constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ)); |
|
114 | --constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ)); | |
112 | -- |
|
115 | -- | |
113 | --constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); |
|
116 | --constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); | |
114 | --constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); |
|
117 | --constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); | |
115 | --constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); |
|
118 | --constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); | |
116 | --constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); |
|
119 | --constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); | |
117 | --constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); |
|
120 | --constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); | |
118 | --constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); |
|
121 | --constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); | |
119 | -- |
|
122 | -- | |
120 | -- |
|
123 | -- | |
121 | --constant celb0 : coef_celT := (b0_0,b0_1,b0_2); |
|
124 | --constant celb0 : coef_celT := (b0_0,b0_1,b0_2); | |
122 | --constant celb1 : coef_celT := (b1_0,b1_1,b1_2); |
|
125 | --constant celb1 : coef_celT := (b1_0,b1_1,b1_2); | |
123 | --constant celb2 : coef_celT := (b2_0,b2_1,b2_2); |
|
126 | --constant celb2 : coef_celT := (b2_0,b2_1,b2_2); | |
124 | --constant celb3 : coef_celT := (b3_0,b3_1,b3_2); |
|
127 | --constant celb3 : coef_celT := (b3_0,b3_1,b3_2); | |
125 | --constant celb4 : coef_celT := (b4_0,b4_1,b4_2); |
|
128 | --constant celb4 : coef_celT := (b4_0,b4_1,b4_2); | |
126 | --constant celb5 : coef_celT := (b5_0,b5_1,b5_2); |
|
129 | --constant celb5 : coef_celT := (b5_0,b5_1,b5_2); | |
127 | --constant celb6 : coef_celT := (b6_0,b6_1,b6_2); |
|
130 | --constant celb6 : coef_celT := (b6_0,b6_1,b6_2); | |
128 | -- |
|
131 | -- | |
129 | --constant cela0 : coef_celT := (a0_0,a0_1,a0_2); |
|
132 | --constant cela0 : coef_celT := (a0_0,a0_1,a0_2); | |
130 | --constant cela1 : coef_celT := (a1_0,a1_1,a1_2); |
|
133 | --constant cela1 : coef_celT := (a1_0,a1_1,a1_2); | |
131 | --constant cela2 : coef_celT := (a2_0,a2_1,a2_2); |
|
134 | --constant cela2 : coef_celT := (a2_0,a2_1,a2_2); | |
132 | --constant cela3 : coef_celT := (a3_0,a3_1,a3_2); |
|
135 | --constant cela3 : coef_celT := (a3_0,a3_1,a3_2); | |
133 | --constant cela4 : coef_celT := (a4_0,a4_1,a4_2); |
|
136 | --constant cela4 : coef_celT := (a4_0,a4_1,a4_2); | |
134 | --constant cela5 : coef_celT := (a5_0,a5_1,a5_2); |
|
137 | --constant cela5 : coef_celT := (a5_0,a5_1,a5_2); | |
135 | --constant cela6 : coef_celT := (a6_0,a6_1,a6_2); |
|
138 | --constant cela6 : coef_celT := (a6_0,a6_1,a6_2); | |
136 | -- |
|
139 | -- | |
137 | -- |
|
140 | -- | |
138 | -- |
|
141 | -- | |
139 | --constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4); |
|
142 | --constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4); | |
140 | --constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4); |
|
143 | --constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4); | |
141 | --constant virgPos : integer := 7; |
|
144 | --constant virgPos : integer := 7; | |
142 | -- |
|
145 | -- | |
143 | -- |
|
146 | -- | |
144 | -- |
|
147 | -- | |
145 | -- |
|
148 | -- | |
146 | -- |
|
149 | -- | |
147 | -- |
|
150 | -- | |
148 | -- |
|
151 | -- | |
149 | --signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6); |
|
152 | --signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6); | |
150 | --signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4); |
|
153 | --signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4); | |
151 | -- |
|
154 | -- | |
152 | -- |
|
155 | -- | |
153 | --signal sample_Tbl : samplT; |
|
156 | --signal sample_Tbl : samplT; | |
154 |
|
157 | |||
155 |
|
158 | |||
156 | end; |
|
159 | end; | |
157 |
|
160 | |||
158 |
|
161 | |||
159 |
|
162 | |||
160 |
|
163 | |||
161 |
|
164 | |||
162 |
|
165 | |||
163 |
|
166 | |||
164 |
|
167 | |||
165 |
|
168 | |||
166 |
|
169 | |||
167 |
|
170 | |||
168 |
|
171 | |||
169 |
|
172 | |||
170 |
|
173 | |||
171 |
|
174 | |||
172 |
|
175 | |||
173 |
|
176 | |||
174 |
|
177 | |||
175 |
|
178 | |||
176 |
|
179 | |||
177 |
|
180 | |||
178 |
|
181 | |||
179 |
|
182 | |||
180 |
|
183 | |||
181 |
|
184 | |||
182 |
|
185 | |||
183 |
|
186 | |||
184 |
|
187 | |||
185 |
|
188 | |||
186 |
|
189 | |||
187 |
|
190 | |||
188 |
|
191 | |||
189 |
|
192 | |||
190 |
|
193 | |||
191 |
|
194 | |||
192 |
|
195 | |||
193 |
|
196 |
@@ -1,262 +1,265 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.iir_filter.all; |
|
26 | use lpp.iir_filter.all; | |
24 | use lpp.FILTERcfg.all; |
|
27 | use lpp.FILTERcfg.all; | |
25 | use lpp.general_purpose.all; |
|
28 | use lpp.general_purpose.all; | |
26 |
|
29 | |||
27 | --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre |
|
30 | --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre | |
28 |
|
31 | |||
29 | entity FilterCTRLR is |
|
32 | entity FilterCTRLR is | |
30 | port( |
|
33 | port( | |
31 | reset : in std_logic; |
|
34 | reset : in std_logic; | |
32 | clk : in std_logic; |
|
35 | clk : in std_logic; | |
33 | sample_clk : in std_logic; |
|
36 | sample_clk : in std_logic; | |
34 | ALU_Ctrl : out std_logic_vector(3 downto 0); |
|
37 | ALU_Ctrl : out std_logic_vector(3 downto 0); | |
35 | sample_in : in samplT; |
|
38 | sample_in : in samplT; | |
36 | coef : out std_logic_vector(Coef_SZ-1 downto 0); |
|
39 | coef : out std_logic_vector(Coef_SZ-1 downto 0); | |
37 | sample : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
40 | sample : out std_logic_vector(Smpl_SZ-1 downto 0) | |
38 | ); |
|
41 | ); | |
39 | end FilterCTRLR; |
|
42 | end FilterCTRLR; | |
40 |
|
43 | |||
41 |
|
44 | |||
42 | architecture ar_FilterCTRLR of FilterCTRLR is |
|
45 | architecture ar_FilterCTRLR of FilterCTRLR is | |
43 |
|
46 | |||
44 | constant NUMCoefsCnt : integer:= NumeratorCoefs'high; |
|
47 | constant NUMCoefsCnt : integer:= NumeratorCoefs'high; | |
45 | constant DENCoefsCnt : integer:= DenominatorCoefs'high; |
|
48 | constant DENCoefsCnt : integer:= DenominatorCoefs'high; | |
46 |
|
49 | |||
47 | signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0; |
|
50 | signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0; | |
48 | signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0; |
|
51 | signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0; | |
49 |
|
52 | |||
50 | signal chanelCnt : integer range 0 to 15:=0; |
|
53 | signal chanelCnt : integer range 0 to 15:=0; | |
51 |
|
54 | |||
52 | signal WD : std_logic_vector(35 downto 0); |
|
55 | signal WD : std_logic_vector(35 downto 0); | |
53 | signal WD_D : std_logic_vector(35 downto 0); |
|
56 | signal WD_D : std_logic_vector(35 downto 0); | |
54 | signal RD : std_logic_vector(35 downto 0); |
|
57 | signal RD : std_logic_vector(35 downto 0); | |
55 | signal WEN, REN,WEN_D : std_logic; |
|
58 | signal WEN, REN,WEN_D : std_logic; | |
56 | signal WADDR_back : std_logic_vector(7 downto 0); |
|
59 | signal WADDR_back : std_logic_vector(7 downto 0); | |
57 | signal ADDR : std_logic_vector(7 downto 0); |
|
60 | signal ADDR : std_logic_vector(7 downto 0); | |
58 | signal ADDR_D : std_logic_vector(7 downto 0); |
|
61 | signal ADDR_D : std_logic_vector(7 downto 0); | |
59 | signal clk_inv : std_logic; |
|
62 | signal clk_inv : std_logic; | |
60 |
|
63 | |||
61 | type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0); |
|
64 | type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0); | |
62 | signal in_Rotate_Buff : Rotate_BuffT; |
|
65 | signal in_Rotate_Buff : Rotate_BuffT; | |
63 | signal out_Rotate_Buff : Rotate_BuffT; |
|
66 | signal out_Rotate_Buff : Rotate_BuffT; | |
64 |
|
67 | |||
65 | signal sample_clk_old : std_logic; |
|
68 | signal sample_clk_old : std_logic; | |
66 |
|
69 | |||
67 | type stateT is (waiting,computeNUM,computeDEN,NextChanel); |
|
70 | type stateT is (waiting,computeNUM,computeDEN,NextChanel); | |
68 | signal state : stateT; |
|
71 | signal state : stateT; | |
69 |
|
72 | |||
70 | begin |
|
73 | begin | |
71 | clk_inv <= not clk; |
|
74 | clk_inv <= not clk; | |
72 |
|
75 | |||
73 | process(clk,reset) |
|
76 | process(clk,reset) | |
74 | begin |
|
77 | begin | |
75 | if reset = '0' then |
|
78 | if reset = '0' then | |
76 | state <= waiting; |
|
79 | state <= waiting; | |
77 | WEN <= '1'; |
|
80 | WEN <= '1'; | |
78 | REN <= '1'; |
|
81 | REN <= '1'; | |
79 | ADDR <= (others => '0'); |
|
82 | ADDR <= (others => '0'); | |
80 | WD <= (others => '0'); |
|
83 | WD <= (others => '0'); | |
81 | NcoefCnt <= 0; |
|
84 | NcoefCnt <= 0; | |
82 | DcoefCnt <= 0; |
|
85 | DcoefCnt <= 0; | |
83 | chanelCnt <= 0; |
|
86 | chanelCnt <= 0; | |
84 | ALU_Ctrl <= clr_mac; |
|
87 | ALU_Ctrl <= clr_mac; | |
85 | sample_clk_old <= '0'; |
|
88 | sample_clk_old <= '0'; | |
86 | coef <= (others => '0'); |
|
89 | coef <= (others => '0'); | |
87 | sample <= (others => '0'); |
|
90 | sample <= (others => '0'); | |
88 | rst:for i in 0 to ChanelsCNT-1 loop |
|
91 | rst:for i in 0 to ChanelsCNT-1 loop | |
89 | in_Rotate_Buff(i) <= (others => '0'); |
|
92 | in_Rotate_Buff(i) <= (others => '0'); | |
90 | end loop; |
|
93 | end loop; | |
91 | elsif clk'event and clk = '1' then |
|
94 | elsif clk'event and clk = '1' then | |
92 |
|
95 | |||
93 | sample_clk_old <= sample_clk; |
|
96 | sample_clk_old <= sample_clk; | |
94 |
|
97 | |||
95 | --================================================================= |
|
98 | --================================================================= | |
96 | --===============DATA processing=================================== |
|
99 | --===============DATA processing=================================== | |
97 | --================================================================= |
|
100 | --================================================================= | |
98 | case state is |
|
101 | case state is | |
99 | when waiting=> |
|
102 | when waiting=> | |
100 |
|
103 | |||
101 | if sample_clk_old = '0' and sample_clk = '1' then |
|
104 | if sample_clk_old = '0' and sample_clk = '1' then | |
102 | ALU_Ctrl <= MAC_op; |
|
105 | ALU_Ctrl <= MAC_op; | |
103 | sample <= in_Rotate_Buff(0); |
|
106 | sample <= in_Rotate_Buff(0); | |
104 | coef <= std_logic_vector(NumeratorCoefs(0)); |
|
107 | coef <= std_logic_vector(NumeratorCoefs(0)); | |
105 | else |
|
108 | else | |
106 | ALU_Ctrl <= clr_mac; |
|
109 | ALU_Ctrl <= clr_mac; | |
107 | loadinput: for i in 0 to ChanelsCNT-1 loop |
|
110 | loadinput: for i in 0 to ChanelsCNT-1 loop | |
108 | in_Rotate_Buff(i) <= sample_in(i); |
|
111 | in_Rotate_Buff(i) <= sample_in(i); | |
109 | end loop; |
|
112 | end loop; | |
110 | end if; |
|
113 | end if; | |
111 |
|
114 | |||
112 | when computeNUM=> |
|
115 | when computeNUM=> | |
113 | ALU_Ctrl <= MAC_op; |
|
116 | ALU_Ctrl <= MAC_op; | |
114 | sample <= RD(Smpl_SZ-1 downto 0); |
|
117 | sample <= RD(Smpl_SZ-1 downto 0); | |
115 | coef <= std_logic_vector(NumeratorCoefs(NcoefCnt)); |
|
118 | coef <= std_logic_vector(NumeratorCoefs(NcoefCnt)); | |
116 |
|
119 | |||
117 | when computeDEN=> |
|
120 | when computeDEN=> | |
118 | ALU_Ctrl <= MAC_op; |
|
121 | ALU_Ctrl <= MAC_op; | |
119 | sample <= RD(Smpl_SZ-1 downto 0); |
|
122 | sample <= RD(Smpl_SZ-1 downto 0); | |
120 | coef <= std_logic_vector(DenominatorCoefs(DcoefCnt)); |
|
123 | coef <= std_logic_vector(DenominatorCoefs(DcoefCnt)); | |
121 |
|
124 | |||
122 | when NextChanel=> |
|
125 | when NextChanel=> | |
123 | rotate : for i in 0 to ChanelsCNT-2 loop |
|
126 | rotate : for i in 0 to ChanelsCNT-2 loop | |
124 | in_Rotate_Buff(i) <= in_Rotate_Buff(i+1); |
|
127 | in_Rotate_Buff(i) <= in_Rotate_Buff(i+1); | |
125 | end loop; |
|
128 | end loop; | |
126 | rotatetoo: if ChanelsCNT > 1 then |
|
129 | rotatetoo: if ChanelsCNT > 1 then | |
127 | sample <= in_Rotate_Buff(1); |
|
130 | sample <= in_Rotate_Buff(1); | |
128 | coef <= std_logic_vector(NumeratorCoefs(0)); |
|
131 | coef <= std_logic_vector(NumeratorCoefs(0)); | |
129 | end if; |
|
132 | end if; | |
130 | end case; |
|
133 | end case; | |
131 |
|
134 | |||
132 | --================================================================= |
|
135 | --================================================================= | |
133 | --===============RAM read write==================================== |
|
136 | --===============RAM read write==================================== | |
134 | --================================================================= |
|
137 | --================================================================= | |
135 | case state is |
|
138 | case state is | |
136 | when waiting=> |
|
139 | when waiting=> | |
137 | if sample_clk_old = '0' and sample_clk = '1' then |
|
140 | if sample_clk_old = '0' and sample_clk = '1' then | |
138 | REN <= '0'; |
|
141 | REN <= '0'; | |
139 | else |
|
142 | else | |
140 | REN <= '1'; |
|
143 | REN <= '1'; | |
141 | end if; |
|
144 | end if; | |
142 | ADDR <= (others => '0'); |
|
145 | ADDR <= (others => '0'); | |
143 | WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0); |
|
146 | WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0); | |
144 | WEN <= '1'; |
|
147 | WEN <= '1'; | |
145 |
|
148 | |||
146 | when computeNUM=> |
|
149 | when computeNUM=> | |
147 | WD <= RD; |
|
150 | WD <= RD; | |
148 | REN <= '0'; |
|
151 | REN <= '0'; | |
149 | WEN <= '0'; |
|
152 | WEN <= '0'; | |
150 | ADDR <= std_logic_vector(unsigned(ADDR)+1); |
|
153 | ADDR <= std_logic_vector(unsigned(ADDR)+1); | |
151 | when computeDEN=> |
|
154 | when computeDEN=> | |
152 | WD <= RD; |
|
155 | WD <= RD; | |
153 | REN <= '0'; |
|
156 | REN <= '0'; | |
154 | WEN <= '0'; |
|
157 | WEN <= '0'; | |
155 | ADDR <= std_logic_vector(unsigned(ADDR)+1); |
|
158 | ADDR <= std_logic_vector(unsigned(ADDR)+1); | |
156 | when NextChanel=> |
|
159 | when NextChanel=> | |
157 | REN <= '1'; |
|
160 | REN <= '1'; | |
158 | WEN <= '1'; |
|
161 | WEN <= '1'; | |
159 | end case; |
|
162 | end case; | |
160 | --================================================================= |
|
163 | --================================================================= | |
161 |
|
164 | |||
162 |
|
165 | |||
163 | --================================================================= |
|
166 | --================================================================= | |
164 | --===============FSM Management==================================== |
|
167 | --===============FSM Management==================================== | |
165 | --================================================================= |
|
168 | --================================================================= | |
166 | case state is |
|
169 | case state is | |
167 | when waiting=> |
|
170 | when waiting=> | |
168 | if sample_clk_old = '0' and sample_clk = '1' then |
|
171 | if sample_clk_old = '0' and sample_clk = '1' then | |
169 | state <= computeNUM; |
|
172 | state <= computeNUM; | |
170 | end if; |
|
173 | end if; | |
171 | DcoefCnt <= 0; |
|
174 | DcoefCnt <= 0; | |
172 | NcoefCnt <= 1; |
|
175 | NcoefCnt <= 1; | |
173 | chanelCnt<= 0; |
|
176 | chanelCnt<= 0; | |
174 | when computeNUM=> |
|
177 | when computeNUM=> | |
175 | if NcoefCnt = NumCoefsCnt then |
|
178 | if NcoefCnt = NumCoefsCnt then | |
176 | state <= computeDEN; |
|
179 | state <= computeDEN; | |
177 | NcoefCnt <= 1; |
|
180 | NcoefCnt <= 1; | |
178 | else |
|
181 | else | |
179 | NcoefCnt <= NcoefCnt+1; |
|
182 | NcoefCnt <= NcoefCnt+1; | |
180 | end if; |
|
183 | end if; | |
181 | when computeDEN=> |
|
184 | when computeDEN=> | |
182 | if DcoefCnt = DENCoefsCnt then |
|
185 | if DcoefCnt = DENCoefsCnt then | |
183 | state <= NextChanel; |
|
186 | state <= NextChanel; | |
184 | DcoefCnt <= 0; |
|
187 | DcoefCnt <= 0; | |
185 | else |
|
188 | else | |
186 | DcoefCnt <= DcoefCnt+1; |
|
189 | DcoefCnt <= DcoefCnt+1; | |
187 | end if; |
|
190 | end if; | |
188 | when NextChanel=> |
|
191 | when NextChanel=> | |
189 | if chanelCnt = (ChanelsCNT-1) then |
|
192 | if chanelCnt = (ChanelsCNT-1) then | |
190 | state <= waiting; |
|
193 | state <= waiting; | |
191 | else |
|
194 | else | |
192 | chanelCnt<= chanelCnt+1; |
|
195 | chanelCnt<= chanelCnt+1; | |
193 | state <= computeNUM; |
|
196 | state <= computeNUM; | |
194 | end if; |
|
197 | end if; | |
195 | end case; |
|
198 | end case; | |
196 | --================================================================= |
|
199 | --================================================================= | |
197 |
|
200 | |||
198 | end if; |
|
201 | end if; | |
199 | end process; |
|
202 | end process; | |
200 |
|
203 | |||
201 | ADDRreg : REG |
|
204 | ADDRreg : REG | |
202 | generic map(size => 8) |
|
205 | generic map(size => 8) | |
203 | port map( |
|
206 | port map( | |
204 | reset => reset, |
|
207 | reset => reset, | |
205 | clk => clk, |
|
208 | clk => clk, | |
206 | D => ADDR, |
|
209 | D => ADDR, | |
207 | Q => ADDR_D |
|
210 | Q => ADDR_D | |
208 | ); |
|
211 | ); | |
209 |
|
212 | |||
210 | WDreg :REG |
|
213 | WDreg :REG | |
211 | generic map(size => 36) |
|
214 | generic map(size => 36) | |
212 | port map( |
|
215 | port map( | |
213 | reset => reset, |
|
216 | reset => reset, | |
214 | clk => clk, |
|
217 | clk => clk, | |
215 | D => WD, |
|
218 | D => WD, | |
216 | Q => WD_D |
|
219 | Q => WD_D | |
217 | ); |
|
220 | ); | |
218 |
|
221 | |||
219 | WRreg :REG |
|
222 | WRreg :REG | |
220 | generic map(size => 1) |
|
223 | generic map(size => 1) | |
221 | port map( |
|
224 | port map( | |
222 | reset => reset, |
|
225 | reset => reset, | |
223 | clk => clk, |
|
226 | clk => clk, | |
224 | D(0) => WEN, |
|
227 | D(0) => WEN, | |
225 | Q(0) => WEN_D |
|
228 | Q(0) => WEN_D | |
226 | ); |
|
229 | ); | |
227 | --============================================================== |
|
230 | --============================================================== | |
228 | --=========================R A M================================ |
|
231 | --=========================R A M================================ | |
229 | --============================================================== |
|
232 | --============================================================== | |
230 | memRAM : if Mem_use = use_RAM generate |
|
233 | memRAM : if Mem_use = use_RAM generate | |
231 | RAMblk :RAM |
|
234 | RAMblk :RAM | |
232 | port map( |
|
235 | port map( | |
233 | WD => WD_D, |
|
236 | WD => WD_D, | |
234 | RD => RD, |
|
237 | RD => RD, | |
235 | WEN => WEN_D, |
|
238 | WEN => WEN_D, | |
236 | REN => REN, |
|
239 | REN => REN, | |
237 | WADDR => ADDR_D, |
|
240 | WADDR => ADDR_D, | |
238 | RADDR => ADDR, |
|
241 | RADDR => ADDR, | |
239 | RWCLK => clk_inv, |
|
242 | RWCLK => clk_inv, | |
240 | RESET => reset |
|
243 | RESET => reset | |
241 | ) ; |
|
244 | ) ; | |
242 | end generate; |
|
245 | end generate; | |
243 |
|
246 | |||
244 | memCEL : if Mem_use = use_CEL generate |
|
247 | memCEL : if Mem_use = use_CEL generate | |
245 | RAMblk :RAM |
|
248 | RAMblk :RAM | |
246 | port map( |
|
249 | port map( | |
247 | WD => WD_D, |
|
250 | WD => WD_D, | |
248 | RD => RD, |
|
251 | RD => RD, | |
249 | WEN => WEN_D, |
|
252 | WEN => WEN_D, | |
250 | REN => REN, |
|
253 | REN => REN, | |
251 | WADDR => ADDR_D, |
|
254 | WADDR => ADDR_D, | |
252 | RADDR => ADDR, |
|
255 | RADDR => ADDR, | |
253 | RWCLK => clk_inv, |
|
256 | RWCLK => clk_inv, | |
254 | RESET => reset |
|
257 | RESET => reset | |
255 | ) ; |
|
258 | ) ; | |
256 | end generate; |
|
259 | end generate; | |
257 |
|
260 | |||
258 | --============================================================== |
|
261 | --============================================================== | |
259 |
|
262 | |||
260 |
|
263 | |||
261 |
|
264 | |||
262 | end ar_FilterCTRLR; |
|
265 | end ar_FilterCTRLR; |
@@ -1,327 +1,326 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | ------------------------------------------------------------------------------ |
|
19 | -- Author : Alexis Jeandet | |
20 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
21 | ------------------------------------------------------------------------------- | |
22 | -- |
|
|||
23 |
|
22 | |||
24 | library IEEE; |
|
23 | library IEEE; | |
25 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
26 | use IEEE.std_logic_1164.all; |
|
25 | use IEEE.std_logic_1164.all; | |
27 | library lpp; |
|
26 | library lpp; | |
28 | use lpp.iir_filter.all; |
|
27 | use lpp.iir_filter.all; | |
29 | use lpp.general_purpose.all; |
|
28 | use lpp.general_purpose.all; | |
30 |
|
29 | |||
31 | --TODO amliorer la gestion de la RAM et de la flexibilit du filtre |
|
30 | --TODO amliorer la gestion de la RAM et de la flexibilit du filtre | |
32 |
|
31 | |||
33 | entity IIR_CEL_CTRLR is |
|
32 | entity IIR_CEL_CTRLR is | |
34 | generic(Sample_SZ : integer := 16; |
|
33 | generic(Sample_SZ : integer := 16; | |
35 | ChanelsCount : integer := 1; |
|
34 | ChanelsCount : integer := 1; | |
36 | Coef_SZ : integer := 9; |
|
35 | Coef_SZ : integer := 9; | |
37 | CoefCntPerCel: integer := 3; |
|
36 | CoefCntPerCel: integer := 3; | |
38 | Cels_count : integer := 5; |
|
37 | Cels_count : integer := 5; | |
39 | Mem_use : integer := use_RAM |
|
38 | Mem_use : integer := use_RAM | |
40 | ); |
|
39 | ); | |
41 | port( |
|
40 | port( | |
42 | reset : in std_logic; |
|
41 | reset : in std_logic; | |
43 | clk : in std_logic; |
|
42 | clk : in std_logic; | |
44 | sample_clk : in std_logic; |
|
43 | sample_clk : in std_logic; | |
45 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
44 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
46 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
45 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
47 | virg_pos : in integer; |
|
46 | virg_pos : in integer; | |
48 | coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) |
|
47 | coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) | |
49 | ); |
|
48 | ); | |
50 | end IIR_CEL_CTRLR; |
|
49 | end IIR_CEL_CTRLR; | |
51 |
|
50 | |||
52 |
|
51 | |||
53 |
|
52 | |||
54 |
|
53 | |||
55 | architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is |
|
54 | architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is | |
56 |
|
55 | |||
57 | subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0); |
|
56 | subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0); | |
58 |
|
57 | |||
59 | signal smpl_clk_old : std_logic := '0'; |
|
58 | signal smpl_clk_old : std_logic := '0'; | |
60 | signal WD_sel : std_logic := '0'; |
|
59 | signal WD_sel : std_logic := '0'; | |
61 | signal Read : std_logic := '0'; |
|
60 | signal Read : std_logic := '0'; | |
62 | signal SVG_ADDR : std_logic := '0'; |
|
61 | signal SVG_ADDR : std_logic := '0'; | |
63 | signal count : std_logic := '0'; |
|
62 | signal count : std_logic := '0'; | |
64 | signal Write : std_logic := '0'; |
|
63 | signal Write : std_logic := '0'; | |
65 | signal WADDR_sel : std_logic := '0'; |
|
64 | signal WADDR_sel : std_logic := '0'; | |
66 | signal GO_0 : std_logic := '0'; |
|
65 | signal GO_0 : std_logic := '0'; | |
67 |
|
66 | |||
68 | signal RAM_sample_in : sampleVect; |
|
67 | signal RAM_sample_in : sampleVect; | |
69 | signal RAM_sample_in_bk: sampleVect; |
|
68 | signal RAM_sample_in_bk: sampleVect; | |
70 | signal RAM_sample_out : sampleVect; |
|
69 | signal RAM_sample_out : sampleVect; | |
71 | signal ALU_ctrl : std_logic_vector(3 downto 0); |
|
70 | signal ALU_ctrl : std_logic_vector(3 downto 0); | |
72 | signal ALU_sample_in : sampleVect; |
|
71 | signal ALU_sample_in : sampleVect; | |
73 | signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0); |
|
72 | signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0); | |
74 | signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0); |
|
73 | signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0); | |
75 | signal curentCel : integer range 0 to Cels_count-1 := 0; |
|
74 | signal curentCel : integer range 0 to Cels_count-1 := 0; | |
76 | signal curentChan : integer range 0 to ChanelsCount-1 := 0; |
|
75 | signal curentChan : integer range 0 to ChanelsCount-1 := 0; | |
77 |
|
76 | |||
78 |
|
77 | |||
79 | type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect; |
|
78 | type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect; | |
80 |
|
79 | |||
81 | signal sample_in_BUFF : sampleBuffT; |
|
80 | signal sample_in_BUFF : sampleBuffT; | |
82 | signal sample_out_BUFF : sampleBuffT; |
|
81 | signal sample_out_BUFF : sampleBuffT; | |
83 |
|
82 | |||
84 | type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0); |
|
83 | type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0); | |
85 | type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT; |
|
84 | type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT; | |
86 |
|
85 | |||
87 | type CoefsRegT is record |
|
86 | type CoefsRegT is record | |
88 | numCoefs : CoefTblT; |
|
87 | numCoefs : CoefTblT; | |
89 | denCoefs : CoefTblT; |
|
88 | denCoefs : CoefTblT; | |
90 | end record; |
|
89 | end record; | |
91 |
|
90 | |||
92 | signal CoefsReg : CoefsRegT; |
|
91 | signal CoefsReg : CoefsRegT; | |
93 |
|
92 | |||
94 | type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan); |
|
93 | type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan); | |
95 |
|
94 | |||
96 | signal IIR_CEL_STATE : fsmIIR_CEL_T; |
|
95 | signal IIR_CEL_STATE : fsmIIR_CEL_T; | |
97 |
|
96 | |||
98 | begin |
|
97 | begin | |
99 |
|
98 | |||
100 |
|
99 | |||
101 | coefsConnectL0: for z in 0 to Cels_count-1 generate |
|
100 | coefsConnectL0: for z in 0 to Cels_count-1 generate | |
102 | coefsConnectL1: for y in 0 to CoefCntPerCel-1 generate |
|
101 | coefsConnectL1: for y in 0 to CoefCntPerCel-1 generate | |
103 | coefsConnectL2: for x in 0 to Coef_SZ-1 generate |
|
102 | coefsConnectL2: for x in 0 to Coef_SZ-1 generate | |
104 | CoefsReg.numCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel); |
|
103 | CoefsReg.numCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel); | |
105 | CoefsReg.denCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel); |
|
104 | CoefsReg.denCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel); | |
106 | end generate; |
|
105 | end generate; | |
107 | end generate; |
|
106 | end generate; | |
108 | end generate; |
|
107 | end generate; | |
109 |
|
108 | |||
110 |
|
109 | |||
111 | RAM_CTRLR2inst : RAM_CTRLR2 |
|
110 | RAM_CTRLR2inst : RAM_CTRLR2 | |
112 | generic map(Sample_SZ,Mem_use) |
|
111 | generic map(Sample_SZ,Mem_use) | |
113 | port map( |
|
112 | port map( | |
114 | reset => reset, |
|
113 | reset => reset, | |
115 | clk => clk, |
|
114 | clk => clk, | |
116 | WD_sel => WD_sel, |
|
115 | WD_sel => WD_sel, | |
117 | Read => Read, |
|
116 | Read => Read, | |
118 | WADDR_sel => WADDR_sel, |
|
117 | WADDR_sel => WADDR_sel, | |
119 | count => count, |
|
118 | count => count, | |
120 | SVG_ADDR => SVG_ADDR, |
|
119 | SVG_ADDR => SVG_ADDR, | |
121 | Write => Write, |
|
120 | Write => Write, | |
122 | GO_0 => GO_0, |
|
121 | GO_0 => GO_0, | |
123 | sample_in => RAM_sample_in, |
|
122 | sample_in => RAM_sample_in, | |
124 | sample_out => RAM_sample_out |
|
123 | sample_out => RAM_sample_out | |
125 | ); |
|
124 | ); | |
126 |
|
125 | |||
127 |
|
126 | |||
128 |
|
127 | |||
129 | ALU_inst :ALU |
|
128 | ALU_inst :ALU | |
130 | generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ) |
|
129 | generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ) | |
131 | port map( |
|
130 | port map( | |
132 | clk => clk, |
|
131 | clk => clk, | |
133 | reset => reset, |
|
132 | reset => reset, | |
134 | ctrl => ALU_ctrl, |
|
133 | ctrl => ALU_ctrl, | |
135 | OP1 => ALU_sample_in, |
|
134 | OP1 => ALU_sample_in, | |
136 | OP2 => ALU_coef_in, |
|
135 | OP2 => ALU_coef_in, | |
137 | RES => ALU_out |
|
136 | RES => ALU_out | |
138 | ); |
|
137 | ); | |
139 |
|
138 | |||
140 |
|
139 | |||
141 |
|
140 | |||
142 |
|
141 | |||
143 |
|
142 | |||
144 |
|
143 | |||
145 | WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1'; |
|
144 | WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1'; | |
146 | Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0'; |
|
145 | Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0'; | |
147 | WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0'; |
|
146 | WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0'; | |
148 | count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0'; |
|
147 | count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0'; | |
149 | SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0'; |
|
148 | SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0'; | |
150 | --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0'; |
|
149 | --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0'; | |
151 | Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0'; |
|
150 | Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0'; | |
152 |
|
151 | |||
153 | GO_0 <= '1' when IIR_CEL_STATE = waiting else '0'; |
|
152 | GO_0 <= '1' when IIR_CEL_STATE = waiting else '0'; | |
154 |
|
153 | |||
155 |
|
154 | |||
156 |
|
155 | |||
157 |
|
156 | |||
158 |
|
157 | |||
159 |
|
158 | |||
160 |
|
159 | |||
161 | process(clk,reset) |
|
160 | process(clk,reset) | |
162 | variable result : std_logic_vector(Sample_SZ-1 downto 0); |
|
161 | variable result : std_logic_vector(Sample_SZ-1 downto 0); | |
163 |
|
162 | |||
164 | begin |
|
163 | begin | |
165 |
|
164 | |||
166 | if reset = '0' then |
|
165 | if reset = '0' then | |
167 |
|
166 | |||
168 | smpl_clk_old <= '0'; |
|
167 | smpl_clk_old <= '0'; | |
169 | RAM_sample_in <= (others=> '0'); |
|
168 | RAM_sample_in <= (others=> '0'); | |
170 | ALU_ctrl <= IDLE; |
|
169 | ALU_ctrl <= IDLE; | |
171 | ALU_sample_in <= (others=> '0'); |
|
170 | ALU_sample_in <= (others=> '0'); | |
172 | ALU_Coef_in <= (others=> '0'); |
|
171 | ALU_Coef_in <= (others=> '0'); | |
173 | RAM_sample_in_bk<= (others=> '0'); |
|
172 | RAM_sample_in_bk<= (others=> '0'); | |
174 | curentCel <= 0; |
|
173 | curentCel <= 0; | |
175 | curentChan <= 0; |
|
174 | curentChan <= 0; | |
176 | IIR_CEL_STATE <= waiting; |
|
175 | IIR_CEL_STATE <= waiting; | |
177 | resetL0 : for i in 0 to ChanelsCount-1 loop |
|
176 | resetL0 : for i in 0 to ChanelsCount-1 loop | |
178 | sample_in_BUFF(i) <= (others => '0'); |
|
177 | sample_in_BUFF(i) <= (others => '0'); | |
179 | sample_out_BUFF(i) <= (others => '0'); |
|
178 | sample_out_BUFF(i) <= (others => '0'); | |
180 | resetL1: for j in 0 to Sample_SZ-1 loop |
|
179 | resetL1: for j in 0 to Sample_SZ-1 loop | |
181 | sample_out(i,j) <= '0'; |
|
180 | sample_out(i,j) <= '0'; | |
182 | end loop; |
|
181 | end loop; | |
183 | end loop; |
|
182 | end loop; | |
184 |
|
183 | |||
185 | elsif clk'event and clk = '1' then |
|
184 | elsif clk'event and clk = '1' then | |
186 |
|
185 | |||
187 | smpl_clk_old <= sample_clk; |
|
186 | smpl_clk_old <= sample_clk; | |
188 |
|
187 | |||
189 | case IIR_CEL_STATE is |
|
188 | case IIR_CEL_STATE is | |
190 |
|
189 | |||
191 | when waiting => |
|
190 | when waiting => | |
192 | if sample_clk = '1' and smpl_clk_old = '0' then |
|
191 | if sample_clk = '1' and smpl_clk_old = '0' then | |
193 | IIR_CEL_STATE <= pipe1; |
|
192 | IIR_CEL_STATE <= pipe1; | |
194 | RAM_sample_in <= std_logic_vector(sample_in_BUFF(0)); |
|
193 | RAM_sample_in <= std_logic_vector(sample_in_BUFF(0)); | |
195 | ALU_sample_in <= std_logic_vector(sample_in_BUFF(0)); |
|
194 | ALU_sample_in <= std_logic_vector(sample_in_BUFF(0)); | |
196 |
|
195 | |||
197 | else |
|
196 | else | |
198 | ALU_ctrl <= IDLE; |
|
197 | ALU_ctrl <= IDLE; | |
199 | smplConnectL0: for i in 0 to ChanelsCount-1 loop |
|
198 | smplConnectL0: for i in 0 to ChanelsCount-1 loop | |
200 | smplConnectL1: for j in 0 to Sample_SZ-1 loop |
|
199 | smplConnectL1: for j in 0 to Sample_SZ-1 loop | |
201 | sample_in_BUFF(i)(j) <= sample_in(i,j); |
|
200 | sample_in_BUFF(i)(j) <= sample_in(i,j); | |
202 | sample_out(i,j) <= sample_out_BUFF(i)(j); |
|
201 | sample_out(i,j) <= sample_out_BUFF(i)(j); | |
203 | end loop; |
|
202 | end loop; | |
204 | end loop; |
|
203 | end loop; | |
205 | end if; |
|
204 | end if; | |
206 | curentCel <= 0; |
|
205 | curentCel <= 0; | |
207 | curentChan <= 0; |
|
206 | curentChan <= 0; | |
208 |
|
207 | |||
209 | when pipe1 => |
|
208 | when pipe1 => | |
210 | IIR_CEL_STATE <= computeb1; |
|
209 | IIR_CEL_STATE <= computeb1; | |
211 | ALU_ctrl <= MAC_op; |
|
210 | ALU_ctrl <= MAC_op; | |
212 | ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0)); |
|
211 | ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0)); | |
213 |
|
212 | |||
214 | when computeb1 => |
|
213 | when computeb1 => | |
215 |
|
214 | |||
216 | ALU_ctrl <= MAC_op; |
|
215 | ALU_ctrl <= MAC_op; | |
217 | ALU_sample_in <= RAM_sample_out; |
|
216 | ALU_sample_in <= RAM_sample_out; | |
218 | ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1)); |
|
217 | ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1)); | |
219 | IIR_CEL_STATE <= computeb2; |
|
218 | IIR_CEL_STATE <= computeb2; | |
220 | RAM_sample_in <= RAM_sample_in_bk; |
|
219 | RAM_sample_in <= RAM_sample_in_bk; | |
221 | when computeb2 => |
|
220 | when computeb2 => | |
222 | ALU_sample_in <= RAM_sample_out; |
|
221 | ALU_sample_in <= RAM_sample_out; | |
223 | ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2)); |
|
222 | ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2)); | |
224 | IIR_CEL_STATE <= computea1; |
|
223 | IIR_CEL_STATE <= computea1; | |
225 |
|
224 | |||
226 |
|
225 | |||
227 | when computea1 => |
|
226 | when computea1 => | |
228 | ALU_sample_in <= RAM_sample_out; |
|
227 | ALU_sample_in <= RAM_sample_out; | |
229 | ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1)); |
|
228 | ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1)); | |
230 | IIR_CEL_STATE <= computea2; |
|
229 | IIR_CEL_STATE <= computea2; | |
231 |
|
230 | |||
232 |
|
231 | |||
233 | when computea2 => |
|
232 | when computea2 => | |
234 | ALU_sample_in <= RAM_sample_out; |
|
233 | ALU_sample_in <= RAM_sample_out; | |
235 | ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2)); |
|
234 | ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2)); | |
236 | IIR_CEL_STATE <= next_cel; |
|
235 | IIR_CEL_STATE <= next_cel; | |
237 |
|
236 | |||
238 |
|
237 | |||
239 | when next_cel => |
|
238 | when next_cel => | |
240 | ALU_ctrl <= clr_mac; |
|
239 | ALU_ctrl <= clr_mac; | |
241 | IIR_CEL_STATE <= pipe2; |
|
240 | IIR_CEL_STATE <= pipe2; | |
242 |
|
241 | |||
243 | when pipe2 => |
|
242 | when pipe2 => | |
244 | IIR_CEL_STATE <= pipe3; |
|
243 | IIR_CEL_STATE <= pipe3; | |
245 |
|
244 | |||
246 |
|
245 | |||
247 | when pipe3 => |
|
246 | when pipe3 => | |
248 |
|
247 | |||
249 | result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos); |
|
248 | result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos); | |
250 |
|
249 | |||
251 | sample_out_BUFF(0) <= result; |
|
250 | sample_out_BUFF(0) <= result; | |
252 | RAM_sample_in_bk <= result; |
|
251 | RAM_sample_in_bk <= result; | |
253 | RAM_sample_in <= result; |
|
252 | RAM_sample_in <= result; | |
254 | if curentCel = Cels_count-1 then |
|
253 | if curentCel = Cels_count-1 then | |
255 | IIR_CEL_STATE <= next_chan; |
|
254 | IIR_CEL_STATE <= next_chan; | |
256 | curentCel <= 0; |
|
255 | curentCel <= 0; | |
257 | else |
|
256 | else | |
258 | curentCel <= curentCel + 1; |
|
257 | curentCel <= curentCel + 1; | |
259 | IIR_CEL_STATE <= pipe1; |
|
258 | IIR_CEL_STATE <= pipe1; | |
260 | ALU_sample_in <= result; |
|
259 | ALU_sample_in <= result; | |
261 | end if; |
|
260 | end if; | |
262 | when next_chan => |
|
261 | when next_chan => | |
263 |
|
262 | |||
264 | rotate : for i in 1 to ChanelsCount-1 loop |
|
263 | rotate : for i in 1 to ChanelsCount-1 loop | |
265 | sample_in_BUFF(i-1) <= sample_in_BUFF(i); |
|
264 | sample_in_BUFF(i-1) <= sample_in_BUFF(i); | |
266 | sample_out_BUFF(i-1) <= sample_out_BUFF(i); |
|
265 | sample_out_BUFF(i-1) <= sample_out_BUFF(i); | |
267 | end loop; |
|
266 | end loop; | |
268 | sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0); |
|
267 | sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0); | |
269 | sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0); |
|
268 | sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0); | |
270 |
|
269 | |||
271 | if curentChan = (ChanelsCount-1) then |
|
270 | if curentChan = (ChanelsCount-1) then | |
272 | IIR_CEL_STATE <= waiting; |
|
271 | IIR_CEL_STATE <= waiting; | |
273 | ALU_ctrl <= clr_mac; |
|
272 | ALU_ctrl <= clr_mac; | |
274 | elsif ChanelsCount>1 then |
|
273 | elsif ChanelsCount>1 then | |
275 | curentChan <= curentChan + 1; |
|
274 | curentChan <= curentChan + 1; | |
276 | IIR_CEL_STATE <= pipe1; |
|
275 | IIR_CEL_STATE <= pipe1; | |
277 | ALU_sample_in <= sample_in_BUFF(1); |
|
276 | ALU_sample_in <= sample_in_BUFF(1); | |
278 | RAM_sample_in <= sample_in_BUFF(1); |
|
277 | RAM_sample_in <= sample_in_BUFF(1); | |
279 | end if; |
|
278 | end if; | |
280 | end case; |
|
279 | end case; | |
281 |
|
280 | |||
282 | end if; |
|
281 | end if; | |
283 | end process; |
|
282 | end process; | |
284 |
|
283 | |||
285 |
|
284 | |||
286 |
|
285 | |||
287 |
|
286 | |||
288 |
|
287 | |||
289 |
|
288 | |||
290 | end ar_IIR_CEL_CTRLR; |
|
289 | end ar_IIR_CEL_CTRLR; | |
291 |
|
290 | |||
292 |
|
291 | |||
293 |
|
292 | |||
294 |
|
293 | |||
295 |
|
294 | |||
296 |
|
295 | |||
297 |
|
296 | |||
298 |
|
297 | |||
299 |
|
298 | |||
300 |
|
299 | |||
301 |
|
300 | |||
302 |
|
301 | |||
303 |
|
302 | |||
304 |
|
303 | |||
305 |
|
304 | |||
306 |
|
305 | |||
307 |
|
306 | |||
308 |
|
307 | |||
309 |
|
308 | |||
310 |
|
309 | |||
311 |
|
310 | |||
312 |
|
311 | |||
313 |
|
312 | |||
314 |
|
313 | |||
315 |
|
314 | |||
316 |
|
315 | |||
317 |
|
316 | |||
318 |
|
317 | |||
319 |
|
318 | |||
320 |
|
319 | |||
321 |
|
320 | |||
322 |
|
321 | |||
323 |
|
322 | |||
324 |
|
323 | |||
325 |
|
324 | |||
326 |
|
325 | |||
327 |
|
326 |
@@ -1,92 +1,95 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.iir_filter.all; |
|
26 | use lpp.iir_filter.all; | |
24 | use lpp.general_purpose.all; |
|
27 | use lpp.general_purpose.all; | |
25 |
|
28 | |||
26 | --TODO amliorer la gestion de la RAM et de la flexibilit du filtre |
|
29 | --TODO amliorer la gestion de la RAM et de la flexibilit du filtre | |
27 |
|
30 | |||
28 | entity IIR_CEL_FILTER is |
|
31 | entity IIR_CEL_FILTER is | |
29 | generic(Sample_SZ : integer := 16; |
|
32 | generic(Sample_SZ : integer := 16; | |
30 | ChanelsCount : integer := 1; |
|
33 | ChanelsCount : integer := 1; | |
31 | Coef_SZ : integer := 9; |
|
34 | Coef_SZ : integer := 9; | |
32 | CoefCntPerCel: integer := 3; |
|
35 | CoefCntPerCel: integer := 3; | |
33 | Cels_count : integer := 5; |
|
36 | Cels_count : integer := 5; | |
34 | Mem_use : integer := use_RAM); |
|
37 | Mem_use : integer := use_RAM); | |
35 | port( |
|
38 | port( | |
36 | reset : in std_logic; |
|
39 | reset : in std_logic; | |
37 | clk : in std_logic; |
|
40 | clk : in std_logic; | |
38 | sample_clk : in std_logic; |
|
41 | sample_clk : in std_logic; | |
39 | regs_in : in in_IIR_CEL_reg; |
|
42 | regs_in : in in_IIR_CEL_reg; | |
40 | regs_out : in out_IIR_CEL_reg; |
|
43 | regs_out : in out_IIR_CEL_reg; | |
41 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
44 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
42 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
45 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
43 | coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) |
|
46 | coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) | |
44 |
|
47 | |||
45 | ); |
|
48 | ); | |
46 | end IIR_CEL_FILTER; |
|
49 | end IIR_CEL_FILTER; | |
47 |
|
50 | |||
48 |
|
51 | |||
49 |
|
52 | |||
50 |
|
53 | |||
51 | architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is |
|
54 | architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is | |
52 |
|
55 | |||
53 | signal virg_pos : integer; |
|
56 | signal virg_pos : integer; | |
54 | begin |
|
57 | begin | |
55 |
|
58 | |||
56 | virg_pos <= to_integer(unsigned(regs_in.virgPos)); |
|
59 | virg_pos <= to_integer(unsigned(regs_in.virgPos)); | |
57 |
|
60 | |||
58 | CTRLR : IIR_CEL_CTRLR |
|
61 | CTRLR : IIR_CEL_CTRLR | |
59 | generic map (Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) |
|
62 | generic map (Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) | |
60 | port map( |
|
63 | port map( | |
61 | reset => reset, |
|
64 | reset => reset, | |
62 | clk => clk, |
|
65 | clk => clk, | |
63 | sample_clk => sample_clk, |
|
66 | sample_clk => sample_clk, | |
64 | sample_in => sample_in, |
|
67 | sample_in => sample_in, | |
65 | sample_out => sample_out, |
|
68 | sample_out => sample_out, | |
66 | virg_pos => virg_pos, |
|
69 | virg_pos => virg_pos, | |
67 | coefs => coefs |
|
70 | coefs => coefs | |
68 | ); |
|
71 | ); | |
69 |
|
72 | |||
70 |
|
73 | |||
71 |
|
74 | |||
72 |
|
75 | |||
73 |
|
76 | |||
74 | end ar_IIR_CEL_FILTER; |
|
77 | end ar_IIR_CEL_FILTER; | |
75 |
|
78 | |||
76 |
|
79 | |||
77 |
|
80 | |||
78 |
|
81 | |||
79 |
|
82 | |||
80 |
|
83 | |||
81 |
|
84 | |||
82 |
|
85 | |||
83 |
|
86 | |||
84 |
|
87 | |||
85 |
|
88 | |||
86 |
|
89 | |||
87 |
|
90 | |||
88 |
|
91 | |||
89 |
|
92 | |||
90 |
|
93 | |||
91 |
|
94 | |||
92 |
|
95 |
@@ -1,61 +1,64 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library ieee; |
|
22 | library ieee; | |
20 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
21 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
22 |
|
25 | |||
23 | entity RAM is |
|
26 | entity RAM is | |
24 | port( WD : in std_logic_vector(35 downto 0); RD : out |
|
27 | port( WD : in std_logic_vector(35 downto 0); RD : out | |
25 | std_logic_vector(35 downto 0);WEN, REN : in std_logic; |
|
28 | std_logic_vector(35 downto 0);WEN, REN : in std_logic; | |
26 | WADDR : in std_logic_vector(7 downto 0); RADDR : in |
|
29 | WADDR : in std_logic_vector(7 downto 0); RADDR : in | |
27 | std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic |
|
30 | std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic | |
28 | ) ; |
|
31 | ) ; | |
29 | end RAM; |
|
32 | end RAM; | |
30 |
|
33 | |||
31 |
|
34 | |||
32 | architecture DEF_ARCH of RAM is |
|
35 | architecture DEF_ARCH of RAM is | |
33 | type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0); |
|
36 | type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0); | |
34 | signal RAMarray : RAMarrayT:=(others => X"000000000"); |
|
37 | signal RAMarray : RAMarrayT:=(others => X"000000000"); | |
35 | signal RD_int : std_logic_vector(35 downto 0); |
|
38 | signal RD_int : std_logic_vector(35 downto 0); | |
36 |
|
39 | |||
37 | begin |
|
40 | begin | |
38 |
|
41 | |||
39 | RD_int <= RAMarray(to_integer(unsigned(RADDR))); |
|
42 | RD_int <= RAMarray(to_integer(unsigned(RADDR))); | |
40 |
|
43 | |||
41 |
|
44 | |||
42 | process(RWclk,reset) |
|
45 | process(RWclk,reset) | |
43 | begin |
|
46 | begin | |
44 | if reset = '0' then |
|
47 | if reset = '0' then | |
45 | RD <= (X"000000000"); |
|
48 | RD <= (X"000000000"); | |
46 | rst:for i in 0 to 255 loop |
|
49 | rst:for i in 0 to 255 loop | |
47 | RAMarray(i) <= (others => '0'); |
|
50 | RAMarray(i) <= (others => '0'); | |
48 | end loop; |
|
51 | end loop; | |
49 |
|
52 | |||
50 | elsif RWclk'event and RWclk = '1' then |
|
53 | elsif RWclk'event and RWclk = '1' then | |
51 | if REN = '0' then |
|
54 | if REN = '0' then | |
52 | RD <= RD_int; |
|
55 | RD <= RD_int; | |
53 | end if; |
|
56 | end if; | |
54 |
|
57 | |||
55 | if WEN = '0' then |
|
58 | if WEN = '0' then | |
56 | RAMarray(to_integer(unsigned(WADDR))) <= WD; |
|
59 | RAMarray(to_integer(unsigned(WADDR))) <= WD; | |
57 | end if; |
|
60 | end if; | |
58 |
|
61 | |||
59 | end if; |
|
62 | end if; | |
60 | end process; |
|
63 | end process; | |
61 | end DEF_ARCH; |
|
64 | end DEF_ARCH; |
@@ -1,90 +1,93 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library ieee; |
|
22 | library ieee; | |
20 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
21 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
22 |
|
25 | |||
23 | entity RAM_CEL is |
|
26 | entity RAM_CEL is | |
24 | port( WD : in std_logic_vector(35 downto 0); RD : out |
|
27 | port( WD : in std_logic_vector(35 downto 0); RD : out | |
25 | std_logic_vector(35 downto 0);WEN, REN : in std_logic; |
|
28 | std_logic_vector(35 downto 0);WEN, REN : in std_logic; | |
26 | WADDR : in std_logic_vector(7 downto 0); RADDR : in |
|
29 | WADDR : in std_logic_vector(7 downto 0); RADDR : in | |
27 | std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic |
|
30 | std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic | |
28 | ) ; |
|
31 | ) ; | |
29 | end RAM_CEL; |
|
32 | end RAM_CEL; | |
30 |
|
33 | |||
31 |
|
34 | |||
32 |
|
35 | |||
33 | architecture ar_RAM_CEL of RAM_CEL is |
|
36 | architecture ar_RAM_CEL of RAM_CEL is | |
34 | type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0); |
|
37 | type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0); | |
35 | signal RAMarray : RAMarrayT:=(others => X"000000000"); |
|
38 | signal RAMarray : RAMarrayT:=(others => X"000000000"); | |
36 | signal RD_int : std_logic_vector(35 downto 0); |
|
39 | signal RD_int : std_logic_vector(35 downto 0); | |
37 |
|
40 | |||
38 | begin |
|
41 | begin | |
39 |
|
42 | |||
40 | RD_int <= RAMarray(to_integer(unsigned(RADDR))); |
|
43 | RD_int <= RAMarray(to_integer(unsigned(RADDR))); | |
41 |
|
44 | |||
42 |
|
45 | |||
43 | process(RWclk,reset) |
|
46 | process(RWclk,reset) | |
44 | begin |
|
47 | begin | |
45 | if reset = '0' then |
|
48 | if reset = '0' then | |
46 | RD <= (X"000000000"); |
|
49 | RD <= (X"000000000"); | |
47 | rst:for i in 0 to 255 loop |
|
50 | rst:for i in 0 to 255 loop | |
48 | RAMarray(i) <= (others => '0'); |
|
51 | RAMarray(i) <= (others => '0'); | |
49 | end loop; |
|
52 | end loop; | |
50 |
|
53 | |||
51 | elsif RWclk'event and RWclk = '1' then |
|
54 | elsif RWclk'event and RWclk = '1' then | |
52 | if REN = '0' then |
|
55 | if REN = '0' then | |
53 | RD <= RD_int; |
|
56 | RD <= RD_int; | |
54 | end if; |
|
57 | end if; | |
55 |
|
58 | |||
56 | if WEN = '0' then |
|
59 | if WEN = '0' then | |
57 | RAMarray(to_integer(unsigned(WADDR))) <= WD; |
|
60 | RAMarray(to_integer(unsigned(WADDR))) <= WD; | |
58 | end if; |
|
61 | end if; | |
59 |
|
62 | |||
60 | end if; |
|
63 | end if; | |
61 | end process; |
|
64 | end process; | |
62 | end ar_RAM_CEL; |
|
65 | end ar_RAM_CEL; | |
63 |
|
66 | |||
64 |
|
67 | |||
65 |
|
68 | |||
66 |
|
69 | |||
67 |
|
70 | |||
68 |
|
71 | |||
69 |
|
72 | |||
70 |
|
73 | |||
71 |
|
74 | |||
72 |
|
75 | |||
73 |
|
76 | |||
74 |
|
77 | |||
75 |
|
78 | |||
76 |
|
79 | |||
77 |
|
80 | |||
78 |
|
81 | |||
79 |
|
82 | |||
80 |
|
83 | |||
81 |
|
84 | |||
82 |
|
85 | |||
83 |
|
86 | |||
84 |
|
87 | |||
85 |
|
88 | |||
86 |
|
89 | |||
87 |
|
90 | |||
88 |
|
91 | |||
89 |
|
92 | |||
90 |
|
93 |
@@ -1,210 +1,213 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.iir_filter.all; |
|
26 | use lpp.iir_filter.all; | |
24 | use lpp.FILTERcfg.all; |
|
27 | use lpp.FILTERcfg.all; | |
25 | use lpp.general_purpose.all; |
|
28 | use lpp.general_purpose.all; | |
26 |
|
29 | |||
27 | --TODO amliorer la flexibilit de la config de la RAM. |
|
30 | --TODO amliorer la flexibilit de la config de la RAM. | |
28 |
|
31 | |||
29 | entity RAM_CTRLR2 is |
|
32 | entity RAM_CTRLR2 is | |
30 | generic( |
|
33 | generic( | |
31 | Input_SZ_1 : integer := 16; |
|
34 | Input_SZ_1 : integer := 16; | |
32 | Mem_use : integer := use_RAM |
|
35 | Mem_use : integer := use_RAM | |
33 | ); |
|
36 | ); | |
34 | port( |
|
37 | port( | |
35 | reset : in std_logic; |
|
38 | reset : in std_logic; | |
36 | clk : in std_logic; |
|
39 | clk : in std_logic; | |
37 | WD_sel : in std_logic; |
|
40 | WD_sel : in std_logic; | |
38 | Read : in std_logic; |
|
41 | Read : in std_logic; | |
39 | WADDR_sel : in std_logic; |
|
42 | WADDR_sel : in std_logic; | |
40 | count : in std_logic; |
|
43 | count : in std_logic; | |
41 | SVG_ADDR : in std_logic; |
|
44 | SVG_ADDR : in std_logic; | |
42 | Write : in std_logic; |
|
45 | Write : in std_logic; | |
43 | GO_0 : in std_logic; |
|
46 | GO_0 : in std_logic; | |
44 | sample_in : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
47 | sample_in : in std_logic_vector(Input_SZ_1-1 downto 0); | |
45 | sample_out : out std_logic_vector(Input_SZ_1-1 downto 0) |
|
48 | sample_out : out std_logic_vector(Input_SZ_1-1 downto 0) | |
46 | ); |
|
49 | ); | |
47 | end RAM_CTRLR2; |
|
50 | end RAM_CTRLR2; | |
48 |
|
51 | |||
49 |
|
52 | |||
50 | architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is |
|
53 | architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is | |
51 |
|
54 | |||
52 | signal WD : std_logic_vector(35 downto 0); |
|
55 | signal WD : std_logic_vector(35 downto 0); | |
53 | signal WD_D : std_logic_vector(35 downto 0); |
|
56 | signal WD_D : std_logic_vector(35 downto 0); | |
54 | signal RD : std_logic_vector(35 downto 0); |
|
57 | signal RD : std_logic_vector(35 downto 0); | |
55 | signal WEN, REN : std_logic; |
|
58 | signal WEN, REN : std_logic; | |
56 | signal WADDR_back : std_logic_vector(7 downto 0); |
|
59 | signal WADDR_back : std_logic_vector(7 downto 0); | |
57 | signal WADDR_back_D: std_logic_vector(7 downto 0); |
|
60 | signal WADDR_back_D: std_logic_vector(7 downto 0); | |
58 | signal RADDR : std_logic_vector(7 downto 0); |
|
61 | signal RADDR : std_logic_vector(7 downto 0); | |
59 | signal WADDR : std_logic_vector(7 downto 0); |
|
62 | signal WADDR : std_logic_vector(7 downto 0); | |
60 | signal WADDR_D : std_logic_vector(7 downto 0); |
|
63 | signal WADDR_D : std_logic_vector(7 downto 0); | |
61 |
|
64 | |||
62 |
|
65 | |||
63 |
|
66 | |||
64 | begin |
|
67 | begin | |
65 |
|
68 | |||
66 | sample_out <= RD(Input_SZ_1-1 downto 0); |
|
69 | sample_out <= RD(Input_SZ_1-1 downto 0); | |
67 |
|
70 | |||
68 |
|
71 | |||
69 | WEN <= not Write; |
|
72 | WEN <= not Write; | |
70 | REN <= not read; |
|
73 | REN <= not read; | |
71 |
|
74 | |||
72 |
|
75 | |||
73 | --============================================================== |
|
76 | --============================================================== | |
74 | --=========================R A M================================ |
|
77 | --=========================R A M================================ | |
75 | --============================================================== |
|
78 | --============================================================== | |
76 | memRAM : if Mem_use = use_RAM generate |
|
79 | memRAM : if Mem_use = use_RAM generate | |
77 | RAMblk :RAM |
|
80 | RAMblk :RAM | |
78 | port map( |
|
81 | port map( | |
79 | WD => WD_D, |
|
82 | WD => WD_D, | |
80 | RD => RD, |
|
83 | RD => RD, | |
81 | WEN => WEN, |
|
84 | WEN => WEN, | |
82 | REN => REN, |
|
85 | REN => REN, | |
83 | WADDR => WADDR, |
|
86 | WADDR => WADDR, | |
84 | RADDR => RADDR, |
|
87 | RADDR => RADDR, | |
85 | RWCLK => clk, |
|
88 | RWCLK => clk, | |
86 | RESET => reset |
|
89 | RESET => reset | |
87 | ) ; |
|
90 | ) ; | |
88 | end generate; |
|
91 | end generate; | |
89 |
|
92 | |||
90 | memCEL : if Mem_use = use_CEL generate |
|
93 | memCEL : if Mem_use = use_CEL generate | |
91 | RAMblk :RAM_CEL |
|
94 | RAMblk :RAM_CEL | |
92 | port map( |
|
95 | port map( | |
93 | WD => WD_D, |
|
96 | WD => WD_D, | |
94 | RD => RD, |
|
97 | RD => RD, | |
95 | WEN => WEN, |
|
98 | WEN => WEN, | |
96 | REN => REN, |
|
99 | REN => REN, | |
97 | WADDR => WADDR, |
|
100 | WADDR => WADDR, | |
98 | RADDR => RADDR, |
|
101 | RADDR => RADDR, | |
99 | RWCLK => clk, |
|
102 | RWCLK => clk, | |
100 | RESET => reset |
|
103 | RESET => reset | |
101 | ) ; |
|
104 | ) ; | |
102 | end generate; |
|
105 | end generate; | |
103 | --============================================================== |
|
106 | --============================================================== | |
104 | --============================================================== |
|
107 | --============================================================== | |
105 |
|
108 | |||
106 |
|
109 | |||
107 | ADDRcntr_inst : ADDRcntr |
|
110 | ADDRcntr_inst : ADDRcntr | |
108 | port map( |
|
111 | port map( | |
109 | clk => clk, |
|
112 | clk => clk, | |
110 | reset => reset, |
|
113 | reset => reset, | |
111 | count => count, |
|
114 | count => count, | |
112 | clr => GO_0, |
|
115 | clr => GO_0, | |
113 | Q => RADDR |
|
116 | Q => RADDR | |
114 | ); |
|
117 | ); | |
115 |
|
118 | |||
116 |
|
119 | |||
117 |
|
120 | |||
118 | MUX2_inst1 :MUX2 |
|
121 | MUX2_inst1 :MUX2 | |
119 | generic map(Input_SZ => Input_SZ_1) |
|
122 | generic map(Input_SZ => Input_SZ_1) | |
120 | port map( |
|
123 | port map( | |
121 | sel => WD_sel, |
|
124 | sel => WD_sel, | |
122 | IN1 => sample_in, |
|
125 | IN1 => sample_in, | |
123 | IN2 => RD(Input_SZ_1-1 downto 0), |
|
126 | IN2 => RD(Input_SZ_1-1 downto 0), | |
124 | RES => WD(Input_SZ_1-1 downto 0) |
|
127 | RES => WD(Input_SZ_1-1 downto 0) | |
125 | ); |
|
128 | ); | |
126 |
|
129 | |||
127 |
|
130 | |||
128 | MUX2_inst2 :MUX2 |
|
131 | MUX2_inst2 :MUX2 | |
129 | generic map(Input_SZ => 8) |
|
132 | generic map(Input_SZ => 8) | |
130 | port map( |
|
133 | port map( | |
131 | sel => WADDR_sel, |
|
134 | sel => WADDR_sel, | |
132 | IN1 => WADDR_D, |
|
135 | IN1 => WADDR_D, | |
133 | IN2 => WADDR_back_D, |
|
136 | IN2 => WADDR_back_D, | |
134 | RES => WADDR |
|
137 | RES => WADDR | |
135 | ); |
|
138 | ); | |
136 |
|
139 | |||
137 |
|
140 | |||
138 |
|
141 | |||
139 |
|
142 | |||
140 | WADDR_backreg :REG |
|
143 | WADDR_backreg :REG | |
141 | generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2) |
|
144 | generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2) | |
142 | port map( |
|
145 | port map( | |
143 | reset => reset, |
|
146 | reset => reset, | |
144 | clk => SVG_ADDR, |
|
147 | clk => SVG_ADDR, | |
145 | D => RADDR, |
|
148 | D => RADDR, | |
146 | Q => WADDR_back |
|
149 | Q => WADDR_back | |
147 | ); |
|
150 | ); | |
148 |
|
151 | |||
149 | WADDR_backreg2 :REG |
|
152 | WADDR_backreg2 :REG | |
150 | generic map(size => 8) |
|
153 | generic map(size => 8) | |
151 | port map( |
|
154 | port map( | |
152 | reset => reset, |
|
155 | reset => reset, | |
153 | clk => SVG_ADDR, |
|
156 | clk => SVG_ADDR, | |
154 | D => WADDR_back, |
|
157 | D => WADDR_back, | |
155 | Q => WADDR_back_D |
|
158 | Q => WADDR_back_D | |
156 | ); |
|
159 | ); | |
157 |
|
160 | |||
158 | WDRreg :REG |
|
161 | WDRreg :REG | |
159 | generic map(size => Input_SZ_1) |
|
162 | generic map(size => Input_SZ_1) | |
160 | port map( |
|
163 | port map( | |
161 | reset => reset, |
|
164 | reset => reset, | |
162 | clk => clk, |
|
165 | clk => clk, | |
163 | D => WD(Input_SZ_1-1 downto 0), |
|
166 | D => WD(Input_SZ_1-1 downto 0), | |
164 | Q => WD_D(Input_SZ_1-1 downto 0) |
|
167 | Q => WD_D(Input_SZ_1-1 downto 0) | |
165 | ); |
|
168 | ); | |
166 |
|
169 | |||
167 |
|
170 | |||
168 |
|
171 | |||
169 |
|
172 | |||
170 | ADDRreg :REG |
|
173 | ADDRreg :REG | |
171 | generic map(size => 8) |
|
174 | generic map(size => 8) | |
172 | port map( |
|
175 | port map( | |
173 | reset => reset, |
|
176 | reset => reset, | |
174 | clk => clk, |
|
177 | clk => clk, | |
175 | D => RADDR, |
|
178 | D => RADDR, | |
176 | Q => WADDR_D |
|
179 | Q => WADDR_D | |
177 | ); |
|
180 | ); | |
178 |
|
181 | |||
179 |
|
182 | |||
180 |
|
183 | |||
181 | end ar_RAM_CTRLR2; |
|
184 | end ar_RAM_CTRLR2; | |
182 |
|
185 | |||
183 |
|
186 | |||
184 |
|
187 | |||
185 |
|
188 | |||
186 |
|
189 | |||
187 |
|
190 | |||
188 |
|
191 | |||
189 |
|
192 | |||
190 |
|
193 | |||
191 |
|
194 | |||
192 |
|
195 | |||
193 |
|
196 | |||
194 |
|
197 | |||
195 |
|
198 | |||
196 |
|
199 | |||
197 |
|
200 | |||
198 |
|
201 | |||
199 |
|
202 | |||
200 |
|
203 | |||
201 |
|
204 | |||
202 |
|
205 | |||
203 |
|
206 | |||
204 |
|
207 | |||
205 |
|
208 | |||
206 |
|
209 | |||
207 |
|
210 | |||
208 |
|
211 | |||
209 |
|
212 | |||
210 |
|
213 |
@@ -1,113 +1,116 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 |
|
25 | |||
23 |
|
26 | |||
24 |
|
27 | |||
25 | entity TestbenshMAC is |
|
28 | entity TestbenshMAC is | |
26 | end TestbenshMAC; |
|
29 | end TestbenshMAC; | |
27 |
|
30 | |||
28 |
|
31 | |||
29 |
|
32 | |||
30 |
|
33 | |||
31 | architecture ar_TestbenshMAC of TestbenshMAC is |
|
34 | architecture ar_TestbenshMAC of TestbenshMAC is | |
32 |
|
35 | |||
33 |
|
36 | |||
34 |
|
37 | |||
35 | constant OP1sz : integer := 16; |
|
38 | constant OP1sz : integer := 16; | |
36 | constant OP2sz : integer := 12; |
|
39 | constant OP2sz : integer := 12; | |
37 | --IDLE =00 MAC =01 MULT =10 ADD =11 |
|
40 | --IDLE =00 MAC =01 MULT =10 ADD =11 | |
38 | constant IDLE : std_logic_vector(1 downto 0) := "00"; |
|
41 | constant IDLE : std_logic_vector(1 downto 0) := "00"; | |
39 | constant MAC : std_logic_vector(1 downto 0) := "01"; |
|
42 | constant MAC : std_logic_vector(1 downto 0) := "01"; | |
40 | constant MULT : std_logic_vector(1 downto 0) := "10"; |
|
43 | constant MULT : std_logic_vector(1 downto 0) := "10"; | |
41 | constant ADD : std_logic_vector(1 downto 0) := "11"; |
|
44 | constant ADD : std_logic_vector(1 downto 0) := "11"; | |
42 |
|
45 | |||
43 | signal clk : std_logic:='0'; |
|
46 | signal clk : std_logic:='0'; | |
44 | signal reset : std_logic:='0'; |
|
47 | signal reset : std_logic:='0'; | |
45 | signal clrMAC : std_logic:='0'; |
|
48 | signal clrMAC : std_logic:='0'; | |
46 | signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE; |
|
49 | signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE; | |
47 | signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0'); |
|
50 | signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0'); | |
48 | signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0'); |
|
51 | signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0'); | |
49 | signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0); |
|
52 | signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0); | |
50 |
|
53 | |||
51 |
|
54 | |||
52 |
|
55 | |||
53 |
|
56 | |||
54 | begin |
|
57 | begin | |
55 |
|
58 | |||
56 |
|
59 | |||
57 | MAC1 : entity LPP_IIR_FILTER.MAC |
|
60 | MAC1 : entity LPP_IIR_FILTER.MAC | |
58 | generic map( |
|
61 | generic map( | |
59 | Input_SZ_A => OP1sz, |
|
62 | Input_SZ_A => OP1sz, | |
60 | Input_SZ_B => OP2sz |
|
63 | Input_SZ_B => OP2sz | |
61 |
|
64 | |||
62 | ) |
|
65 | ) | |
63 | port map( |
|
66 | port map( | |
64 | clk => clk, |
|
67 | clk => clk, | |
65 | reset => reset, |
|
68 | reset => reset, | |
66 | clr_MAC => clrMAC, |
|
69 | clr_MAC => clrMAC, | |
67 | MAC_MUL_ADD => MAC_MUL_ADD, |
|
70 | MAC_MUL_ADD => MAC_MUL_ADD, | |
68 | OP1 => Operand1, |
|
71 | OP1 => Operand1, | |
69 | OP2 => Operand2, |
|
72 | OP2 => Operand2, | |
70 | RES => Resultat |
|
73 | RES => Resultat | |
71 | ); |
|
74 | ); | |
72 |
|
75 | |||
73 | clk <= not clk after 25 ns; |
|
76 | clk <= not clk after 25 ns; | |
74 |
|
77 | |||
75 | process |
|
78 | process | |
76 | begin |
|
79 | begin | |
77 | wait for 40 ns; |
|
80 | wait for 40 ns; | |
78 | reset <= '1'; |
|
81 | reset <= '1'; | |
79 | wait for 11 ns; |
|
82 | wait for 11 ns; | |
80 | Operand1 <= X"0001"; |
|
83 | Operand1 <= X"0001"; | |
81 | Operand2 <= X"001"; |
|
84 | Operand2 <= X"001"; | |
82 | MAC_MUL_ADD <= ADD; |
|
85 | MAC_MUL_ADD <= ADD; | |
83 | wait for 50 ns; |
|
86 | wait for 50 ns; | |
84 | Operand1 <= X"0001"; |
|
87 | Operand1 <= X"0001"; | |
85 | Operand2 <= X"100"; |
|
88 | Operand2 <= X"100"; | |
86 | wait for 50 ns; |
|
89 | wait for 50 ns; | |
87 | Operand1 <= X"0001"; |
|
90 | Operand1 <= X"0001"; | |
88 | Operand2 <= X"001"; |
|
91 | Operand2 <= X"001"; | |
89 | MAC_MUL_ADD <= MULT; |
|
92 | MAC_MUL_ADD <= MULT; | |
90 | wait for 50 ns; |
|
93 | wait for 50 ns; | |
91 | Operand1 <= X"0002"; |
|
94 | Operand1 <= X"0002"; | |
92 | Operand2 <= X"002"; |
|
95 | Operand2 <= X"002"; | |
93 | wait for 50 ns; |
|
96 | wait for 50 ns; | |
94 | clrMAC <= '1'; |
|
97 | clrMAC <= '1'; | |
95 | wait for 50 ns; |
|
98 | wait for 50 ns; | |
96 | clrMAC <= '0'; |
|
99 | clrMAC <= '0'; | |
97 | Operand1 <= X"0001"; |
|
100 | Operand1 <= X"0001"; | |
98 | Operand2 <= X"003"; |
|
101 | Operand2 <= X"003"; | |
99 | MAC_MUL_ADD <= MAC; |
|
102 | MAC_MUL_ADD <= MAC; | |
100 | wait; |
|
103 | wait; | |
101 | end process; |
|
104 | end process; | |
102 | end ar_TestbenshMAC; |
|
105 | end ar_TestbenshMAC; | |
103 |
|
106 | |||
104 |
|
107 | |||
105 |
|
108 | |||
106 |
|
109 | |||
107 |
|
110 | |||
108 |
|
111 | |||
109 |
|
112 | |||
110 |
|
113 | |||
111 |
|
114 | |||
112 |
|
115 | |||
113 |
|
116 |
@@ -1,223 +1,225 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | ------------------------------------------------------------------------------ |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
20 | library ieee; |
|
22 | library ieee; | |
21 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
22 | library grlib; |
|
24 | library grlib; | |
23 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
24 | use grlib.stdlib.all; |
|
26 | use grlib.stdlib.all; | |
25 | use grlib.devices.all; |
|
27 | use grlib.devices.all; | |
26 | library lpp; |
|
28 | library lpp; | |
27 |
|
29 | |||
28 |
|
30 | |||
29 |
|
31 | |||
30 |
|
32 | |||
31 | package iir_filter is |
|
33 | package iir_filter is | |
32 |
|
34 | |||
33 |
|
35 | |||
34 | --===========================================================| |
|
36 | --===========================================================| | |
35 | --================A L U C O N T R O L======================| |
|
37 | --================A L U C O N T R O L======================| | |
36 | --===========================================================| |
|
38 | --===========================================================| | |
37 | constant IDLE : std_logic_vector(3 downto 0) := "0000"; |
|
39 | constant IDLE : std_logic_vector(3 downto 0) := "0000"; | |
38 | constant MAC_op : std_logic_vector(3 downto 0) := "0001"; |
|
40 | constant MAC_op : std_logic_vector(3 downto 0) := "0001"; | |
39 | constant MULT : std_logic_vector(3 downto 0) := "0010"; |
|
41 | constant MULT : std_logic_vector(3 downto 0) := "0010"; | |
40 | constant ADD : std_logic_vector(3 downto 0) := "0011"; |
|
42 | constant ADD : std_logic_vector(3 downto 0) := "0011"; | |
41 | constant clr_mac : std_logic_vector(3 downto 0) := "0100"; |
|
43 | constant clr_mac : std_logic_vector(3 downto 0) := "0100"; | |
42 |
|
44 | |||
43 | --____ |
|
45 | --____ | |
44 | --RAM | |
|
46 | --RAM | | |
45 | --____| |
|
47 | --____| | |
46 | constant use_RAM : integer := 1; |
|
48 | constant use_RAM : integer := 1; | |
47 | constant use_CEL : integer := 0; |
|
49 | constant use_CEL : integer := 0; | |
48 |
|
50 | |||
49 |
|
51 | |||
50 | --===========================================================| |
|
52 | --===========================================================| | |
51 | --=============C O E F S ====================================| |
|
53 | --=============C O E F S ====================================| | |
52 | --===========================================================| |
|
54 | --===========================================================| | |
53 | -- create a specific type of data for coefs to avoid errors | |
|
55 | -- create a specific type of data for coefs to avoid errors | | |
54 | --===========================================================| |
|
56 | --===========================================================| | |
55 |
|
57 | |||
56 | type scaleValT is array(natural range <>) of integer; |
|
58 | type scaleValT is array(natural range <>) of integer; | |
57 |
|
59 | |||
58 | type samplT is array(natural range <>,natural range <>) of std_logic; |
|
60 | type samplT is array(natural range <>,natural range <>) of std_logic; | |
59 |
|
61 | |||
60 | type in_IIR_CEL_reg is record |
|
62 | type in_IIR_CEL_reg is record | |
61 | config : std_logic_vector(31 downto 0); |
|
63 | config : std_logic_vector(31 downto 0); | |
62 | virgPos : std_logic_vector(4 downto 0); |
|
64 | virgPos : std_logic_vector(4 downto 0); | |
63 | end record; |
|
65 | end record; | |
64 |
|
66 | |||
65 | type out_IIR_CEL_reg is record |
|
67 | type out_IIR_CEL_reg is record | |
66 | config : std_logic_vector(31 downto 0); |
|
68 | config : std_logic_vector(31 downto 0); | |
67 | status : std_logic_vector(31 downto 0); |
|
69 | status : std_logic_vector(31 downto 0); | |
68 | end record; |
|
70 | end record; | |
69 |
|
71 | |||
70 |
|
72 | |||
71 |
|
73 | |||
72 | component APB_IIR_CEL is |
|
74 | component APB_IIR_CEL is | |
73 | generic ( |
|
75 | generic ( | |
74 | pindex : integer := 0; |
|
76 | pindex : integer := 0; | |
75 | paddr : integer := 0; |
|
77 | paddr : integer := 0; | |
76 | pmask : integer := 16#fff#; |
|
78 | pmask : integer := 16#fff#; | |
77 | pirq : integer := 0; |
|
79 | pirq : integer := 0; | |
78 | abits : integer := 8; |
|
80 | abits : integer := 8; | |
79 | Sample_SZ : integer := 16; |
|
81 | Sample_SZ : integer := 16; | |
80 | ChanelsCount : integer := 1; |
|
82 | ChanelsCount : integer := 1; | |
81 | Coef_SZ : integer := 9; |
|
83 | Coef_SZ : integer := 9; | |
82 | CoefCntPerCel: integer := 3; |
|
84 | CoefCntPerCel: integer := 3; | |
83 | Cels_count : integer := 5; |
|
85 | Cels_count : integer := 5; | |
84 | virgPos : integer := 3; |
|
86 | virgPos : integer := 3; | |
85 | Mem_use : integer := use_RAM |
|
87 | Mem_use : integer := use_RAM | |
86 | ); |
|
88 | ); | |
87 | port ( |
|
89 | port ( | |
88 | rst : in std_logic; |
|
90 | rst : in std_logic; | |
89 | clk : in std_logic; |
|
91 | clk : in std_logic; | |
90 | apbi : in apb_slv_in_type; |
|
92 | apbi : in apb_slv_in_type; | |
91 | apbo : out apb_slv_out_type; |
|
93 | apbo : out apb_slv_out_type; | |
92 | sample_clk : in std_logic; |
|
94 | sample_clk : in std_logic; | |
93 | sample_clk_out : out std_logic; |
|
95 | sample_clk_out : out std_logic; | |
94 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
96 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
95 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0) |
|
97 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0) | |
96 | ); |
|
98 | ); | |
97 | end component; |
|
99 | end component; | |
98 |
|
100 | |||
99 |
|
101 | |||
100 | --component FILTER is |
|
102 | --component FILTER is | |
101 | --generic(Smpl_SZ : integer := 16; |
|
103 | --generic(Smpl_SZ : integer := 16; | |
102 | -- ChanelsCNT : integer := 3 |
|
104 | -- ChanelsCNT : integer := 3 | |
103 | --); |
|
105 | --); | |
104 | --port( |
|
106 | --port( | |
105 | -- |
|
107 | -- | |
106 | -- reset : in std_logic; |
|
108 | -- reset : in std_logic; | |
107 | -- clk : in std_logic; |
|
109 | -- clk : in std_logic; | |
108 | -- sample_clk : in std_logic; |
|
110 | -- sample_clk : in std_logic; | |
109 | -- Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0); |
|
111 | -- Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0); | |
110 | -- Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0) |
|
112 | -- Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0) | |
111 | --); |
|
113 | --); | |
112 | --end component; |
|
114 | --end component; | |
113 |
|
115 | |||
114 |
|
116 | |||
115 |
|
117 | |||
116 | --component FilterCTRLR is |
|
118 | --component FilterCTRLR is | |
117 | --port( |
|
119 | --port( | |
118 | -- reset : in std_logic; |
|
120 | -- reset : in std_logic; | |
119 | -- clk : in std_logic; |
|
121 | -- clk : in std_logic; | |
120 | -- sample_clk : in std_logic; |
|
122 | -- sample_clk : in std_logic; | |
121 | -- ALU_Ctrl : out std_logic_vector(3 downto 0); |
|
123 | -- ALU_Ctrl : out std_logic_vector(3 downto 0); | |
122 | -- sample_in : in samplT; |
|
124 | -- sample_in : in samplT; | |
123 | -- coef : out std_logic_vector(Coef_SZ-1 downto 0); |
|
125 | -- coef : out std_logic_vector(Coef_SZ-1 downto 0); | |
124 | -- sample : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
126 | -- sample : out std_logic_vector(Smpl_SZ-1 downto 0) | |
125 | --); |
|
127 | --); | |
126 | --end component; |
|
128 | --end component; | |
127 |
|
129 | |||
128 |
|
130 | |||
129 | --component FILTER_RAM_CTRLR is |
|
131 | --component FILTER_RAM_CTRLR is | |
130 | --port( |
|
132 | --port( | |
131 | -- reset : in std_logic; |
|
133 | -- reset : in std_logic; | |
132 | -- clk : in std_logic; |
|
134 | -- clk : in std_logic; | |
133 | -- run : in std_logic; |
|
135 | -- run : in std_logic; | |
134 | -- GO_0 : in std_logic; |
|
136 | -- GO_0 : in std_logic; | |
135 | -- B_A : in std_logic; |
|
137 | -- B_A : in std_logic; | |
136 | -- writeForce : in std_logic; |
|
138 | -- writeForce : in std_logic; | |
137 | -- next_blk : in std_logic; |
|
139 | -- next_blk : in std_logic; | |
138 | -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); |
|
140 | -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); | |
139 | -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
141 | -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) | |
140 | --); |
|
142 | --); | |
141 | --end component; |
|
143 | --end component; | |
142 |
|
144 | |||
143 |
|
145 | |||
144 | component IIR_CEL_CTRLR is |
|
146 | component IIR_CEL_CTRLR is | |
145 | generic(Sample_SZ : integer := 16; |
|
147 | generic(Sample_SZ : integer := 16; | |
146 | ChanelsCount : integer := 1; |
|
148 | ChanelsCount : integer := 1; | |
147 | Coef_SZ : integer := 9; |
|
149 | Coef_SZ : integer := 9; | |
148 | CoefCntPerCel: integer := 3; |
|
150 | CoefCntPerCel: integer := 3; | |
149 | Cels_count : integer := 5; |
|
151 | Cels_count : integer := 5; | |
150 | Mem_use : integer := use_RAM |
|
152 | Mem_use : integer := use_RAM | |
151 | ); |
|
153 | ); | |
152 | port( |
|
154 | port( | |
153 | reset : in std_logic; |
|
155 | reset : in std_logic; | |
154 | clk : in std_logic; |
|
156 | clk : in std_logic; | |
155 | sample_clk : in std_logic; |
|
157 | sample_clk : in std_logic; | |
156 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
158 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
157 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
159 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
158 | virg_pos : in integer; |
|
160 | virg_pos : in integer; | |
159 | coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) |
|
161 | coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) | |
160 | ); |
|
162 | ); | |
161 | end component; |
|
163 | end component; | |
162 |
|
164 | |||
163 |
|
165 | |||
164 | component RAM is |
|
166 | component RAM is | |
165 | port( WD : in std_logic_vector(35 downto 0); RD : out |
|
167 | port( WD : in std_logic_vector(35 downto 0); RD : out | |
166 | std_logic_vector(35 downto 0);WEN, REN : in std_logic; |
|
168 | std_logic_vector(35 downto 0);WEN, REN : in std_logic; | |
167 | WADDR : in std_logic_vector(7 downto 0); RADDR : in |
|
169 | WADDR : in std_logic_vector(7 downto 0); RADDR : in | |
168 | std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic |
|
170 | std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic | |
169 | ) ; |
|
171 | ) ; | |
170 | end component; |
|
172 | end component; | |
171 |
|
173 | |||
172 |
|
174 | |||
173 | component RAM_CEL is |
|
175 | component RAM_CEL is | |
174 | port( WD : in std_logic_vector(35 downto 0); RD : out |
|
176 | port( WD : in std_logic_vector(35 downto 0); RD : out | |
175 | std_logic_vector(35 downto 0);WEN, REN : in std_logic; |
|
177 | std_logic_vector(35 downto 0);WEN, REN : in std_logic; | |
176 | WADDR : in std_logic_vector(7 downto 0); RADDR : in |
|
178 | WADDR : in std_logic_vector(7 downto 0); RADDR : in | |
177 | std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic |
|
179 | std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic | |
178 | ) ; |
|
180 | ) ; | |
179 | end component; |
|
181 | end component; | |
180 |
|
182 | |||
181 | component IIR_CEL_FILTER is |
|
183 | component IIR_CEL_FILTER is | |
182 | generic(Sample_SZ : integer := 16; |
|
184 | generic(Sample_SZ : integer := 16; | |
183 | ChanelsCount : integer := 1; |
|
185 | ChanelsCount : integer := 1; | |
184 | Coef_SZ : integer := 9; |
|
186 | Coef_SZ : integer := 9; | |
185 | CoefCntPerCel: integer := 3; |
|
187 | CoefCntPerCel: integer := 3; | |
186 | Cels_count : integer := 5; |
|
188 | Cels_count : integer := 5; | |
187 | Mem_use : integer := use_RAM); |
|
189 | Mem_use : integer := use_RAM); | |
188 | port( |
|
190 | port( | |
189 | reset : in std_logic; |
|
191 | reset : in std_logic; | |
190 | clk : in std_logic; |
|
192 | clk : in std_logic; | |
191 | sample_clk : in std_logic; |
|
193 | sample_clk : in std_logic; | |
192 | regs_in : in in_IIR_CEL_reg; |
|
194 | regs_in : in in_IIR_CEL_reg; | |
193 | regs_out : in out_IIR_CEL_reg; |
|
195 | regs_out : in out_IIR_CEL_reg; | |
194 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
196 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
195 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
197 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
196 | coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) |
|
198 | coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) | |
197 |
|
199 | |||
198 | ); |
|
200 | ); | |
199 | end component; |
|
201 | end component; | |
200 |
|
202 | |||
201 |
|
203 | |||
202 | component RAM_CTRLR2 is |
|
204 | component RAM_CTRLR2 is | |
203 | generic( |
|
205 | generic( | |
204 | Input_SZ_1 : integer := 16; |
|
206 | Input_SZ_1 : integer := 16; | |
205 | Mem_use : integer := use_RAM |
|
207 | Mem_use : integer := use_RAM | |
206 | ); |
|
208 | ); | |
207 | port( |
|
209 | port( | |
208 | reset : in std_logic; |
|
210 | reset : in std_logic; | |
209 | clk : in std_logic; |
|
211 | clk : in std_logic; | |
210 | WD_sel : in std_logic; |
|
212 | WD_sel : in std_logic; | |
211 | Read : in std_logic; |
|
213 | Read : in std_logic; | |
212 | WADDR_sel : in std_logic; |
|
214 | WADDR_sel : in std_logic; | |
213 | count : in std_logic; |
|
215 | count : in std_logic; | |
214 | SVG_ADDR : in std_logic; |
|
216 | SVG_ADDR : in std_logic; | |
215 | Write : in std_logic; |
|
217 | Write : in std_logic; | |
216 | GO_0 : in std_logic; |
|
218 | GO_0 : in std_logic; | |
217 | sample_in : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
219 | sample_in : in std_logic_vector(Input_SZ_1-1 downto 0); | |
218 | sample_out : out std_logic_vector(Input_SZ_1-1 downto 0) |
|
220 | sample_out : out std_logic_vector(Input_SZ_1-1 downto 0) | |
219 | ); |
|
221 | ); | |
220 | end component; |
|
222 | end component; | |
221 |
|
223 | |||
222 |
|
224 | |||
223 | end; |
|
225 | end; |
@@ -1,61 +1,64 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
24 |
|
27 | |||
25 |
|
28 | |||
26 |
|
29 | |||
27 | entity ADDRcntr is |
|
30 | entity ADDRcntr is | |
28 | port( |
|
31 | port( | |
29 | clk : in std_logic; |
|
32 | clk : in std_logic; | |
30 | reset : in std_logic; |
|
33 | reset : in std_logic; | |
31 | count : in std_logic; |
|
34 | count : in std_logic; | |
32 | clr : in std_logic; |
|
35 | clr : in std_logic; | |
33 | Q : out std_logic_vector(7 downto 0) |
|
36 | Q : out std_logic_vector(7 downto 0) | |
34 | ); |
|
37 | ); | |
35 | end entity; |
|
38 | end entity; | |
36 |
|
39 | |||
37 |
|
40 | |||
38 |
|
41 | |||
39 |
|
42 | |||
40 | architecture ar_ADDRcntr of ADDRcntr is |
|
43 | architecture ar_ADDRcntr of ADDRcntr is | |
41 |
|
44 | |||
42 | signal reg : std_logic_vector(7 downto 0); |
|
45 | signal reg : std_logic_vector(7 downto 0); | |
43 |
|
46 | |||
44 | begin |
|
47 | begin | |
45 |
|
48 | |||
46 | Q <= REG; |
|
49 | Q <= REG; | |
47 |
|
50 | |||
48 | process(clk,reset) |
|
51 | process(clk,reset) | |
49 | begin |
|
52 | begin | |
50 | if reset = '0' then |
|
53 | if reset = '0' then | |
51 | REG <= (others => '0'); |
|
54 | REG <= (others => '0'); | |
52 | elsif clk'event and clk ='1' then |
|
55 | elsif clk'event and clk ='1' then | |
53 | if clr = '1' then |
|
56 | if clr = '1' then | |
54 | REG <= (others => '0'); |
|
57 | REG <= (others => '0'); | |
55 | elsif count ='1' then |
|
58 | elsif count ='1' then | |
56 | REG <= std_logic_vector(unsigned(REG)+1); |
|
59 | REG <= std_logic_vector(unsigned(REG)+1); | |
57 | end if; |
|
60 | end if; | |
58 | end if; |
|
61 | end if; | |
59 | end process; |
|
62 | end process; | |
60 |
|
63 | |||
61 | end ar_ADDRcntr; |
|
64 | end ar_ADDRcntr; |
@@ -1,81 +1,81 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | ------------------------------------------------------------------------------ |
|
19 | -- Author : Alexis Jeandet | |
20 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
21 | ---------------------------------------------------------------------------- | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
25 | library lpp; |
|
25 | library lpp; | |
26 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
27 | --IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100 |
|
27 | --IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100 | |
28 | --NOT =0101 AND =0110 OR =0111 XOR =1000 |
|
28 | --NOT =0101 AND =0110 OR =0111 XOR =1000 | |
29 | --SHIFTleft =1001 SHIFTright =1010 |
|
29 | --SHIFTleft =1001 SHIFTright =1010 | |
30 |
|
30 | |||
31 | entity ALU is |
|
31 | entity ALU is | |
32 | generic( |
|
32 | generic( | |
33 | Arith_en : integer := 1; |
|
33 | Arith_en : integer := 1; | |
34 | Logic_en : integer := 1; |
|
34 | Logic_en : integer := 1; | |
35 | Input_SZ_1 : integer := 16; |
|
35 | Input_SZ_1 : integer := 16; | |
36 | Input_SZ_2 : integer := 9 |
|
36 | Input_SZ_2 : integer := 9 | |
37 |
|
37 | |||
38 | ); |
|
38 | ); | |
39 | port( |
|
39 | port( | |
40 | clk : in std_logic; |
|
40 | clk : in std_logic; | |
41 | reset : in std_logic; |
|
41 | reset : in std_logic; | |
42 | ctrl : in std_logic_vector(3 downto 0); |
|
42 | ctrl : in std_logic_vector(3 downto 0); | |
43 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
43 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); | |
44 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
44 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); | |
45 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) |
|
45 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) | |
46 | ); |
|
46 | ); | |
47 | end entity; |
|
47 | end entity; | |
48 |
|
48 | |||
49 |
|
49 | |||
50 |
|
50 | |||
51 | architecture ar_ALU of ALU is |
|
51 | architecture ar_ALU of ALU is | |
52 |
|
52 | |||
53 |
|
53 | |||
54 |
|
54 | |||
55 | signal clr_MAC : std_logic:='1'; |
|
55 | signal clr_MAC : std_logic:='1'; | |
56 |
|
56 | |||
57 |
|
57 | |||
58 | begin |
|
58 | begin | |
59 |
|
59 | |||
60 | clr_MAC <= '1' when ctrl = "0100" else '0'; |
|
60 | clr_MAC <= '1' when ctrl = "0100" else '0'; | |
61 |
|
61 | |||
62 |
|
62 | |||
63 | arith : if Arith_en = 1 generate |
|
63 | arith : if Arith_en = 1 generate | |
64 | MACinst : MAC |
|
64 | MACinst : MAC | |
65 | generic map(Input_SZ_1,Input_SZ_2) |
|
65 | generic map(Input_SZ_1,Input_SZ_2) | |
66 | port map(clk,reset,clr_MAC,ctrl(1 downto 0),OP1,OP2,RES); |
|
66 | port map(clk,reset,clr_MAC,ctrl(1 downto 0),OP1,OP2,RES); | |
67 | end generate; |
|
67 | end generate; | |
68 |
|
68 | |||
69 | end architecture; |
|
69 | end architecture; | |
70 |
|
70 | |||
71 |
|
71 | |||
72 |
|
72 | |||
73 |
|
73 | |||
74 |
|
74 | |||
75 |
|
75 | |||
76 |
|
76 | |||
77 |
|
77 | |||
78 |
|
78 | |||
79 |
|
79 | |||
80 |
|
80 | |||
81 |
|
81 |
@@ -1,69 +1,72 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
24 |
|
27 | |||
25 |
|
28 | |||
26 |
|
29 | |||
27 | entity Adder is |
|
30 | entity Adder is | |
28 | generic( |
|
31 | generic( | |
29 | Input_SZ_A : integer := 16; |
|
32 | Input_SZ_A : integer := 16; | |
30 | Input_SZ_B : integer := 16 |
|
33 | Input_SZ_B : integer := 16 | |
31 |
|
34 | |||
32 | ); |
|
35 | ); | |
33 | port( |
|
36 | port( | |
34 | clk : in std_logic; |
|
37 | clk : in std_logic; | |
35 | reset : in std_logic; |
|
38 | reset : in std_logic; | |
36 | clr : in std_logic; |
|
39 | clr : in std_logic; | |
37 | add : in std_logic; |
|
40 | add : in std_logic; | |
38 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
41 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
39 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
42 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
40 | RES : out std_logic_vector(Input_SZ_A-1 downto 0) |
|
43 | RES : out std_logic_vector(Input_SZ_A-1 downto 0) | |
41 | ); |
|
44 | ); | |
42 | end entity; |
|
45 | end entity; | |
43 |
|
46 | |||
44 |
|
47 | |||
45 |
|
48 | |||
46 |
|
49 | |||
47 | architecture ar_Adder of Adder is |
|
50 | architecture ar_Adder of Adder is | |
48 |
|
51 | |||
49 | signal REG : std_logic_vector(Input_SZ_A-1 downto 0); |
|
52 | signal REG : std_logic_vector(Input_SZ_A-1 downto 0); | |
50 | signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0); |
|
53 | signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0); | |
51 |
|
54 | |||
52 | begin |
|
55 | begin | |
53 |
|
56 | |||
54 | RES <= REG; |
|
57 | RES <= REG; | |
55 | RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A)); |
|
58 | RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A)); | |
56 |
|
59 | |||
57 | process(clk,reset) |
|
60 | process(clk,reset) | |
58 | begin |
|
61 | begin | |
59 | if reset = '0' then |
|
62 | if reset = '0' then | |
60 | REG <= (others => '0'); |
|
63 | REG <= (others => '0'); | |
61 | elsif clk'event and clk ='1' then |
|
64 | elsif clk'event and clk ='1' then | |
62 | if clr = '1' then |
|
65 | if clr = '1' then | |
63 | REG <= (others => '0'); |
|
66 | REG <= (others => '0'); | |
64 | elsif add = '1' then |
|
67 | elsif add = '1' then | |
65 | REG <= RESADD; |
|
68 | REG <= RESADD; | |
66 | end if; |
|
69 | end if; | |
67 | end if; |
|
70 | end if; | |
68 | end process; |
|
71 | end process; | |
69 | end ar_Adder; |
|
72 | end ar_Adder; |
@@ -1,64 +1,67 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 |
|
24 | |||
22 |
|
25 | |||
23 | entity Clk_divider is |
|
26 | entity Clk_divider is | |
24 | generic(OSC_freqHz : integer := 50000000; |
|
27 | generic(OSC_freqHz : integer := 50000000; | |
25 | TargetFreq_Hz : integer := 50000); |
|
28 | TargetFreq_Hz : integer := 50000); | |
26 | Port ( clk : in STD_LOGIC; |
|
29 | Port ( clk : in STD_LOGIC; | |
27 | reset : in STD_LOGIC; |
|
30 | reset : in STD_LOGIC; | |
28 | clk_divided : out STD_LOGIC); |
|
31 | clk_divided : out STD_LOGIC); | |
29 | end Clk_divider; |
|
32 | end Clk_divider; | |
30 |
|
33 | |||
31 | architecture ar_Clk_divider of Clk_divider is |
|
34 | architecture ar_Clk_divider of Clk_divider is | |
32 |
|
35 | |||
33 | Constant clk_TRIGER : integer := (OSC_freqHz/(2*TargetFreq_Hz))+1; |
|
36 | Constant clk_TRIGER : integer := (OSC_freqHz/(2*TargetFreq_Hz))+1; | |
34 |
|
37 | |||
35 |
|
38 | |||
36 | signal cpt1 : integer; |
|
39 | signal cpt1 : integer; | |
37 |
|
40 | |||
38 | signal clk_int : std_logic := '0'; |
|
41 | signal clk_int : std_logic := '0'; | |
39 |
|
42 | |||
40 |
|
43 | |||
41 | begin |
|
44 | begin | |
42 |
|
45 | |||
43 | clk_divided <= clk_int; |
|
46 | clk_divided <= clk_int; | |
44 |
|
47 | |||
45 |
|
48 | |||
46 | process(reset,clk) |
|
49 | process(reset,clk) | |
47 | begin |
|
50 | begin | |
48 | if reset = '0' then |
|
51 | if reset = '0' then | |
49 | cpt1 <= 0; |
|
52 | cpt1 <= 0; | |
50 | clk_int <= '0'; |
|
53 | clk_int <= '0'; | |
51 | elsif clk'event and clk = '1' then |
|
54 | elsif clk'event and clk = '1' then | |
52 | if cpt1 = clk_TRIGER then |
|
55 | if cpt1 = clk_TRIGER then | |
53 | clk_int <= not clk_int; |
|
56 | clk_int <= not clk_int; | |
54 | cpt1 <= 0; |
|
57 | cpt1 <= 0; | |
55 | else |
|
58 | else | |
56 | cpt1 <= cpt1 + 1; |
|
59 | cpt1 <= cpt1 + 1; | |
57 | end if; |
|
60 | end if; | |
58 | end if; |
|
61 | end if; | |
59 | end process; |
|
62 | end process; | |
60 |
|
63 | |||
61 |
|
64 | |||
62 | end ar_Clk_divider; |
|
65 | end ar_Clk_divider; | |
63 |
|
66 | |||
64 |
|
67 |
@@ -1,262 +1,278 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
6 | library IEEE; |
|
22 | library IEEE; | |
7 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
8 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
9 | library lpp; |
|
25 | library lpp; | |
10 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
11 | --TODO |
|
27 | --TODO | |
12 | --terminer le testbensh puis changer le resize dans les instanciations |
|
28 | --terminer le testbensh puis changer le resize dans les instanciations | |
13 | --par un resize sur un vecteur en combi |
|
29 | --par un resize sur un vecteur en combi | |
14 |
|
30 | |||
15 |
|
31 | |||
16 |
|
32 | |||
17 |
|
33 | |||
18 |
|
34 | |||
19 | entity MAC is |
|
35 | entity MAC is | |
20 | generic( |
|
36 | generic( | |
21 | Input_SZ_A : integer := 8; |
|
37 | Input_SZ_A : integer := 8; | |
22 | Input_SZ_B : integer := 8 |
|
38 | Input_SZ_B : integer := 8 | |
23 |
|
39 | |||
24 | ); |
|
40 | ); | |
25 | port( |
|
41 | port( | |
26 | clk : in std_logic; |
|
42 | clk : in std_logic; | |
27 | reset : in std_logic; |
|
43 | reset : in std_logic; | |
28 | clr_MAC : in std_logic; |
|
44 | clr_MAC : in std_logic; | |
29 | MAC_MUL_ADD : in std_logic_vector(1 downto 0); |
|
45 | MAC_MUL_ADD : in std_logic_vector(1 downto 0); | |
30 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
46 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
31 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
47 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
32 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) |
|
48 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
33 | ); |
|
49 | ); | |
34 | end MAC; |
|
50 | end MAC; | |
35 |
|
51 | |||
36 |
|
52 | |||
37 |
|
53 | |||
38 |
|
54 | |||
39 | architecture ar_MAC of MAC is |
|
55 | architecture ar_MAC of MAC is | |
40 |
|
56 | |||
41 |
|
57 | |||
42 |
|
58 | |||
43 |
|
59 | |||
44 |
|
60 | |||
45 | signal add,mult : std_logic; |
|
61 | signal add,mult : std_logic; | |
46 | signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); |
|
62 | signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
47 |
|
63 | |||
48 | signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); |
|
64 | signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
49 | signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); |
|
65 | signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
50 | signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); |
|
66 | signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
51 |
|
67 | |||
52 |
|
68 | |||
53 | signal MACMUXsel : std_logic; |
|
69 | signal MACMUXsel : std_logic; | |
54 | signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); |
|
70 | signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
55 | signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); |
|
71 | signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
56 |
|
72 | |||
57 |
|
73 | |||
58 |
|
74 | |||
59 | signal MACMUX2sel : std_logic; |
|
75 | signal MACMUX2sel : std_logic; | |
60 |
|
76 | |||
61 | signal add_D : std_logic; |
|
77 | signal add_D : std_logic; | |
62 | signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0); |
|
78 | signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0); | |
63 | signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0); |
|
79 | signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0); | |
64 | signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); |
|
80 | signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
65 | signal MACMUXsel_D : std_logic; |
|
81 | signal MACMUXsel_D : std_logic; | |
66 | signal MACMUX2sel_D : std_logic; |
|
82 | signal MACMUX2sel_D : std_logic; | |
67 | signal MACMUX2sel_D_D : std_logic; |
|
83 | signal MACMUX2sel_D_D : std_logic; | |
68 | signal clr_MAC_D : std_logic; |
|
84 | signal clr_MAC_D : std_logic; | |
69 | signal clr_MAC_D_D : std_logic; |
|
85 | signal clr_MAC_D_D : std_logic; | |
70 |
|
86 | |||
71 |
|
87 | |||
72 |
|
88 | |||
73 |
|
89 | |||
74 |
|
90 | |||
75 | begin |
|
91 | begin | |
76 |
|
92 | |||
77 |
|
93 | |||
78 |
|
94 | |||
79 |
|
95 | |||
80 | --============================================================== |
|
96 | --============================================================== | |
81 | --=============M A C C O N T R O L E R========================= |
|
97 | --=============M A C C O N T R O L E R========================= | |
82 | --============================================================== |
|
98 | --============================================================== | |
83 | MAC_CONTROLER1 : MAC_CONTROLER |
|
99 | MAC_CONTROLER1 : MAC_CONTROLER | |
84 | port map( |
|
100 | port map( | |
85 | ctrl => MAC_MUL_ADD, |
|
101 | ctrl => MAC_MUL_ADD, | |
86 | MULT => mult, |
|
102 | MULT => mult, | |
87 | ADD => add, |
|
103 | ADD => add, | |
88 | MACMUX_sel => MACMUXsel, |
|
104 | MACMUX_sel => MACMUXsel, | |
89 | MACMUX2_sel => MACMUX2sel |
|
105 | MACMUX2_sel => MACMUX2sel | |
90 |
|
106 | |||
91 | ); |
|
107 | ); | |
92 | --============================================================== |
|
108 | --============================================================== | |
93 |
|
109 | |||
94 |
|
110 | |||
95 |
|
111 | |||
96 |
|
112 | |||
97 | --============================================================== |
|
113 | --============================================================== | |
98 | --=============M U L T I P L I E R============================== |
|
114 | --=============M U L T I P L I E R============================== | |
99 | --============================================================== |
|
115 | --============================================================== | |
100 | Multiplieri_nst : Multiplier |
|
116 | Multiplieri_nst : Multiplier | |
101 | generic map( |
|
117 | generic map( | |
102 | Input_SZ_A => Input_SZ_A, |
|
118 | Input_SZ_A => Input_SZ_A, | |
103 | Input_SZ_B => Input_SZ_B |
|
119 | Input_SZ_B => Input_SZ_B | |
104 | ) |
|
120 | ) | |
105 | port map( |
|
121 | port map( | |
106 | clk => clk, |
|
122 | clk => clk, | |
107 | reset => reset, |
|
123 | reset => reset, | |
108 | mult => mult, |
|
124 | mult => mult, | |
109 | OP1 => OP1, |
|
125 | OP1 => OP1, | |
110 | OP2 => OP2, |
|
126 | OP2 => OP2, | |
111 | RES => MULTout |
|
127 | RES => MULTout | |
112 | ); |
|
128 | ); | |
113 |
|
129 | |||
114 | --============================================================== |
|
130 | --============================================================== | |
115 |
|
131 | |||
116 |
|
132 | |||
117 |
|
133 | |||
118 |
|
134 | |||
119 | --============================================================== |
|
135 | --============================================================== | |
120 | --======================A D D E R ============================== |
|
136 | --======================A D D E R ============================== | |
121 | --============================================================== |
|
137 | --============================================================== | |
122 | adder_inst : Adder |
|
138 | adder_inst : Adder | |
123 | generic map( |
|
139 | generic map( | |
124 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
140 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
125 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
141 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
126 | ) |
|
142 | ) | |
127 | port map( |
|
143 | port map( | |
128 | clk => clk, |
|
144 | clk => clk, | |
129 | reset => reset, |
|
145 | reset => reset, | |
130 | clr => clr_MAC_D, |
|
146 | clr => clr_MAC_D, | |
131 | add => add_D, |
|
147 | add => add_D, | |
132 | OP1 => ADDERinA, |
|
148 | OP1 => ADDERinA, | |
133 | OP2 => ADDERinB, |
|
149 | OP2 => ADDERinB, | |
134 | RES => ADDERout |
|
150 | RES => ADDERout | |
135 | ); |
|
151 | ); | |
136 |
|
152 | |||
137 | --============================================================== |
|
153 | --============================================================== | |
138 |
|
154 | |||
139 |
|
155 | |||
140 | clr_MACREG1 : MAC_REG |
|
156 | clr_MACREG1 : MAC_REG | |
141 | generic map(size => 1) |
|
157 | generic map(size => 1) | |
142 | port map( |
|
158 | port map( | |
143 | reset => reset, |
|
159 | reset => reset, | |
144 | clk => clk, |
|
160 | clk => clk, | |
145 | D(0) => clr_MAC, |
|
161 | D(0) => clr_MAC, | |
146 | Q(0) => clr_MAC_D |
|
162 | Q(0) => clr_MAC_D | |
147 | ); |
|
163 | ); | |
148 |
|
164 | |||
149 | clr_MACREG2 : MAC_REG |
|
165 | clr_MACREG2 : MAC_REG | |
150 | generic map(size => 1) |
|
166 | generic map(size => 1) | |
151 | port map( |
|
167 | port map( | |
152 | reset => reset, |
|
168 | reset => reset, | |
153 | clk => clk, |
|
169 | clk => clk, | |
154 | D(0) => clr_MAC_D, |
|
170 | D(0) => clr_MAC_D, | |
155 | Q(0) => clr_MAC_D_D |
|
171 | Q(0) => clr_MAC_D_D | |
156 | ); |
|
172 | ); | |
157 |
|
173 | |||
158 | addREG : MAC_REG |
|
174 | addREG : MAC_REG | |
159 | generic map(size => 1) |
|
175 | generic map(size => 1) | |
160 | port map( |
|
176 | port map( | |
161 | reset => reset, |
|
177 | reset => reset, | |
162 | clk => clk, |
|
178 | clk => clk, | |
163 | D(0) => add, |
|
179 | D(0) => add, | |
164 | Q(0) => add_D |
|
180 | Q(0) => add_D | |
165 | ); |
|
181 | ); | |
166 |
|
182 | |||
167 | OP1REG : MAC_REG |
|
183 | OP1REG : MAC_REG | |
168 | generic map(size => Input_SZ_A) |
|
184 | generic map(size => Input_SZ_A) | |
169 | port map( |
|
185 | port map( | |
170 | reset => reset, |
|
186 | reset => reset, | |
171 | clk => clk, |
|
187 | clk => clk, | |
172 | D => OP1, |
|
188 | D => OP1, | |
173 | Q => OP1_D |
|
189 | Q => OP1_D | |
174 | ); |
|
190 | ); | |
175 |
|
191 | |||
176 |
|
192 | |||
177 | OP2REG : MAC_REG |
|
193 | OP2REG : MAC_REG | |
178 | generic map(size => Input_SZ_B) |
|
194 | generic map(size => Input_SZ_B) | |
179 | port map( |
|
195 | port map( | |
180 | reset => reset, |
|
196 | reset => reset, | |
181 | clk => clk, |
|
197 | clk => clk, | |
182 | D => OP2, |
|
198 | D => OP2, | |
183 | Q => OP2_D |
|
199 | Q => OP2_D | |
184 | ); |
|
200 | ); | |
185 |
|
201 | |||
186 |
|
202 | |||
187 | MULToutREG : MAC_REG |
|
203 | MULToutREG : MAC_REG | |
188 | generic map(size => Input_SZ_A+Input_SZ_B) |
|
204 | generic map(size => Input_SZ_A+Input_SZ_B) | |
189 | port map( |
|
205 | port map( | |
190 | reset => reset, |
|
206 | reset => reset, | |
191 | clk => clk, |
|
207 | clk => clk, | |
192 | D => MULTout, |
|
208 | D => MULTout, | |
193 | Q => MULTout_D |
|
209 | Q => MULTout_D | |
194 | ); |
|
210 | ); | |
195 |
|
211 | |||
196 |
|
212 | |||
197 | MACMUXselREG : MAC_REG |
|
213 | MACMUXselREG : MAC_REG | |
198 | generic map(size => 1) |
|
214 | generic map(size => 1) | |
199 | port map( |
|
215 | port map( | |
200 | reset => reset, |
|
216 | reset => reset, | |
201 | clk => clk, |
|
217 | clk => clk, | |
202 | D(0) => MACMUXsel, |
|
218 | D(0) => MACMUXsel, | |
203 | Q(0) => MACMUXsel_D |
|
219 | Q(0) => MACMUXsel_D | |
204 | ); |
|
220 | ); | |
205 |
|
221 | |||
206 | MACMUX2selREG : MAC_REG |
|
222 | MACMUX2selREG : MAC_REG | |
207 | generic map(size => 1) |
|
223 | generic map(size => 1) | |
208 | port map( |
|
224 | port map( | |
209 | reset => reset, |
|
225 | reset => reset, | |
210 | clk => clk, |
|
226 | clk => clk, | |
211 | D(0) => MACMUX2sel, |
|
227 | D(0) => MACMUX2sel, | |
212 | Q(0) => MACMUX2sel_D |
|
228 | Q(0) => MACMUX2sel_D | |
213 | ); |
|
229 | ); | |
214 |
|
230 | |||
215 | MACMUX2selREG2 : MAC_REG |
|
231 | MACMUX2selREG2 : MAC_REG | |
216 | generic map(size => 1) |
|
232 | generic map(size => 1) | |
217 | port map( |
|
233 | port map( | |
218 | reset => reset, |
|
234 | reset => reset, | |
219 | clk => clk, |
|
235 | clk => clk, | |
220 | D(0) => MACMUX2sel_D, |
|
236 | D(0) => MACMUX2sel_D, | |
221 | Q(0) => MACMUX2sel_D_D |
|
237 | Q(0) => MACMUX2sel_D_D | |
222 | ); |
|
238 | ); | |
223 |
|
239 | |||
224 | --============================================================== |
|
240 | --============================================================== | |
225 | --======================M A C M U X =========================== |
|
241 | --======================M A C M U X =========================== | |
226 | --============================================================== |
|
242 | --============================================================== | |
227 | MACMUX_inst : MAC_MUX |
|
243 | MACMUX_inst : MAC_MUX | |
228 | generic map( |
|
244 | generic map( | |
229 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
245 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
230 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
246 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
231 |
|
247 | |||
232 | ) |
|
248 | ) | |
233 | port map( |
|
249 | port map( | |
234 | sel => MACMUXsel_D, |
|
250 | sel => MACMUXsel_D, | |
235 | INA1 => ADDERout, |
|
251 | INA1 => ADDERout, | |
236 | INA2 => OP2_D_Resz, |
|
252 | INA2 => OP2_D_Resz, | |
237 | INB1 => MULTout, |
|
253 | INB1 => MULTout, | |
238 | INB2 => OP1_D_Resz, |
|
254 | INB2 => OP1_D_Resz, | |
239 | OUTA => ADDERinA, |
|
255 | OUTA => ADDERinA, | |
240 | OUTB => ADDERinB |
|
256 | OUTB => ADDERinB | |
241 | ); |
|
257 | ); | |
242 | OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B)); |
|
258 | OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B)); | |
243 | OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B)); |
|
259 | OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B)); | |
244 | --============================================================== |
|
260 | --============================================================== | |
245 |
|
261 | |||
246 |
|
262 | |||
247 | --============================================================== |
|
263 | --============================================================== | |
248 | --======================M A C M U X2 ========================== |
|
264 | --======================M A C M U X2 ========================== | |
249 | --============================================================== |
|
265 | --============================================================== | |
250 | MAC_MUX2_inst : MAC_MUX2 |
|
266 | MAC_MUX2_inst : MAC_MUX2 | |
251 | generic map(Input_SZ => Input_SZ_A+Input_SZ_B) |
|
267 | generic map(Input_SZ => Input_SZ_A+Input_SZ_B) | |
252 | port map( |
|
268 | port map( | |
253 | sel => MACMUX2sel_D_D, |
|
269 | sel => MACMUX2sel_D_D, | |
254 | RES2 => MULTout_D, |
|
270 | RES2 => MULTout_D, | |
255 | RES1 => ADDERout, |
|
271 | RES1 => ADDERout, | |
256 | RES => RES |
|
272 | RES => RES | |
257 | ); |
|
273 | ); | |
258 |
|
274 | |||
259 |
|
275 | |||
260 | --============================================================== |
|
276 | --============================================================== | |
261 |
|
277 | |||
262 | end ar_MAC; |
|
278 | end ar_MAC; |
@@ -1,67 +1,69 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | ------------------------------------------------------------------------------ |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
20 | library IEEE; |
|
22 | library IEEE; | |
21 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
22 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
23 | library lpp; |
|
25 | library lpp; | |
24 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
25 |
|
27 | |||
26 |
|
28 | |||
27 | --IDLE =00 MAC =01 MULT =10 ADD =11 |
|
29 | --IDLE =00 MAC =01 MULT =10 ADD =11 | |
28 |
|
30 | |||
29 |
|
31 | |||
30 | entity MAC_CONTROLER is |
|
32 | entity MAC_CONTROLER is | |
31 | port( |
|
33 | port( | |
32 | ctrl : in std_logic_vector(1 downto 0); |
|
34 | ctrl : in std_logic_vector(1 downto 0); | |
33 | MULT : out std_logic; |
|
35 | MULT : out std_logic; | |
34 | ADD : out std_logic; |
|
36 | ADD : out std_logic; | |
35 | MACMUX_sel : out std_logic; |
|
37 | MACMUX_sel : out std_logic; | |
36 | MACMUX2_sel : out std_logic |
|
38 | MACMUX2_sel : out std_logic | |
37 |
|
39 | |||
38 | ); |
|
40 | ); | |
39 | end MAC_CONTROLER; |
|
41 | end MAC_CONTROLER; | |
40 |
|
42 | |||
41 |
|
43 | |||
42 |
|
44 | |||
43 |
|
45 | |||
44 |
|
46 | |||
45 | architecture ar_MAC_CONTROLER of MAC_CONTROLER is |
|
47 | architecture ar_MAC_CONTROLER of MAC_CONTROLER is | |
46 |
|
48 | |||
47 | begin |
|
49 | begin | |
48 |
|
50 | |||
49 |
|
51 | |||
50 |
|
52 | |||
51 | MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1'; |
|
53 | MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1'; | |
52 | ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1'; |
|
54 | ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1'; | |
53 | MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1'; |
|
55 | MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1'; | |
54 | MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01"or ctrl = "11") else '1'; |
|
56 | MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01"or ctrl = "11") else '1'; | |
55 |
|
57 | |||
56 |
|
58 | |||
57 | end ar_MAC_CONTROLER; |
|
59 | end ar_MAC_CONTROLER; | |
58 |
|
60 | |||
59 |
|
61 | |||
60 |
|
62 | |||
61 |
|
63 | |||
62 |
|
64 | |||
63 |
|
65 | |||
64 |
|
66 | |||
65 |
|
67 | |||
66 |
|
68 | |||
67 |
|
69 |
@@ -1,54 +1,57 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
24 |
|
27 | |||
25 |
|
28 | |||
26 |
|
29 | |||
27 | entity MAC_MUX is |
|
30 | entity MAC_MUX is | |
28 | generic( |
|
31 | generic( | |
29 | Input_SZ_A : integer := 16; |
|
32 | Input_SZ_A : integer := 16; | |
30 | Input_SZ_B : integer := 16 |
|
33 | Input_SZ_B : integer := 16 | |
31 |
|
34 | |||
32 | ); |
|
35 | ); | |
33 | port( |
|
36 | port( | |
34 | sel : in std_logic; |
|
37 | sel : in std_logic; | |
35 | INA1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
38 | INA1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
36 | INA2 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
39 | INA2 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
37 | INB1 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
40 | INB1 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
38 | INB2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
41 | INB2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
39 | OUTA : out std_logic_vector(Input_SZ_A-1 downto 0); |
|
42 | OUTA : out std_logic_vector(Input_SZ_A-1 downto 0); | |
40 | OUTB : out std_logic_vector(Input_SZ_B-1 downto 0) |
|
43 | OUTB : out std_logic_vector(Input_SZ_B-1 downto 0) | |
41 | ); |
|
44 | ); | |
42 | end entity; |
|
45 | end entity; | |
43 |
|
46 | |||
44 |
|
47 | |||
45 |
|
48 | |||
46 |
|
49 | |||
47 | architecture ar_MAC_MUX of MAC_MUX is |
|
50 | architecture ar_MAC_MUX of MAC_MUX is | |
48 |
|
51 | |||
49 | begin |
|
52 | begin | |
50 |
|
53 | |||
51 | OUTA <= INA1 when sel = '0' else INA2; |
|
54 | OUTA <= INA1 when sel = '0' else INA2; | |
52 | OUTB <= INB1 when sel = '0' else INB2; |
|
55 | OUTB <= INB1 when sel = '0' else INB2; | |
53 |
|
56 | |||
54 | end ar_MAC_MUX; |
|
57 | end ar_MAC_MUX; |
@@ -1,46 +1,49 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
24 |
|
27 | |||
25 |
|
28 | |||
26 |
|
29 | |||
27 | entity MAC_MUX2 is |
|
30 | entity MAC_MUX2 is | |
28 | generic(Input_SZ : integer := 16); |
|
31 | generic(Input_SZ : integer := 16); | |
29 | port( |
|
32 | port( | |
30 | sel : in std_logic; |
|
33 | sel : in std_logic; | |
31 | RES1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
34 | RES1 : in std_logic_vector(Input_SZ-1 downto 0); | |
32 | RES2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
35 | RES2 : in std_logic_vector(Input_SZ-1 downto 0); | |
33 | RES : out std_logic_vector(Input_SZ-1 downto 0) |
|
36 | RES : out std_logic_vector(Input_SZ-1 downto 0) | |
34 | ); |
|
37 | ); | |
35 | end entity; |
|
38 | end entity; | |
36 |
|
39 | |||
37 |
|
40 | |||
38 |
|
41 | |||
39 |
|
42 | |||
40 | architecture ar_MAC_MUX2 of MAC_MUX2 is |
|
43 | architecture ar_MAC_MUX2 of MAC_MUX2 is | |
41 |
|
44 | |||
42 | begin |
|
45 | begin | |
43 |
|
46 | |||
44 | RES <= RES1 when sel = '0' else RES2; |
|
47 | RES <= RES1 when sel = '0' else RES2; | |
45 |
|
48 | |||
46 | end ar_MAC_MUX2; |
|
49 | end ar_MAC_MUX2; |
@@ -1,59 +1,62 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
24 |
|
27 | |||
25 |
|
28 | |||
26 |
|
29 | |||
27 | entity MAC_REG is |
|
30 | entity MAC_REG is | |
28 | generic(size : integer := 16); |
|
31 | generic(size : integer := 16); | |
29 | port( |
|
32 | port( | |
30 | reset : in std_logic; |
|
33 | reset : in std_logic; | |
31 | clk : in std_logic; |
|
34 | clk : in std_logic; | |
32 | D : in std_logic_vector(size-1 downto 0); |
|
35 | D : in std_logic_vector(size-1 downto 0); | |
33 | Q : out std_logic_vector(size-1 downto 0) |
|
36 | Q : out std_logic_vector(size-1 downto 0) | |
34 | ); |
|
37 | ); | |
35 | end entity; |
|
38 | end entity; | |
36 |
|
39 | |||
37 |
|
40 | |||
38 |
|
41 | |||
39 | architecture ar_MAC_REG of MAC_REG is |
|
42 | architecture ar_MAC_REG of MAC_REG is | |
40 | begin |
|
43 | begin | |
41 | process(clk,reset) |
|
44 | process(clk,reset) | |
42 | begin |
|
45 | begin | |
43 | if reset = '0' then |
|
46 | if reset = '0' then | |
44 | Q <= (others => '0'); |
|
47 | Q <= (others => '0'); | |
45 | elsif clk'event and clk ='1' then |
|
48 | elsif clk'event and clk ='1' then | |
46 | Q <= D; |
|
49 | Q <= D; | |
47 | end if; |
|
50 | end if; | |
48 | end process; |
|
51 | end process; | |
49 | end ar_MAC_REG; |
|
52 | end ar_MAC_REG; | |
50 |
|
53 | |||
51 |
|
54 | |||
52 |
|
55 | |||
53 |
|
56 | |||
54 |
|
57 | |||
55 |
|
58 | |||
56 |
|
59 | |||
57 |
|
60 | |||
58 |
|
61 | |||
59 |
|
62 |
@@ -1,46 +1,49 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
24 |
|
27 | |||
25 |
|
28 | |||
26 |
|
29 | |||
27 | entity MUX2 is |
|
30 | entity MUX2 is | |
28 | generic(Input_SZ : integer := 16); |
|
31 | generic(Input_SZ : integer := 16); | |
29 | port( |
|
32 | port( | |
30 | sel : in std_logic; |
|
33 | sel : in std_logic; | |
31 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
34 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); | |
32 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
35 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); | |
33 | RES : out std_logic_vector(Input_SZ-1 downto 0) |
|
36 | RES : out std_logic_vector(Input_SZ-1 downto 0) | |
34 | ); |
|
37 | ); | |
35 | end entity; |
|
38 | end entity; | |
36 |
|
39 | |||
37 |
|
40 | |||
38 |
|
41 | |||
39 |
|
42 | |||
40 | architecture ar_MUX2 of MUX2 is |
|
43 | architecture ar_MUX2 of MUX2 is | |
41 |
|
44 | |||
42 | begin |
|
45 | begin | |
43 |
|
46 | |||
44 | RES <= IN1 when sel = '0' else IN2; |
|
47 | RES <= IN1 when sel = '0' else IN2; | |
45 |
|
48 | |||
46 | end ar_MUX2; |
|
49 | end ar_MUX2; |
@@ -1,77 +1,80 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 |
|
25 | |||
23 | library lpp; |
|
26 | library lpp; | |
24 | use lpp.general_purpose.all; |
|
27 | use lpp.general_purpose.all; | |
25 |
|
28 | |||
26 |
|
29 | |||
27 |
|
30 | |||
28 | entity Multiplier is |
|
31 | entity Multiplier is | |
29 | generic( |
|
32 | generic( | |
30 | Input_SZ_A : integer := 16; |
|
33 | Input_SZ_A : integer := 16; | |
31 | Input_SZ_B : integer := 16 |
|
34 | Input_SZ_B : integer := 16 | |
32 |
|
35 | |||
33 | ); |
|
36 | ); | |
34 | port( |
|
37 | port( | |
35 | clk : in std_logic; |
|
38 | clk : in std_logic; | |
36 | reset : in std_logic; |
|
39 | reset : in std_logic; | |
37 | mult : in std_logic; |
|
40 | mult : in std_logic; | |
38 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
41 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
39 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
42 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
40 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) |
|
43 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
41 | ); |
|
44 | ); | |
42 | end Multiplier; |
|
45 | end Multiplier; | |
43 |
|
46 | |||
44 |
|
47 | |||
45 |
|
48 | |||
46 |
|
49 | |||
47 |
|
50 | |||
48 | architecture ar_Multiplier of Multiplier is |
|
51 | architecture ar_Multiplier of Multiplier is | |
49 |
|
52 | |||
50 | signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); |
|
53 | signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
51 | signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); |
|
54 | signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
52 |
|
55 | |||
53 |
|
56 | |||
54 | begin |
|
57 | begin | |
55 |
|
58 | |||
56 | RES <= REG; |
|
59 | RES <= REG; | |
57 | RESMULT <= std_logic_vector(signed(OP1)*signed(OP2)); |
|
60 | RESMULT <= std_logic_vector(signed(OP1)*signed(OP2)); | |
58 | process(clk,reset) |
|
61 | process(clk,reset) | |
59 | begin |
|
62 | begin | |
60 | if reset = '0' then |
|
63 | if reset = '0' then | |
61 | REG <= (others => '0'); |
|
64 | REG <= (others => '0'); | |
62 | elsif clk'event and clk ='1' then |
|
65 | elsif clk'event and clk ='1' then | |
63 | if mult = '1' then |
|
66 | if mult = '1' then | |
64 | REG <= RESMULT; |
|
67 | REG <= RESMULT; | |
65 | end if; |
|
68 | end if; | |
66 | end if; |
|
69 | end if; | |
67 | end process; |
|
70 | end process; | |
68 |
|
71 | |||
69 | end ar_Multiplier; |
|
72 | end ar_Multiplier; | |
70 |
|
73 | |||
71 |
|
74 | |||
72 |
|
75 | |||
73 |
|
76 | |||
74 |
|
77 | |||
75 |
|
78 | |||
76 |
|
79 | |||
77 |
|
80 |
@@ -1,47 +1,50 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
24 |
|
27 | |||
25 | entity REG is |
|
28 | entity REG is | |
26 | generic(size : integer := 16 ; initial_VALUE : integer := 0); |
|
29 | generic(size : integer := 16 ; initial_VALUE : integer := 0); | |
27 | port( |
|
30 | port( | |
28 | reset : in std_logic; |
|
31 | reset : in std_logic; | |
29 | clk : in std_logic; |
|
32 | clk : in std_logic; | |
30 | D : in std_logic_vector(size-1 downto 0); |
|
33 | D : in std_logic_vector(size-1 downto 0); | |
31 | Q : out std_logic_vector(size-1 downto 0) |
|
34 | Q : out std_logic_vector(size-1 downto 0) | |
32 | ); |
|
35 | ); | |
33 | end entity; |
|
36 | end entity; | |
34 |
|
37 | |||
35 |
|
38 | |||
36 |
|
39 | |||
37 | architecture ar_REG of REG is |
|
40 | architecture ar_REG of REG is | |
38 | begin |
|
41 | begin | |
39 | process(clk,reset) |
|
42 | process(clk,reset) | |
40 | begin |
|
43 | begin | |
41 | if reset = '0' then |
|
44 | if reset = '0' then | |
42 | Q <= std_logic_vector(to_unsigned(initial_VALUE,size)); |
|
45 | Q <= std_logic_vector(to_unsigned(initial_VALUE,size)); | |
43 | elsif clk'event and clk ='1' then |
|
46 | elsif clk'event and clk ='1' then | |
44 | Q <= D; |
|
47 | Q <= D; | |
45 | end if; |
|
48 | end if; | |
46 | end process; |
|
49 | end process; | |
47 | end ar_REG; |
|
50 | end ar_REG; |
@@ -1,65 +1,68 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
24 |
|
27 | |||
25 |
|
28 | |||
26 |
|
29 | |||
27 | entity RShifter is |
|
30 | entity RShifter is | |
28 | generic( |
|
31 | generic( | |
29 | Input_SZ : integer := 16; |
|
32 | Input_SZ : integer := 16; | |
30 | shift_SZ : integer := 4 |
|
33 | shift_SZ : integer := 4 | |
31 | ); |
|
34 | ); | |
32 | port( |
|
35 | port( | |
33 | clk : in std_logic; |
|
36 | clk : in std_logic; | |
34 | reset : in std_logic; |
|
37 | reset : in std_logic; | |
35 | shift : in std_logic; |
|
38 | shift : in std_logic; | |
36 | OP : in std_logic_vector(Input_SZ-1 downto 0); |
|
39 | OP : in std_logic_vector(Input_SZ-1 downto 0); | |
37 | cnt : in std_logic_vector(shift_SZ-1 downto 0); |
|
40 | cnt : in std_logic_vector(shift_SZ-1 downto 0); | |
38 | RES : out std_logic_vector(Input_SZ-1 downto 0) |
|
41 | RES : out std_logic_vector(Input_SZ-1 downto 0) | |
39 | ); |
|
42 | ); | |
40 | end entity; |
|
43 | end entity; | |
41 |
|
44 | |||
42 |
|
45 | |||
43 |
|
46 | |||
44 |
|
47 | |||
45 | architecture ar_RShifter of RShifter is |
|
48 | architecture ar_RShifter of RShifter is | |
46 |
|
49 | |||
47 | signal REG : std_logic_vector(Input_SZ-1 downto 0); |
|
50 | signal REG : std_logic_vector(Input_SZ-1 downto 0); | |
48 | signal RESSHIFT: std_logic_vector(Input_SZ-1 downto 0); |
|
51 | signal RESSHIFT: std_logic_vector(Input_SZ-1 downto 0); | |
49 |
|
52 | |||
50 | begin |
|
53 | begin | |
51 |
|
54 | |||
52 | RES <= REG; |
|
55 | RES <= REG; | |
53 | RESSHIFT <= std_logic_vector(SHIFT_RIGHT(signed(OP),to_integer(unsigned(cnt)))); |
|
56 | RESSHIFT <= std_logic_vector(SHIFT_RIGHT(signed(OP),to_integer(unsigned(cnt)))); | |
54 |
|
57 | |||
55 | process(clk,reset) |
|
58 | process(clk,reset) | |
56 | begin |
|
59 | begin | |
57 | if reset = '0' then |
|
60 | if reset = '0' then | |
58 | REG <= (others => '0'); |
|
61 | REG <= (others => '0'); | |
59 | elsif clk'event and clk ='1' then |
|
62 | elsif clk'event and clk ='1' then | |
60 | if shift = '1' then |
|
63 | if shift = '1' then | |
61 | REG <= RESSHIFT; |
|
64 | REG <= RESSHIFT; | |
62 | end if; |
|
65 | end if; | |
63 | end if; |
|
66 | end if; | |
64 | end process; |
|
67 | end process; | |
65 | end ar_RShifter; |
|
68 | end ar_RShifter; |
@@ -1,135 +1,138 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 |
|
25 | |||
23 |
|
26 | |||
24 |
|
27 | |||
25 | entity TestbenshALU is |
|
28 | entity TestbenshALU is | |
26 | end TestbenshALU; |
|
29 | end TestbenshALU; | |
27 |
|
30 | |||
28 |
|
31 | |||
29 |
|
32 | |||
30 |
|
33 | |||
31 | architecture ar_TestbenshALU of TestbenshALU is |
|
34 | architecture ar_TestbenshALU of TestbenshALU is | |
32 |
|
35 | |||
33 |
|
36 | |||
34 |
|
37 | |||
35 | constant OP1sz : integer := 16; |
|
38 | constant OP1sz : integer := 16; | |
36 | constant OP2sz : integer := 12; |
|
39 | constant OP2sz : integer := 12; | |
37 | --IDLE =00 MAC =01 MULT =10 ADD =11 |
|
40 | --IDLE =00 MAC =01 MULT =10 ADD =11 | |
38 | constant IDLE : std_logic_vector(3 downto 0) := "0000"; |
|
41 | constant IDLE : std_logic_vector(3 downto 0) := "0000"; | |
39 | constant MAC : std_logic_vector(3 downto 0) := "0001"; |
|
42 | constant MAC : std_logic_vector(3 downto 0) := "0001"; | |
40 | constant MULT : std_logic_vector(3 downto 0) := "0010"; |
|
43 | constant MULT : std_logic_vector(3 downto 0) := "0010"; | |
41 | constant ADD : std_logic_vector(3 downto 0) := "0011"; |
|
44 | constant ADD : std_logic_vector(3 downto 0) := "0011"; | |
42 | constant clr_mac : std_logic_vector(3 downto 0) := "0100"; |
|
45 | constant clr_mac : std_logic_vector(3 downto 0) := "0100"; | |
43 |
|
46 | |||
44 | signal clk : std_logic:='0'; |
|
47 | signal clk : std_logic:='0'; | |
45 | signal reset : std_logic:='0'; |
|
48 | signal reset : std_logic:='0'; | |
46 | signal ctrl : std_logic_vector(3 downto 0):=IDLE; |
|
49 | signal ctrl : std_logic_vector(3 downto 0):=IDLE; | |
47 | signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0'); |
|
50 | signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0'); | |
48 | signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0'); |
|
51 | signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0'); | |
49 | signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0); |
|
52 | signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0); | |
50 |
|
53 | |||
51 |
|
54 | |||
52 |
|
55 | |||
53 |
|
56 | |||
54 | begin |
|
57 | begin | |
55 |
|
58 | |||
56 | ALU1 : entity LPP_IIR_FILTER.ALU |
|
59 | ALU1 : entity LPP_IIR_FILTER.ALU | |
57 | generic map( |
|
60 | generic map( | |
58 | Arith_en => 1, |
|
61 | Arith_en => 1, | |
59 | Logic_en => 0, |
|
62 | Logic_en => 0, | |
60 | Input_SZ_1 => OP1sz, |
|
63 | Input_SZ_1 => OP1sz, | |
61 | Input_SZ_2 => OP2sz |
|
64 | Input_SZ_2 => OP2sz | |
62 |
|
65 | |||
63 | ) |
|
66 | ) | |
64 | port map( |
|
67 | port map( | |
65 | clk => clk, |
|
68 | clk => clk, | |
66 | reset => reset, |
|
69 | reset => reset, | |
67 | ctrl => ctrl, |
|
70 | ctrl => ctrl, | |
68 | OP1 => Operand1, |
|
71 | OP1 => Operand1, | |
69 | OP2 => Operand2, |
|
72 | OP2 => Operand2, | |
70 | RES => Resultat |
|
73 | RES => Resultat | |
71 | ); |
|
74 | ); | |
72 |
|
75 | |||
73 |
|
76 | |||
74 |
|
77 | |||
75 |
|
78 | |||
76 | clk <= not clk after 25 ns; |
|
79 | clk <= not clk after 25 ns; | |
77 |
|
80 | |||
78 | process |
|
81 | process | |
79 | begin |
|
82 | begin | |
80 | wait for 40 ns; |
|
83 | wait for 40 ns; | |
81 | reset <= '1'; |
|
84 | reset <= '1'; | |
82 | wait for 11 ns; |
|
85 | wait for 11 ns; | |
83 | Operand1 <= X"0001"; |
|
86 | Operand1 <= X"0001"; | |
84 | Operand2 <= X"001"; |
|
87 | Operand2 <= X"001"; | |
85 | ctrl <= ADD; |
|
88 | ctrl <= ADD; | |
86 | wait for 50 ns; |
|
89 | wait for 50 ns; | |
87 | Operand1 <= X"0001"; |
|
90 | Operand1 <= X"0001"; | |
88 | Operand2 <= X"100"; |
|
91 | Operand2 <= X"100"; | |
89 | wait for 50 ns; |
|
92 | wait for 50 ns; | |
90 | Operand1 <= X"0001"; |
|
93 | Operand1 <= X"0001"; | |
91 | Operand2 <= X"001"; |
|
94 | Operand2 <= X"001"; | |
92 | ctrl <= MULT; |
|
95 | ctrl <= MULT; | |
93 | wait for 50 ns; |
|
96 | wait for 50 ns; | |
94 | Operand1 <= X"0002"; |
|
97 | Operand1 <= X"0002"; | |
95 | Operand2 <= X"002"; |
|
98 | Operand2 <= X"002"; | |
96 | wait for 50 ns; |
|
99 | wait for 50 ns; | |
97 | ctrl <= clr_mac; |
|
100 | ctrl <= clr_mac; | |
98 | wait for 50 ns; |
|
101 | wait for 50 ns; | |
99 | Operand1 <= X"0001"; |
|
102 | Operand1 <= X"0001"; | |
100 | Operand2 <= X"003"; |
|
103 | Operand2 <= X"003"; | |
101 | ctrl <= MAC; |
|
104 | ctrl <= MAC; | |
102 | wait for 50 ns; |
|
105 | wait for 50 ns; | |
103 | Operand1 <= X"0001"; |
|
106 | Operand1 <= X"0001"; | |
104 | Operand2 <= X"001"; |
|
107 | Operand2 <= X"001"; | |
105 | wait for 50 ns; |
|
108 | wait for 50 ns; | |
106 | Operand1 <= X"0011"; |
|
109 | Operand1 <= X"0011"; | |
107 | Operand2 <= X"003"; |
|
110 | Operand2 <= X"003"; | |
108 | wait for 50 ns; |
|
111 | wait for 50 ns; | |
109 | Operand1 <= X"1001"; |
|
112 | Operand1 <= X"1001"; | |
110 | Operand2 <= X"003"; |
|
113 | Operand2 <= X"003"; | |
111 | wait for 50 ns; |
|
114 | wait for 50 ns; | |
112 | Operand1 <= X"0001"; |
|
115 | Operand1 <= X"0001"; | |
113 | Operand2 <= X"000"; |
|
116 | Operand2 <= X"000"; | |
114 | wait for 50 ns; |
|
117 | wait for 50 ns; | |
115 | Operand1 <= X"0001"; |
|
118 | Operand1 <= X"0001"; | |
116 | Operand2 <= X"003"; |
|
119 | Operand2 <= X"003"; | |
117 | wait for 50 ns; |
|
120 | wait for 50 ns; | |
118 | Operand1 <= X"0101"; |
|
121 | Operand1 <= X"0101"; | |
119 | Operand2 <= X"053"; |
|
122 | Operand2 <= X"053"; | |
120 | wait for 50 ns; |
|
123 | wait for 50 ns; | |
121 | ctrl <= clr_mac; |
|
124 | ctrl <= clr_mac; | |
122 | wait; |
|
125 | wait; | |
123 | end process; |
|
126 | end process; | |
124 | end ar_TestbenshALU; |
|
127 | end ar_TestbenshALU; | |
125 |
|
128 | |||
126 |
|
129 | |||
127 |
|
130 | |||
128 |
|
131 | |||
129 |
|
132 | |||
130 |
|
133 | |||
131 |
|
134 | |||
132 |
|
135 | |||
133 |
|
136 | |||
134 |
|
137 | |||
135 |
|
138 |
@@ -1,208 +1,208 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library ieee; |
|
22 | library ieee; | |
20 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
21 |
|
24 | |||
22 |
|
25 | |||
23 |
|
26 | |||
24 | package general_purpose is |
|
27 | package general_purpose is | |
25 |
|
28 | |||
26 |
|
29 | |||
27 |
|
30 | |||
28 | component Clk_divider is |
|
31 | component Clk_divider is | |
29 | generic(OSC_freqHz : integer := 50000000; |
|
32 | generic(OSC_freqHz : integer := 50000000; | |
30 |
|
|
33 | TargetFreq_Hz : integer := 50000); | |
31 | Port ( clk : in STD_LOGIC; |
|
34 | Port ( clk : in STD_LOGIC; | |
32 | reset : in STD_LOGIC; |
|
35 | reset : in STD_LOGIC; | |
33 | clk_divided : out STD_LOGIC); |
|
36 | clk_divided : out STD_LOGIC); | |
34 | end component; |
|
37 | end component; | |
35 |
|
38 | |||
36 |
|
39 | |||
37 |
|
||||
38 |
|
||||
39 |
|
||||
40 | component Adder is |
|
40 | component Adder is | |
41 | generic( |
|
41 | generic( | |
42 | Input_SZ_A : integer := 16; |
|
42 | Input_SZ_A : integer := 16; | |
43 | Input_SZ_B : integer := 16 |
|
43 | Input_SZ_B : integer := 16 | |
44 |
|
44 | |||
45 | ); |
|
45 | ); | |
46 | port( |
|
46 | port( | |
47 | clk : in std_logic; |
|
47 | clk : in std_logic; | |
48 | reset : in std_logic; |
|
48 | reset : in std_logic; | |
49 | clr : in std_logic; |
|
49 | clr : in std_logic; | |
50 | add : in std_logic; |
|
50 | add : in std_logic; | |
51 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
51 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
52 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
52 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
53 | RES : out std_logic_vector(Input_SZ_A-1 downto 0) |
|
53 | RES : out std_logic_vector(Input_SZ_A-1 downto 0) | |
54 | ); |
|
54 | ); | |
55 | end component; |
|
55 | end component; | |
56 |
|
56 | |||
57 | component ADDRcntr is |
|
57 | component ADDRcntr is | |
58 | port( |
|
58 | port( | |
59 | clk : in std_logic; |
|
59 | clk : in std_logic; | |
60 | reset : in std_logic; |
|
60 | reset : in std_logic; | |
61 | count : in std_logic; |
|
61 | count : in std_logic; | |
62 | clr : in std_logic; |
|
62 | clr : in std_logic; | |
63 | Q : out std_logic_vector(7 downto 0) |
|
63 | Q : out std_logic_vector(7 downto 0) | |
64 | ); |
|
64 | ); | |
65 | end component; |
|
65 | end component; | |
66 |
|
66 | |||
67 | component ALU is |
|
67 | component ALU is | |
68 | generic( |
|
68 | generic( | |
69 | Arith_en : integer := 1; |
|
69 | Arith_en : integer := 1; | |
70 | Logic_en : integer := 1; |
|
70 | Logic_en : integer := 1; | |
71 | Input_SZ_1 : integer := 16; |
|
71 | Input_SZ_1 : integer := 16; | |
72 | Input_SZ_2 : integer := 9 |
|
72 | Input_SZ_2 : integer := 9 | |
73 |
|
73 | |||
74 | ); |
|
74 | ); | |
75 | port( |
|
75 | port( | |
76 | clk : in std_logic; |
|
76 | clk : in std_logic; | |
77 | reset : in std_logic; |
|
77 | reset : in std_logic; | |
78 | ctrl : in std_logic_vector(3 downto 0); |
|
78 | ctrl : in std_logic_vector(3 downto 0); | |
79 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
79 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); | |
80 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
80 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); | |
81 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) |
|
81 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) | |
82 | ); |
|
82 | ); | |
83 | end component; |
|
83 | end component; | |
84 |
|
84 | |||
85 |
|
85 | |||
86 | component MAC is |
|
86 | component MAC is | |
87 | generic( |
|
87 | generic( | |
88 | Input_SZ_A : integer := 8; |
|
88 | Input_SZ_A : integer := 8; | |
89 | Input_SZ_B : integer := 8 |
|
89 | Input_SZ_B : integer := 8 | |
90 |
|
90 | |||
91 | ); |
|
91 | ); | |
92 | port( |
|
92 | port( | |
93 | clk : in std_logic; |
|
93 | clk : in std_logic; | |
94 | reset : in std_logic; |
|
94 | reset : in std_logic; | |
95 | clr_MAC : in std_logic; |
|
95 | clr_MAC : in std_logic; | |
96 | MAC_MUL_ADD : in std_logic_vector(1 downto 0); |
|
96 | MAC_MUL_ADD : in std_logic_vector(1 downto 0); | |
97 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
97 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
98 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
98 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
99 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) |
|
99 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
100 | ); |
|
100 | ); | |
101 | end component; |
|
101 | end component; | |
102 |
|
102 | |||
103 |
|
103 | |||
104 | component MAC_CONTROLER is |
|
104 | component MAC_CONTROLER is | |
105 | port( |
|
105 | port( | |
106 | ctrl : in std_logic_vector(1 downto 0); |
|
106 | ctrl : in std_logic_vector(1 downto 0); | |
107 | MULT : out std_logic; |
|
107 | MULT : out std_logic; | |
108 | ADD : out std_logic; |
|
108 | ADD : out std_logic; | |
109 | MACMUX_sel : out std_logic; |
|
109 | MACMUX_sel : out std_logic; | |
110 | MACMUX2_sel : out std_logic |
|
110 | MACMUX2_sel : out std_logic | |
111 |
|
111 | |||
112 | ); |
|
112 | ); | |
113 | end component; |
|
113 | end component; | |
114 |
|
114 | |||
115 | component MAC_MUX is |
|
115 | component MAC_MUX is | |
116 | generic( |
|
116 | generic( | |
117 | Input_SZ_A : integer := 16; |
|
117 | Input_SZ_A : integer := 16; | |
118 | Input_SZ_B : integer := 16 |
|
118 | Input_SZ_B : integer := 16 | |
119 |
|
119 | |||
120 | ); |
|
120 | ); | |
121 | port( |
|
121 | port( | |
122 | sel : in std_logic; |
|
122 | sel : in std_logic; | |
123 | INA1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
123 | INA1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
124 | INA2 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
124 | INA2 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
125 | INB1 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
125 | INB1 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
126 | INB2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
126 | INB2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
127 | OUTA : out std_logic_vector(Input_SZ_A-1 downto 0); |
|
127 | OUTA : out std_logic_vector(Input_SZ_A-1 downto 0); | |
128 | OUTB : out std_logic_vector(Input_SZ_B-1 downto 0) |
|
128 | OUTB : out std_logic_vector(Input_SZ_B-1 downto 0) | |
129 | ); |
|
129 | ); | |
130 | end component; |
|
130 | end component; | |
131 |
|
131 | |||
132 |
|
132 | |||
133 | component MAC_MUX2 is |
|
133 | component MAC_MUX2 is | |
134 | generic(Input_SZ : integer := 16); |
|
134 | generic(Input_SZ : integer := 16); | |
135 | port( |
|
135 | port( | |
136 | sel : in std_logic; |
|
136 | sel : in std_logic; | |
137 | RES1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
137 | RES1 : in std_logic_vector(Input_SZ-1 downto 0); | |
138 | RES2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
138 | RES2 : in std_logic_vector(Input_SZ-1 downto 0); | |
139 | RES : out std_logic_vector(Input_SZ-1 downto 0) |
|
139 | RES : out std_logic_vector(Input_SZ-1 downto 0) | |
140 | ); |
|
140 | ); | |
141 | end component; |
|
141 | end component; | |
142 |
|
142 | |||
143 |
|
143 | |||
144 | component MAC_REG is |
|
144 | component MAC_REG is | |
145 | generic(size : integer := 16); |
|
145 | generic(size : integer := 16); | |
146 | port( |
|
146 | port( | |
147 | reset : in std_logic; |
|
147 | reset : in std_logic; | |
148 | clk : in std_logic; |
|
148 | clk : in std_logic; | |
149 | D : in std_logic_vector(size-1 downto 0); |
|
149 | D : in std_logic_vector(size-1 downto 0); | |
150 | Q : out std_logic_vector(size-1 downto 0) |
|
150 | Q : out std_logic_vector(size-1 downto 0) | |
151 | ); |
|
151 | ); | |
152 | end component; |
|
152 | end component; | |
153 |
|
153 | |||
154 |
|
154 | |||
155 | component MUX2 is |
|
155 | component MUX2 is | |
156 | generic(Input_SZ : integer := 16); |
|
156 | generic(Input_SZ : integer := 16); | |
157 | port( |
|
157 | port( | |
158 | sel : in std_logic; |
|
158 | sel : in std_logic; | |
159 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
159 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); | |
160 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
160 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); | |
161 | RES : out std_logic_vector(Input_SZ-1 downto 0) |
|
161 | RES : out std_logic_vector(Input_SZ-1 downto 0) | |
162 | ); |
|
162 | ); | |
163 | end component; |
|
163 | end component; | |
164 |
|
164 | |||
165 | component Multiplier is |
|
165 | component Multiplier is | |
166 | generic( |
|
166 | generic( | |
167 | Input_SZ_A : integer := 16; |
|
167 | Input_SZ_A : integer := 16; | |
168 | Input_SZ_B : integer := 16 |
|
168 | Input_SZ_B : integer := 16 | |
169 |
|
169 | |||
170 | ); |
|
170 | ); | |
171 | port( |
|
171 | port( | |
172 | clk : in std_logic; |
|
172 | clk : in std_logic; | |
173 | reset : in std_logic; |
|
173 | reset : in std_logic; | |
174 | mult : in std_logic; |
|
174 | mult : in std_logic; | |
175 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
175 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
176 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
176 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
177 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) |
|
177 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
178 | ); |
|
178 | ); | |
179 | end component; |
|
179 | end component; | |
180 |
|
180 | |||
181 | component REG is |
|
181 | component REG is | |
182 | generic(size : integer := 16 ; initial_VALUE : integer := 0); |
|
182 | generic(size : integer := 16 ; initial_VALUE : integer := 0); | |
183 | port( |
|
183 | port( | |
184 | reset : in std_logic; |
|
184 | reset : in std_logic; | |
185 | clk : in std_logic; |
|
185 | clk : in std_logic; | |
186 | D : in std_logic_vector(size-1 downto 0); |
|
186 | D : in std_logic_vector(size-1 downto 0); | |
187 | Q : out std_logic_vector(size-1 downto 0) |
|
187 | Q : out std_logic_vector(size-1 downto 0) | |
188 | ); |
|
188 | ); | |
189 | end component; |
|
189 | end component; | |
190 |
|
190 | |||
191 |
|
191 | |||
192 |
|
192 | |||
193 | component RShifter is |
|
193 | component RShifter is | |
194 | generic( |
|
194 | generic( | |
195 | Input_SZ : integer := 16; |
|
195 | Input_SZ : integer := 16; | |
196 | shift_SZ : integer := 4 |
|
196 | shift_SZ : integer := 4 | |
197 | ); |
|
197 | ); | |
198 | port( |
|
198 | port( | |
199 | clk : in std_logic; |
|
199 | clk : in std_logic; | |
200 | reset : in std_logic; |
|
200 | reset : in std_logic; | |
201 | shift : in std_logic; |
|
201 | shift : in std_logic; | |
202 | OP : in std_logic_vector(Input_SZ-1 downto 0); |
|
202 | OP : in std_logic_vector(Input_SZ-1 downto 0); | |
203 | cnt : in std_logic_vector(shift_SZ-1 downto 0); |
|
203 | cnt : in std_logic_vector(shift_SZ-1 downto 0); | |
204 | RES : out std_logic_vector(Input_SZ-1 downto 0) |
|
204 | RES : out std_logic_vector(Input_SZ-1 downto 0) | |
205 | ); |
|
205 | ); | |
206 | end component; |
|
206 | end component; | |
207 |
|
207 | |||
208 | end; |
|
208 | end; |
@@ -1,98 +1,101 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 | library lpp; |
|
24 | library lpp; | |
22 | use lpp.lpp_ad_conv.all; |
|
25 | use lpp.lpp_ad_conv.all; | |
23 | use lpp.general_purpose.Clk_divider; |
|
26 | use lpp.general_purpose.Clk_divider; | |
24 |
|
27 | |||
25 | entity AD7688_drvr is |
|
28 | entity AD7688_drvr is | |
26 | generic(ChanelCount : integer; |
|
29 | generic(ChanelCount : integer; | |
27 | clkkHz : integer); |
|
30 | clkkHz : integer); | |
28 | Port ( clk : in STD_LOGIC; |
|
31 | Port ( clk : in STD_LOGIC; | |
29 | reset : in STD_LOGIC; |
|
32 | reset : in STD_LOGIC; | |
30 | smplClk: in STD_LOGIC; |
|
33 | smplClk: in STD_LOGIC; | |
31 | DataReady : out std_logic; |
|
34 | DataReady : out std_logic; | |
32 | smpout : out Samples_out(ChanelCount-1 downto 0); |
|
35 | smpout : out Samples_out(ChanelCount-1 downto 0); | |
33 | AD_in : in AD7688_in(ChanelCount-1 downto 0); |
|
36 | AD_in : in AD7688_in(ChanelCount-1 downto 0); | |
34 | AD_out : out AD7688_out); |
|
37 | AD_out : out AD7688_out); | |
35 | end AD7688_drvr; |
|
38 | end AD7688_drvr; | |
36 |
|
39 | |||
37 | architecture ar_AD7688_drvr of AD7688_drvr is |
|
40 | architecture ar_AD7688_drvr of AD7688_drvr is | |
38 |
|
41 | |||
39 | constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs |
|
42 | constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs | |
40 |
|
43 | |||
41 | signal i : integer range 0 to convTrigger :=0; |
|
44 | signal i : integer range 0 to convTrigger :=0; | |
42 | signal clk_int : std_logic; |
|
45 | signal clk_int : std_logic; | |
43 | signal smplClk_reg : std_logic; |
|
46 | signal smplClk_reg : std_logic; | |
44 | signal cnv_int : std_logic; |
|
47 | signal cnv_int : std_logic; | |
45 |
|
48 | |||
46 | begin |
|
49 | begin | |
47 |
|
50 | |||
48 | clkdiv: if clkkHz>=66000 generate |
|
51 | clkdiv: if clkkHz>=66000 generate | |
49 | clkdivider: Clk_divider |
|
52 | clkdivider: Clk_divider | |
50 | generic map(clkkHz*1000,60000000) |
|
53 | generic map(clkkHz*1000,60000000) | |
51 | Port map( clk ,reset,clk_int); |
|
54 | Port map( clk ,reset,clk_int); | |
52 | end generate; |
|
55 | end generate; | |
53 |
|
56 | |||
54 | clknodiv: if clkkHz<66000 generate |
|
57 | clknodiv: if clkkHz<66000 generate | |
55 | nodiv: clk_int <= clk; |
|
58 | nodiv: clk_int <= clk; | |
56 | end generate; |
|
59 | end generate; | |
57 |
|
60 | |||
58 | AD_out.CNV <= cnv_int; |
|
61 | AD_out.CNV <= cnv_int; | |
59 | AD_out.SCK <= clk_int; |
|
62 | AD_out.SCK <= clk_int; | |
60 |
|
63 | |||
61 |
|
64 | |||
62 | sckgen: process(clk,reset) |
|
65 | sckgen: process(clk,reset) | |
63 | begin |
|
66 | begin | |
64 | if reset = '0' then |
|
67 | if reset = '0' then | |
65 | i <= 0; |
|
68 | i <= 0; | |
66 | cnv_int <= '0'; |
|
69 | cnv_int <= '0'; | |
67 | smplClk_reg <= '0'; |
|
70 | smplClk_reg <= '0'; | |
68 | elsif clk'event and clk = '1' then |
|
71 | elsif clk'event and clk = '1' then | |
69 | if smplClk = '1' and smplClk_reg = '0' then |
|
72 | if smplClk = '1' and smplClk_reg = '0' then | |
70 | if i = convTrigger then |
|
73 | if i = convTrigger then | |
71 | smplClk_reg <= '1'; |
|
74 | smplClk_reg <= '1'; | |
72 | i <= 0; |
|
75 | i <= 0; | |
73 | cnv_int <= '0'; |
|
76 | cnv_int <= '0'; | |
74 | else |
|
77 | else | |
75 | i <= i+1; |
|
78 | i <= i+1; | |
76 | cnv_int <= '1'; |
|
79 | cnv_int <= '1'; | |
77 | end if; |
|
80 | end if; | |
78 | elsif smplClk = '0' and smplClk_reg = '1' then |
|
81 | elsif smplClk = '0' and smplClk_reg = '1' then | |
79 | smplClk_reg <= '0'; |
|
82 | smplClk_reg <= '0'; | |
80 | end if; |
|
83 | end if; | |
81 | end if; |
|
84 | end if; | |
82 | end process; |
|
85 | end process; | |
83 |
|
86 | |||
84 |
|
87 | |||
85 |
|
88 | |||
86 | spidrvr: AD7688_spi_if |
|
89 | spidrvr: AD7688_spi_if | |
87 | generic map(ChanelCount) |
|
90 | generic map(ChanelCount) | |
88 | Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout); |
|
91 | Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout); | |
89 |
|
92 | |||
90 |
|
93 | |||
91 |
|
94 | |||
92 | end ar_AD7688_drvr; |
|
95 | end ar_AD7688_drvr; | |
93 |
|
96 | |||
94 |
|
97 | |||
95 |
|
98 | |||
96 |
|
99 | |||
97 |
|
100 | |||
98 |
|
101 |
@@ -1,75 +1,78 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 | library lpp; |
|
24 | library lpp; | |
22 | use lpp.lpp_ad_conv.all; |
|
25 | use lpp.lpp_ad_conv.all; | |
23 | use lpp.general_purpose.Clk_divider; |
|
26 | use lpp.general_purpose.Clk_divider; | |
24 |
|
27 | |||
25 | entity AD7688_spi_if is |
|
28 | entity AD7688_spi_if is | |
26 | generic(ChanelCount : integer); |
|
29 | generic(ChanelCount : integer); | |
27 | Port( clk : in STD_LOGIC; |
|
30 | Port( clk : in STD_LOGIC; | |
28 | reset : in STD_LOGIC; |
|
31 | reset : in STD_LOGIC; | |
29 | cnv : in STD_LOGIC; |
|
32 | cnv : in STD_LOGIC; | |
30 | DataReady: out std_logic; |
|
33 | DataReady: out std_logic; | |
31 | sdi : in AD7688_in(ChanelCount-1 downto 0); |
|
34 | sdi : in AD7688_in(ChanelCount-1 downto 0); | |
32 | smpout : out Samples_out(ChanelCount-1 downto 0) |
|
35 | smpout : out Samples_out(ChanelCount-1 downto 0) | |
33 | ); |
|
36 | ); | |
34 | end AD7688_spi_if; |
|
37 | end AD7688_spi_if; | |
35 |
|
38 | |||
36 | architecture ar_AD7688_spi_if of AD7688_spi_if is |
|
39 | architecture ar_AD7688_spi_if of AD7688_spi_if is | |
37 |
|
40 | |||
38 | signal shift_reg : Samples_out(ChanelCount-1 downto 0); |
|
41 | signal shift_reg : Samples_out(ChanelCount-1 downto 0); | |
39 | signal i : integer range 0 to 15 :=0; |
|
42 | signal i : integer range 0 to 15 :=0; | |
40 | signal cnv_reg : std_logic := '0'; |
|
43 | signal cnv_reg : std_logic := '0'; | |
41 |
|
44 | |||
42 | begin |
|
45 | begin | |
43 |
|
46 | |||
44 |
|
47 | |||
45 |
|
48 | |||
46 | process(clk,reset) |
|
49 | process(clk,reset) | |
47 | begin |
|
50 | begin | |
48 | if reset = '0' then |
|
51 | if reset = '0' then | |
49 | for l in 0 to ChanelCount-1 loop |
|
52 | for l in 0 to ChanelCount-1 loop | |
50 | shift_reg(l) <= (others => '0'); |
|
53 | shift_reg(l) <= (others => '0'); | |
51 | end loop; |
|
54 | end loop; | |
52 | i <= 0; |
|
55 | i <= 0; | |
53 | cnv_reg <= '0'; |
|
56 | cnv_reg <= '0'; | |
54 | elsif clk'event and clk = '1' then |
|
57 | elsif clk'event and clk = '1' then | |
55 | if cnv = '0' and cnv_reg = '0' then |
|
58 | if cnv = '0' and cnv_reg = '0' then | |
56 | if i = 15 then |
|
59 | if i = 15 then | |
57 | i <= 0; |
|
60 | i <= 0; | |
58 | cnv_reg <= '1'; |
|
61 | cnv_reg <= '1'; | |
59 | else |
|
62 | else | |
60 | DataReady <= '0'; |
|
63 | DataReady <= '0'; | |
61 | i <= i+1; |
|
64 | i <= i+1; | |
62 | for l in 0 to ChanelCount-1 loop |
|
65 | for l in 0 to ChanelCount-1 loop | |
63 | shift_reg(l)(0) <= sdi(l).SDI; |
|
66 | shift_reg(l)(0) <= sdi(l).SDI; | |
64 | shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0); |
|
67 | shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0); | |
65 | end loop; |
|
68 | end loop; | |
66 | end if; |
|
69 | end if; | |
67 | else |
|
70 | else | |
68 | cnv_reg <= not cnv; |
|
71 | cnv_reg <= not cnv; | |
69 | smpout <= shift_reg; |
|
72 | smpout <= shift_reg; | |
70 | DataReady <= '1'; |
|
73 | DataReady <= '1'; | |
71 | end if; |
|
74 | end if; | |
72 | end if; |
|
75 | end if; | |
73 | end process; |
|
76 | end process; | |
74 |
|
77 | |||
75 | end ar_AD7688_spi_if; |
|
78 | end ar_AD7688_spi_if; |
@@ -1,102 +1,105 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 | library lpp; |
|
24 | library lpp; | |
22 | use lpp.lpp_ad_conv.all; |
|
25 | use lpp.lpp_ad_conv.all; | |
23 | use lpp.general_purpose.Clk_divider; |
|
26 | use lpp.general_purpose.Clk_divider; | |
24 |
|
27 | |||
25 | entity ADS7886_drvr is |
|
28 | entity ADS7886_drvr is | |
26 | generic(ChanelCount : integer; |
|
29 | generic(ChanelCount : integer; | |
27 | clkkHz : integer); |
|
30 | clkkHz : integer); | |
28 | Port ( clk : in STD_LOGIC; |
|
31 | Port ( clk : in STD_LOGIC; | |
29 | reset : in STD_LOGIC; |
|
32 | reset : in STD_LOGIC; | |
30 | smplClk: in STD_LOGIC; |
|
33 | smplClk: in STD_LOGIC; | |
31 | DataReady : out std_logic; |
|
34 | DataReady : out std_logic; | |
32 | smpout : out Samples_out(ChanelCount-1 downto 0); |
|
35 | smpout : out Samples_out(ChanelCount-1 downto 0); | |
33 | AD_in : in AD7688_in(ChanelCount-1 downto 0); |
|
36 | AD_in : in AD7688_in(ChanelCount-1 downto 0); | |
34 | AD_out : out AD7688_out); |
|
37 | AD_out : out AD7688_out); | |
35 | end ADS7886_drvr; |
|
38 | end ADS7886_drvr; | |
36 |
|
39 | |||
37 | architecture ar_ADS7886_drvr of ADS7886_drvr is |
|
40 | architecture ar_ADS7886_drvr of ADS7886_drvr is | |
38 |
|
41 | |||
39 | constant convTrigger : integer:= clkkHz*1/1000; --tconv = 1.6µs |
|
42 | constant convTrigger : integer:= clkkHz*1/1000; --tconv = 1.6µs | |
40 |
|
43 | |||
41 | signal i : integer range 0 to convTrigger :=0; |
|
44 | signal i : integer range 0 to convTrigger :=0; | |
42 | signal clk_int : std_logic; |
|
45 | signal clk_int : std_logic; | |
43 | signal smplClk_reg : std_logic; |
|
46 | signal smplClk_reg : std_logic; | |
44 | signal cnv_int : std_logic; |
|
47 | signal cnv_int : std_logic; | |
45 | signal smpout_int : Samples_out(ChanelCount-1 downto 0); |
|
48 | signal smpout_int : Samples_out(ChanelCount-1 downto 0); | |
46 |
|
49 | |||
47 |
|
50 | |||
48 | begin |
|
51 | begin | |
49 |
|
52 | |||
50 |
|
53 | |||
51 | clkdiv: if clkkHz>=20000 generate |
|
54 | clkdiv: if clkkHz>=20000 generate | |
52 | clkdivider: Clk_divider |
|
55 | clkdivider: Clk_divider | |
53 | generic map(clkkHz*1000,19000000) |
|
56 | generic map(clkkHz*1000,19000000) | |
54 | Port map( clk ,reset,clk_int); |
|
57 | Port map( clk ,reset,clk_int); | |
55 | end generate; |
|
58 | end generate; | |
56 |
|
59 | |||
57 |
|
60 | |||
58 | clknodiv: if clkkHz<20000 generate |
|
61 | clknodiv: if clkkHz<20000 generate | |
59 | nodiv: clk_int <= clk; |
|
62 | nodiv: clk_int <= clk; | |
60 | end generate; |
|
63 | end generate; | |
61 |
|
64 | |||
62 | AD_out.CNV <= cnv_int; |
|
65 | AD_out.CNV <= cnv_int; | |
63 | AD_out.SCK <= clk_int; |
|
66 | AD_out.SCK <= clk_int; | |
64 |
|
67 | |||
65 |
|
68 | |||
66 | sckgen: process(clk,reset) |
|
69 | sckgen: process(clk,reset) | |
67 | begin |
|
70 | begin | |
68 | if reset = '0' then |
|
71 | if reset = '0' then | |
69 | i <= 0; |
|
72 | i <= 0; | |
70 | cnv_int <= '0'; |
|
73 | cnv_int <= '0'; | |
71 | smplClk_reg <= '0'; |
|
74 | smplClk_reg <= '0'; | |
72 | elsif clk'event and clk = '1' then |
|
75 | elsif clk'event and clk = '1' then | |
73 | if smplClk = '1' and smplClk_reg = '0' then |
|
76 | if smplClk = '1' and smplClk_reg = '0' then | |
74 | if i = convTrigger then |
|
77 | if i = convTrigger then | |
75 | smplClk_reg <= '1'; |
|
78 | smplClk_reg <= '1'; | |
76 | i <= 0; |
|
79 | i <= 0; | |
77 | cnv_int <= '0'; |
|
80 | cnv_int <= '0'; | |
78 | else |
|
81 | else | |
79 | i <= i+1; |
|
82 | i <= i+1; | |
80 | cnv_int <= '1'; |
|
83 | cnv_int <= '1'; | |
81 | end if; |
|
84 | end if; | |
82 | elsif smplClk = '0' and smplClk_reg = '1' then |
|
85 | elsif smplClk = '0' and smplClk_reg = '1' then | |
83 | smplClk_reg <= '0'; |
|
86 | smplClk_reg <= '0'; | |
84 | end if; |
|
87 | end if; | |
85 | end if; |
|
88 | end if; | |
86 | end process; |
|
89 | end process; | |
87 |
|
90 | |||
88 |
|
91 | |||
89 | NDMSK: for i in 0 to ChanelCount-1 |
|
92 | NDMSK: for i in 0 to ChanelCount-1 | |
90 | generate |
|
93 | generate | |
91 | smpout(i) <= smpout_int(i) and X"0FFF"; |
|
94 | smpout(i) <= smpout_int(i) and X"0FFF"; | |
92 | end generate; |
|
95 | end generate; | |
93 |
|
96 | |||
94 |
|
97 | |||
95 | spidrvr: AD7688_spi_if |
|
98 | spidrvr: AD7688_spi_if | |
96 | generic map(ChanelCount) |
|
99 | generic map(ChanelCount) | |
97 | Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout_int); |
|
100 | Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout_int); | |
98 |
|
101 | |||
99 |
|
102 | |||
100 |
|
103 | |||
101 | end ar_ADS7886_drvr; |
|
104 | end ar_ADS7886_drvr; | |
102 |
|
105 |
@@ -1,112 +1,115 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 |
|
22 | |||
20 | library IEEE; |
|
23 | library IEEE; | |
21 | use IEEE.STD_LOGIC_1164.all; |
|
24 | use IEEE.STD_LOGIC_1164.all; | |
22 | library grlib; |
|
25 | library grlib; | |
23 | use grlib.amba.all; |
|
26 | use grlib.amba.all; | |
24 | use grlib.stdlib.all; |
|
27 | use grlib.stdlib.all; | |
25 | use grlib.devices.all; |
|
28 | use grlib.devices.all; | |
26 |
|
29 | |||
27 |
|
30 | |||
28 | package lpp_ad_conv is |
|
31 | package lpp_ad_conv is | |
29 |
|
32 | |||
30 |
|
33 | |||
31 | constant AD7688 : integer := 0; |
|
34 | constant AD7688 : integer := 0; | |
32 | constant ADS7886 : integer := 1; |
|
35 | constant ADS7886 : integer := 1; | |
33 |
|
36 | |||
34 |
|
37 | |||
35 | type AD7688_out is |
|
38 | type AD7688_out is | |
36 | record |
|
39 | record | |
37 | CNV : std_logic; |
|
40 | CNV : std_logic; | |
38 | SCK : std_logic; |
|
41 | SCK : std_logic; | |
39 | end record; |
|
42 | end record; | |
40 |
|
43 | |||
41 | type AD7688_in_element is |
|
44 | type AD7688_in_element is | |
42 | record |
|
45 | record | |
43 | SDI : std_logic; |
|
46 | SDI : std_logic; | |
44 | end record; |
|
47 | end record; | |
45 |
|
48 | |||
46 | type AD7688_in is array(natural range <>) of AD7688_in_element; |
|
49 | type AD7688_in is array(natural range <>) of AD7688_in_element; | |
47 |
|
50 | |||
48 | type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0); |
|
51 | type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0); | |
49 |
|
52 | |||
50 | component AD7688_drvr is |
|
53 | component AD7688_drvr is | |
51 | generic(ChanelCount : integer; |
|
54 | generic(ChanelCount : integer; | |
52 | clkkHz : integer); |
|
55 | clkkHz : integer); | |
53 | Port ( clk : in STD_LOGIC; |
|
56 | Port ( clk : in STD_LOGIC; | |
54 | reset : in STD_LOGIC; |
|
57 | reset : in STD_LOGIC; | |
55 | smplClk: in STD_LOGIC; |
|
58 | smplClk: in STD_LOGIC; | |
56 | DataReady : out std_logic; |
|
59 | DataReady : out std_logic; | |
57 | smpout : out Samples_out(ChanelCount-1 downto 0); |
|
60 | smpout : out Samples_out(ChanelCount-1 downto 0); | |
58 | AD_in : in AD7688_in(ChanelCount-1 downto 0); |
|
61 | AD_in : in AD7688_in(ChanelCount-1 downto 0); | |
59 | AD_out : out AD7688_out); |
|
62 | AD_out : out AD7688_out); | |
60 | end component; |
|
63 | end component; | |
61 |
|
64 | |||
62 |
|
65 | |||
63 | component AD7688_spi_if is |
|
66 | component AD7688_spi_if is | |
64 | generic(ChanelCount : integer); |
|
67 | generic(ChanelCount : integer); | |
65 | Port( clk : in STD_LOGIC; |
|
68 | Port( clk : in STD_LOGIC; | |
66 | reset : in STD_LOGIC; |
|
69 | reset : in STD_LOGIC; | |
67 | cnv : in STD_LOGIC; |
|
70 | cnv : in STD_LOGIC; | |
68 | DataReady: out std_logic; |
|
71 | DataReady: out std_logic; | |
69 | sdi : in AD7688_in(ChanelCount-1 downto 0); |
|
72 | sdi : in AD7688_in(ChanelCount-1 downto 0); | |
70 | smpout : out Samples_out(ChanelCount-1 downto 0) |
|
73 | smpout : out Samples_out(ChanelCount-1 downto 0) | |
71 | ); |
|
74 | ); | |
72 | end component; |
|
75 | end component; | |
73 |
|
76 | |||
74 |
|
77 | |||
75 | component lpp_apb_ad_conv |
|
78 | component lpp_apb_ad_conv | |
76 | generic( |
|
79 | generic( | |
77 | pindex : integer := 0; |
|
80 | pindex : integer := 0; | |
78 | paddr : integer := 0; |
|
81 | paddr : integer := 0; | |
79 | pmask : integer := 16#fff#; |
|
82 | pmask : integer := 16#fff#; | |
80 | pirq : integer := 0; |
|
83 | pirq : integer := 0; | |
81 | abits : integer := 8; |
|
84 | abits : integer := 8; | |
82 | ChanelCount : integer := 1; |
|
85 | ChanelCount : integer := 1; | |
83 | clkkHz : integer := 50000; |
|
86 | clkkHz : integer := 50000; | |
84 | smpClkHz : integer := 100; |
|
87 | smpClkHz : integer := 100; | |
85 | ADCref : integer := AD7688); |
|
88 | ADCref : integer := AD7688); | |
86 | Port ( |
|
89 | Port ( | |
87 | clk : in STD_LOGIC; |
|
90 | clk : in STD_LOGIC; | |
88 | reset : in STD_LOGIC; |
|
91 | reset : in STD_LOGIC; | |
89 | apbi : in apb_slv_in_type; |
|
92 | apbi : in apb_slv_in_type; | |
90 | apbo : out apb_slv_out_type; |
|
93 | apbo : out apb_slv_out_type; | |
91 | AD_in : in AD7688_in(ChanelCount-1 downto 0); |
|
94 | AD_in : in AD7688_in(ChanelCount-1 downto 0); | |
92 | AD_out : out AD7688_out); |
|
95 | AD_out : out AD7688_out); | |
93 | end component; |
|
96 | end component; | |
94 |
|
97 | |||
95 | component ADS7886_drvr is |
|
98 | component ADS7886_drvr is | |
96 | generic(ChanelCount : integer; |
|
99 | generic(ChanelCount : integer; | |
97 | clkkHz : integer); |
|
100 | clkkHz : integer); | |
98 | Port ( |
|
101 | Port ( | |
99 | clk : in STD_LOGIC; |
|
102 | clk : in STD_LOGIC; | |
100 | reset : in STD_LOGIC; |
|
103 | reset : in STD_LOGIC; | |
101 | smplClk : in STD_LOGIC; |
|
104 | smplClk : in STD_LOGIC; | |
102 | DataReady : out std_logic; |
|
105 | DataReady : out std_logic; | |
103 | smpout : out Samples_out(ChanelCount-1 downto 0); |
|
106 | smpout : out Samples_out(ChanelCount-1 downto 0); | |
104 | AD_in : in AD7688_in(ChanelCount-1 downto 0); |
|
107 | AD_in : in AD7688_in(ChanelCount-1 downto 0); | |
105 | AD_out : out AD7688_out |
|
108 | AD_out : out AD7688_out | |
106 | ); |
|
109 | ); | |
107 | end component; |
|
110 | end component; | |
108 |
|
111 | |||
109 |
|
112 | |||
110 | end lpp_ad_conv; |
|
113 | end lpp_ad_conv; | |
111 |
|
114 | |||
112 |
|
115 |
@@ -1,143 +1,146 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | use IEEE.STD_LOGIC_1164.ALL; | |
21 | use ieee.numeric_std.all; |
|
24 | use ieee.numeric_std.all; | |
22 | library grlib; |
|
25 | library grlib; | |
23 | use grlib.amba.all; |
|
26 | use grlib.amba.all; | |
24 | use grlib.stdlib.all; |
|
27 | use grlib.stdlib.all; | |
25 | use grlib.devices.all; |
|
28 | use grlib.devices.all; | |
26 | library lpp; |
|
29 | library lpp; | |
27 | use lpp.lpp_ad_conv.all; |
|
30 | use lpp.lpp_ad_conv.all; | |
28 | use lpp.lpp_amba.all; |
|
31 | use lpp.lpp_amba.all; | |
29 | use lpp.apb_devices_list.all; |
|
32 | use lpp.apb_devices_list.all; | |
30 | use lpp.general_purpose.Clk_divider; |
|
33 | use lpp.general_purpose.Clk_divider; | |
31 |
|
34 | |||
32 | entity lpp_apb_ad_conv is |
|
35 | entity lpp_apb_ad_conv is | |
33 | generic( |
|
36 | generic( | |
34 | pindex : integer := 0; |
|
37 | pindex : integer := 0; | |
35 | paddr : integer := 0; |
|
38 | paddr : integer := 0; | |
36 | pmask : integer := 16#fff#; |
|
39 | pmask : integer := 16#fff#; | |
37 | pirq : integer := 0; |
|
40 | pirq : integer := 0; | |
38 | abits : integer := 8; |
|
41 | abits : integer := 8; | |
39 | ChanelCount : integer := 1; |
|
42 | ChanelCount : integer := 1; | |
40 | clkkHz : integer := 50000; |
|
43 | clkkHz : integer := 50000; | |
41 | smpClkHz : integer := 100; |
|
44 | smpClkHz : integer := 100; | |
42 | ADCref : integer := AD7688); |
|
45 | ADCref : integer := AD7688); | |
43 | Port ( |
|
46 | Port ( | |
44 | clk : in STD_LOGIC; |
|
47 | clk : in STD_LOGIC; | |
45 | reset : in STD_LOGIC; |
|
48 | reset : in STD_LOGIC; | |
46 | apbi : in apb_slv_in_type; |
|
49 | apbi : in apb_slv_in_type; | |
47 | apbo : out apb_slv_out_type; |
|
50 | apbo : out apb_slv_out_type; | |
48 | AD_in : in AD7688_in(ChanelCount-1 downto 0); |
|
51 | AD_in : in AD7688_in(ChanelCount-1 downto 0); | |
49 | AD_out : out AD7688_out); |
|
52 | AD_out : out AD7688_out); | |
50 | end lpp_apb_ad_conv; |
|
53 | end lpp_apb_ad_conv; | |
51 |
|
54 | |||
52 |
|
55 | |||
53 | architecture ar_lpp_apb_ad_conv of lpp_apb_ad_conv is |
|
56 | architecture ar_lpp_apb_ad_conv of lpp_apb_ad_conv is | |
54 | constant REVISION : integer := 1; |
|
57 | constant REVISION : integer := 1; | |
55 |
|
58 | |||
56 | constant pconfig : apb_config_type := ( |
|
59 | constant pconfig : apb_config_type := ( | |
57 | 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADC, 0, REVISION, 0), |
|
60 | 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADC, 0, REVISION, 0), | |
58 | 1 => apb_iobar(paddr, pmask)); |
|
61 | 1 => apb_iobar(paddr, pmask)); | |
59 |
|
62 | |||
60 | signal Rdata : std_logic_vector(31 downto 0); |
|
63 | signal Rdata : std_logic_vector(31 downto 0); | |
61 | signal smpout : Samples_out(ChanelCount-1 downto 0); |
|
64 | signal smpout : Samples_out(ChanelCount-1 downto 0); | |
62 | signal smplClk : STD_LOGIC; |
|
65 | signal smplClk : STD_LOGIC; | |
63 | signal DataReady : STD_LOGIC; |
|
66 | signal DataReady : STD_LOGIC; | |
64 |
|
67 | |||
65 | type lpp_apb_ad_conv_Reg is record |
|
68 | type lpp_apb_ad_conv_Reg is record | |
66 | CTRL_Reg : std_logic_vector(31 downto 0); |
|
69 | CTRL_Reg : std_logic_vector(31 downto 0); | |
67 | sample : Samples_out(ChanelCount-1 downto 0); |
|
70 | sample : Samples_out(ChanelCount-1 downto 0); | |
68 | end record; |
|
71 | end record; | |
69 |
|
72 | |||
70 | signal r : lpp_apb_ad_conv_Reg; |
|
73 | signal r : lpp_apb_ad_conv_Reg; | |
71 |
|
74 | |||
72 | begin |
|
75 | begin | |
73 |
|
76 | |||
74 |
|
77 | |||
75 | caseAD7688: if ADCref = AD7688 generate |
|
78 | caseAD7688: if ADCref = AD7688 generate | |
76 | AD7688: AD7688_drvr |
|
79 | AD7688: AD7688_drvr | |
77 | generic map(ChanelCount,clkkHz) |
|
80 | generic map(ChanelCount,clkkHz) | |
78 | Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out); |
|
81 | Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out); | |
79 | end generate; |
|
82 | end generate; | |
80 |
|
83 | |||
81 | caseADS786: if ADCref = ADS7886 generate |
|
84 | caseADS786: if ADCref = ADS7886 generate | |
82 | ADS7886: ADS7886_drvr |
|
85 | ADS7886: ADS7886_drvr | |
83 | generic map(ChanelCount,clkkHz) |
|
86 | generic map(ChanelCount,clkkHz) | |
84 | Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out); |
|
87 | Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out); | |
85 | end generate; |
|
88 | end generate; | |
86 |
|
89 | |||
87 |
|
90 | |||
88 | clkdivider: Clk_divider |
|
91 | clkdivider: Clk_divider | |
89 | generic map(clkkHz*1000,smpClkHz) |
|
92 | generic map(clkkHz*1000,smpClkHz) | |
90 | Port map( clk ,reset,smplClk); |
|
93 | Port map( clk ,reset,smplClk); | |
91 |
|
94 | |||
92 |
|
95 | |||
93 |
|
96 | |||
94 | r.CTRL_Reg(0) <= DataReady; |
|
97 | r.CTRL_Reg(0) <= DataReady; | |
95 |
|
98 | |||
96 | r.sample <= smpout; |
|
99 | r.sample <= smpout; | |
97 |
|
100 | |||
98 |
|
101 | |||
99 | process(reset,clk) |
|
102 | process(reset,clk) | |
100 | begin |
|
103 | begin | |
101 | if reset = '0' then |
|
104 | if reset = '0' then | |
102 | --r.CTRL_Reg(9 downto 0) <= (others => '0'); |
|
105 | --r.CTRL_Reg(9 downto 0) <= (others => '0'); | |
103 | elsif clk'event and clk = '1' then |
|
106 | elsif clk'event and clk = '1' then | |
104 |
|
107 | |||
105 | --APB Write OP |
|
108 | --APB Write OP | |
106 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
109 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
107 | case apbi.paddr(7 downto 2) is |
|
110 | case apbi.paddr(7 downto 2) is | |
108 | when "000000" => |
|
111 | when "000000" => | |
109 | --r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0); |
|
112 | --r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0); | |
110 | when others => |
|
113 | when others => | |
111 | end case; |
|
114 | end case; | |
112 | end if; |
|
115 | end if; | |
113 |
|
116 | |||
114 | --APB READ OP |
|
117 | --APB READ OP | |
115 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
118 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
116 | case apbi.paddr(7 downto 2) is |
|
119 | case apbi.paddr(7 downto 2) is | |
117 | when "000000" => |
|
120 | when "000000" => | |
118 | Rdata <= r.CTRL_Reg; |
|
121 | Rdata <= r.CTRL_Reg; | |
119 | when others => |
|
122 | when others => | |
120 | readC: for i in 1 to ChanelCount loop |
|
123 | readC: for i in 1 to ChanelCount loop | |
121 | if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then |
|
124 | if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then | |
122 | Rdata(15 downto 0) <= r.sample(i-1)(15 downto 0); |
|
125 | Rdata(15 downto 0) <= r.sample(i-1)(15 downto 0); | |
123 | end if; |
|
126 | end if; | |
124 | end loop; |
|
127 | end loop; | |
125 | end case; |
|
128 | end case; | |
126 | end if; |
|
129 | end if; | |
127 | end if; |
|
130 | end if; | |
128 | apbo.pconfig <= pconfig; |
|
131 | apbo.pconfig <= pconfig; | |
129 | end process; |
|
132 | end process; | |
130 |
|
133 | |||
131 | apbo.prdata <= Rdata when apbi.penable = '1' ; |
|
134 | apbo.prdata <= Rdata when apbi.penable = '1' ; | |
132 |
|
135 | |||
133 |
|
136 | |||
134 | end ar_lpp_apb_ad_conv; |
|
137 | end ar_lpp_apb_ad_conv; | |
135 |
|
138 | |||
136 |
|
139 | |||
137 |
|
140 | |||
138 |
|
141 | |||
139 |
|
142 | |||
140 |
|
143 | |||
141 |
|
144 | |||
142 |
|
145 | |||
143 |
|
146 |
@@ -1,127 +1,130 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library ieee; |
|
22 | library ieee; | |
20 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
21 | --use ieee.numeric_std.all; |
|
24 | --use ieee.numeric_std.all; | |
22 | library grlib; |
|
25 | library grlib; | |
23 | use grlib.amba.all; |
|
26 | use grlib.amba.all; | |
24 | use grlib.stdlib.all; |
|
27 | use grlib.stdlib.all; | |
25 | use grlib.devices.all; |
|
28 | use grlib.devices.all; | |
26 | library lpp; |
|
29 | library lpp; | |
27 | use lpp.lpp_amba.all; |
|
30 | use lpp.lpp_amba.all; | |
28 |
|
31 | |||
29 |
|
32 | |||
30 | entity APB_SIMPLE_DIODE is |
|
33 | entity APB_SIMPLE_DIODE is | |
31 | generic ( |
|
34 | generic ( | |
32 | pindex : integer := 0; |
|
35 | pindex : integer := 0; | |
33 | paddr : integer := 0; |
|
36 | paddr : integer := 0; | |
34 | pmask : integer := 16#fff#; |
|
37 | pmask : integer := 16#fff#; | |
35 | pirq : integer := 0; |
|
38 | pirq : integer := 0; | |
36 | abits : integer := 8); |
|
39 | abits : integer := 8); | |
37 | port ( |
|
40 | port ( | |
38 | rst : in std_ulogic; |
|
41 | rst : in std_ulogic; | |
39 | clk : in std_ulogic; |
|
42 | clk : in std_ulogic; | |
40 | apbi : in apb_slv_in_type; |
|
43 | apbi : in apb_slv_in_type; | |
41 | apbo : out apb_slv_out_type; |
|
44 | apbo : out apb_slv_out_type; | |
42 | LED : out std_ulogic |
|
45 | LED : out std_ulogic | |
43 | ); |
|
46 | ); | |
44 | end; |
|
47 | end; | |
45 |
|
48 | |||
46 |
|
49 | |||
47 | architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is |
|
50 | architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is | |
48 |
|
51 | |||
49 | constant REVISION : integer := 1; |
|
52 | constant REVISION : integer := 1; | |
50 |
|
53 | |||
51 | constant pconfig : apb_config_type := ( |
|
54 | constant pconfig : apb_config_type := ( | |
52 | 0 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0), |
|
55 | 0 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0), | |
53 | 1 => apb_iobar(paddr, pmask)); |
|
56 | 1 => apb_iobar(paddr, pmask)); | |
54 |
|
57 | |||
55 |
|
58 | |||
56 |
|
59 | |||
57 | type LEDregs is record |
|
60 | type LEDregs is record | |
58 | DATAin : std_logic_vector(31 downto 0); |
|
61 | DATAin : std_logic_vector(31 downto 0); | |
59 | DATAout : std_logic_vector(31 downto 0); |
|
62 | DATAout : std_logic_vector(31 downto 0); | |
60 | end record; |
|
63 | end record; | |
61 |
|
64 | |||
62 | signal r : LEDregs; |
|
65 | signal r : LEDregs; | |
63 | signal Rdata : std_logic_vector(31 downto 0); |
|
66 | signal Rdata : std_logic_vector(31 downto 0); | |
64 |
|
67 | |||
65 | begin |
|
68 | begin | |
66 |
|
69 | |||
67 | r.DATAout <= r.DATAin xor X"FFFFFFFF"; |
|
70 | r.DATAout <= r.DATAin xor X"FFFFFFFF"; | |
68 |
|
71 | |||
69 | process(rst,clk) |
|
72 | process(rst,clk) | |
70 | begin |
|
73 | begin | |
71 | if rst = '0' then |
|
74 | if rst = '0' then | |
72 | LED <= '0'; |
|
75 | LED <= '0'; | |
73 | r.DATAin <= (others => '0'); |
|
76 | r.DATAin <= (others => '0'); | |
74 |
|
77 | |||
75 | elsif clk'event and clk = '1' then |
|
78 | elsif clk'event and clk = '1' then | |
76 |
|
79 | |||
77 | LED <= r.DATAin(0); |
|
80 | LED <= r.DATAin(0); | |
78 |
|
81 | |||
79 | --APB Write OP |
|
82 | --APB Write OP | |
80 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
83 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
81 | case apbi.paddr(abits-1 downto 2) is |
|
84 | case apbi.paddr(abits-1 downto 2) is | |
82 | when "000000" => |
|
85 | when "000000" => | |
83 | r.DATAin <= apbi.pwdata; |
|
86 | r.DATAin <= apbi.pwdata; | |
84 | when others => |
|
87 | when others => | |
85 | null; |
|
88 | null; | |
86 | end case; |
|
89 | end case; | |
87 | end if; |
|
90 | end if; | |
88 |
|
91 | |||
89 | --APB READ OP |
|
92 | --APB READ OP | |
90 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
93 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
91 | case apbi.paddr(abits-1 downto 2) is |
|
94 | case apbi.paddr(abits-1 downto 2) is | |
92 | when "000000" => |
|
95 | when "000000" => | |
93 | Rdata <= r.DATAin; |
|
96 | Rdata <= r.DATAin; | |
94 | when others => |
|
97 | when others => | |
95 | Rdata <= r.DATAout; |
|
98 | Rdata <= r.DATAout; | |
96 | end case; |
|
99 | end case; | |
97 | end if; |
|
100 | end if; | |
98 |
|
101 | |||
99 | end if; |
|
102 | end if; | |
100 | apbo.pconfig <= pconfig; |
|
103 | apbo.pconfig <= pconfig; | |
101 | end process; |
|
104 | end process; | |
102 |
|
105 | |||
103 | apbo.prdata <= Rdata when apbi.penable = '1'; |
|
106 | apbo.prdata <= Rdata when apbi.penable = '1'; | |
104 |
|
107 | |||
105 | -- pragma translate_off |
|
108 | -- pragma translate_off | |
106 | -- bootmsg : report_version |
|
109 | -- bootmsg : report_version | |
107 | -- generic map ("apbuart" & tost(pindex) & |
|
110 | -- generic map ("apbuart" & tost(pindex) & | |
108 | -- ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) & |
|
111 | -- ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) & | |
109 | -- ", irq " & tost(pirq)); |
|
112 | -- ", irq " & tost(pirq)); | |
110 | -- pragma translate_on |
|
113 | -- pragma translate_on | |
111 |
|
114 | |||
112 |
|
115 | |||
113 |
|
116 | |||
114 | end ar_APB_SIMPLE_DIODE; |
|
117 | end ar_APB_SIMPLE_DIODE; | |
115 |
|
118 | |||
116 |
|
119 | |||
117 |
|
120 | |||
118 |
|
121 | |||
119 |
|
122 | |||
120 |
|
123 | |||
121 |
|
124 | |||
122 |
|
125 | |||
123 |
|
126 | |||
124 |
|
127 | |||
125 |
|
128 | |||
126 |
|
129 | |||
127 |
|
130 |
@@ -1,79 +1,82 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library ieee; |
|
22 | library ieee; | |
20 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
21 | library grlib; |
|
24 | library grlib; | |
22 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
23 | use std.textio.all; |
|
26 | use std.textio.all; | |
24 |
|
27 | |||
25 |
|
28 | |||
26 |
|
29 | |||
27 | package lpp_amba is |
|
30 | package lpp_amba is | |
28 |
|
31 | |||
29 | component APB_CHENILLARD is |
|
32 | component APB_CHENILLARD is | |
30 | generic ( |
|
33 | generic ( | |
31 | pindex : integer := 0; |
|
34 | pindex : integer := 0; | |
32 | paddr : integer := 0; |
|
35 | paddr : integer := 0; | |
33 | pmask : integer := 16#fff#; |
|
36 | pmask : integer := 16#fff#; | |
34 | pirq : integer := 0; |
|
37 | pirq : integer := 0; | |
35 | abits : integer := 8); |
|
38 | abits : integer := 8); | |
36 | port ( |
|
39 | port ( | |
37 | rst : in std_ulogic; |
|
40 | rst : in std_ulogic; | |
38 | clk : in std_ulogic; |
|
41 | clk : in std_ulogic; | |
39 | RegLed : in std_logic_vector (7 downto 0); |
|
42 | RegLed : in std_logic_vector (7 downto 0); | |
40 | apbi : in apb_slv_in_type; |
|
43 | apbi : in apb_slv_in_type; | |
41 | apbo : out apb_slv_out_type; |
|
44 | apbo : out apb_slv_out_type; | |
42 | Leds : out std_logic_vector (7 downto 0) |
|
45 | Leds : out std_logic_vector (7 downto 0) | |
43 | ); |
|
46 | ); | |
44 | end component; |
|
47 | end component; | |
45 |
|
48 | |||
46 | component APB_SIMPLE_DIODE is |
|
49 | component APB_SIMPLE_DIODE is | |
47 | generic ( |
|
50 | generic ( | |
48 | pindex : integer := 0; |
|
51 | pindex : integer := 0; | |
49 | paddr : integer := 0; |
|
52 | paddr : integer := 0; | |
50 | pmask : integer := 16#fff#; |
|
53 | pmask : integer := 16#fff#; | |
51 | pirq : integer := 0; |
|
54 | pirq : integer := 0; | |
52 | abits : integer := 8); |
|
55 | abits : integer := 8); | |
53 | port ( |
|
56 | port ( | |
54 | rst : in std_ulogic; |
|
57 | rst : in std_ulogic; | |
55 | clk : in std_ulogic; |
|
58 | clk : in std_ulogic; | |
56 | apbi : in apb_slv_in_type; |
|
59 | apbi : in apb_slv_in_type; | |
57 | apbo : out apb_slv_out_type; |
|
60 | apbo : out apb_slv_out_type; | |
58 | LED : out std_ulogic |
|
61 | LED : out std_ulogic | |
59 | ); |
|
62 | ); | |
60 | end component; |
|
63 | end component; | |
61 |
|
64 | |||
62 |
|
65 | |||
63 | component APB_MULTI_DIODE is |
|
66 | component APB_MULTI_DIODE is | |
64 | generic ( |
|
67 | generic ( | |
65 | pindex : integer := 0; |
|
68 | pindex : integer := 0; | |
66 | paddr : integer := 0; |
|
69 | paddr : integer := 0; | |
67 | pmask : integer := 16#fff#; |
|
70 | pmask : integer := 16#fff#; | |
68 | pirq : integer := 0; |
|
71 | pirq : integer := 0; | |
69 | abits : integer := 8); |
|
72 | abits : integer := 8); | |
70 | port ( |
|
73 | port ( | |
71 | rst : in std_ulogic; |
|
74 | rst : in std_ulogic; | |
72 | clk : in std_ulogic; |
|
75 | clk : in std_ulogic; | |
73 | apbi : in apb_slv_in_type; |
|
76 | apbi : in apb_slv_in_type; | |
74 | apbo : out apb_slv_out_type; |
|
77 | apbo : out apb_slv_out_type; | |
75 | LED : out std_logic_vector(2 downto 0) |
|
78 | LED : out std_logic_vector(2 downto 0) | |
76 | ); |
|
79 | ); | |
77 | end component; |
|
80 | end component; | |
78 |
|
81 | |||
79 | end; |
|
82 | end; |
@@ -1,5 +1,6 | |||||
|
1 | apb_devices_list.vhd | |||
1 | APB_MULTI_DIODE.vhd |
|
2 | APB_MULTI_DIODE.vhd | |
2 | APB_MULTI_DIODE.vhd.orig |
|
3 | APB_MULTI_DIODE.vhd.orig | |
3 | APB_SIMPLE_DIODE.vhd |
|
4 | APB_SIMPLE_DIODE.vhd | |
4 | APB_SIMPLE_DIODE.vhd.orig |
|
5 | APB_SIMPLE_DIODE.vhd.orig | |
5 | lpp_amba.vhd |
|
6 | lpp_amba.vhd |
@@ -1,101 +1,119 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
1 | -- APB_CNA.vhd |
|
19 | -- APB_CNA.vhd | |
2 |
|
20 | |||
3 | library ieee; |
|
21 | library ieee; | |
4 | use ieee.std_logic_1164.all; |
|
22 | use ieee.std_logic_1164.all; | |
5 | library grlib; |
|
23 | library grlib; | |
6 | use grlib.amba.all; |
|
24 | use grlib.amba.all; | |
7 | use grlib.stdlib.all; |
|
25 | use grlib.stdlib.all; | |
8 | use grlib.devices.all; |
|
26 | use grlib.devices.all; | |
9 | library lpp; |
|
27 | library lpp; | |
10 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
11 | use lpp.apb_devices_list.all; |
|
29 | use lpp.apb_devices_list.all; | |
12 | use lpp.lpp_cna.all; |
|
30 | use lpp.lpp_cna.all; | |
13 |
|
31 | |||
14 |
|
32 | |||
15 | entity APB_CNA is |
|
33 | entity APB_CNA is | |
16 | generic ( |
|
34 | generic ( | |
17 | pindex : integer := 0; |
|
35 | pindex : integer := 0; | |
18 | paddr : integer := 0; |
|
36 | paddr : integer := 0; | |
19 | pmask : integer := 16#fff#; |
|
37 | pmask : integer := 16#fff#; | |
20 | pirq : integer := 0; |
|
38 | pirq : integer := 0; | |
21 | abits : integer := 8); |
|
39 | abits : integer := 8); | |
22 | port ( |
|
40 | port ( | |
23 | clk : in std_logic; |
|
41 | clk : in std_logic; | |
24 | rst : in std_logic; |
|
42 | rst : in std_logic; | |
25 | apbi : in apb_slv_in_type; |
|
43 | apbi : in apb_slv_in_type; | |
26 | apbo : out apb_slv_out_type; |
|
44 | apbo : out apb_slv_out_type; | |
27 | SYNC : out std_logic; |
|
45 | SYNC : out std_logic; | |
28 | SCLK : out std_logic; |
|
46 | SCLK : out std_logic; | |
29 | DATA : out std_logic |
|
47 | DATA : out std_logic | |
30 | ); |
|
48 | ); | |
31 | end APB_CNA; |
|
49 | end APB_CNA; | |
32 |
|
50 | |||
33 |
|
51 | |||
34 | architecture ar_APB_CNA of APB_CNA is |
|
52 | architecture ar_APB_CNA of APB_CNA is | |
35 |
|
53 | |||
36 | constant REVISION : integer := 1; |
|
54 | constant REVISION : integer := 1; | |
37 |
|
55 | |||
38 | constant pconfig : apb_config_type := ( |
|
56 | constant pconfig : apb_config_type := ( | |
39 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), |
|
57 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), | |
40 | 1 => apb_iobar(paddr, pmask)); |
|
58 | 1 => apb_iobar(paddr, pmask)); | |
41 |
|
59 | |||
42 | signal enable : std_logic; |
|
60 | signal enable : std_logic; | |
43 | signal flag_sd : std_logic; |
|
61 | signal flag_sd : std_logic; | |
44 |
|
62 | |||
45 | type CNA_ctrlr_Reg is record |
|
63 | type CNA_ctrlr_Reg is record | |
46 | CNA_Cfg : std_logic_vector(1 downto 0); |
|
64 | CNA_Cfg : std_logic_vector(1 downto 0); | |
47 | CNA_Data : std_logic_vector(15 downto 0); |
|
65 | CNA_Data : std_logic_vector(15 downto 0); | |
48 | end record; |
|
66 | end record; | |
49 |
|
67 | |||
50 | signal Rec : CNA_ctrlr_Reg; |
|
68 | signal Rec : CNA_ctrlr_Reg; | |
51 | signal Rdata : std_logic_vector(31 downto 0); |
|
69 | signal Rdata : std_logic_vector(31 downto 0); | |
52 |
|
70 | |||
53 | begin |
|
71 | begin | |
54 |
|
72 | |||
55 | enable <= Rec.CNA_Cfg(0); |
|
73 | enable <= Rec.CNA_Cfg(0); | |
56 | Rec.CNA_Cfg(1) <= flag_sd; |
|
74 | Rec.CNA_Cfg(1) <= flag_sd; | |
57 |
|
75 | |||
58 | CONVERTER : entity Work.CNA_TabloC |
|
76 | CONVERTER : entity Work.CNA_TabloC | |
59 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); |
|
77 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); | |
60 |
|
78 | |||
61 |
|
79 | |||
62 | process(rst,clk) |
|
80 | process(rst,clk) | |
63 | begin |
|
81 | begin | |
64 | if(rst='0')then |
|
82 | if(rst='0')then | |
65 | Rec.CNA_Data <= (others => '0'); |
|
83 | Rec.CNA_Data <= (others => '0'); | |
66 |
|
84 | |||
67 | elsif(clk'event and clk='1')then |
|
85 | elsif(clk'event and clk='1')then | |
68 |
|
86 | |||
69 |
|
87 | |||
70 | --APB Write OP |
|
88 | --APB Write OP | |
71 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
89 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
72 | case apbi.paddr(abits-1 downto 2) is |
|
90 | case apbi.paddr(abits-1 downto 2) is | |
73 | when "000000" => |
|
91 | when "000000" => | |
74 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); |
|
92 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); | |
75 | when "000001" => |
|
93 | when "000001" => | |
76 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); |
|
94 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); | |
77 | when others => |
|
95 | when others => | |
78 | null; |
|
96 | null; | |
79 | end case; |
|
97 | end case; | |
80 | end if; |
|
98 | end if; | |
81 |
|
99 | |||
82 | --APB READ OP |
|
100 | --APB READ OP | |
83 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
101 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
84 | case apbi.paddr(abits-1 downto 2) is |
|
102 | case apbi.paddr(abits-1 downto 2) is | |
85 | when "000000" => |
|
103 | when "000000" => | |
86 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; |
|
104 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; | |
87 | Rdata(1 downto 0) <= Rec.CNA_Cfg; |
|
105 | Rdata(1 downto 0) <= Rec.CNA_Cfg; | |
88 | when "000001" => |
|
106 | when "000001" => | |
89 | Rdata(31 downto 16) <= X"FD18"; |
|
107 | Rdata(31 downto 16) <= X"FD18"; | |
90 | Rdata(15 downto 0) <= Rec.CNA_Data; |
|
108 | Rdata(15 downto 0) <= Rec.CNA_Data; | |
91 | when others => |
|
109 | when others => | |
92 | Rdata <= (others => '0'); |
|
110 | Rdata <= (others => '0'); | |
93 | end case; |
|
111 | end case; | |
94 | end if; |
|
112 | end if; | |
95 |
|
113 | |||
96 | end if; |
|
114 | end if; | |
97 | apbo.pconfig <= pconfig; |
|
115 | apbo.pconfig <= pconfig; | |
98 | end process; |
|
116 | end process; | |
99 |
|
117 | |||
100 | apbo.prdata <= Rdata when apbi.penable = '1'; |
|
118 | apbo.prdata <= Rdata when apbi.penable = '1'; | |
101 | end ar_APB_CNA; |
|
119 | end ar_APB_CNA; |
@@ -1,67 +1,85 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
1 | -- CNA_TabloC.vhd |
|
19 | -- CNA_TabloC.vhd | |
2 | library IEEE; |
|
20 | library IEEE; | |
3 | use IEEE.std_logic_1164.all; |
|
21 | use IEEE.std_logic_1164.all; | |
4 | use IEEE.numeric_std.all; |
|
22 | use IEEE.numeric_std.all; | |
5 | use work.Convertisseur_config.all; |
|
23 | use work.Convertisseur_config.all; | |
6 |
|
24 | |||
7 | entity CNA_TabloC is |
|
25 | entity CNA_TabloC is | |
8 | port( |
|
26 | port( | |
9 | clock : in std_logic; |
|
27 | clock : in std_logic; | |
10 | rst : in std_logic; |
|
28 | rst : in std_logic; | |
11 | enable : in std_logic; |
|
29 | enable : in std_logic; | |
12 | --bp : in std_logic; |
|
30 | --bp : in std_logic; | |
13 | Data_C : in std_logic_vector(15 downto 0); |
|
31 | Data_C : in std_logic_vector(15 downto 0); | |
14 | SYNC : out std_logic; |
|
32 | SYNC : out std_logic; | |
15 | SCLK : out std_logic; |
|
33 | SCLK : out std_logic; | |
16 | --Rz : out std_logic; |
|
34 | --Rz : out std_logic; | |
17 | flag_sd : out std_logic; |
|
35 | flag_sd : out std_logic; | |
18 | Data : out std_logic |
|
36 | Data : out std_logic | |
19 | ); |
|
37 | ); | |
20 | end CNA_TabloC; |
|
38 | end CNA_TabloC; | |
21 |
|
39 | |||
22 |
|
40 | |||
23 | architecture ar_CNA_TabloC of CNA_TabloC is |
|
41 | architecture ar_CNA_TabloC of CNA_TabloC is | |
24 |
|
42 | |||
25 | component CLKINT |
|
43 | component CLKINT | |
26 | port( A : in std_logic := 'U'; |
|
44 | port( A : in std_logic := 'U'; | |
27 | Y : out std_logic); |
|
45 | Y : out std_logic); | |
28 | end component; |
|
46 | end component; | |
29 |
|
47 | |||
30 | signal clk : std_logic; |
|
48 | signal clk : std_logic; | |
31 |
|
49 | |||
32 | signal raz : std_logic; |
|
50 | signal raz : std_logic; | |
33 | signal s_SCLK : std_logic; |
|
51 | signal s_SCLK : std_logic; | |
34 | signal OKAI_send : std_logic; |
|
52 | signal OKAI_send : std_logic; | |
35 | --signal Data_int : std_logic_vector(15 downto 0); |
|
53 | --signal Data_int : std_logic_vector(15 downto 0); | |
36 |
|
54 | |||
37 | begin |
|
55 | begin | |
38 |
|
56 | |||
39 |
|
57 | |||
40 | CLKINT_0 : CLKINT |
|
58 | CLKINT_0 : CLKINT | |
41 | port map(A => clock, Y => clk); |
|
59 | port map(A => clock, Y => clk); | |
42 |
|
60 | |||
43 | CLKINT_1 : CLKINT |
|
61 | CLKINT_1 : CLKINT | |
44 | port map(A => rst, Y => raz); |
|
62 | port map(A => rst, Y => raz); | |
45 |
|
63 | |||
46 |
|
64 | |||
47 | SystemCLK : entity work.Systeme_Clock |
|
65 | SystemCLK : entity work.Systeme_Clock | |
48 | generic map (nb_serial) |
|
66 | generic map (nb_serial) | |
49 | port map (clk,raz,s_SCLK); |
|
67 | port map (clk,raz,s_SCLK); | |
50 |
|
68 | |||
51 |
|
69 | |||
52 | Signal_sync : entity work.Gene_SYNC |
|
70 | Signal_sync : entity work.Gene_SYNC | |
53 | port map (s_SCLK,raz,enable,OKAI_send,SYNC); |
|
71 | port map (s_SCLK,raz,enable,OKAI_send,SYNC); | |
54 |
|
72 | |||
55 |
|
73 | |||
56 | Serial : entity work.serialize |
|
74 | Serial : entity work.serialize | |
57 | port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data); |
|
75 | port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
58 |
|
76 | |||
59 |
|
77 | |||
60 | --Rz <= raz; |
|
78 | --Rz <= raz; | |
61 | SCLK <= s_SCLK; |
|
79 | SCLK <= s_SCLK; | |
62 |
|
80 | |||
63 | --with bp select |
|
81 | --with bp select | |
64 | -- Data_int <= X"9555" when '1', |
|
82 | -- Data_int <= X"9555" when '1', | |
65 | -- Data_C when others; |
|
83 | -- Data_C when others; | |
66 |
|
84 | |||
67 | end ar_CNA_TabloC; No newline at end of file |
|
85 | end ar_CNA_TabloC; |
@@ -1,24 +1,42 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
1 | -- Convertisseur_config.vhd |
|
19 | -- Convertisseur_config.vhd | |
2 | library IEEE; |
|
20 | library IEEE; | |
3 | use IEEE.std_logic_1164.all; |
|
21 | use IEEE.std_logic_1164.all; | |
4 | use IEEE.numeric_std.all; |
|
22 | use IEEE.numeric_std.all; | |
5 |
|
23 | |||
6 | Package Convertisseur_config is |
|
24 | Package Convertisseur_config is | |
7 |
|
25 | |||
8 |
|
26 | |||
9 | --===========================================================| |
|
27 | --===========================================================| | |
10 | --================= Valeurs Sinus 1Khz ======================| |
|
28 | --================= Valeurs Sinus 1Khz ======================| | |
11 | --===========================================================| |
|
29 | --===========================================================| | |
12 | type Tbl is array(natural range <>) of std_logic_vector(11 downto 0); |
|
30 | type Tbl is array(natural range <>) of std_logic_vector(11 downto 0); | |
13 | constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF"); |
|
31 | constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF"); | |
14 |
|
32 | |||
15 | --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80"); |
|
33 | --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80"); | |
16 |
|
34 | |||
17 |
|
35 | |||
18 | --===========================================================| |
|
36 | --===========================================================| | |
19 | --============= Fr�quence de s�rialisation ==================| |
|
37 | --============= Fr�quence de s�rialisation ==================| | |
20 | --===========================================================| |
|
38 | --===========================================================| | |
21 | constant Freq_serial : integer := 5_000_000; |
|
39 | constant Freq_serial : integer := 5_000_000; | |
22 | constant nb_serial : integer := 30_000_000 / Freq_serial; |
|
40 | constant nb_serial : integer := 30_000_000 / Freq_serial; | |
23 |
|
41 | |||
24 | end; No newline at end of file |
|
42 | end; |
@@ -1,53 +1,71 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
1 | -- Gene_SYNC.vhd |
|
19 | -- Gene_SYNC.vhd | |
2 | library IEEE; |
|
20 | library IEEE; | |
3 | use IEEE.std_logic_1164.all; |
|
21 | use IEEE.std_logic_1164.all; | |
4 | use IEEE.numeric_std.all; |
|
22 | use IEEE.numeric_std.all; | |
5 |
|
23 | |||
6 | entity Gene_SYNC is |
|
24 | entity Gene_SYNC is | |
7 |
|
25 | |||
8 | port( |
|
26 | port( | |
9 | SCLK,raz : in std_logic; |
|
27 | SCLK,raz : in std_logic; | |
10 | enable : in std_logic; |
|
28 | enable : in std_logic; | |
11 | -- Sysclk : in std_logic; |
|
29 | -- Sysclk : in std_logic; | |
12 | OKAI_send : out std_logic; |
|
30 | OKAI_send : out std_logic; | |
13 | SYNC : out std_logic |
|
31 | SYNC : out std_logic | |
14 | ); |
|
32 | ); | |
15 |
|
33 | |||
16 | end Gene_SYNC; |
|
34 | end Gene_SYNC; | |
17 |
|
35 | |||
18 |
|
36 | |||
19 | architecture ar_Gene_SYNC of Gene_SYNC is |
|
37 | architecture ar_Gene_SYNC of Gene_SYNC is | |
20 |
|
38 | |||
21 | --signal Sysclk_reg : std_logic; |
|
39 | --signal Sysclk_reg : std_logic; | |
22 | signal count : integer; |
|
40 | signal count : integer; | |
23 |
|
41 | |||
24 |
|
42 | |||
25 | begin |
|
43 | begin | |
26 | process (SCLK,raz) |
|
44 | process (SCLK,raz) | |
27 | begin |
|
45 | begin | |
28 | if(raz='0')then |
|
46 | if(raz='0')then | |
29 | SYNC <= '0'; |
|
47 | SYNC <= '0'; | |
30 | -- Sysclk_reg <= '0'; |
|
48 | -- Sysclk_reg <= '0'; | |
31 | count <= 14; |
|
49 | count <= 14; | |
32 | OKAI_send <= '0'; |
|
50 | OKAI_send <= '0'; | |
33 |
|
51 | |||
34 | elsif(SCLK' event and SCLK='1')then |
|
52 | elsif(SCLK' event and SCLK='1')then | |
35 | if(enable='1')then |
|
53 | if(enable='1')then | |
36 |
|
54 | |||
37 | -- Sysclk_reg <= Sysclk; |
|
55 | -- Sysclk_reg <= Sysclk; | |
38 | if(count=15)then |
|
56 | if(count=15)then | |
39 | SYNC <= '1'; |
|
57 | SYNC <= '1'; | |
40 | count <= count+1; |
|
58 | count <= count+1; | |
41 | elsif(count=16)then |
|
59 | elsif(count=16)then | |
42 | count <= 0; |
|
60 | count <= 0; | |
43 | SYNC <= '0'; |
|
61 | SYNC <= '0'; | |
44 | OKAI_send <= '1'; |
|
62 | OKAI_send <= '1'; | |
45 | else |
|
63 | else | |
46 | count <= count+1; |
|
64 | count <= count+1; | |
47 | OKAI_send <= '0'; |
|
65 | OKAI_send <= '0'; | |
48 | end if; |
|
66 | end if; | |
49 | end if; |
|
67 | end if; | |
50 | end if; |
|
68 | end if; | |
51 | end process; |
|
69 | end process; | |
52 |
|
70 | |||
53 | end ar_Gene_SYNC; No newline at end of file |
|
71 | end ar_Gene_SYNC; |
@@ -1,86 +1,104 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
1 | -- Serialize.vhd |
|
19 | -- Serialize.vhd | |
2 | library IEEE; |
|
20 | library IEEE; | |
3 | use IEEE.numeric_std.all; |
|
21 | use IEEE.numeric_std.all; | |
4 | use IEEE.std_logic_1164.all; |
|
22 | use IEEE.std_logic_1164.all; | |
5 |
|
23 | |||
6 | entity Serialize is |
|
24 | entity Serialize is | |
7 |
|
25 | |||
8 | port( |
|
26 | port( | |
9 | clk,raz : in std_logic; |
|
27 | clk,raz : in std_logic; | |
10 | sclk : in std_logic; |
|
28 | sclk : in std_logic; | |
11 | vectin : in std_logic_vector(15 downto 0); |
|
29 | vectin : in std_logic_vector(15 downto 0); | |
12 | send : in std_logic; |
|
30 | send : in std_logic; | |
13 | sended : out std_logic; |
|
31 | sended : out std_logic; | |
14 | Data : out std_logic); |
|
32 | Data : out std_logic); | |
15 |
|
33 | |||
16 | end Serialize; |
|
34 | end Serialize; | |
17 |
|
35 | |||
18 |
|
36 | |||
19 | architecture ar_Serialize of Serialize is |
|
37 | architecture ar_Serialize of Serialize is | |
20 |
|
38 | |||
21 | type etat is (attente,serialize); |
|
39 | type etat is (attente,serialize); | |
22 | signal ect : etat; |
|
40 | signal ect : etat; | |
23 |
|
41 | |||
24 | signal vector_int : std_logic_vector(16 downto 0); |
|
42 | signal vector_int : std_logic_vector(16 downto 0); | |
25 | signal vectin_reg : std_logic_vector(15 downto 0); |
|
43 | signal vectin_reg : std_logic_vector(15 downto 0); | |
26 | signal load : std_logic; |
|
44 | signal load : std_logic; | |
27 | signal N : integer range 0 to 16; |
|
45 | signal N : integer range 0 to 16; | |
28 | signal CPT_ended : std_logic:='0'; |
|
46 | signal CPT_ended : std_logic:='0'; | |
29 |
|
47 | |||
30 | begin |
|
48 | begin | |
31 | process(clk,raz) |
|
49 | process(clk,raz) | |
32 | begin |
|
50 | begin | |
33 | if(raz='0')then |
|
51 | if(raz='0')then | |
34 | ect <= attente; |
|
52 | ect <= attente; | |
35 | vectin_reg <= (others=> '0'); |
|
53 | vectin_reg <= (others=> '0'); | |
36 | load <= '0'; |
|
54 | load <= '0'; | |
37 | sended <= '1'; |
|
55 | sended <= '1'; | |
38 |
|
56 | |||
39 | elsif(clk'event and clk='1')then |
|
57 | elsif(clk'event and clk='1')then | |
40 | vectin_reg <= vectin; |
|
58 | vectin_reg <= vectin; | |
41 |
|
59 | |||
42 | case ect is |
|
60 | case ect is | |
43 | when attente => |
|
61 | when attente => | |
44 | if (send='1') then |
|
62 | if (send='1') then | |
45 | sended <= '0'; |
|
63 | sended <= '0'; | |
46 | load <= '1'; |
|
64 | load <= '1'; | |
47 | ect <= serialize; |
|
65 | ect <= serialize; | |
48 | else |
|
66 | else | |
49 | ect <= attente; |
|
67 | ect <= attente; | |
50 | end if; |
|
68 | end if; | |
51 |
|
69 | |||
52 | when serialize => |
|
70 | when serialize => | |
53 | load <= '0'; |
|
71 | load <= '0'; | |
54 | if(CPT_ended='1')then |
|
72 | if(CPT_ended='1')then | |
55 | ect <= attente; |
|
73 | ect <= attente; | |
56 | sended <= '1'; |
|
74 | sended <= '1'; | |
57 | end if; |
|
75 | end if; | |
58 |
|
76 | |||
59 | end case; |
|
77 | end case; | |
60 | end if; |
|
78 | end if; | |
61 | end process; |
|
79 | end process; | |
62 |
|
80 | |||
63 | process(sclk,load,raz) |
|
81 | process(sclk,load,raz) | |
64 | begin |
|
82 | begin | |
65 | if (raz='0')then |
|
83 | if (raz='0')then | |
66 | vector_int <= (others=> '0'); |
|
84 | vector_int <= (others=> '0'); | |
67 | N <= 16; |
|
85 | N <= 16; | |
68 | elsif(load='1')then |
|
86 | elsif(load='1')then | |
69 | vector_int <= vectin & '0'; |
|
87 | vector_int <= vectin & '0'; | |
70 | N <= 0; |
|
88 | N <= 0; | |
71 | elsif(sclk'event and sclk='1')then |
|
89 | elsif(sclk'event and sclk='1')then | |
72 | if (CPT_ended='0') then |
|
90 | if (CPT_ended='0') then | |
73 | vector_int <= vector_int(15 downto 0) & '0'; |
|
91 | vector_int <= vector_int(15 downto 0) & '0'; | |
74 | N <= N+1; |
|
92 | N <= N+1; | |
75 | end if; |
|
93 | end if; | |
76 | end if; |
|
94 | end if; | |
77 | end process; |
|
95 | end process; | |
78 |
|
96 | |||
79 | CPT_ended <= '1' when N = 16 else '0'; |
|
97 | CPT_ended <= '1' when N = 16 else '0'; | |
80 |
|
98 | |||
81 | with ect select |
|
99 | with ect select | |
82 | Data <= vector_int(16) when serialize, |
|
100 | Data <= vector_int(16) when serialize, | |
83 | '0' when others; |
|
101 | '0' when others; | |
84 |
|
102 | |||
85 | end ar_Serialize; |
|
103 | end ar_Serialize; | |
86 |
|
104 |
@@ -1,40 +1,58 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
1 | -- Systeme_Clock.vhd |
|
19 | -- Systeme_Clock.vhd | |
2 | library IEEE; |
|
20 | library IEEE; | |
3 | use IEEE.std_logic_1164.all; |
|
21 | use IEEE.std_logic_1164.all; | |
4 | use IEEE.numeric_std.all; |
|
22 | use IEEE.numeric_std.all; | |
5 |
|
23 | |||
6 | --! Programme qui va permetre de g�n�rer l'horloge systeme (sclk) |
|
24 | --! Programme qui va permetre de g�n�rer l'horloge systeme (sclk) | |
7 |
|
25 | |||
8 | entity Systeme_Clock is |
|
26 | entity Systeme_Clock is | |
9 | generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk |
|
27 | generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk | |
10 | port( |
|
28 | port( | |
11 | clk, raz : in std_logic; --! Horloge et Reset globale |
|
29 | clk, raz : in std_logic; --! Horloge et Reset globale | |
12 | sclk : out std_logic --! Horloge Systeme g�n�r�e |
|
30 | sclk : out std_logic --! Horloge Systeme g�n�r�e | |
13 | ); |
|
31 | ); | |
14 | end Systeme_Clock; |
|
32 | end Systeme_Clock; | |
15 |
|
33 | |||
16 | --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois |
|
34 | --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois | |
17 | architecture ar_Systeme_Clock of Systeme_Clock is |
|
35 | architecture ar_Systeme_Clock of Systeme_Clock is | |
18 |
|
36 | |||
19 | signal clockint : std_logic; |
|
37 | signal clockint : std_logic; | |
20 | signal countint : integer range 0 to N/2-1; |
|
38 | signal countint : integer range 0 to N/2-1; | |
21 |
|
39 | |||
22 | begin |
|
40 | begin | |
23 | process (clk,raz) |
|
41 | process (clk,raz) | |
24 | begin |
|
42 | begin | |
25 | if(raz = '0') then |
|
43 | if(raz = '0') then | |
26 | countint <= 0; |
|
44 | countint <= 0; | |
27 | clockint <= '0'; |
|
45 | clockint <= '0'; | |
28 | elsif (clk' event and clk='1') then |
|
46 | elsif (clk' event and clk='1') then | |
29 | if (countint = N/2-1) then |
|
47 | if (countint = N/2-1) then | |
30 | countint <= 0; |
|
48 | countint <= 0; | |
31 | clockint <= not clockint; |
|
49 | clockint <= not clockint; | |
32 | else |
|
50 | else | |
33 | countint <= countint+1; |
|
51 | countint <= countint+1; | |
34 | end if; |
|
52 | end if; | |
35 | end if; |
|
53 | end if; | |
36 | end process; |
|
54 | end process; | |
37 |
|
55 | |||
38 | sclk <= clockint; |
|
56 | sclk <= clockint; | |
39 |
|
57 | |||
40 | end ar_Systeme_Clock; No newline at end of file |
|
58 | end ar_Systeme_Clock; |
@@ -1,77 +1,95 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
1 | library ieee; |
|
19 | library ieee; | |
2 | use ieee.std_logic_1164.all; |
|
20 | use ieee.std_logic_1164.all; | |
3 | library grlib; |
|
21 | library grlib; | |
4 | use grlib.amba.all; |
|
22 | use grlib.amba.all; | |
5 | -- pragma translate_off |
|
23 | -- pragma translate_off | |
6 | use std.textio.all; |
|
24 | use std.textio.all; | |
7 | -- pragma translate_on |
|
25 | -- pragma translate_on | |
8 | library lpp; |
|
26 | library lpp; | |
9 | use lpp.lpp_amba.all; |
|
27 | use lpp.lpp_amba.all; | |
10 |
|
28 | |||
11 |
|
29 | |||
12 | package lpp_cna is |
|
30 | package lpp_cna is | |
13 |
|
31 | |||
14 | component APB_CNA is |
|
32 | component APB_CNA is | |
15 | generic ( |
|
33 | generic ( | |
16 | pindex : integer := 0; |
|
34 | pindex : integer := 0; | |
17 | paddr : integer := 0; |
|
35 | paddr : integer := 0; | |
18 | pmask : integer := 16#fff#; |
|
36 | pmask : integer := 16#fff#; | |
19 | pirq : integer := 0; |
|
37 | pirq : integer := 0; | |
20 | abits : integer := 8); |
|
38 | abits : integer := 8); | |
21 | port ( |
|
39 | port ( | |
22 | clk : in std_logic; |
|
40 | clk : in std_logic; | |
23 | rst : in std_logic; |
|
41 | rst : in std_logic; | |
24 | apbi : in apb_slv_in_type; |
|
42 | apbi : in apb_slv_in_type; | |
25 | apbo : out apb_slv_out_type; |
|
43 | apbo : out apb_slv_out_type; | |
26 | SYNC : out std_logic; |
|
44 | SYNC : out std_logic; | |
27 | SCLK : out std_logic; |
|
45 | SCLK : out std_logic; | |
28 | DATA : out std_logic |
|
46 | DATA : out std_logic | |
29 | ); |
|
47 | ); | |
30 | end component; |
|
48 | end component; | |
31 |
|
49 | |||
32 |
|
50 | |||
33 | component CNA_TabloC is |
|
51 | component CNA_TabloC is | |
34 | port( |
|
52 | port( | |
35 | clock : in std_logic; |
|
53 | clock : in std_logic; | |
36 | rst : in std_logic; |
|
54 | rst : in std_logic; | |
37 | flag_nw : in std_logic; |
|
55 | flag_nw : in std_logic; | |
38 | bp : in std_logic; |
|
56 | bp : in std_logic; | |
39 | Data_C : in std_logic_vector(15 downto 0); |
|
57 | Data_C : in std_logic_vector(15 downto 0); | |
40 | SYNC : out std_logic; |
|
58 | SYNC : out std_logic; | |
41 | SCLK : out std_logic; |
|
59 | SCLK : out std_logic; | |
42 | Rz : out std_logic; |
|
60 | Rz : out std_logic; | |
43 | flag_sd : out std_logic; |
|
61 | flag_sd : out std_logic; | |
44 | Data : out std_logic |
|
62 | Data : out std_logic | |
45 | ); |
|
63 | ); | |
46 | end component; |
|
64 | end component; | |
47 |
|
65 | |||
48 |
|
66 | |||
49 | component Systeme_Clock is |
|
67 | component Systeme_Clock is | |
50 | generic(N :integer := 695); |
|
68 | generic(N :integer := 695); | |
51 | port( |
|
69 | port( | |
52 | clk, raz : in std_logic ; |
|
70 | clk, raz : in std_logic ; | |
53 | clock : out std_logic); |
|
71 | clock : out std_logic); | |
54 | end component; |
|
72 | end component; | |
55 |
|
73 | |||
56 |
|
74 | |||
57 | component Gene_SYNC is |
|
75 | component Gene_SYNC is | |
58 | port( |
|
76 | port( | |
59 | clk,raz : in std_logic; |
|
77 | clk,raz : in std_logic; | |
60 | send : in std_logic; |
|
78 | send : in std_logic; | |
61 | Sysclk : in std_logic; |
|
79 | Sysclk : in std_logic; | |
62 | OKAI_send : out std_logic; |
|
80 | OKAI_send : out std_logic; | |
63 | SYNC : out std_logic); |
|
81 | SYNC : out std_logic); | |
64 | end component; |
|
82 | end component; | |
65 |
|
83 | |||
66 |
|
84 | |||
67 | component Serialize is |
|
85 | component Serialize is | |
68 | port( |
|
86 | port( | |
69 | clk,raz : in std_logic; |
|
87 | clk,raz : in std_logic; | |
70 | sclk : in std_logic; |
|
88 | sclk : in std_logic; | |
71 | vectin : in std_logic_vector(15 downto 0); |
|
89 | vectin : in std_logic_vector(15 downto 0); | |
72 | send : in std_logic; |
|
90 | send : in std_logic; | |
73 | sended : out std_logic; |
|
91 | sended : out std_logic; | |
74 | Data : out std_logic); |
|
92 | Data : out std_logic); | |
75 | end component; |
|
93 | end component; | |
76 |
|
94 | |||
77 | end; |
|
95 | end; |
@@ -1,99 +1,102 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 |
|
25 | |||
23 | --! Generateur de Bauds |
|
26 | --! Generateur de Bauds | |
24 |
|
27 | |||
25 | entity BaudGen is |
|
28 | entity BaudGen is | |
26 |
|
29 | |||
27 | port( |
|
30 | port( | |
28 | clk : in std_logic; |
|
31 | clk : in std_logic; | |
29 | reset : in std_logic; |
|
32 | reset : in std_logic; | |
30 | Capture : in std_logic; |
|
33 | Capture : in std_logic; | |
31 | Bclk : out std_logic; |
|
34 | Bclk : out std_logic; | |
32 | RXD : in std_logic; |
|
35 | RXD : in std_logic; | |
33 | BTrigger : out std_logic_vector(11 downto 0) |
|
36 | BTrigger : out std_logic_vector(11 downto 0) | |
34 | ); |
|
37 | ); | |
35 | end BaudGen; |
|
38 | end BaudGen; | |
36 |
|
39 | |||
37 |
|
40 | |||
38 | architecture ar_BaudGen of BaudGen is |
|
41 | architecture ar_BaudGen of BaudGen is | |
39 | signal cpt : std_logic_vector(11 downto 0) := (others => '0'); |
|
42 | signal cpt : std_logic_vector(11 downto 0) := (others => '0'); | |
40 | signal errorFlag : std_logic; |
|
43 | signal errorFlag : std_logic; | |
41 | signal triger : std_logic_vector(11 downto 0) := (others => '0'); |
|
44 | signal triger : std_logic_vector(11 downto 0) := (others => '0'); | |
42 | signal RX_reg : std_logic:='1'; |
|
45 | signal RX_reg : std_logic:='1'; | |
43 |
|
46 | |||
44 | begin |
|
47 | begin | |
45 |
|
48 | |||
46 |
|
49 | |||
47 | BTrigger <= triger; |
|
50 | BTrigger <= triger; | |
48 |
|
51 | |||
49 |
|
52 | |||
50 | BaudGeneration: |
|
53 | BaudGeneration: | |
51 | process(clk,reset) |
|
54 | process(clk,reset) | |
52 | begin |
|
55 | begin | |
53 | if reset = '0' then |
|
56 | if reset = '0' then | |
54 | cpt <= (others => '0'); |
|
57 | cpt <= (others => '0'); | |
55 | triger <= (others => '1'); |
|
58 | triger <= (others => '1'); | |
56 | errorFlag <= '0'; |
|
59 | errorFlag <= '0'; | |
57 | elsif clk'event and clk = '1'then |
|
60 | elsif clk'event and clk = '1'then | |
58 | RX_reg <= RXD; |
|
61 | RX_reg <= RXD; | |
59 | if capture = '1' then |
|
62 | if capture = '1' then | |
60 | cpt <= (others => '0'); |
|
63 | cpt <= (others => '0'); | |
61 | triger <= (others => '1'); |
|
64 | triger <= (others => '1'); | |
62 | errorFlag <= '0'; |
|
65 | errorFlag <= '0'; | |
63 | else |
|
66 | else | |
64 | if RX_reg /= RXD then |
|
67 | if RX_reg /= RXD then | |
65 | cpt <= (others => '0'); |
|
68 | cpt <= (others => '0'); | |
66 | if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then |
|
69 | if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then | |
67 | errorFlag <= '1'; |
|
70 | errorFlag <= '1'; | |
68 | elsif errorFlag = '1' then |
|
71 | elsif errorFlag = '1' then | |
69 | triger <= cpt; |
|
72 | triger <= cpt; | |
70 | errorFlag <= '0'; |
|
73 | errorFlag <= '0'; | |
71 | else |
|
74 | else | |
72 | errorFlag <= '1'; |
|
75 | errorFlag <= '1'; | |
73 | end if; |
|
76 | end if; | |
74 | else |
|
77 | else | |
75 | if cpt = triger then |
|
78 | if cpt = triger then | |
76 | cpt <= (others => '0'); |
|
79 | cpt <= (others => '0'); | |
77 | errorFlag <= '0'; |
|
80 | errorFlag <= '0'; | |
78 | else |
|
81 | else | |
79 | cpt <= std_logic_vector(unsigned(cpt) + 1); |
|
82 | cpt <= std_logic_vector(unsigned(cpt) + 1); | |
80 | end if; |
|
83 | end if; | |
81 | end if; |
|
84 | end if; | |
82 | end if; |
|
85 | end if; | |
83 | end if; |
|
86 | end if; | |
84 | end process; |
|
87 | end process; | |
85 |
|
88 | |||
86 |
|
89 | |||
87 | process(clk) |
|
90 | process(clk) | |
88 | begin |
|
91 | begin | |
89 | if clk'event and clk = '1' then |
|
92 | if clk'event and clk = '1' then | |
90 | if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then |
|
93 | if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then | |
91 | Bclk <= '0'; |
|
94 | Bclk <= '0'; | |
92 | elsif cpt = '0' & triger(11 downto 1) then |
|
95 | elsif cpt = '0' & triger(11 downto 1) then | |
93 | Bclk <= '1'; |
|
96 | Bclk <= '1'; | |
94 | end if; |
|
97 | end if; | |
95 | end if; |
|
98 | end if; | |
96 | end process; |
|
99 | end process; | |
97 |
|
100 | |||
98 |
|
101 | |||
99 | end ar_BaudGen; |
|
102 | end ar_BaudGen; |
@@ -1,109 +1,112 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 |
|
25 | |||
23 | --! Gestion Reception/Transmission |
|
26 | --! Gestion Reception/Transmission | |
24 |
|
27 | |||
25 | entity Shift_REG is |
|
28 | entity Shift_REG is | |
26 | generic(Data_sz : integer := 10); |
|
29 | generic(Data_sz : integer := 10); | |
27 | port( |
|
30 | port( | |
28 | clk : in std_logic; |
|
31 | clk : in std_logic; | |
29 | Sclk : in std_logic; |
|
32 | Sclk : in std_logic; | |
30 | reset : in std_logic; |
|
33 | reset : in std_logic; | |
31 | SIN : in std_logic; |
|
34 | SIN : in std_logic; | |
32 | SOUT : out std_logic; |
|
35 | SOUT : out std_logic; | |
33 | Serialize : in std_logic; |
|
36 | Serialize : in std_logic; | |
34 | Serialized : out std_logic; |
|
37 | Serialized : out std_logic; | |
35 | D : in std_logic_vector(Data_sz-1 downto 0); |
|
38 | D : in std_logic_vector(Data_sz-1 downto 0); | |
36 | Q : out std_logic_vector(Data_sz-1 downto 0) |
|
39 | Q : out std_logic_vector(Data_sz-1 downto 0) | |
37 | ); |
|
40 | ); | |
38 | end entity; |
|
41 | end entity; | |
39 |
|
42 | |||
40 |
|
43 | |||
41 | architecture ar_Shift_REG of Shift_REG is |
|
44 | architecture ar_Shift_REG of Shift_REG is | |
42 |
|
45 | |||
43 | signal REG : std_logic_vector(Data_sz-1 downto 0); |
|
46 | signal REG : std_logic_vector(Data_sz-1 downto 0); | |
44 | signal Serialized_int : std_logic; |
|
47 | signal Serialized_int : std_logic; | |
45 | signal Serialize_reg : std_logic; |
|
48 | signal Serialize_reg : std_logic; | |
46 | signal CptBits : std_logic_vector(Data_sz-1 downto 0); |
|
49 | signal CptBits : std_logic_vector(Data_sz-1 downto 0); | |
47 | constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1'); |
|
50 | constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1'); | |
48 | signal CptBits_flag : std_logic; |
|
51 | signal CptBits_flag : std_logic; | |
49 | signal CptBits_flag_reg : std_logic; |
|
52 | signal CptBits_flag_reg : std_logic; | |
50 |
|
53 | |||
51 | begin |
|
54 | begin | |
52 |
|
55 | |||
53 | Serialized <= Serialized_int; |
|
56 | Serialized <= Serialized_int; | |
54 | CptBits_flag <= '1' when CptBits = CptBits_trig else '0'; |
|
57 | CptBits_flag <= '1' when CptBits = CptBits_trig else '0'; | |
55 |
|
58 | |||
56 | process(reset,clk) |
|
59 | process(reset,clk) | |
57 | begin |
|
60 | begin | |
58 | if reset = '0' then |
|
61 | if reset = '0' then | |
59 | Serialized_int <= '1'; |
|
62 | Serialized_int <= '1'; | |
60 | CptBits_flag_reg <= '0'; |
|
63 | CptBits_flag_reg <= '0'; | |
61 | Q <= (others => '0'); |
|
64 | Q <= (others => '0'); | |
62 | elsif clk'event and clk = '1' then |
|
65 | elsif clk'event and clk = '1' then | |
63 | CptBits_flag_reg <= CptBits_flag; |
|
66 | CptBits_flag_reg <= CptBits_flag; | |
64 |
|
67 | |||
65 | if CptBits_flag = '1' and CptBits_flag_reg = '0' then |
|
68 | if CptBits_flag = '1' and CptBits_flag_reg = '0' then | |
66 | Serialized_int <= '1'; |
|
69 | Serialized_int <= '1'; | |
67 | Q <= REG; |
|
70 | Q <= REG; | |
68 | elsif Serialize = '1' then |
|
71 | elsif Serialize = '1' then | |
69 | Serialized_int <= '0'; |
|
72 | Serialized_int <= '0'; | |
70 | end if; |
|
73 | end if; | |
71 | end if; |
|
74 | end if; | |
72 | end process; |
|
75 | end process; | |
73 |
|
76 | |||
74 |
|
77 | |||
75 | process(reset,Sclk) |
|
78 | process(reset,Sclk) | |
76 | begin |
|
79 | begin | |
77 | if reset = '0' then |
|
80 | if reset = '0' then | |
78 | CptBits <= (others => '0'); |
|
81 | CptBits <= (others => '0'); | |
79 | REG <= (others => '0'); |
|
82 | REG <= (others => '0'); | |
80 | SOUT <= '1'; |
|
83 | SOUT <= '1'; | |
81 | Serialize_reg <= '0'; |
|
84 | Serialize_reg <= '0'; | |
82 | elsif Sclk'event and Sclk = '1' then |
|
85 | elsif Sclk'event and Sclk = '1' then | |
83 | Serialize_reg <= Serialized_int; |
|
86 | Serialize_reg <= Serialized_int; | |
84 | if (Serialized_int = '0' and Serialize_reg ='1') then |
|
87 | if (Serialized_int = '0' and Serialize_reg ='1') then | |
85 | REG <= SIN & D(Data_sz-1 downto 1); |
|
88 | REG <= SIN & D(Data_sz-1 downto 1); | |
86 | SOUT <= D(0); |
|
89 | SOUT <= D(0); | |
87 | elsif CptBits_flag ='1' then |
|
90 | elsif CptBits_flag ='1' then | |
88 | REG <= SIN & D(Data_sz-1 downto 1); |
|
91 | REG <= SIN & D(Data_sz-1 downto 1); | |
89 | SOUT <= D(0); |
|
92 | SOUT <= D(0); | |
90 | elsif Serialized_int = '0' then |
|
93 | elsif Serialized_int = '0' then | |
91 | REG <= SIN & REG(Data_sz-1 downto 1); |
|
94 | REG <= SIN & REG(Data_sz-1 downto 1); | |
92 | SOUT <= REG(0); |
|
95 | SOUT <= REG(0); | |
93 | else |
|
96 | else | |
94 | SOUT <= '1'; |
|
97 | SOUT <= '1'; | |
95 | end if; |
|
98 | end if; | |
96 | if Serialized_int = '0' then |
|
99 | if Serialized_int = '0' then | |
97 | if CptBits_flag = '1' then |
|
100 | if CptBits_flag = '1' then | |
98 | CptBits <= (others => '0'); |
|
101 | CptBits <= (others => '0'); | |
99 | else |
|
102 | else | |
100 | CptBits <= '1' & CptBits(Data_sz-1 downto 1); |
|
103 | CptBits <= '1' & CptBits(Data_sz-1 downto 1); | |
101 | end if; |
|
104 | end if; | |
102 | else |
|
105 | else | |
103 | CptBits <= (others => '0'); |
|
106 | CptBits <= (others => '0'); | |
104 | end if; |
|
107 | end if; | |
105 |
|
108 | |||
106 | end if; |
|
109 | end if; | |
107 | end process; |
|
110 | end process; | |
108 |
|
111 | |||
109 | end ar_Shift_REG; |
|
112 | end ar_Shift_REG; |
@@ -1,103 +1,106 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
19 | library IEEE; |
|
22 | library IEEE; | |
20 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
21 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
22 | library lpp; |
|
25 | library lpp; | |
23 | use lpp.lpp_uart.all; |
|
26 | use lpp.lpp_uart.all; | |
24 |
|
27 | |||
25 | --! Programme qui va gerer toute la communication entre le PC et le FPGA |
|
28 | --! Programme qui va gerer toute la communication entre le PC et le FPGA | |
26 |
|
29 | |||
27 | entity UART is |
|
30 | entity UART is | |
28 | generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee |
|
31 | generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee | |
29 | port( |
|
32 | port( | |
30 | clk : in std_logic; --! Horloge a 25Mhz du systeme |
|
33 | clk : in std_logic; --! Horloge a 25Mhz du systeme | |
31 | reset : in std_logic; --! Reset du systeme |
|
34 | reset : in std_logic; --! Reset du systeme | |
32 | TXD : out std_logic; --! Transmission, cote PC |
|
35 | TXD : out std_logic; --! Transmission, cote PC | |
33 | RXD : in std_logic; --! Reception, cote PC |
|
36 | RXD : in std_logic; --! Reception, cote PC | |
34 | Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global |
|
37 | Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global | |
35 | NwDat : out std_logic; --! Flag, Nouvelle donnee presente |
|
38 | NwDat : out std_logic; --! Flag, Nouvelle donnee presente | |
36 | ACK : in std_logic; --! Flag, Reponse au flag precedent |
|
39 | ACK : in std_logic; --! Flag, Reponse au flag precedent | |
37 | Send : in std_logic; --! Flag, Demande d'envoi sur le bus |
|
40 | Send : in std_logic; --! Flag, Demande d'envoi sur le bus | |
38 | Sended : out std_logic; --! Flag, Envoi termine |
|
41 | Sended : out std_logic; --! Flag, Envoi termine | |
39 | BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission |
|
42 | BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission | |
40 | RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur |
|
43 | RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur | |
41 | WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur |
|
44 | WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur | |
42 | ); |
|
45 | ); | |
43 | end entity; |
|
46 | end entity; | |
44 |
|
47 | |||
45 |
|
48 | |||
46 | --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation |
|
49 | --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation | |
47 | --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds) |
|
50 | --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds) | |
48 | architecture ar_UART of UART is |
|
51 | architecture ar_UART of UART is | |
49 | signal Bclk : std_logic; |
|
52 | signal Bclk : std_logic; | |
50 |
|
53 | |||
51 | signal RDATA_int : std_logic_vector(Data_sz+1 downto 0); |
|
54 | signal RDATA_int : std_logic_vector(Data_sz+1 downto 0); | |
52 | signal WDATA_int : std_logic_vector(Data_sz+1 downto 0); |
|
55 | signal WDATA_int : std_logic_vector(Data_sz+1 downto 0); | |
53 |
|
56 | |||
54 | signal TXD_Dummy : std_logic; |
|
57 | signal TXD_Dummy : std_logic; | |
55 | signal NwDat_int : std_logic; |
|
58 | signal NwDat_int : std_logic; | |
56 | signal NwDat_int_reg : std_logic; |
|
59 | signal NwDat_int_reg : std_logic; | |
57 | signal receive : std_logic; |
|
60 | signal receive : std_logic; | |
58 | constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0'); |
|
61 | constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0'); | |
59 |
|
62 | |||
60 | begin |
|
63 | begin | |
61 |
|
64 | |||
62 |
|
65 | |||
63 |
|
66 | |||
64 | WDATA_int <= '1' & WDATA & '0'; |
|
67 | WDATA_int <= '1' & WDATA & '0'; | |
65 |
|
68 | |||
66 | BaudGenerator : BaudGen |
|
69 | BaudGenerator : BaudGen | |
67 | port map(clk,reset,Capture,Bclk,RXD,BTrigger); |
|
70 | port map(clk,reset,Capture,Bclk,RXD,BTrigger); | |
68 |
|
71 | |||
69 |
|
72 | |||
70 | RX_REG : Shift_REG |
|
73 | RX_REG : Shift_REG | |
71 | generic map(Data_sz+2) |
|
74 | generic map(Data_sz+2) | |
72 | port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int); |
|
75 | port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int); | |
73 |
|
76 | |||
74 | TX_REG : Shift_REG |
|
77 | TX_REG : Shift_REG | |
75 | generic map(Data_sz+2) |
|
78 | generic map(Data_sz+2) | |
76 | port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int); |
|
79 | port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int); | |
77 |
|
80 | |||
78 |
|
81 | |||
79 |
|
82 | |||
80 | process(clk,reset) |
|
83 | process(clk,reset) | |
81 | begin |
|
84 | begin | |
82 | if reset = '0' then |
|
85 | if reset = '0' then | |
83 | NwDat <= '0'; |
|
86 | NwDat <= '0'; | |
84 | elsif clk'event and clk = '1' then |
|
87 | elsif clk'event and clk = '1' then | |
85 | NwDat_int_reg <= NwDat_int; |
|
88 | NwDat_int_reg <= NwDat_int; | |
86 | if RXD = '1' and NwDat_int = '1' then |
|
89 | if RXD = '1' and NwDat_int = '1' then | |
87 | receive <= '0'; |
|
90 | receive <= '0'; | |
88 | elsif RXD = '0' then |
|
91 | elsif RXD = '0' then | |
89 | receive <= '1'; |
|
92 | receive <= '1'; | |
90 | end if; |
|
93 | end if; | |
91 | if NwDat_int_reg = '0' and NwDat_int = '1' then |
|
94 | if NwDat_int_reg = '0' and NwDat_int = '1' then | |
92 | NwDat <= '1'; |
|
95 | NwDat <= '1'; | |
93 | RDATA <= RDATA_int(8 downto 1); |
|
96 | RDATA <= RDATA_int(8 downto 1); | |
94 | elsif ack = '1' then |
|
97 | elsif ack = '1' then | |
95 | NwDat <= '0'; |
|
98 | NwDat <= '0'; | |
96 | end if; |
|
99 | end if; | |
97 | end if; |
|
100 | end if; | |
98 | end process; |
|
101 | end process; | |
99 |
|
102 | |||
100 | end ar_UART; |
|
103 | end ar_UART; | |
101 |
|
104 | |||
102 |
|
105 | |||
103 |
|
106 |
@@ -1,77 +1,77 | |||||
1 | echo "=======================================================================================" |
|
1 | echo "=======================================================================================" | |
2 | echo "---------------------------------------------------------------------------------------" |
|
2 | echo "---------------------------------------------------------------------------------------" | |
3 | echo " LPP VHDL APB Devices List Updater " |
|
3 | echo " LPP VHDL APB Devices List Updater " | |
4 | echo " Copyright (C) 2010 Laboratory of Plasmas Physic. " |
|
4 | echo " Copyright (C) 2010 Laboratory of Plasmas Physic. " | |
5 | echo "=======================================================================================" |
|
5 | echo "=======================================================================================" | |
6 | echo '---------------------------------------------------------------------------------------- |
|
6 | echo '---------------------------------------------------------------------------------------- | |
7 | This file is a part of the LPP VHDL IP LIBRARY |
|
7 | This file is a part of the LPP VHDL IP LIBRARY | |
8 | Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS |
|
8 | Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS | |
9 |
|
9 | |||
10 | This program is free software; you can redistribute it and/or modify |
|
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by |
|
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 3 of the License, or |
|
12 | the Free Software Foundation; either version 3 of the License, or | |
13 | (at your option) any later version. |
|
13 | (at your option) any later version. | |
14 |
|
14 | |||
15 | This program is distributed in the hope that it will be useful, |
|
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. |
|
18 | GNU General Public License for more details. | |
19 |
|
19 | |||
20 | You should have received a copy of the GNU General Public License |
|
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software |
|
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
22 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | ----------------------------------------------------------------------------------------' |
|
23 | ----------------------------------------------------------------------------------------' | |
24 | echo |
|
24 | echo | |
25 | echo |
|
25 | echo | |
26 | echo |
|
26 | echo | |
27 |
|
27 | |||
28 | LPP_PATCHPATH=`pwd -L` |
|
28 | LPP_PATCHPATH=`pwd -L` | |
29 |
|
29 | |||
30 | cd $LPP_PATCHPATH/lib/lpp |
|
30 | cd $LPP_PATCHPATH/lib/lpp | |
31 |
|
31 | |||
32 |
|
32 | |||
33 | VHDFileStart=$LPP_PATCHPATH/APB_DEVICES/VHDListSTART |
|
33 | VHDFileStart=$LPP_PATCHPATH/APB_DEVICES/VHDListSTART | |
34 | VHDFileEnd=$LPP_PATCHPATH/APB_DEVICES/VHDListEND |
|
34 | VHDFileEnd=$LPP_PATCHPATH/APB_DEVICES/VHDListEND | |
35 |
|
35 | |||
36 | CFileStart=$LPP_PATCHPATH/APB_DEVICES/CListSTART |
|
36 | CFileStart=$LPP_PATCHPATH/APB_DEVICES/CListSTART | |
37 | CFileEnd=$LPP_PATCHPATH/APB_DEVICES/CListEND |
|
37 | CFileEnd=$LPP_PATCHPATH/APB_DEVICES/CListEND | |
38 |
|
38 | |||
39 | ListFILE=$LPP_PATCHPATH/APB_DEVICES/apb_devices_list.txt |
|
39 | ListFILE=$LPP_PATCHPATH/APB_DEVICES/apb_devices_list.txt | |
40 |
|
40 | |||
41 | VHDListFILE=$LPP_PATCHPATH/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
41 | VHDListFILE=$LPP_PATCHPATH/lib/lpp/lpp_amba/apb_devices_list.vhd | |
42 | CListFILE=$LPP_PATCHPATH/LPP_drivers/libsrc/AMBA/apb_devices_list.h |
|
42 | CListFILE=$LPP_PATCHPATH/LPP_drivers/libsrc/AMBA/apb_devices_list.h | |
43 |
|
43 | |||
44 |
|
44 | |||
45 | cat $VHDFileStart>$VHDListFILE |
|
45 | cat $VHDFileStart>$VHDListFILE | |
46 | cat $CFileStart>$CListFILE |
|
46 | cat $CFileStart>$CListFILE | |
47 |
|
47 | |||
48 | grep vendor $ListFILE | sed "s/vendor /constant /" | sed "s/.* /& : amba_vendor_type := 16#/" | sed "s/.*#*/&;/" >> $VHDListFILE |
|
48 | grep vendor $ListFILE | sed "s/vendor /constant /" | sed "s/.* /& : amba_vendor_type := 16#/" | sed "s/.*#*/&#;/" >> $VHDListFILE | |
49 | grep vendor $ListFILE | sed "s/vendor /#define /" | sed "s/.* /& 0x/" >> $CListFILE |
|
49 | grep vendor $ListFILE | sed "s/vendor /#define /" | sed "s/.* /& 0x/" >> $CListFILE | |
50 |
|
50 | |||
51 | echo " ">>$VHDListFILE |
|
51 | echo " ">>$VHDListFILE | |
52 | echo " ">>$CListFILE |
|
52 | echo " ">>$CListFILE | |
53 |
|
53 | |||
54 | grep device $ListFILE | sed "s/device /constant /" | sed "s/.* /& : amba_device_type := 16#/" | sed "s/.*#*/&;/" >> $VHDListFILE |
|
54 | grep device $ListFILE | sed "s/device /constant /" | sed "s/.* /& : amba_device_type := 16#/" | sed "s/.*#*/&#;/" >> $VHDListFILE | |
55 | grep device $ListFILE | sed "s/device /#define /" | sed "s/.* /& 0x/" >> $CListFILE |
|
55 | grep device $ListFILE | sed "s/device /#define /" | sed "s/.* /& 0x/" >> $CListFILE | |
56 |
|
56 | |||
57 | cat $VHDFileEnd>>$VHDListFILE |
|
57 | cat $VHDFileEnd>>$VHDListFILE | |
58 | cat $CFileEnd>>$CListFILE |
|
58 | cat $CFileEnd>>$CListFILE | |
59 |
|
59 | |||
60 |
sh $ |
|
60 | sh $LPP_PATCHPATH/scripts/GPL_Patcher.sh vhd $LPP_PATCHPATH/lib/lpp/lpp_amba/ | |
61 |
sh $ |
|
61 | sh $LPP_PATCHPATH/scripts/GPL_Patcher.sh h $LPP_PATCHPATH/LPP_drivers/libsrc/AMBA/ | |
62 |
|
62 | |||
63 | cd $LPP_PATCHPATH |
|
63 | cd $LPP_PATCHPATH | |
64 |
|
64 | |||
65 |
|
65 | |||
66 |
|
66 | |||
67 |
|
67 | |||
68 |
|
68 | |||
69 |
|
69 | |||
70 |
|
70 | |||
71 |
|
71 | |||
72 |
|
72 | |||
73 |
|
73 | |||
74 |
|
74 | |||
75 |
|
75 | |||
76 |
|
76 | |||
77 |
|
77 |
General Comments 0
You need to be logged in to leave comments.
Login now