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MINI-LFR_WFP - v10
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
43 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_debug_lfr_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 --
121 --
122 SIGNAL errorn : STD_LOGIC;
122 SIGNAL errorn : STD_LOGIC;
123 -- UART AHB ---------------------------------------------------------------
123 -- UART AHB ---------------------------------------------------------------
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126
126
127 -- UART APB ---------------------------------------------------------------
127 -- UART APB ---------------------------------------------------------------
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 --
130 --
131 SIGNAL I00_s : STD_LOGIC;
131 SIGNAL I00_s : STD_LOGIC;
132
133 -- CONSTANTS
134 CONSTANT CFG_PADTECH : INTEGER := inferred;
132 --
135 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 4; -- previous value 1, 3 takes the waveform picker and the time manager into account
136 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
137 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- previous value 1, 2 takes the waveform picker into account
138 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
136
139
137 SIGNAL apbi_ext : apb_slv_in_type;
140 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
141 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
142 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
143 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
144 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
145 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
143
146
144 -- Spacewire signals
147 -- Spacewire signals
145 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
147 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL spw_rxtxclk : STD_ULOGIC;
151 SIGNAL spw_rxtxclk : STD_ULOGIC;
149 SIGNAL spw_rxclkn : STD_ULOGIC;
152 SIGNAL spw_rxclkn : STD_ULOGIC;
150 SIGNAL spw_clk : STD_LOGIC;
153 SIGNAL spw_clk : STD_LOGIC;
151 SIGNAL swni : grspw_in_type;
154 SIGNAL swni : grspw_in_type;
152 SIGNAL swno : grspw_out_type;
155 SIGNAL swno : grspw_out_type;
153 -- SIGNAL clkmn : STD_ULOGIC;
156 -- SIGNAL clkmn : STD_ULOGIC;
154 -- SIGNAL txclk : STD_ULOGIC;
157 -- SIGNAL txclk : STD_ULOGIC;
155
158
156 -- AD Converter RHF1401
159 --GPIO
160 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioo : gpio_out_type;
162
163 -- AD Converter ADS7886
157 SIGNAL sample : Samples14v(7 DOWNTO 0);
164 SIGNAL sample : Samples14v(7 DOWNTO 0);
158 SIGNAL sample_val : STD_LOGIC;
165 SIGNAL sample_val : STD_LOGIC;
159 -- ADC --------------------------------------------------------------------
166 SIGNAL ADC_nCS_sig : STD_LOGIC;
160 SIGNAL ADC_OEB_bar_CH_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
167 SIGNAL ADC_CLK_sig : STD_LOGIC;
161 SIGNAL ADC_smpclk_sig : STD_LOGIC;
168 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
162 SIGNAL ADC_data_sig : STD_LOGIC_VECTOR(13 DOWNTO 0);
163
169
164 SIGNAL bias_fail_sw_sig : STD_LOGIC;
170 SIGNAL bias_fail_sw_sig : STD_LOGIC;
165 -----------------------------------------------------------------------------
171
166 SIGNAL sample_val_s : STD_LOGIC;
167 SIGNAL sample_val_s2 : STD_LOGIC;
168 BEGIN -- beh
172 BEGIN -- beh
169
173
170 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
171 -- CLK
175 -- CLK
172 -----------------------------------------------------------------------------
176 -----------------------------------------------------------------------------
173
177
174 PROCESS(clk_50)
178 PROCESS(clk_50)
175 BEGIN
179 BEGIN
176 IF clk_50'EVENT AND clk_50 = '1' THEN
180 IF clk_50'EVENT AND clk_50 = '1' THEN
177 clk_50_s <= NOT clk_50_s;
181 clk_50_s <= NOT clk_50_s;
178 END IF;
182 END IF;
179 END PROCESS;
183 END PROCESS;
180
184
181 PROCESS(clk_50_s)
185 PROCESS(clk_50_s)
182 BEGIN
186 BEGIN
183 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
187 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
184 clk_25 <= NOT clk_25;
188 clk_25 <= NOT clk_25;
185 END IF;
189 END IF;
186 END PROCESS;
190 END PROCESS;
187
191
188 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
189
193
190 PROCESS (clk_25, reset)
194 PROCESS (clk_25, reset)
191 BEGIN -- PROCESS
195 BEGIN -- PROCESS
192 IF reset = '0' THEN -- asynchronous reset (active low)
196 IF reset = '0' THEN -- asynchronous reset (active low)
193 LED0 <= '0';
197 LED0 <= '0';
194 LED1 <= '0';
198 LED1 <= '0';
195 LED2 <= '0';
199 LED2 <= '0';
196 IO0 <= '0';
197 --IO1 <= '0';
200 --IO1 <= '0';
198 IO2 <= '1';
201 --IO2 <= '1';
199 IO3 <= '0';
202 --IO3 <= '0';
200 IO4 <= '0';
203 --IO4 <= '0';
201 IO5 <= '0';
204 --IO5 <= '0';
202 IO6 <= '0';
205 --IO6 <= '0';
203 IO7 <= '0';
206 --IO7 <= '0';
204 IO8 <= '0';
207 --IO8 <= '0';
205 IO9 <= '0';
208 --IO9 <= '0';
206 IO10 <= '0';
209 --IO10 <= '0';
207 IO11 <= '0';
210 --IO11 <= '0';
208 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
211 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
209 LED0 <= '0';
212 LED0 <= '0';
210 LED1 <= '1';
213 LED1 <= '1';
211 LED2 <= BP0;
214 LED2 <= BP0;
212 IO0 <= '1';
213 --IO1 <= '1';
215 --IO1 <= '1';
214 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
216 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
215 IO3 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2) OR ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
217 --IO3 <= ADC_SDO(0);
216 IO4 <= sample_val;
218 --IO4 <= ADC_SDO(1);
217 IO5 <= ahbi_m_ext.HREADY;
219 --IO5 <= ADC_SDO(2);
218 IO6 <= ahbi_m_ext.HRESP(0);
220 --IO6 <= ADC_SDO(3);
219 IO7 <= ahbi_m_ext.HRESP(1);
221 --IO7 <= ADC_SDO(4);
220 IO8 <= ahbi_m_ext.HGRANT(2);
222 --IO8 <= ADC_SDO(5);
221 IO9 <= ahbo_m_ext(2).HLOCK;
223 --IO9 <= ADC_SDO(6);
222 IO10 <= ahbo_m_ext(2).HBUSREQ;
224 --IO10 <= ADC_SDO(7);
223 IO11 <= sample_val_s2;
225 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
224 END IF;
226 END IF;
225 END PROCESS;
227 END PROCESS;
226
228
227 --PROCESS (clk_49, reset)
229 PROCESS (clk_49, reset)
228 --BEGIN -- PROCESS
230 BEGIN -- PROCESS
229 -- IF reset = '0' THEN -- asynchronous reset (active low)
231 IF reset = '0' THEN -- asynchronous reset (active low)
230 -- I00_s <= '0';
232 I00_s <= '0';
231 -- ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
233 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
232 -- I00_s <= NOT I00_s;
234 I00_s <= NOT I00_s;
233 -- END IF;
235 END IF;
234 --END PROCESS;
236 END PROCESS;
235 --IO0 <= I00_s;
237 -- IO0 <= I00_s;
236
238
237 --UARTs
239 --UARTs
238 nCTS1 <= '1';
240 nCTS1 <= '1';
239 nCTS2 <= '1';
241 nCTS2 <= '1';
240 nDCD2 <= '1';
242 nDCD2 <= '1';
241
243
242 --EXT CONNECTOR
244 --EXT CONNECTOR
243
245
244 --SPACE WIRE
246 --SPACE WIRE
245
247
246 ADC_nCS <= '0';
247 ADC_CLK <= '0';
248
249
250 leon3_soc_1 : leon3_soc
248 leon3_soc_1 : leon3_soc
251 GENERIC MAP (
249 GENERIC MAP (
252 fabtech => apa3e,
250 fabtech => apa3e,
253 memtech => apa3e,
251 memtech => apa3e,
254 padtech => inferred,
252 padtech => inferred,
255 clktech => inferred,
253 clktech => inferred,
256 disas => 0,
254 disas => 0,
257 dbguart => 0,
255 dbguart => 0,
258 pclow => 2,
256 pclow => 2,
259 clk_freq => 25000,
257 clk_freq => 25000,
260 NB_CPU => 1,
258 NB_CPU => 1,
261 ENABLE_FPU => 0,
259 ENABLE_FPU => 1,
262 FPU_NETLIST => 0,
260 FPU_NETLIST => 0,
263 ENABLE_DSU => 1,
261 ENABLE_DSU => 1,
264 ENABLE_AHB_UART => 1,
262 ENABLE_AHB_UART => 1,
265 ENABLE_APB_UART => 1,
263 ENABLE_APB_UART => 1,
266 ENABLE_IRQMP => 1,
264 ENABLE_IRQMP => 1,
267 ENABLE_GPT => 1,
265 ENABLE_GPT => 1,
268 NB_AHB_MASTER => NB_AHB_MASTER,
266 NB_AHB_MASTER => NB_AHB_MASTER,
269 NB_AHB_SLAVE => NB_AHB_SLAVE,
267 NB_AHB_SLAVE => NB_AHB_SLAVE,
270 NB_APB_SLAVE => NB_APB_SLAVE)
268 NB_APB_SLAVE => NB_APB_SLAVE)
271 PORT MAP (
269 PORT MAP (
272 clk => clk_25,
270 clk => clk_25,
273 reset => reset,
271 reset => reset,
274 errorn => errorn,
272 errorn => errorn,
275 ahbrxd => TXD1,
273 ahbrxd => TXD1,
276 ahbtxd => RXD1,
274 ahbtxd => RXD1,
277 urxd1 => TXD2,
275 urxd1 => TXD2,
278 utxd1 => RXD2,
276 utxd1 => RXD2,
279 address => SRAM_A,
277 address => SRAM_A,
280 data => SRAM_DQ,
278 data => SRAM_DQ,
281 nSRAM_BE0 => SRAM_nBE(0),
279 nSRAM_BE0 => SRAM_nBE(0),
282 nSRAM_BE1 => SRAM_nBE(1),
280 nSRAM_BE1 => SRAM_nBE(1),
283 nSRAM_BE2 => SRAM_nBE(2),
281 nSRAM_BE2 => SRAM_nBE(2),
284 nSRAM_BE3 => SRAM_nBE(3),
282 nSRAM_BE3 => SRAM_nBE(3),
285 nSRAM_WE => SRAM_nWE,
283 nSRAM_WE => SRAM_nWE,
286 nSRAM_CE => SRAM_CE,
284 nSRAM_CE => SRAM_CE,
287 nSRAM_OE => SRAM_nOE,
285 nSRAM_OE => SRAM_nOE,
288
286
289 apbi_ext => apbi_ext,
287 apbi_ext => apbi_ext,
290 apbo_ext => apbo_ext,
288 apbo_ext => apbo_ext,
291 ahbi_s_ext => ahbi_s_ext,
289 ahbi_s_ext => ahbi_s_ext,
292 ahbo_s_ext => ahbo_s_ext,
290 ahbo_s_ext => ahbo_s_ext,
293 ahbi_m_ext => ahbi_m_ext,
291 ahbi_m_ext => ahbi_m_ext,
294 ahbo_m_ext => ahbo_m_ext);
292 ahbo_m_ext => ahbo_m_ext);
295
293
296 -------------------------------------------------------------------------------
294 -------------------------------------------------------------------------------
297 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
295 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
298 -------------------------------------------------------------------------------
296 -------------------------------------------------------------------------------
299 apb_lfr_time_management_1 : apb_lfr_time_management
297 apb_lfr_time_management_1 : apb_lfr_time_management
300 GENERIC MAP (
298 GENERIC MAP (
301 pindex => 7,
299 pindex => 6,
302 paddr => 7,
300 paddr => 6,
303 pmask => 16#fff#,
301 pmask => 16#fff#,
304 pirq => 12)
302 pirq => 12)
305 PORT MAP (
303 PORT MAP (
306 clk25MHz => clk_25,
304 clk25MHz => clk_25,
307 clk49_152MHz => clk_49,
305 clk49_152MHz => clk_49,
308 resetn => reset,
306 resetn => reset,
309 grspw_tick => swno.tickout,
307 grspw_tick => swno.tickout,
310 apbi => apbi_ext,
308 apbi => apbi_ext,
311 apbo => apbo_ext(7),
309 apbo => apbo_ext(6),
312 coarse_time => coarse_time,
310 coarse_time => coarse_time,
313 fine_time => fine_time);
311 fine_time => fine_time);
314
312
315 -----------------------------------------------------------------------
313 -----------------------------------------------------------------------
316 --- SpaceWire --------------------------------------------------------
314 --- SpaceWire --------------------------------------------------------
317 -----------------------------------------------------------------------
315 -----------------------------------------------------------------------
318
316
319 SPW_EN <= '1';
317 SPW_EN <= '1';
320
318
321 spw_clk <= clk_50_s;
319 spw_clk <= clk_50_s;
322 spw_rxtxclk <= spw_clk;
320 spw_rxtxclk <= spw_clk;
323 spw_rxclkn <= NOT spw_rxtxclk;
321 spw_rxclkn <= NOT spw_rxtxclk;
324
322
325 -- PADS for SPW1
323 -- PADS for SPW1
326 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
324 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
327 PORT MAP (SPW_NOM_DIN, dtmp(0));
325 PORT MAP (SPW_NOM_DIN, dtmp(0));
328 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
326 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
329 PORT MAP (SPW_NOM_SIN, stmp(0));
327 PORT MAP (SPW_NOM_SIN, stmp(0));
330 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
328 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
331 PORT MAP (SPW_NOM_DOUT, swno.d(0));
329 PORT MAP (SPW_NOM_DOUT, swno.d(0));
332 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
330 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
333 PORT MAP (SPW_NOM_SOUT, swno.s(0));
331 PORT MAP (SPW_NOM_SOUT, swno.s(0));
334 -- PADS FOR SPW2
332 -- PADS FOR SPW2
335 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
333 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
336 PORT MAP (SPW_RED_SIN, dtmp(1));
334 PORT MAP (SPW_RED_SIN, dtmp(1));
337 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
335 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
338 PORT MAP (SPW_RED_DIN, stmp(1));
336 PORT MAP (SPW_RED_DIN, stmp(1));
339 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
337 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_RED_DOUT, swno.d(1));
338 PORT MAP (SPW_RED_DOUT, swno.d(1));
341 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
339 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_RED_SOUT, swno.s(1));
340 PORT MAP (SPW_RED_SOUT, swno.s(1));
343
341
344 -- GRSPW PHY
342 -- GRSPW PHY
345 --spw1_input: if CFG_SPW_GRSPW = 1 generate
343 --spw1_input: if CFG_SPW_GRSPW = 1 generate
346 spw_inputloop : FOR j IN 0 TO 1 GENERATE
344 spw_inputloop : FOR j IN 0 TO 1 GENERATE
347 spw_phy0 : grspw_phy
345 spw_phy0 : grspw_phy
348 GENERIC MAP(
346 GENERIC MAP(
349 tech => apa3e,
347 tech => apa3e,
350 rxclkbuftype => 1,
348 rxclkbuftype => 1,
351 scantest => 0)
349 scantest => 0)
352 PORT MAP(
350 PORT MAP(
353 rxrst => swno.rxrst,
351 rxrst => swno.rxrst,
354 di => dtmp(j),
352 di => dtmp(j),
355 si => stmp(j),
353 si => stmp(j),
356 rxclko => spw_rxclk(j),
354 rxclko => spw_rxclk(j),
357 do => swni.d(j),
355 do => swni.d(j),
358 ndo => swni.nd(j*5+4 DOWNTO j*5),
356 ndo => swni.nd(j*5+4 DOWNTO j*5),
359 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
357 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
360 END GENERATE spw_inputloop;
358 END GENERATE spw_inputloop;
361
359
362 -- SPW core
360 -- SPW core
363 sw0 : grspwm GENERIC MAP(
361 sw0 : grspwm GENERIC MAP(
364 tech => apa3e,
362 tech => apa3e,
365 hindex => 1,
363 hindex => 1,
366 pindex => 5,
364 pindex => 5,
367 paddr => 5,
365 paddr => 5,
368 pirq => 11,
366 pirq => 11,
369 sysfreq => 25000, -- CPU_FREQ
367 sysfreq => 25000, -- CPU_FREQ
370 rmap => 1,
368 rmap => 1,
371 rmapcrc => 1,
369 rmapcrc => 1,
372 fifosize1 => 16,
370 fifosize1 => 16,
373 fifosize2 => 16,
371 fifosize2 => 16,
374 rxclkbuftype => 1,
372 rxclkbuftype => 1,
375 rxunaligned => 0,
373 rxunaligned => 0,
376 rmapbufs => 4,
374 rmapbufs => 4,
377 ft => 0,
375 ft => 0,
378 netlist => 0,
376 netlist => 0,
379 ports => 2,
377 ports => 2,
380 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
378 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
381 memtech => apa3e,
379 memtech => apa3e,
382 destkey => 2,
380 destkey => 2,
383 spwcore => 1
381 spwcore => 1
384 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
382 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
385 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
383 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
386 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
384 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
387 )
385 )
388 PORT MAP(reset, clk_25, spw_rxclk(0),
386 PORT MAP(reset, clk_25, spw_rxclk(0),
389 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
387 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
390 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
388 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
391 swni, swno);
389 swni, swno);
392
390
393 swni.tickin <= '0';
391 swni.tickin <= '0';
394 swni.rmapen <= '1';
392 swni.rmapen <= '1';
395 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
393 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
396 swni.tickinraw <= '0';
394 swni.tickinraw <= '0';
397 swni.timein <= (OTHERS => '0');
395 swni.timein <= (OTHERS => '0');
398 swni.dcrstval <= (OTHERS => '0');
396 swni.dcrstval <= (OTHERS => '0');
399 swni.timerrstval <= (OTHERS => '0');
397 swni.timerrstval <= (OTHERS => '0');
400
398
401 -------------------------------------------------------------------------------
399 -------------------------------------------------------------------------------
402 -- LFR ------------------------------------------------------------------------
400 -- LFR ------------------------------------------------------------------------
403 -------------------------------------------------------------------------------
401 -------------------------------------------------------------------------------
404 lpp_lfr_1 : lpp_lfr
402 lpp_lfr_1 : lpp_lfr
405 GENERIC MAP (
403 GENERIC MAP (
406 Mem_use => use_RAM,
404 Mem_use => use_RAM,
407 nb_data_by_buffer_size => 32,
405 nb_data_by_buffer_size => 32,
408 nb_word_by_buffer_size => 30,
406 nb_word_by_buffer_size => 30,
409 nb_snapshot_param_size => 32,
407 nb_snapshot_param_size => 32,
410 delta_vector_size => 32,
408 delta_vector_size => 32,
411 delta_vector_size_f0_2 => 7, -- log2(96)
409 delta_vector_size_f0_2 => 7, -- log2(96)
412 pindex => 6,
410 pindex => 15,
413 paddr => 6,
411 paddr => 15,
414 pmask => 16#fff#,
412 pmask => 16#fff#,
415 pirq_ms => 6,
413 pirq_ms => 6,
416 pirq_wfp => 14,
414 pirq_wfp => 14,
417 hindex => 2,
415 hindex => 2,
418 top_lfr_version => X"00000009")
416 top_lfr_version => X"0000000A")
419 PORT MAP (
417 PORT MAP (
420 clk => clk_25,
418 clk => clk_25,
421 rstn => reset,
419 rstn => reset,
422 sample_B => sample(2 DOWNTO 0),
420 sample_B => sample(2 DOWNTO 0),
423 sample_E => sample(7 DOWNTO 3),
421 sample_E => sample(7 DOWNTO 3),
424 sample_val => sample_val,
422 sample_val => sample_val,
425 apbi => apbi_ext,
423 apbi => apbi_ext,
426 apbo => apbo_ext(6),
424 apbo => apbo_ext(15),
427 ahbi => ahbi_m_ext,
425 ahbi => ahbi_m_ext,
428 ahbo => ahbo_m_ext(2),
426 ahbo => ahbo_m_ext(2),
429 coarse_time => coarse_time,
427 coarse_time => coarse_time,
430 fine_time => fine_time,
428 fine_time => fine_time,
431 data_shaping_BW => bias_fail_sw_sig);
429 data_shaping_BW => bias_fail_sw_sig);
432
430
433 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
431 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
434 GENERIC MAP (
432 GENERIC MAP(
435 ChanelCount => 8,
433 ChannelCount => 8,
436 ncycle_cnv_high => 79,
434 SampleNbBits => 14,
437 ncycle_cnv => 500)
435 ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63
436 ncycle_cnv => 500) -- 49 152 000 / 98304
438 PORT MAP (
437 PORT MAP (
438 -- CONV
439 cnv_clk => clk_49,
439 cnv_clk => clk_49,
440 cnv_rstn => reset,
440 cnv_rstn => reset,
441 cnv => ADC_smpclk_sig,
441 cnv => ADC_nCS_sig,
442 -- DATA
442 clk => clk_25,
443 clk => clk_25,
443 rstn => reset,
444 rstn => reset,
444 ADC_data => ADC_data_sig,
445 sck => ADC_CLK_sig,
445 ADC_nOE => ADC_OEB_bar_CH_sig,
446 sdo => ADC_SDO_sig,
446 sample => OPEN,
447 -- SAMPLE
447 sample_val => sample_val);--OPEN );--
448 sample => sample,
449 sample_val => sample_val);
450
451 IO10 <= ADC_SDO_sig(5);
452 IO9 <= ADC_SDO_sig(4);
453 IO8 <= ADC_SDO_sig(3);
448
454
449 ADC_data_sig <= (OTHERS => '1');
455 ADC_nCS <= ADC_nCS_sig;
456 ADC_CLK <= ADC_CLK_sig;
457 ADC_SDO_sig <= ADC_SDO;
458
459 ----------------------------------------------------------------------
460 --- GPIO -----------------------------------------------------------
461 ----------------------------------------------------------------------
462
463 grgpio0 : grgpio
464 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
465 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
450
466
451 lpp_debug_lfr_1 : lpp_debug_lfr
467 pio_pad_0 : iopad
452 GENERIC MAP (
468 GENERIC MAP (tech => CFG_PADTECH)
453 pindex => 8,
469 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
454 paddr => 8,
470 pio_pad_1 : iopad
455 pmask => 16#fff#)
471 GENERIC MAP (tech => CFG_PADTECH)
456 PORT MAP (
472 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
457 HCLK => clk_25,
473 pio_pad_2 : iopad
458 HRESETn => reset,
474 GENERIC MAP (tech => CFG_PADTECH)
459 apbi => apbi_ext,
475 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
460 apbo => apbo_ext(8),
476 pio_pad_3 : iopad
461 sample_B => sample(2 DOWNTO 0),
477 GENERIC MAP (tech => CFG_PADTECH)
462 sample_E => sample(7 DOWNTO 3));
478 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
463
479 pio_pad_4 : iopad
464 PROCESS (clk_25, reset)
480 GENERIC MAP (tech => CFG_PADTECH)
465 BEGIN -- PROCESS
481 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
466 IF reset = '0' THEN -- asynchronous reset (active low)
482 pio_pad_5 : iopad
467 sample_val_s2 <= '0';
483 GENERIC MAP (tech => CFG_PADTECH)
468 sample_val_s <= '0';
484 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
469 --sample_val <= '0';
485 pio_pad_6 : iopad
470 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
486 GENERIC MAP (tech => CFG_PADTECH)
471 sample_val_s <= IO1;
487 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
472 sample_val_s2 <= sample_val_s;
488 pio_pad_7 : iopad
473 --sample_val <= (NOT sample_val_s2) AND sample_val_s;
489 GENERIC MAP (tech => CFG_PADTECH)
474 END IF;
490 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
475 END PROCESS;
476
477
478
491
479 END beh;
492 END beh;
Show file before | Show file after | Hide comments
@@ -1,10 +1,6
1 lpp_ad_Conv.vhd
1 lpp_ad_Conv.vhd
2 AD7688_drvr.vhd
3 AD7688_drvr_sync.vhd
4 WriteGen_ADC.vhd
5 TestModule_ADS7886.vhd
6 RHF1401.vhd
2 RHF1401.vhd
7 top_ad_conv_RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
8 TestModule_RHF1401.vhd
4 TestModule_RHF1401.vhd
9 top_ad_conv_ADS7886_v2.vhd
5 top_ad_conv_ADS7886_v2.vhd
10 ADS7886_drvr_v2.vhd
6 ADS7886_drvr_v2.vhd
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