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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY gaisler;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.spacewire.ALL;
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_lfr_time_management.ALL;
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USE lpp.lpp_leon3_soc_pkg.ALL;
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USE lpp.lpp_debug_lfr_pkg.ALL;
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ENTITY MINI_LFR_top IS
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PORT (
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clk_50 : IN STD_LOGIC;
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clk_49 : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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--BPs
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BP0 : IN STD_LOGIC;
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BP1 : IN STD_LOGIC;
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--LEDs
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LED0 : OUT STD_LOGIC;
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LED1 : OUT STD_LOGIC;
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LED2 : OUT STD_LOGIC;
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--UARTs
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TXD1 : IN STD_LOGIC;
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RXD1 : OUT STD_LOGIC;
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nCTS1 : OUT STD_LOGIC;
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nRTS1 : IN STD_LOGIC;
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TXD2 : IN STD_LOGIC;
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RXD2 : OUT STD_LOGIC;
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nCTS2 : OUT STD_LOGIC;
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nDTR2 : IN STD_LOGIC;
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nRTS2 : IN STD_LOGIC;
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nDCD2 : OUT STD_LOGIC;
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--EXT CONNECTOR
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IO0 : INOUT STD_LOGIC;
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IO1 : INOUT STD_LOGIC;
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IO2 : INOUT STD_LOGIC;
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IO3 : INOUT STD_LOGIC;
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IO4 : INOUT STD_LOGIC;
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IO5 : INOUT STD_LOGIC;
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IO6 : INOUT STD_LOGIC;
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IO7 : INOUT STD_LOGIC;
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IO8 : INOUT STD_LOGIC;
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IO9 : INOUT STD_LOGIC;
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IO10 : INOUT STD_LOGIC;
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IO11 : INOUT STD_LOGIC;
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--SPACE WIRE
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SPW_EN : OUT STD_LOGIC; -- 0 => off
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SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
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SPW_NOM_SIN : IN STD_LOGIC;
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SPW_NOM_DOUT : OUT STD_LOGIC;
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SPW_NOM_SOUT : OUT STD_LOGIC;
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SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
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SPW_RED_SIN : IN STD_LOGIC;
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SPW_RED_DOUT : OUT STD_LOGIC;
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SPW_RED_SOUT : OUT STD_LOGIC;
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-- MINI LFR ADC INPUTS
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ADC_nCS : OUT STD_LOGIC;
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ADC_CLK : OUT STD_LOGIC;
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ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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-- SRAM
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SRAM_nWE : OUT STD_LOGIC;
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SRAM_CE : OUT STD_LOGIC;
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SRAM_nOE : OUT STD_LOGIC;
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SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END MINI_LFR_top;
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ARCHITECTURE beh OF MINI_LFR_top IS
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SIGNAL clk_50_s : STD_LOGIC := '0';
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SIGNAL clk_25 : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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--
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SIGNAL errorn : STD_LOGIC;
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-- UART AHB ---------------------------------------------------------------
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SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
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SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
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-- UART APB ---------------------------------------------------------------
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SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
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SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
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--
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SIGNAL I00_s : STD_LOGIC;
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--
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CONSTANT NB_APB_SLAVE : INTEGER := 4; -- previous value 1, 3 takes the waveform picker and the time manager into account
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CONSTANT NB_AHB_SLAVE : INTEGER := 1;
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CONSTANT NB_AHB_MASTER : INTEGER := 2; -- previous value 1, 2 takes the waveform picker into account
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SIGNAL apbi_ext : apb_slv_in_type;
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SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
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SIGNAL ahbi_s_ext : ahb_slv_in_type;
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SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
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SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
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SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
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-- Spacewire signals
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SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL spw_rxtxclk : STD_ULOGIC;
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SIGNAL spw_rxclkn : STD_ULOGIC;
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SIGNAL spw_clk : STD_LOGIC;
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SIGNAL swni : grspw_in_type;
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SIGNAL swno : grspw_out_type;
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-- SIGNAL clkmn : STD_ULOGIC;
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-- SIGNAL txclk : STD_ULOGIC;
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-- AD Converter RHF1401
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SIGNAL sample : Samples14v(7 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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-- ADC --------------------------------------------------------------------
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SIGNAL ADC_OEB_bar_CH_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL ADC_smpclk_sig : STD_LOGIC;
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SIGNAL ADC_data_sig : STD_LOGIC_VECTOR(13 DOWNTO 0);
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SIGNAL bias_fail_sw_sig : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL sample_val_s : STD_LOGIC;
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SIGNAL sample_val_s2 : STD_LOGIC;
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BEGIN -- beh
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-----------------------------------------------------------------------------
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-- CLK
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-----------------------------------------------------------------------------
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PROCESS(clk_50)
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BEGIN
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IF clk_50'EVENT AND clk_50 = '1' THEN
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clk_50_s <= NOT clk_50_s;
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END IF;
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END PROCESS;
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PROCESS(clk_50_s)
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BEGIN
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IF clk_50_s'EVENT AND clk_50_s = '1' THEN
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clk_25 <= NOT clk_25;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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PROCESS (clk_25, reset)
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BEGIN -- PROCESS
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IF reset = '0' THEN -- asynchronous reset (active low)
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LED0 <= '0';
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LED1 <= '0';
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LED2 <= '0';
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IO0 <= '0';
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--IO1 <= '0';
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IO2 <= '1';
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IO3 <= '0';
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IO4 <= '0';
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IO5 <= '0';
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IO6 <= '0';
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IO7 <= '0';
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IO8 <= '0';
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IO9 <= '0';
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IO10 <= '0';
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IO11 <= '0';
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ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
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LED0 <= '0';
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LED1 <= '1';
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LED2 <= BP0;
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IO0 <= '1';
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--IO1 <= '1';
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IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
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IO3 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2) OR ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
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IO4 <= sample_val;
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IO5 <= ahbi_m_ext.HREADY;
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IO6 <= ahbi_m_ext.HRESP(0);
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IO7 <= ahbi_m_ext.HRESP(1);
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IO8 <= ahbi_m_ext.HGRANT(2);
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IO9 <= ahbo_m_ext(2).HLOCK;
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IO10 <= ahbo_m_ext(2).HBUSREQ;
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IO11 <= sample_val_s2;
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END IF;
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END PROCESS;
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--PROCESS (clk_49, reset)
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--BEGIN -- PROCESS
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-- IF reset = '0' THEN -- asynchronous reset (active low)
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-- I00_s <= '0';
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-- ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
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-- I00_s <= NOT I00_s;
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-- END IF;
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--END PROCESS;
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--IO0 <= I00_s;
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--UARTs
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nCTS1 <= '1';
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nCTS2 <= '1';
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nDCD2 <= '1';
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--EXT CONNECTOR
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--SPACE WIRE
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ADC_nCS <= '0';
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ADC_CLK <= '0';
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leon3_soc_1 : leon3_soc
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GENERIC MAP (
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fabtech => apa3e,
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memtech => apa3e,
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padtech => inferred,
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clktech => inferred,
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disas => 0,
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dbguart => 0,
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pclow => 2,
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clk_freq => 25000,
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NB_CPU => 1,
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ENABLE_FPU => 0,
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FPU_NETLIST => 0,
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ENABLE_DSU => 1,
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ENABLE_AHB_UART => 1,
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ENABLE_APB_UART => 1,
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ENABLE_IRQMP => 1,
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ENABLE_GPT => 1,
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NB_AHB_MASTER => NB_AHB_MASTER,
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NB_AHB_SLAVE => NB_AHB_SLAVE,
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NB_APB_SLAVE => NB_APB_SLAVE)
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PORT MAP (
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clk => clk_25,
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reset => reset,
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errorn => errorn,
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ahbrxd => TXD1,
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ahbtxd => RXD1,
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urxd1 => TXD2,
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utxd1 => RXD2,
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address => SRAM_A,
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data => SRAM_DQ,
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nSRAM_BE0 => SRAM_nBE(0),
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nSRAM_BE1 => SRAM_nBE(1),
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nSRAM_BE2 => SRAM_nBE(2),
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nSRAM_BE3 => SRAM_nBE(3),
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nSRAM_WE => SRAM_nWE,
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nSRAM_CE => SRAM_CE,
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nSRAM_OE => SRAM_nOE,
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apbi_ext => apbi_ext,
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apbo_ext => apbo_ext,
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ahbi_s_ext => ahbi_s_ext,
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ahbo_s_ext => ahbo_s_ext,
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ahbi_m_ext => ahbi_m_ext,
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ahbo_m_ext => ahbo_m_ext);
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-------------------------------------------------------------------------------
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-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
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-------------------------------------------------------------------------------
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apb_lfr_time_management_1 : apb_lfr_time_management
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GENERIC MAP (
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pindex => 7,
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paddr => 7,
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pmask => 16#fff#,
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pirq => 12)
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PORT MAP (
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clk25MHz => clk_25,
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clk49_152MHz => clk_49,
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resetn => reset,
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grspw_tick => swno.tickout,
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apbi => apbi_ext,
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apbo => apbo_ext(7),
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coarse_time => coarse_time,
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fine_time => fine_time);
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-----------------------------------------------------------------------
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--- SpaceWire --------------------------------------------------------
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-----------------------------------------------------------------------
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SPW_EN <= '1';
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spw_clk <= clk_50_s;
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spw_rxtxclk <= spw_clk;
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spw_rxclkn <= NOT spw_rxtxclk;
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-- PADS for SPW1
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spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
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PORT MAP (SPW_NOM_DIN, dtmp(0));
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spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
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PORT MAP (SPW_NOM_SIN, stmp(0));
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spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
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PORT MAP (SPW_NOM_DOUT, swno.d(0));
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spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
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PORT MAP (SPW_NOM_SOUT, swno.s(0));
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-- PADS FOR SPW2
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spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
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PORT MAP (SPW_RED_SIN, dtmp(1));
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spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
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PORT MAP (SPW_RED_DIN, stmp(1));
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spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
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PORT MAP (SPW_RED_DOUT, swno.d(1));
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spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
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PORT MAP (SPW_RED_SOUT, swno.s(1));
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-- GRSPW PHY
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--spw1_input: if CFG_SPW_GRSPW = 1 generate
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spw_inputloop : FOR j IN 0 TO 1 GENERATE
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spw_phy0 : grspw_phy
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GENERIC MAP(
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tech => apa3e,
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rxclkbuftype => 1,
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scantest => 0)
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PORT MAP(
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rxrst => swno.rxrst,
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di => dtmp(j),
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si => stmp(j),
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rxclko => spw_rxclk(j),
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do => swni.d(j),
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ndo => swni.nd(j*5+4 DOWNTO j*5),
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dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
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END GENERATE spw_inputloop;
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-- SPW core
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sw0 : grspwm GENERIC MAP(
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tech => apa3e,
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hindex => 1,
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pindex => 5,
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paddr => 5,
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pirq => 11,
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sysfreq => 25000, -- CPU_FREQ
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rmap => 1,
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rmapcrc => 1,
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fifosize1 => 16,
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fifosize2 => 16,
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rxclkbuftype => 1,
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rxunaligned => 0,
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rmapbufs => 4,
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ft => 0,
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netlist => 0,
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ports => 2,
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--dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
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memtech => apa3e,
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destkey => 2,
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spwcore => 1
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--input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
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--output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
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--rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
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)
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PORT MAP(reset, clk_25, spw_rxclk(0),
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spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
|
|
|
ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
|
|
|
swni, swno);
|
|
|
|
|
|
swni.tickin <= '0';
|
|
|
swni.rmapen <= '1';
|
|
|
swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
|
|
|
swni.tickinraw <= '0';
|
|
|
swni.timein <= (OTHERS => '0');
|
|
|
swni.dcrstval <= (OTHERS => '0');
|
|
|
swni.timerrstval <= (OTHERS => '0');
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
|
-- LFR ------------------------------------------------------------------------
|
|
|
-------------------------------------------------------------------------------
|
|
|
lpp_lfr_1 : lpp_lfr
|
|
|
GENERIC MAP (
|
|
|
Mem_use => use_RAM,
|
|
|
nb_data_by_buffer_size => 32,
|
|
|
nb_word_by_buffer_size => 30,
|
|
|
nb_snapshot_param_size => 32,
|
|
|
delta_vector_size => 32,
|
|
|
delta_vector_size_f0_2 => 7, -- log2(96)
|
|
|
pindex => 6,
|
|
|
paddr => 6,
|
|
|
pmask => 16#fff#,
|
|
|
pirq_ms => 6,
|
|
|
pirq_wfp => 14,
|
|
|
hindex => 2,
|
|
|
top_lfr_version => X"00000009")
|
|
|
PORT MAP (
|
|
|
clk => clk_25,
|
|
|
rstn => reset,
|
|
|
sample_B => sample(2 DOWNTO 0),
|
|
|
sample_E => sample(7 DOWNTO 3),
|
|
|
sample_val => sample_val,
|
|
|
apbi => apbi_ext,
|
|
|
apbo => apbo_ext(6),
|
|
|
ahbi => ahbi_m_ext,
|
|
|
ahbo => ahbo_m_ext(2),
|
|
|
coarse_time => coarse_time,
|
|
|
fine_time => fine_time,
|
|
|
data_shaping_BW => bias_fail_sw_sig);
|
|
|
|
|
|
top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 8,
|
|
|
ncycle_cnv_high => 79,
|
|
|
ncycle_cnv => 500)
|
|
|
PORT MAP (
|
|
|
cnv_clk => clk_49,
|
|
|
cnv_rstn => reset,
|
|
|
cnv => ADC_smpclk_sig,
|
|
|
clk => clk_25,
|
|
|
rstn => reset,
|
|
|
ADC_data => ADC_data_sig,
|
|
|
ADC_nOE => ADC_OEB_bar_CH_sig,
|
|
|
sample => OPEN,
|
|
|
sample_val => sample_val);--OPEN );--
|
|
|
|
|
|
ADC_data_sig <= (OTHERS => '1');
|
|
|
|
|
|
lpp_debug_lfr_1 : lpp_debug_lfr
|
|
|
GENERIC MAP (
|
|
|
pindex => 8,
|
|
|
paddr => 8,
|
|
|
pmask => 16#fff#)
|
|
|
PORT MAP (
|
|
|
HCLK => clk_25,
|
|
|
HRESETn => reset,
|
|
|
apbi => apbi_ext,
|
|
|
apbo => apbo_ext(8),
|
|
|
sample_B => sample(2 DOWNTO 0),
|
|
|
sample_E => sample(7 DOWNTO 3));
|
|
|
|
|
|
PROCESS (clk_25, reset)
|
|
|
BEGIN -- PROCESS
|
|
|
IF reset = '0' THEN -- asynchronous reset (active low)
|
|
|
sample_val_s2 <= '0';
|
|
|
sample_val_s <= '0';
|
|
|
--sample_val <= '0';
|
|
|
ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
|
|
|
sample_val_s <= IO1;
|
|
|
sample_val_s2 <= sample_val_s;
|
|
|
--sample_val <= (NOT sample_val_s2) AND sample_val_s;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
|
|
|
|
|
|
END beh;
|
|
|
|