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MINI-LFR_WFP - v10
pellion -
r288:345ed9a37e6e JC
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@@ -38,12 +38,12 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
43 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_debug_lfr_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
@@ -125,14 +125,17 ARCHITECTURE beh OF MINI_LFR_top IS
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126
126
127 -- UART APB ---------------------------------------------------------------
127 -- UART APB ---------------------------------------------------------------
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 --
130 --
131 SIGNAL I00_s : STD_LOGIC;
131 SIGNAL I00_s : STD_LOGIC;
132
133 -- CONSTANTS
134 CONSTANT CFG_PADTECH : INTEGER := inferred;
132 --
135 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 4; -- previous value 1, 3 takes the waveform picker and the time manager into account
136 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
137 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- previous value 1, 2 takes the waveform picker into account
138 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
136
139
137 SIGNAL apbi_ext : apb_slv_in_type;
140 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
141 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
@@ -153,18 +156,19 ARCHITECTURE beh OF MINI_LFR_top IS
153 -- SIGNAL clkmn : STD_ULOGIC;
156 -- SIGNAL clkmn : STD_ULOGIC;
154 -- SIGNAL txclk : STD_ULOGIC;
157 -- SIGNAL txclk : STD_ULOGIC;
155
158
156 -- AD Converter RHF1401
159 --GPIO
157 SIGNAL sample : Samples14v(7 DOWNTO 0);
160 SIGNAL gpioi : gpio_in_type;
158 SIGNAL sample_val : STD_LOGIC;
161 SIGNAL gpioo : gpio_out_type;
159 -- ADC --------------------------------------------------------------------
162
160 SIGNAL ADC_OEB_bar_CH_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
163 -- AD Converter ADS7886
161 SIGNAL ADC_smpclk_sig : STD_LOGIC;
164 SIGNAL sample : Samples14v(7 DOWNTO 0);
162 SIGNAL ADC_data_sig : STD_LOGIC_VECTOR(13 DOWNTO 0);
165 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
163
169
164 SIGNAL bias_fail_sw_sig : STD_LOGIC;
170 SIGNAL bias_fail_sw_sig : STD_LOGIC;
165 -----------------------------------------------------------------------------
171
166 SIGNAL sample_val_s : STD_LOGIC;
167 SIGNAL sample_val_s2 : STD_LOGIC;
168 BEGIN -- beh
172 BEGIN -- beh
169
173
170 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
@@ -193,46 +197,44 BEGIN -- beh
193 LED0 <= '0';
197 LED0 <= '0';
194 LED1 <= '0';
198 LED1 <= '0';
195 LED2 <= '0';
199 LED2 <= '0';
196 IO0 <= '0';
197 --IO1 <= '0';
200 --IO1 <= '0';
198 IO2 <= '1';
201 --IO2 <= '1';
199 IO3 <= '0';
202 --IO3 <= '0';
200 IO4 <= '0';
203 --IO4 <= '0';
201 IO5 <= '0';
204 --IO5 <= '0';
202 IO6 <= '0';
205 --IO6 <= '0';
203 IO7 <= '0';
206 --IO7 <= '0';
204 IO8 <= '0';
207 --IO8 <= '0';
205 IO9 <= '0';
208 --IO9 <= '0';
206 IO10 <= '0';
209 --IO10 <= '0';
207 IO11 <= '0';
210 --IO11 <= '0';
208 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
211 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
209 LED0 <= '0';
212 LED0 <= '0';
210 LED1 <= '1';
213 LED1 <= '1';
211 LED2 <= BP0;
214 LED2 <= BP0;
212 IO0 <= '1';
213 --IO1 <= '1';
215 --IO1 <= '1';
214 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
216 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
215 IO3 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2) OR ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
217 --IO3 <= ADC_SDO(0);
216 IO4 <= sample_val;
218 --IO4 <= ADC_SDO(1);
217 IO5 <= ahbi_m_ext.HREADY;
219 --IO5 <= ADC_SDO(2);
218 IO6 <= ahbi_m_ext.HRESP(0);
220 --IO6 <= ADC_SDO(3);
219 IO7 <= ahbi_m_ext.HRESP(1);
221 --IO7 <= ADC_SDO(4);
220 IO8 <= ahbi_m_ext.HGRANT(2);
222 --IO8 <= ADC_SDO(5);
221 IO9 <= ahbo_m_ext(2).HLOCK;
223 --IO9 <= ADC_SDO(6);
222 IO10 <= ahbo_m_ext(2).HBUSREQ;
224 --IO10 <= ADC_SDO(7);
223 IO11 <= sample_val_s2;
225 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
224 END IF;
226 END IF;
225 END PROCESS;
227 END PROCESS;
226
228
227 --PROCESS (clk_49, reset)
229 PROCESS (clk_49, reset)
228 --BEGIN -- PROCESS
230 BEGIN -- PROCESS
229 -- IF reset = '0' THEN -- asynchronous reset (active low)
231 IF reset = '0' THEN -- asynchronous reset (active low)
230 -- I00_s <= '0';
232 I00_s <= '0';
231 -- ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
233 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
232 -- I00_s <= NOT I00_s;
234 I00_s <= NOT I00_s;
233 -- END IF;
235 END IF;
234 --END PROCESS;
236 END PROCESS;
235 --IO0 <= I00_s;
237 -- IO0 <= I00_s;
236
238
237 --UARTs
239 --UARTs
238 nCTS1 <= '1';
240 nCTS1 <= '1';
@@ -243,10 +245,6 BEGIN -- beh
243
245
244 --SPACE WIRE
246 --SPACE WIRE
245
247
246 ADC_nCS <= '0';
247 ADC_CLK <= '0';
248
249
250 leon3_soc_1 : leon3_soc
248 leon3_soc_1 : leon3_soc
251 GENERIC MAP (
249 GENERIC MAP (
252 fabtech => apa3e,
250 fabtech => apa3e,
@@ -258,7 +256,7 BEGIN -- beh
258 pclow => 2,
256 pclow => 2,
259 clk_freq => 25000,
257 clk_freq => 25000,
260 NB_CPU => 1,
258 NB_CPU => 1,
261 ENABLE_FPU => 0,
259 ENABLE_FPU => 1,
262 FPU_NETLIST => 0,
260 FPU_NETLIST => 0,
263 ENABLE_DSU => 1,
261 ENABLE_DSU => 1,
264 ENABLE_AHB_UART => 1,
262 ENABLE_AHB_UART => 1,
@@ -298,8 +296,8 BEGIN -- beh
298 -------------------------------------------------------------------------------
296 -------------------------------------------------------------------------------
299 apb_lfr_time_management_1 : apb_lfr_time_management
297 apb_lfr_time_management_1 : apb_lfr_time_management
300 GENERIC MAP (
298 GENERIC MAP (
301 pindex => 7,
299 pindex => 6,
302 paddr => 7,
300 paddr => 6,
303 pmask => 16#fff#,
301 pmask => 16#fff#,
304 pirq => 12)
302 pirq => 12)
305 PORT MAP (
303 PORT MAP (
@@ -308,7 +306,7 BEGIN -- beh
308 resetn => reset,
306 resetn => reset,
309 grspw_tick => swno.tickout,
307 grspw_tick => swno.tickout,
310 apbi => apbi_ext,
308 apbi => apbi_ext,
311 apbo => apbo_ext(7),
309 apbo => apbo_ext(6),
312 coarse_time => coarse_time,
310 coarse_time => coarse_time,
313 fine_time => fine_time);
311 fine_time => fine_time);
314
312
@@ -409,13 +407,13 BEGIN -- beh
409 nb_snapshot_param_size => 32,
407 nb_snapshot_param_size => 32,
410 delta_vector_size => 32,
408 delta_vector_size => 32,
411 delta_vector_size_f0_2 => 7, -- log2(96)
409 delta_vector_size_f0_2 => 7, -- log2(96)
412 pindex => 6,
410 pindex => 15,
413 paddr => 6,
411 paddr => 15,
414 pmask => 16#fff#,
412 pmask => 16#fff#,
415 pirq_ms => 6,
413 pirq_ms => 6,
416 pirq_wfp => 14,
414 pirq_wfp => 14,
417 hindex => 2,
415 hindex => 2,
418 top_lfr_version => X"00000009")
416 top_lfr_version => X"0000000A")
419 PORT MAP (
417 PORT MAP (
420 clk => clk_25,
418 clk => clk_25,
421 rstn => reset,
419 rstn => reset,
@@ -423,57 +421,72 BEGIN -- beh
423 sample_E => sample(7 DOWNTO 3),
421 sample_E => sample(7 DOWNTO 3),
424 sample_val => sample_val,
422 sample_val => sample_val,
425 apbi => apbi_ext,
423 apbi => apbi_ext,
426 apbo => apbo_ext(6),
424 apbo => apbo_ext(15),
427 ahbi => ahbi_m_ext,
425 ahbi => ahbi_m_ext,
428 ahbo => ahbo_m_ext(2),
426 ahbo => ahbo_m_ext(2),
429 coarse_time => coarse_time,
427 coarse_time => coarse_time,
430 fine_time => fine_time,
428 fine_time => fine_time,
431 data_shaping_BW => bias_fail_sw_sig);
429 data_shaping_BW => bias_fail_sw_sig);
432
430
433 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
431 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
434 GENERIC MAP (
432 GENERIC MAP(
435 ChanelCount => 8,
433 ChannelCount => 8,
436 ncycle_cnv_high => 79,
434 SampleNbBits => 14,
437 ncycle_cnv => 500)
435 ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63
436 ncycle_cnv => 500) -- 49 152 000 / 98304
438 PORT MAP (
437 PORT MAP (
438 -- CONV
439 cnv_clk => clk_49,
439 cnv_clk => clk_49,
440 cnv_rstn => reset,
440 cnv_rstn => reset,
441 cnv => ADC_smpclk_sig,
441 cnv => ADC_nCS_sig,
442 -- DATA
442 clk => clk_25,
443 clk => clk_25,
443 rstn => reset,
444 rstn => reset,
444 ADC_data => ADC_data_sig,
445 sck => ADC_CLK_sig,
445 ADC_nOE => ADC_OEB_bar_CH_sig,
446 sdo => ADC_SDO_sig,
446 sample => OPEN,
447 -- SAMPLE
447 sample_val => sample_val);--OPEN );--
448 sample => sample,
449 sample_val => sample_val);
448
450
449 ADC_data_sig <= (OTHERS => '1');
451 IO10 <= ADC_SDO_sig(5);
452 IO9 <= ADC_SDO_sig(4);
453 IO8 <= ADC_SDO_sig(3);
454
455 ADC_nCS <= ADC_nCS_sig;
456 ADC_CLK <= ADC_CLK_sig;
457 ADC_SDO_sig <= ADC_SDO;
458
459 ----------------------------------------------------------------------
460 --- GPIO -----------------------------------------------------------
461 ----------------------------------------------------------------------
450
462
451 lpp_debug_lfr_1 : lpp_debug_lfr
463 grgpio0 : grgpio
452 GENERIC MAP (
464 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
453 pindex => 8,
465 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
454 paddr => 8,
466
455 pmask => 16#fff#)
467 pio_pad_0 : iopad
456 PORT MAP (
468 GENERIC MAP (tech => CFG_PADTECH)
457 HCLK => clk_25,
469 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
458 HRESETn => reset,
470 pio_pad_1 : iopad
459 apbi => apbi_ext,
471 GENERIC MAP (tech => CFG_PADTECH)
460 apbo => apbo_ext(8),
472 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
461 sample_B => sample(2 DOWNTO 0),
473 pio_pad_2 : iopad
462 sample_E => sample(7 DOWNTO 3));
474 GENERIC MAP (tech => CFG_PADTECH)
475 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
476 pio_pad_3 : iopad
477 GENERIC MAP (tech => CFG_PADTECH)
478 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
479 pio_pad_4 : iopad
480 GENERIC MAP (tech => CFG_PADTECH)
481 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
482 pio_pad_5 : iopad
483 GENERIC MAP (tech => CFG_PADTECH)
484 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
485 pio_pad_6 : iopad
486 GENERIC MAP (tech => CFG_PADTECH)
487 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
488 pio_pad_7 : iopad
489 GENERIC MAP (tech => CFG_PADTECH)
490 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
463
491
464 PROCESS (clk_25, reset)
465 BEGIN -- PROCESS
466 IF reset = '0' THEN -- asynchronous reset (active low)
467 sample_val_s2 <= '0';
468 sample_val_s <= '0';
469 --sample_val <= '0';
470 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
471 sample_val_s <= IO1;
472 sample_val_s2 <= sample_val_s;
473 --sample_val <= (NOT sample_val_s2) AND sample_val_s;
474 END IF;
475 END PROCESS;
476
477
478
479 END beh;
492 END beh;
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@@ -1,8 +1,4
1 lpp_ad_Conv.vhd
1 lpp_ad_Conv.vhd
2 AD7688_drvr.vhd
3 AD7688_drvr_sync.vhd
4 WriteGen_ADC.vhd
5 TestModule_ADS7886.vhd
6 RHF1401.vhd
2 RHF1401.vhd
7 top_ad_conv_RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
8 TestModule_RHF1401.vhd
4 TestModule_RHF1401.vhd
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