@@ -38,12 +38,12 USE esa.memoryctrl.ALL; | |||
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | USE lpp.lpp_lfr_pkg.ALL; | |
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
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42 | 43 | USE lpp.iir_filter.ALL; |
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43 | 44 | USE lpp.general_purpose.ALL; |
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44 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
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45 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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46 | USE lpp.lpp_debug_lfr_pkg.ALL; | |
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47 | 47 | |
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48 | 48 | ENTITY MINI_LFR_top IS |
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49 | 49 | |
@@ -125,14 +125,17 ARCHITECTURE beh OF MINI_LFR_top IS | |||
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125 | 125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
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126 | 126 | |
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127 | 127 | -- UART APB --------------------------------------------------------------- |
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128 |
SIGNAL |
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129 |
SIGNAL |
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128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
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129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
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130 | 130 | -- |
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131 |
SIGNAL |
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131 | SIGNAL I00_s : STD_LOGIC; | |
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132 | ||
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133 | -- CONSTANTS | |
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134 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
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132 | 135 | -- |
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133 |
CONSTANT NB_APB_SLAVE : INTEGER := |
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136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
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134 | 137 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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135 |
CONSTANT NB_AHB_MASTER : INTEGER := 2; |
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138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
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136 | 139 | |
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137 | 140 | SIGNAL apbi_ext : apb_slv_in_type; |
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138 | 141 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
@@ -153,18 +156,19 ARCHITECTURE beh OF MINI_LFR_top IS | |||
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153 | 156 | -- SIGNAL clkmn : STD_ULOGIC; |
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154 | 157 | -- SIGNAL txclk : STD_ULOGIC; |
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155 | 158 | |
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156 | -- AD Converter RHF1401 | |
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157 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
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158 | SIGNAL sample_val : STD_LOGIC; | |
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159 | -- ADC -------------------------------------------------------------------- | |
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160 | SIGNAL ADC_OEB_bar_CH_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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161 | SIGNAL ADC_smpclk_sig : STD_LOGIC; | |
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162 | SIGNAL ADC_data_sig : STD_LOGIC_VECTOR(13 DOWNTO 0); | |
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159 | --GPIO | |
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160 | SIGNAL gpioi : gpio_in_type; | |
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161 | SIGNAL gpioo : gpio_out_type; | |
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162 | ||
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163 | -- AD Converter ADS7886 | |
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164 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
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165 | SIGNAL sample_val : STD_LOGIC; | |
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166 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
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167 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
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168 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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163 | 169 | |
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164 | 170 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
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165 | ----------------------------------------------------------------------------- | |
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166 | SIGNAL sample_val_s : STD_LOGIC; | |
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167 | SIGNAL sample_val_s2 : STD_LOGIC; | |
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171 | ||
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168 | 172 | BEGIN -- beh |
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169 | 173 | |
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170 | 174 | ----------------------------------------------------------------------------- |
@@ -193,46 +197,44 BEGIN -- beh | |||
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193 | 197 | LED0 <= '0'; |
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194 | 198 | LED1 <= '0'; |
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195 | 199 | LED2 <= '0'; |
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196 | IO0 <= '0'; | |
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197 | 200 | --IO1 <= '0'; |
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198 | IO2 <= '1'; | |
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199 | IO3 <= '0'; | |
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200 | IO4 <= '0'; | |
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201 | IO5 <= '0'; | |
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202 | IO6 <= '0'; | |
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203 | IO7 <= '0'; | |
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204 | IO8 <= '0'; | |
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205 | IO9 <= '0'; | |
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206 | IO10 <= '0'; | |
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207 | IO11 <= '0'; | |
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201 | --IO2 <= '1'; | |
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202 | --IO3 <= '0'; | |
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203 | --IO4 <= '0'; | |
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204 | --IO5 <= '0'; | |
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205 | --IO6 <= '0'; | |
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206 | --IO7 <= '0'; | |
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207 | --IO8 <= '0'; | |
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208 | --IO9 <= '0'; | |
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209 | --IO10 <= '0'; | |
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210 | --IO11 <= '0'; | |
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208 | 211 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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209 | 212 | LED0 <= '0'; |
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210 | 213 | LED1 <= '1'; |
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211 | 214 | LED2 <= BP0; |
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212 | IO0 <= '1'; | |
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213 | 215 | --IO1 <= '1'; |
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214 |
IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN |
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215 | IO3 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2) OR ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7); | |
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216 |
IO4 <= |
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217 | IO5 <= ahbi_m_ext.HREADY; | |
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218 |
IO6 <= |
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219 |
IO7 <= |
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220 | IO8 <= ahbi_m_ext.HGRANT(2); | |
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221 | IO9 <= ahbo_m_ext(2).HLOCK; | |
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222 | IO10 <= ahbo_m_ext(2).HBUSREQ; | |
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223 | IO11 <= sample_val_s2; | |
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216 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
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217 | --IO3 <= ADC_SDO(0); | |
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218 | --IO4 <= ADC_SDO(1); | |
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219 | --IO5 <= ADC_SDO(2); | |
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220 | --IO6 <= ADC_SDO(3); | |
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221 | --IO7 <= ADC_SDO(4); | |
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222 | --IO8 <= ADC_SDO(5); | |
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223 | --IO9 <= ADC_SDO(6); | |
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224 | --IO10 <= ADC_SDO(7); | |
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225 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
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224 | 226 | END IF; |
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225 | 227 | END PROCESS; |
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226 | 228 | |
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227 |
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228 |
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229 |
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230 |
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231 |
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232 |
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233 |
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234 |
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235 |
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229 | PROCESS (clk_49, reset) | |
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230 | BEGIN -- PROCESS | |
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231 | IF reset = '0' THEN -- asynchronous reset (active low) | |
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232 | I00_s <= '0'; | |
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233 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
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234 | I00_s <= NOT I00_s; | |
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235 | END IF; | |
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236 | END PROCESS; | |
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237 | -- IO0 <= I00_s; | |
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236 | 238 | |
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237 | 239 | --UARTs |
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238 | 240 | nCTS1 <= '1'; |
@@ -243,10 +245,6 BEGIN -- beh | |||
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243 | 245 | |
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244 | 246 | --SPACE WIRE |
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245 | 247 | |
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246 | ADC_nCS <= '0'; | |
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247 | ADC_CLK <= '0'; | |
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248 | ||
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249 | ||
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250 | 248 | leon3_soc_1 : leon3_soc |
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251 | 249 | GENERIC MAP ( |
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252 | 250 | fabtech => apa3e, |
@@ -258,7 +256,7 BEGIN -- beh | |||
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258 | 256 | pclow => 2, |
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259 | 257 | clk_freq => 25000, |
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260 | 258 | NB_CPU => 1, |
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261 |
ENABLE_FPU => |
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259 | ENABLE_FPU => 1, | |
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262 | 260 | FPU_NETLIST => 0, |
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263 | 261 | ENABLE_DSU => 1, |
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264 | 262 | ENABLE_AHB_UART => 1, |
@@ -298,8 +296,8 BEGIN -- beh | |||
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298 | 296 | ------------------------------------------------------------------------------- |
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299 | 297 | apb_lfr_time_management_1 : apb_lfr_time_management |
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300 | 298 | GENERIC MAP ( |
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301 |
pindex => |
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302 |
paddr => |
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299 | pindex => 6, | |
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300 | paddr => 6, | |
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303 | 301 | pmask => 16#fff#, |
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304 | 302 | pirq => 12) |
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305 | 303 | PORT MAP ( |
@@ -308,7 +306,7 BEGIN -- beh | |||
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308 | 306 | resetn => reset, |
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309 | 307 | grspw_tick => swno.tickout, |
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310 | 308 | apbi => apbi_ext, |
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311 |
apbo => apbo_ext( |
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309 | apbo => apbo_ext(6), | |
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312 | 310 | coarse_time => coarse_time, |
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313 | 311 | fine_time => fine_time); |
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314 | 312 | |
@@ -409,13 +407,13 BEGIN -- beh | |||
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409 | 407 | nb_snapshot_param_size => 32, |
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410 | 408 | delta_vector_size => 32, |
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411 | 409 | delta_vector_size_f0_2 => 7, -- log2(96) |
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412 |
pindex => |
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413 |
paddr => |
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410 | pindex => 15, | |
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411 | paddr => 15, | |
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414 | 412 | pmask => 16#fff#, |
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415 | 413 | pirq_ms => 6, |
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416 | 414 | pirq_wfp => 14, |
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417 | 415 | hindex => 2, |
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418 |
top_lfr_version => X"0000000 |
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416 | top_lfr_version => X"0000000A") | |
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419 | 417 | PORT MAP ( |
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420 | 418 | clk => clk_25, |
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421 | 419 | rstn => reset, |
@@ -423,57 +421,72 BEGIN -- beh | |||
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423 | 421 | sample_E => sample(7 DOWNTO 3), |
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424 | 422 | sample_val => sample_val, |
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425 | 423 | apbi => apbi_ext, |
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426 |
apbo => apbo_ext( |
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424 | apbo => apbo_ext(15), | |
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427 | 425 | ahbi => ahbi_m_ext, |
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428 | 426 | ahbo => ahbo_m_ext(2), |
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429 | 427 | coarse_time => coarse_time, |
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430 | 428 | fine_time => fine_time, |
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431 | 429 | data_shaping_BW => bias_fail_sw_sig); |
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432 | 430 | |
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433 |
top_ad_conv_ |
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434 |
GENERIC MAP |
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435 |
ChanelCount |
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436 | ncycle_cnv_high => 79, | |
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437 | ncycle_cnv => 500) | |
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431 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
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432 | GENERIC MAP( | |
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433 | ChannelCount => 8, | |
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434 | SampleNbBits => 14, | |
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435 | ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63 | |
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436 | ncycle_cnv => 500) -- 49 152 000 / 98304 | |
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438 | 437 | PORT MAP ( |
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438 | -- CONV | |
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439 | 439 | cnv_clk => clk_49, |
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440 | 440 | cnv_rstn => reset, |
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441 |
cnv => ADC_ |
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441 | cnv => ADC_nCS_sig, | |
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442 | -- DATA | |
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442 | 443 | clk => clk_25, |
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443 | 444 | rstn => reset, |
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444 |
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445 |
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446 | sample => OPEN, | |
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447 |
sample |
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445 | sck => ADC_CLK_sig, | |
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446 | sdo => ADC_SDO_sig, | |
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447 | -- SAMPLE | |
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448 | sample => sample, | |
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449 | sample_val => sample_val); | |
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448 | 450 | |
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449 | ADC_data_sig <= (OTHERS => '1'); | |
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451 | IO10 <= ADC_SDO_sig(5); | |
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452 | IO9 <= ADC_SDO_sig(4); | |
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453 | IO8 <= ADC_SDO_sig(3); | |
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454 | ||
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455 | ADC_nCS <= ADC_nCS_sig; | |
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456 | ADC_CLK <= ADC_CLK_sig; | |
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457 | ADC_SDO_sig <= ADC_SDO; | |
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458 | ||
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459 | ---------------------------------------------------------------------- | |
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460 | --- GPIO ----------------------------------------------------------- | |
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461 | ---------------------------------------------------------------------- | |
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450 | 462 | |
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451 | lpp_debug_lfr_1 : lpp_debug_lfr | |
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452 | GENERIC MAP ( | |
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453 | pindex => 8, | |
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454 | paddr => 8, | |
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455 | pmask => 16#fff#) | |
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456 | PORT MAP ( | |
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457 | HCLK => clk_25, | |
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458 | HRESETn => reset, | |
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459 | apbi => apbi_ext, | |
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460 | apbo => apbo_ext(8), | |
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461 | sample_B => sample(2 DOWNTO 0), | |
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462 | sample_E => sample(7 DOWNTO 3)); | |
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463 | grgpio0 : grgpio | |
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464 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
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465 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
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466 | ||
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467 | pio_pad_0 : iopad | |
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468 | GENERIC MAP (tech => CFG_PADTECH) | |
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469 | PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
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470 | pio_pad_1 : iopad | |
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471 | GENERIC MAP (tech => CFG_PADTECH) | |
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472 | PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
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473 | pio_pad_2 : iopad | |
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474 | GENERIC MAP (tech => CFG_PADTECH) | |
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475 | PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
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476 | pio_pad_3 : iopad | |
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477 | GENERIC MAP (tech => CFG_PADTECH) | |
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478 | PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
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479 | pio_pad_4 : iopad | |
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480 | GENERIC MAP (tech => CFG_PADTECH) | |
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481 | PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
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482 | pio_pad_5 : iopad | |
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483 | GENERIC MAP (tech => CFG_PADTECH) | |
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484 | PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
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485 | pio_pad_6 : iopad | |
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486 | GENERIC MAP (tech => CFG_PADTECH) | |
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487 | PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
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488 | pio_pad_7 : iopad | |
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489 | GENERIC MAP (tech => CFG_PADTECH) | |
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490 | PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
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463 | 491 | |
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464 | PROCESS (clk_25, reset) | |
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465 | BEGIN -- PROCESS | |
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466 | IF reset = '0' THEN -- asynchronous reset (active low) | |
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467 | sample_val_s2 <= '0'; | |
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468 | sample_val_s <= '0'; | |
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469 | --sample_val <= '0'; | |
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470 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
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471 | sample_val_s <= IO1; | |
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472 | sample_val_s2 <= sample_val_s; | |
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473 | --sample_val <= (NOT sample_val_s2) AND sample_val_s; | |
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474 | END IF; | |
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475 | END PROCESS; | |
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476 | ||
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477 | ||
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478 | ||
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479 | 492 | END beh; |
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