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MINI-LFR_WFP - v10
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r288:345ed9a37e6e JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 43 USE lpp.iir_filter.ALL;
43 44 USE lpp.general_purpose.ALL;
44 45 USE lpp.lpp_lfr_time_management.ALL;
45 46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_debug_lfr_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 -----------------------------------------------------------------------------
119 119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 121 --
122 122 SIGNAL errorn : STD_LOGIC;
123 123 -- UART AHB ---------------------------------------------------------------
124 124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 126
127 127 -- UART APB ---------------------------------------------------------------
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 130 --
131 SIGNAL I00_s : STD_LOGIC;
131 SIGNAL I00_s : STD_LOGIC;
132
133 -- CONSTANTS
134 CONSTANT CFG_PADTECH : INTEGER := inferred;
132 135 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 4; -- previous value 1, 3 takes the waveform picker and the time manager into account
136 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
134 137 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- previous value 1, 2 takes the waveform picker into account
138 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
136 139
137 140 SIGNAL apbi_ext : apb_slv_in_type;
138 141 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
139 142 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 143 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
141 144 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 145 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
143 146
144 147 -- Spacewire signals
145 148 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 149 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
147 150 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 151 SIGNAL spw_rxtxclk : STD_ULOGIC;
149 152 SIGNAL spw_rxclkn : STD_ULOGIC;
150 153 SIGNAL spw_clk : STD_LOGIC;
151 154 SIGNAL swni : grspw_in_type;
152 155 SIGNAL swno : grspw_out_type;
153 156 -- SIGNAL clkmn : STD_ULOGIC;
154 157 -- SIGNAL txclk : STD_ULOGIC;
155 158
156 -- AD Converter RHF1401
157 SIGNAL sample : Samples14v(7 DOWNTO 0);
158 SIGNAL sample_val : STD_LOGIC;
159 -- ADC --------------------------------------------------------------------
160 SIGNAL ADC_OEB_bar_CH_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
161 SIGNAL ADC_smpclk_sig : STD_LOGIC;
162 SIGNAL ADC_data_sig : STD_LOGIC_VECTOR(13 DOWNTO 0);
159 --GPIO
160 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioo : gpio_out_type;
162
163 -- AD Converter ADS7886
164 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
163 169
164 170 SIGNAL bias_fail_sw_sig : STD_LOGIC;
165 -----------------------------------------------------------------------------
166 SIGNAL sample_val_s : STD_LOGIC;
167 SIGNAL sample_val_s2 : STD_LOGIC;
171
168 172 BEGIN -- beh
169 173
170 174 -----------------------------------------------------------------------------
171 175 -- CLK
172 176 -----------------------------------------------------------------------------
173 177
174 178 PROCESS(clk_50)
175 179 BEGIN
176 180 IF clk_50'EVENT AND clk_50 = '1' THEN
177 181 clk_50_s <= NOT clk_50_s;
178 182 END IF;
179 183 END PROCESS;
180 184
181 185 PROCESS(clk_50_s)
182 186 BEGIN
183 187 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
184 188 clk_25 <= NOT clk_25;
185 189 END IF;
186 190 END PROCESS;
187 191
188 192 -----------------------------------------------------------------------------
189 193
190 194 PROCESS (clk_25, reset)
191 195 BEGIN -- PROCESS
192 196 IF reset = '0' THEN -- asynchronous reset (active low)
193 197 LED0 <= '0';
194 198 LED1 <= '0';
195 199 LED2 <= '0';
196 IO0 <= '0';
197 200 --IO1 <= '0';
198 IO2 <= '1';
199 IO3 <= '0';
200 IO4 <= '0';
201 IO5 <= '0';
202 IO6 <= '0';
203 IO7 <= '0';
204 IO8 <= '0';
205 IO9 <= '0';
206 IO10 <= '0';
207 IO11 <= '0';
201 --IO2 <= '1';
202 --IO3 <= '0';
203 --IO4 <= '0';
204 --IO5 <= '0';
205 --IO6 <= '0';
206 --IO7 <= '0';
207 --IO8 <= '0';
208 --IO9 <= '0';
209 --IO10 <= '0';
210 --IO11 <= '0';
208 211 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
209 212 LED0 <= '0';
210 213 LED1 <= '1';
211 214 LED2 <= BP0;
212 IO0 <= '1';
213 215 --IO1 <= '1';
214 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
215 IO3 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2) OR ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
216 IO4 <= sample_val;
217 IO5 <= ahbi_m_ext.HREADY;
218 IO6 <= ahbi_m_ext.HRESP(0);
219 IO7 <= ahbi_m_ext.HRESP(1);
220 IO8 <= ahbi_m_ext.HGRANT(2);
221 IO9 <= ahbo_m_ext(2).HLOCK;
222 IO10 <= ahbo_m_ext(2).HBUSREQ;
223 IO11 <= sample_val_s2;
216 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
217 --IO3 <= ADC_SDO(0);
218 --IO4 <= ADC_SDO(1);
219 --IO5 <= ADC_SDO(2);
220 --IO6 <= ADC_SDO(3);
221 --IO7 <= ADC_SDO(4);
222 --IO8 <= ADC_SDO(5);
223 --IO9 <= ADC_SDO(6);
224 --IO10 <= ADC_SDO(7);
225 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
224 226 END IF;
225 227 END PROCESS;
226 228
227 --PROCESS (clk_49, reset)
228 --BEGIN -- PROCESS
229 -- IF reset = '0' THEN -- asynchronous reset (active low)
230 -- I00_s <= '0';
231 -- ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
232 -- I00_s <= NOT I00_s;
233 -- END IF;
234 --END PROCESS;
235 --IO0 <= I00_s;
229 PROCESS (clk_49, reset)
230 BEGIN -- PROCESS
231 IF reset = '0' THEN -- asynchronous reset (active low)
232 I00_s <= '0';
233 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
234 I00_s <= NOT I00_s;
235 END IF;
236 END PROCESS;
237 -- IO0 <= I00_s;
236 238
237 239 --UARTs
238 240 nCTS1 <= '1';
239 241 nCTS2 <= '1';
240 242 nDCD2 <= '1';
241 243
242 244 --EXT CONNECTOR
243 245
244 246 --SPACE WIRE
245 247
246 ADC_nCS <= '0';
247 ADC_CLK <= '0';
248
249
250 248 leon3_soc_1 : leon3_soc
251 249 GENERIC MAP (
252 250 fabtech => apa3e,
253 251 memtech => apa3e,
254 252 padtech => inferred,
255 253 clktech => inferred,
256 254 disas => 0,
257 255 dbguart => 0,
258 256 pclow => 2,
259 257 clk_freq => 25000,
260 258 NB_CPU => 1,
261 ENABLE_FPU => 0,
259 ENABLE_FPU => 1,
262 260 FPU_NETLIST => 0,
263 261 ENABLE_DSU => 1,
264 262 ENABLE_AHB_UART => 1,
265 263 ENABLE_APB_UART => 1,
266 264 ENABLE_IRQMP => 1,
267 265 ENABLE_GPT => 1,
268 266 NB_AHB_MASTER => NB_AHB_MASTER,
269 267 NB_AHB_SLAVE => NB_AHB_SLAVE,
270 268 NB_APB_SLAVE => NB_APB_SLAVE)
271 269 PORT MAP (
272 270 clk => clk_25,
273 271 reset => reset,
274 272 errorn => errorn,
275 273 ahbrxd => TXD1,
276 274 ahbtxd => RXD1,
277 275 urxd1 => TXD2,
278 276 utxd1 => RXD2,
279 277 address => SRAM_A,
280 278 data => SRAM_DQ,
281 279 nSRAM_BE0 => SRAM_nBE(0),
282 280 nSRAM_BE1 => SRAM_nBE(1),
283 281 nSRAM_BE2 => SRAM_nBE(2),
284 282 nSRAM_BE3 => SRAM_nBE(3),
285 283 nSRAM_WE => SRAM_nWE,
286 284 nSRAM_CE => SRAM_CE,
287 285 nSRAM_OE => SRAM_nOE,
288 286
289 287 apbi_ext => apbi_ext,
290 288 apbo_ext => apbo_ext,
291 289 ahbi_s_ext => ahbi_s_ext,
292 290 ahbo_s_ext => ahbo_s_ext,
293 291 ahbi_m_ext => ahbi_m_ext,
294 292 ahbo_m_ext => ahbo_m_ext);
295 293
296 294 -------------------------------------------------------------------------------
297 295 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
298 296 -------------------------------------------------------------------------------
299 297 apb_lfr_time_management_1 : apb_lfr_time_management
300 298 GENERIC MAP (
301 pindex => 7,
302 paddr => 7,
299 pindex => 6,
300 paddr => 6,
303 301 pmask => 16#fff#,
304 302 pirq => 12)
305 303 PORT MAP (
306 304 clk25MHz => clk_25,
307 305 clk49_152MHz => clk_49,
308 306 resetn => reset,
309 307 grspw_tick => swno.tickout,
310 308 apbi => apbi_ext,
311 apbo => apbo_ext(7),
309 apbo => apbo_ext(6),
312 310 coarse_time => coarse_time,
313 311 fine_time => fine_time);
314 312
315 313 -----------------------------------------------------------------------
316 314 --- SpaceWire --------------------------------------------------------
317 315 -----------------------------------------------------------------------
318 316
319 317 SPW_EN <= '1';
320 318
321 319 spw_clk <= clk_50_s;
322 320 spw_rxtxclk <= spw_clk;
323 321 spw_rxclkn <= NOT spw_rxtxclk;
324 322
325 323 -- PADS for SPW1
326 324 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
327 325 PORT MAP (SPW_NOM_DIN, dtmp(0));
328 326 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
329 327 PORT MAP (SPW_NOM_SIN, stmp(0));
330 328 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
331 329 PORT MAP (SPW_NOM_DOUT, swno.d(0));
332 330 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
333 331 PORT MAP (SPW_NOM_SOUT, swno.s(0));
334 332 -- PADS FOR SPW2
335 333 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
336 334 PORT MAP (SPW_RED_SIN, dtmp(1));
337 335 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
338 336 PORT MAP (SPW_RED_DIN, stmp(1));
339 337 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
340 338 PORT MAP (SPW_RED_DOUT, swno.d(1));
341 339 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
342 340 PORT MAP (SPW_RED_SOUT, swno.s(1));
343 341
344 342 -- GRSPW PHY
345 343 --spw1_input: if CFG_SPW_GRSPW = 1 generate
346 344 spw_inputloop : FOR j IN 0 TO 1 GENERATE
347 345 spw_phy0 : grspw_phy
348 346 GENERIC MAP(
349 347 tech => apa3e,
350 348 rxclkbuftype => 1,
351 349 scantest => 0)
352 350 PORT MAP(
353 351 rxrst => swno.rxrst,
354 352 di => dtmp(j),
355 353 si => stmp(j),
356 354 rxclko => spw_rxclk(j),
357 355 do => swni.d(j),
358 356 ndo => swni.nd(j*5+4 DOWNTO j*5),
359 357 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
360 358 END GENERATE spw_inputloop;
361 359
362 360 -- SPW core
363 361 sw0 : grspwm GENERIC MAP(
364 362 tech => apa3e,
365 363 hindex => 1,
366 364 pindex => 5,
367 365 paddr => 5,
368 366 pirq => 11,
369 367 sysfreq => 25000, -- CPU_FREQ
370 368 rmap => 1,
371 369 rmapcrc => 1,
372 370 fifosize1 => 16,
373 371 fifosize2 => 16,
374 372 rxclkbuftype => 1,
375 373 rxunaligned => 0,
376 374 rmapbufs => 4,
377 375 ft => 0,
378 376 netlist => 0,
379 377 ports => 2,
380 378 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
381 379 memtech => apa3e,
382 380 destkey => 2,
383 381 spwcore => 1
384 382 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
385 383 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
386 384 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
387 385 )
388 386 PORT MAP(reset, clk_25, spw_rxclk(0),
389 387 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
390 388 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
391 389 swni, swno);
392 390
393 391 swni.tickin <= '0';
394 392 swni.rmapen <= '1';
395 393 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
396 394 swni.tickinraw <= '0';
397 395 swni.timein <= (OTHERS => '0');
398 396 swni.dcrstval <= (OTHERS => '0');
399 397 swni.timerrstval <= (OTHERS => '0');
400 398
401 399 -------------------------------------------------------------------------------
402 400 -- LFR ------------------------------------------------------------------------
403 401 -------------------------------------------------------------------------------
404 402 lpp_lfr_1 : lpp_lfr
405 403 GENERIC MAP (
406 404 Mem_use => use_RAM,
407 405 nb_data_by_buffer_size => 32,
408 406 nb_word_by_buffer_size => 30,
409 407 nb_snapshot_param_size => 32,
410 408 delta_vector_size => 32,
411 409 delta_vector_size_f0_2 => 7, -- log2(96)
412 pindex => 6,
413 paddr => 6,
410 pindex => 15,
411 paddr => 15,
414 412 pmask => 16#fff#,
415 413 pirq_ms => 6,
416 414 pirq_wfp => 14,
417 415 hindex => 2,
418 top_lfr_version => X"00000009")
416 top_lfr_version => X"0000000A")
419 417 PORT MAP (
420 418 clk => clk_25,
421 419 rstn => reset,
422 420 sample_B => sample(2 DOWNTO 0),
423 421 sample_E => sample(7 DOWNTO 3),
424 422 sample_val => sample_val,
425 423 apbi => apbi_ext,
426 apbo => apbo_ext(6),
424 apbo => apbo_ext(15),
427 425 ahbi => ahbi_m_ext,
428 426 ahbo => ahbo_m_ext(2),
429 427 coarse_time => coarse_time,
430 428 fine_time => fine_time,
431 429 data_shaping_BW => bias_fail_sw_sig);
432 430
433 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
434 GENERIC MAP (
435 ChanelCount => 8,
436 ncycle_cnv_high => 79,
437 ncycle_cnv => 500)
431 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
432 GENERIC MAP(
433 ChannelCount => 8,
434 SampleNbBits => 14,
435 ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63
436 ncycle_cnv => 500) -- 49 152 000 / 98304
438 437 PORT MAP (
438 -- CONV
439 439 cnv_clk => clk_49,
440 440 cnv_rstn => reset,
441 cnv => ADC_smpclk_sig,
441 cnv => ADC_nCS_sig,
442 -- DATA
442 443 clk => clk_25,
443 444 rstn => reset,
444 ADC_data => ADC_data_sig,
445 ADC_nOE => ADC_OEB_bar_CH_sig,
446 sample => OPEN,
447 sample_val => sample_val);--OPEN );--
445 sck => ADC_CLK_sig,
446 sdo => ADC_SDO_sig,
447 -- SAMPLE
448 sample => sample,
449 sample_val => sample_val);
448 450
449 ADC_data_sig <= (OTHERS => '1');
451 IO10 <= ADC_SDO_sig(5);
452 IO9 <= ADC_SDO_sig(4);
453 IO8 <= ADC_SDO_sig(3);
454
455 ADC_nCS <= ADC_nCS_sig;
456 ADC_CLK <= ADC_CLK_sig;
457 ADC_SDO_sig <= ADC_SDO;
458
459 ----------------------------------------------------------------------
460 --- GPIO -----------------------------------------------------------
461 ----------------------------------------------------------------------
450 462
451 lpp_debug_lfr_1 : lpp_debug_lfr
452 GENERIC MAP (
453 pindex => 8,
454 paddr => 8,
455 pmask => 16#fff#)
456 PORT MAP (
457 HCLK => clk_25,
458 HRESETn => reset,
459 apbi => apbi_ext,
460 apbo => apbo_ext(8),
461 sample_B => sample(2 DOWNTO 0),
462 sample_E => sample(7 DOWNTO 3));
463 grgpio0 : grgpio
464 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
465 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
466
467 pio_pad_0 : iopad
468 GENERIC MAP (tech => CFG_PADTECH)
469 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
470 pio_pad_1 : iopad
471 GENERIC MAP (tech => CFG_PADTECH)
472 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
473 pio_pad_2 : iopad
474 GENERIC MAP (tech => CFG_PADTECH)
475 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
476 pio_pad_3 : iopad
477 GENERIC MAP (tech => CFG_PADTECH)
478 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
479 pio_pad_4 : iopad
480 GENERIC MAP (tech => CFG_PADTECH)
481 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
482 pio_pad_5 : iopad
483 GENERIC MAP (tech => CFG_PADTECH)
484 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
485 pio_pad_6 : iopad
486 GENERIC MAP (tech => CFG_PADTECH)
487 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
488 pio_pad_7 : iopad
489 GENERIC MAP (tech => CFG_PADTECH)
490 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
463 491
464 PROCESS (clk_25, reset)
465 BEGIN -- PROCESS
466 IF reset = '0' THEN -- asynchronous reset (active low)
467 sample_val_s2 <= '0';
468 sample_val_s <= '0';
469 --sample_val <= '0';
470 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
471 sample_val_s <= IO1;
472 sample_val_s2 <= sample_val_s;
473 --sample_val <= (NOT sample_val_s2) AND sample_val_s;
474 END IF;
475 END PROCESS;
476
477
478
479 492 END beh;
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@@ -1,10 +1,6
1 1 lpp_ad_Conv.vhd
2 AD7688_drvr.vhd
3 AD7688_drvr_sync.vhd
4 WriteGen_ADC.vhd
5 TestModule_ADS7886.vhd
6 2 RHF1401.vhd
7 3 top_ad_conv_RHF1401.vhd
8 4 TestModule_RHF1401.vhd
9 5 top_ad_conv_ADS7886_v2.vhd
10 6 ADS7886_drvr_v2.vhd
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