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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- DAC --------------------------------------------------------------------
85 -- DAC --------------------------------------------------------------------
86 DAC_SDO : OUT STD_LOGIC;
86 DAC_SDO : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
90 -- HK ---------------------------------------------------------------------
90 -- HK ---------------------------------------------------------------------
91 HK_smpclk : OUT STD_LOGIC;
91 HK_smpclk : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 TAG8 : IN STD_LOGIC;
95 TAG8 : OUT STD_LOGIC;
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 );
97 );
98
98
99 END LFR_em;
99 END LFR_em;
100
100
101
101
102 ARCHITECTURE beh OF LFR_em IS
102 ARCHITECTURE beh OF LFR_em IS
103
103
104 --==========================================================================
104 --==========================================================================
105 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
105 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
106 -- when enabled, chip enable polarity should be reversed and bank size also
106 -- when enabled, chip enable polarity should be reversed and bank size also
107 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
107 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
108 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
108 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
109 --==========================================================================
109 --==========================================================================
110 CONSTANT USE_IAP_MEMCTRL : integer := 1;
110 CONSTANT USE_IAP_MEMCTRL : integer := 1;
111 --==========================================================================
111 --==========================================================================
112
112
113 SIGNAL clk_50_s : STD_LOGIC := '0';
113 SIGNAL clk_50_s : STD_LOGIC := '0';
114 SIGNAL clk_25 : STD_LOGIC := '0';
114 SIGNAL clk_25 : STD_LOGIC := '0';
115 SIGNAL clk_24 : STD_LOGIC := '0';
115 SIGNAL clk_24 : STD_LOGIC := '0';
116 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
117 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
117 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
118 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119
119
120 -- CONSTANTS
120 -- CONSTANTS
121 CONSTANT CFG_PADTECH : INTEGER := inferred;
121 CONSTANT CFG_PADTECH : INTEGER := inferred;
122 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
122 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
123 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
123 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
124 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
124 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
125
125
126 SIGNAL apbi_ext : apb_slv_in_type;
126 SIGNAL apbi_ext : apb_slv_in_type;
127 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
127 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
128 SIGNAL ahbi_s_ext : ahb_slv_in_type;
128 SIGNAL ahbi_s_ext : ahb_slv_in_type;
129 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
129 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
130 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
130 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
131 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
131 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
132
132
133 -- Spacewire signals
133 -- Spacewire signals
134 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 SIGNAL spw_rxtxclk : STD_ULOGIC;
137 SIGNAL spw_rxtxclk : STD_ULOGIC;
138 SIGNAL spw_rxclkn : STD_ULOGIC;
138 SIGNAL spw_rxclkn : STD_ULOGIC;
139 SIGNAL spw_clk : STD_LOGIC;
139 SIGNAL spw_clk : STD_LOGIC;
140 SIGNAL swni : grspw_in_type;
140 SIGNAL swni : grspw_in_type;
141 SIGNAL swno : grspw_out_type;
141 SIGNAL swno : grspw_out_type;
142
142
143 --GPIO
143 --GPIO
144 SIGNAL gpioi : gpio_in_type;
144 SIGNAL gpioi : gpio_in_type;
145 SIGNAL gpioo : gpio_out_type;
145 SIGNAL gpioo : gpio_out_type;
146
146
147 -- AD Converter ADS7886
147 -- AD Converter ADS7886
148 SIGNAL sample : Samples14v(8 DOWNTO 0);
148 SIGNAL sample : Samples14v(8 DOWNTO 0);
149 SIGNAL sample_s : Samples(8 DOWNTO 0);
149 SIGNAL sample_s : Samples(8 DOWNTO 0);
150 SIGNAL sample_val : STD_LOGIC;
150 SIGNAL sample_val : STD_LOGIC;
151 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
151 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
152
152
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
156 -----------------------------------------------------------------------------
156 -----------------------------------------------------------------------------
157 SIGNAL rstn_25 : STD_LOGIC;
157 SIGNAL rstn_25 : STD_LOGIC;
158 SIGNAL rstn_24 : STD_LOGIC;
158 SIGNAL rstn_24 : STD_LOGIC;
159
159
160 SIGNAL LFR_soft_rstn : STD_LOGIC;
160 SIGNAL LFR_soft_rstn : STD_LOGIC;
161 SIGNAL LFR_rstn : STD_LOGIC;
161 SIGNAL LFR_rstn : STD_LOGIC;
162
162
163 SIGNAL ADC_smpclk_s : STD_LOGIC;
163 SIGNAL ADC_smpclk_s : STD_LOGIC;
164 ----------------------------------------------------------------------------
164 ----------------------------------------------------------------------------
165 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
165 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL nSRAM_READY : STD_LOGIC;
166 SIGNAL nSRAM_READY : STD_LOGIC;
167
167
168 BEGIN -- beh
168 BEGIN -- beh
169
169
170 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
171 -- CLK
171 -- CLK
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
173 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
174 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
174 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
175
175
176 PROCESS(clk100MHz)
176 PROCESS(clk100MHz)
177 BEGIN
177 BEGIN
178 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
178 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
179 clk_50_s <= NOT clk_50_s;
179 clk_50_s <= NOT clk_50_s;
180 END IF;
180 END IF;
181 END PROCESS;
181 END PROCESS;
182
182
183 PROCESS(clk_50_s)
183 PROCESS(clk_50_s)
184 BEGIN
184 BEGIN
185 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
185 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
186 clk_25 <= NOT clk_25;
186 clk_25 <= NOT clk_25;
187 END IF;
187 END IF;
188 END PROCESS;
188 END PROCESS;
189
189
190 PROCESS(clk49_152MHz)
190 PROCESS(clk49_152MHz)
191 BEGIN
191 BEGIN
192 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
193 clk_24 <= NOT clk_24;
193 clk_24 <= NOT clk_24;
194 END IF;
194 END IF;
195 END PROCESS;
195 END PROCESS;
196
196
197 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
198
198
199 PROCESS (clk_25, rstn_25)
199 PROCESS (clk_25, rstn_25)
200 BEGIN -- PROCESS
200 BEGIN -- PROCESS
201 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
201 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
202 led(0) <= '0';
202 led(0) <= '0';
203 led(1) <= '0';
203 led(1) <= '0';
204 led(2) <= '0';
204 led(2) <= '0';
205 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
205 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
206 led(0) <= '0';
206 led(0) <= '0';
207 led(1) <= '1';
207 led(1) <= '1';
208 led(2) <= '1';
208 led(2) <= '1';
209 END IF;
209 END IF;
210 END PROCESS;
210 END PROCESS;
211
211
212 --
212 --
213 leon3_soc_1 : leon3_soc
213 leon3_soc_1 : leon3_soc
214 GENERIC MAP (
214 GENERIC MAP (
215 fabtech => apa3e,
215 fabtech => apa3e,
216 memtech => apa3e,
216 memtech => apa3e,
217 padtech => inferred,
217 padtech => inferred,
218 clktech => inferred,
218 clktech => inferred,
219 disas => 0,
219 disas => 0,
220 dbguart => 0,
220 dbguart => 0,
221 pclow => 2,
221 pclow => 2,
222 clk_freq => 25000,
222 clk_freq => 25000,
223 IS_RADHARD => 0,
223 IS_RADHARD => 0,
224 NB_CPU => 1,
224 NB_CPU => 1,
225 ENABLE_FPU => 1,
225 ENABLE_FPU => 1,
226 FPU_NETLIST => 0,
226 FPU_NETLIST => 0,
227 ENABLE_DSU => 1,
227 ENABLE_DSU => 1,
228 ENABLE_AHB_UART => 1,
228 ENABLE_AHB_UART => 1,
229 ENABLE_APB_UART => 1,
229 ENABLE_APB_UART => 1,
230 ENABLE_IRQMP => 1,
230 ENABLE_IRQMP => 1,
231 ENABLE_GPT => 1,
231 ENABLE_GPT => 1,
232 NB_AHB_MASTER => NB_AHB_MASTER,
232 NB_AHB_MASTER => NB_AHB_MASTER,
233 NB_AHB_SLAVE => NB_AHB_SLAVE,
233 NB_AHB_SLAVE => NB_AHB_SLAVE,
234 NB_APB_SLAVE => NB_APB_SLAVE,
234 NB_APB_SLAVE => NB_APB_SLAVE,
235 ADDRESS_SIZE => 20,
235 ADDRESS_SIZE => 20,
236 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
236 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
237 BYPASS_EDAC_MEMCTRLR => '0',
237 BYPASS_EDAC_MEMCTRLR => '0',
238 SRBANKSZ => 8)
238 SRBANKSZ => 9)
239 PORT MAP (
239 PORT MAP (
240 clk => clk_25,
240 clk => clk_25,
241 reset => rstn_25,
241 reset => rstn_25,
242 errorn => OPEN,
242 errorn => OPEN,
243
243
244 ahbrxd => TAG1,
244 ahbrxd => TAG1,
245 ahbtxd => TAG3,
245 ahbtxd => TAG3,
246 urxd1 => TAG2,
246 urxd1 => TAG2,
247 utxd1 => TAG4,
247 utxd1 => TAG4,
248
248
249 address => address,
249 address => address,
250 data => data,
250 data => data,
251 nSRAM_BE0 => nSRAM_BE0,
251 nSRAM_BE0 => nSRAM_BE0,
252 nSRAM_BE1 => nSRAM_BE1,
252 nSRAM_BE1 => nSRAM_BE1,
253 nSRAM_BE2 => nSRAM_BE2,
253 nSRAM_BE2 => nSRAM_BE2,
254 nSRAM_BE3 => nSRAM_BE3,
254 nSRAM_BE3 => nSRAM_BE3,
255 nSRAM_WE => nSRAM_WE,
255 nSRAM_WE => nSRAM_WE,
256 nSRAM_CE => nSRAM_CE_s,
256 nSRAM_CE => nSRAM_CE_s,
257 nSRAM_OE => nSRAM_OE,
257 nSRAM_OE => nSRAM_OE,
258 nSRAM_READY => nSRAM_READY,
258 nSRAM_READY => nSRAM_READY,
259 SRAM_MBE => OPEN,
259 SRAM_MBE => '0',
260
260
261 apbi_ext => apbi_ext,
261 apbi_ext => apbi_ext,
262 apbo_ext => apbo_ext,
262 apbo_ext => apbo_ext,
263 ahbi_s_ext => ahbi_s_ext,
263 ahbi_s_ext => ahbi_s_ext,
264 ahbo_s_ext => ahbo_s_ext,
264 ahbo_s_ext => ahbo_s_ext,
265 ahbi_m_ext => ahbi_m_ext,
265 ahbi_m_ext => ahbi_m_ext,
266 ahbo_m_ext => ahbo_m_ext);
266 ahbo_m_ext => ahbo_m_ext);
267
267
268 PROCESS (clk_25, rstn_25)
268 PROCESS (clk_25, rstn_25)
269 BEGIN -- PROCESS
269 BEGIN -- PROCESS
270 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
270 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
271 nSRAM_READY <= '1';
271 nSRAM_READY <= '1';
272 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
272 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
273 nSRAM_READY <= '1';
273 nSRAM_READY <= '1';
274 IF TAG8 = '1' THEN
275 nSRAM_READY <= '0';
276 END IF;
277 END IF;
274 END IF;
278 END PROCESS;
275 END PROCESS;
279
276
280 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
277 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
281 nSRAM_CE <= not nSRAM_CE_s(0);
278 nSRAM_CE <= not nSRAM_CE_s(0);
282 END GENERATE;
279 END GENERATE;
283
280
284 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
281 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
285 nSRAM_CE <= nSRAM_CE_s(0);
282 nSRAM_CE <= nSRAM_CE_s(0);
286 END GENERATE;
283 END GENERATE;
287
284
288 -------------------------------------------------------------------------------
285 -------------------------------------------------------------------------------
289 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
286 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
290 -------------------------------------------------------------------------------
287 -------------------------------------------------------------------------------
291 apb_lfr_management_1 : apb_lfr_management
288 apb_lfr_management_1 : apb_lfr_management
292 GENERIC MAP (
289 GENERIC MAP (
293 tech => apa3e,
290 tech => apa3e,
294 pindex => 6,
291 pindex => 6,
295 paddr => 6,
292 paddr => 6,
296 pmask => 16#fff#,
293 pmask => 16#fff#,
297 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
294 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
298 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
295 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
299 PORT MAP (
296 PORT MAP (
300 clk25MHz => clk_25,
297 clk25MHz => clk_25,
301 resetn_25MHz => rstn_25, -- TODO
298 resetn_25MHz => rstn_25, -- TODO
302 -- clk24_576MHz => clk_24, -- 49.152MHz/2
299 -- clk24_576MHz => clk_24, -- 49.152MHz/2
303 -- resetn_24_576MHz => rstn_24, -- TODO
300 -- resetn_24_576MHz => rstn_24, -- TODO
304
301
305 grspw_tick => swno.tickout,
302 grspw_tick => swno.tickout,
306 apbi => apbi_ext,
303 apbi => apbi_ext,
307 apbo => apbo_ext(6),
304 apbo => apbo_ext(6),
308
305
309 HK_sample => sample_s(8),
306 HK_sample => sample_s(8),
310 HK_val => sample_val,
307 HK_val => sample_val,
311 HK_sel => HK_SEL,
308 HK_sel => HK_SEL,
312
309
313 DAC_SDO => DAC_SDO,
310 DAC_SDO => DAC_SDO,
314 DAC_SCK => DAC_SCK,
311 DAC_SCK => DAC_SCK,
315 DAC_SYNC => DAC_SYNC,
312 DAC_SYNC => DAC_SYNC,
316 DAC_CAL_EN => DAC_CAL_EN,
313 DAC_CAL_EN => DAC_CAL_EN,
317
314
318 coarse_time => coarse_time,
315 coarse_time => coarse_time,
319 fine_time => fine_time,
316 fine_time => fine_time,
320 LFR_soft_rstn => LFR_soft_rstn
317 LFR_soft_rstn => LFR_soft_rstn
321 );
318 );
322
319
323 -----------------------------------------------------------------------
320 -----------------------------------------------------------------------
324 --- SpaceWire --------------------------------------------------------
321 --- SpaceWire --------------------------------------------------------
325 -----------------------------------------------------------------------
322 -----------------------------------------------------------------------
326
323
327 -- SPW_EN <= '1';
324 -- SPW_EN <= '1';
328
325
329 spw_clk <= clk_50_s;
326 spw_clk <= clk_50_s;
330 spw_rxtxclk <= spw_clk;
327 spw_rxtxclk <= spw_clk;
331 spw_rxclkn <= NOT spw_rxtxclk;
328 spw_rxclkn <= NOT spw_rxtxclk;
332
329
333 -- PADS for SPW1
330 -- PADS for SPW1
334 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
331 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
335 PORT MAP (spw1_din, dtmp(0));
332 PORT MAP (spw1_din, dtmp(0));
336 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
333 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
337 PORT MAP (spw1_sin, stmp(0));
334 PORT MAP (spw1_sin, stmp(0));
338 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
335 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
339 PORT MAP (spw1_dout, swno.d(0));
336 PORT MAP (spw1_dout, swno.d(0));
340 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
337 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
341 PORT MAP (spw1_sout, swno.s(0));
338 PORT MAP (spw1_sout, swno.s(0));
342 -- PADS FOR SPW2
339 -- PADS FOR SPW2
343 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
340 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
344 PORT MAP (spw2_din, dtmp(1));
341 PORT MAP (spw2_din, dtmp(1));
345 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
342 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 PORT MAP (spw2_sin, stmp(1));
343 PORT MAP (spw2_sin, stmp(1));
347 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
344 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
348 PORT MAP (spw2_dout, swno.d(1));
345 PORT MAP (spw2_dout, swno.d(1));
349 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
346 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (spw2_sout, swno.s(1));
347 PORT MAP (spw2_sout, swno.s(1));
351
348
352 -- GRSPW PHY
349 -- GRSPW PHY
353 --spw1_input: if CFG_SPW_GRSPW = 1 generate
350 --spw1_input: if CFG_SPW_GRSPW = 1 generate
354 spw_inputloop : FOR j IN 0 TO 1 GENERATE
351 spw_inputloop : FOR j IN 0 TO 1 GENERATE
355 spw_phy0 : grspw_phy
352 spw_phy0 : grspw_phy
356 GENERIC MAP(
353 GENERIC MAP(
357 tech => apa3e,
354 tech => apa3e,
358 rxclkbuftype => 1,
355 rxclkbuftype => 1,
359 scantest => 0)
356 scantest => 0)
360 PORT MAP(
357 PORT MAP(
361 rxrst => swno.rxrst,
358 rxrst => swno.rxrst,
362 di => dtmp(j),
359 di => dtmp(j),
363 si => stmp(j),
360 si => stmp(j),
364 rxclko => spw_rxclk(j),
361 rxclko => spw_rxclk(j),
365 do => swni.d(j),
362 do => swni.d(j),
366 ndo => swni.nd(j*5+4 DOWNTO j*5),
363 ndo => swni.nd(j*5+4 DOWNTO j*5),
367 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
364 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
368 END GENERATE spw_inputloop;
365 END GENERATE spw_inputloop;
369
366
370 -- SPW core
367 -- SPW core
371 sw0 : grspwm GENERIC MAP(
368 sw0 : grspwm GENERIC MAP(
372 tech => apa3e,
369 tech => apa3e,
373 hindex => 1,
370 hindex => 1,
374 pindex => 5,
371 pindex => 5,
375 paddr => 5,
372 paddr => 5,
376 pirq => 11,
373 pirq => 11,
377 sysfreq => 25000, -- CPU_FREQ
374 sysfreq => 25000, -- CPU_FREQ
378 rmap => 1,
375 rmap => 1,
379 rmapcrc => 1,
376 rmapcrc => 1,
380 fifosize1 => 16,
377 fifosize1 => 16,
381 fifosize2 => 16,
378 fifosize2 => 16,
382 rxclkbuftype => 1,
379 rxclkbuftype => 1,
383 rxunaligned => 0,
380 rxunaligned => 0,
384 rmapbufs => 4,
381 rmapbufs => 4,
385 ft => 0,
382 ft => 0,
386 netlist => 0,
383 netlist => 0,
387 ports => 2,
384 ports => 2,
388 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
385 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
389 memtech => apa3e,
386 memtech => apa3e,
390 destkey => 2,
387 destkey => 2,
391 spwcore => 1
388 spwcore => 1
392 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
389 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
393 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
390 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
394 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
391 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
395 )
392 )
396 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
393 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
397 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
394 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
398 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
395 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
399 swni, swno);
396 swni, swno);
400
397
401 swni.tickin <= '0';
398 swni.tickin <= '0';
402 swni.rmapen <= '1';
399 swni.rmapen <= '1';
403 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
400 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
404 swni.tickinraw <= '0';
401 swni.tickinraw <= '0';
405 swni.timein <= (OTHERS => '0');
402 swni.timein <= (OTHERS => '0');
406 swni.dcrstval <= (OTHERS => '0');
403 swni.dcrstval <= (OTHERS => '0');
407 swni.timerrstval <= (OTHERS => '0');
404 swni.timerrstval <= (OTHERS => '0');
408
405
409 -------------------------------------------------------------------------------
406 -------------------------------------------------------------------------------
410 -- LFR ------------------------------------------------------------------------
407 -- LFR ------------------------------------------------------------------------
411 -------------------------------------------------------------------------------
408 -------------------------------------------------------------------------------
412 LFR_rstn <= LFR_soft_rstn AND rstn_25;
409 LFR_rstn <= LFR_soft_rstn AND rstn_25;
413
410
414 lpp_lfr_1 : lpp_lfr
411 lpp_lfr_1 : lpp_lfr
415 GENERIC MAP (
412 GENERIC MAP (
416 Mem_use => use_RAM,
413 Mem_use => use_RAM,
417 tech => inferred,
414 tech => inferred,
418 nb_data_by_buffer_size => 32,
415 nb_data_by_buffer_size => 32,
419 --nb_word_by_buffer_size => 30,
416 --nb_word_by_buffer_size => 30,
420 nb_snapshot_param_size => 32,
417 nb_snapshot_param_size => 32,
421 delta_vector_size => 32,
418 delta_vector_size => 32,
422 delta_vector_size_f0_2 => 7, -- log2(96)
419 delta_vector_size_f0_2 => 7, -- log2(96)
423 pindex => 15,
420 pindex => 15,
424 paddr => 15,
421 paddr => 15,
425 pmask => 16#fff#,
422 pmask => 16#fff#,
426 pirq_ms => 6,
423 pirq_ms => 6,
427 pirq_wfp => 14,
424 pirq_wfp => 14,
428 hindex => 2,
425 hindex => 2,
429 top_lfr_version => X"010153") -- aa.bb.cc version
426 top_lfr_version => X"010153", -- aa.bb.cc version
430 -- AA : BOARD NUMBER
427 -- AA : BOARD NUMBER
431 -- 0 => MINI_LFR
428 -- 0 => MINI_LFR
432 -- 1 => EM
429 -- 1 => EM
430 DEBUG_FORCE_DATA_DMA => 0)
433 PORT MAP (
431 PORT MAP (
434 clk => clk_25,
432 clk => clk_25,
435 rstn => LFR_rstn,
433 rstn => LFR_rstn,
436 sample_B => sample_s(2 DOWNTO 0),
434 sample_B => sample_s(2 DOWNTO 0),
437 sample_E => sample_s(7 DOWNTO 3),
435 sample_E => sample_s(7 DOWNTO 3),
438 sample_val => sample_val,
436 sample_val => sample_val,
439 apbi => apbi_ext,
437 apbi => apbi_ext,
440 apbo => apbo_ext(15),
438 apbo => apbo_ext(15),
441 ahbi => ahbi_m_ext,
439 ahbi => ahbi_m_ext,
442 ahbo => ahbo_m_ext(2),
440 ahbo => ahbo_m_ext(2),
443 coarse_time => coarse_time,
441 coarse_time => coarse_time,
444 fine_time => fine_time,
442 fine_time => fine_time,
445 data_shaping_BW => bias_fail_sw,
443 data_shaping_BW => bias_fail_sw,
446 debug_vector => OPEN,
444 debug_vector => OPEN,
447 debug_vector_ms => OPEN); --,
445 debug_vector_ms => OPEN); --,
448 --observation_vector_0 => OPEN,
446 --observation_vector_0 => OPEN,
449 --observation_vector_1 => OPEN,
447 --observation_vector_1 => OPEN,
450 --observation_reg => observation_reg);
448 --observation_reg => observation_reg);
451
449
452
450
453 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
451 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
454 sample_s(I) <= sample(I) & '0' & '0';
452 sample_s(I) <= sample(I) & '0' & '0';
455 END GENERATE all_sample;
453 END GENERATE all_sample;
456 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
454 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
457
455
458 -----------------------------------------------------------------------------
456 -----------------------------------------------------------------------------
459 --
457 --
460 -----------------------------------------------------------------------------
458 -----------------------------------------------------------------------------
461 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
459 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
462 GENERIC MAP (
460 GENERIC MAP (
463 ChanelCount => 9,
461 ChanelCount => 9,
464 ncycle_cnv_high => 12,
462 ncycle_cnv_high => 12,
465 ncycle_cnv => 25,
463 ncycle_cnv => 25,
466 FILTER_ENABLED => 16#FF#)
464 FILTER_ENABLED => 16#FF#)
467 PORT MAP (
465 PORT MAP (
468 cnv_clk => clk_24,
466 cnv_clk => clk_24,
469 cnv_rstn => rstn_24,
467 cnv_rstn => rstn_24,
470 cnv => ADC_smpclk_s,
468 cnv => ADC_smpclk_s,
471 clk => clk_25,
469 clk => clk_25,
472 rstn => rstn_25,
470 rstn => rstn_25,
473 ADC_data => ADC_data,
471 ADC_data => ADC_data,
474 ADC_nOE => ADC_OEB_bar_CH_s,
472 ADC_nOE => ADC_OEB_bar_CH_s,
475 sample => sample,
473 sample => sample,
476 sample_val => sample_val);
474 sample_val => sample_val);
477
475
478 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
476 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
479
477
480 ADC_smpclk <= ADC_smpclk_s;
478 ADC_smpclk <= ADC_smpclk_s;
481 HK_smpclk <= ADC_smpclk_s;
479 HK_smpclk <= ADC_smpclk_s;
482
480
483 -- TAG8 <= ADC_smpclk_s;
481 TAG8 <= ADC_smpclk_s;
484
482
485 -----------------------------------------------------------------------------
483 -----------------------------------------------------------------------------
486 -- HK
484 -- HK
487 -----------------------------------------------------------------------------
485 -----------------------------------------------------------------------------
488 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
486 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
489
487
490 END beh; No newline at end of file
488 END beh;
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