HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r527:32bdf5e8de1b

Update methodology of data dating into LFR

pellion -

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r527:32bdf5e8de1b

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designs/LFR-em-WFP_MS/LFR-em.vhd +1 -1

                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"010139")  -- aa.bb.cc version
+                  top_lfr_version        => X"01013A")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +2 -2

                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
-                  IS_RADHARD      => 1,
+                  IS_RADHARD      => 0,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000138")  -- aa.bb.cc version
+                  top_lfr_version        => X"00013A")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,

lib/lpp/dsp/cic/cic_lfr_r2.vhd 0 -3

               --
               CONSTANT S_parameter : INTEGER := 3;
               SIGNAL carry_reg  : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
-              SIGNAL CARRY_PUSH : STD_LOGIC;
-              SIGNAL CARRY_POP  : STD_LOGIC;
               --
               SIGNAL OPERATION    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               END GENERATE all_channel_out_v;
             END beh;

lib/lpp/lfr_management/apb_lfr_management.vhd +6 -5

               SIGNAL soft_reset           : STD_LOGIC;
               SIGNAL soft_reset_sync      : STD_LOGIC;
               -----------------------------------------------------------------------------
-              SIGNAL HK_temp_0_s          : STD_LOGIC_VECTOR(15 DOWNTO 0);
-              SIGNAL HK_temp_1_s          : STD_LOGIC_VECTOR(15 DOWNTO 0);
-              SIGNAL HK_temp_2_s          : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL HK_sel_s             : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL previous_fine_time_bit : STD_LOGIC;
               -----------------------------------------------------------------------------
               PROCESS (clk25MHz, resetn)
-                CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 11;  -- freq = 2^(16-BIT)
+                CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14;  -- freq = 2^(16-BIT)
-                                                                -- for 11, the update frequency is 32Hz
                                                                 -- for each HK, the update frequency is freq/3
+                                                                --
+                                                                -- for 14, the update frequency is
+                                                                -- 4Hz and update for each
+                                                                -- HK is 1.33Hz
               BEGIN  -- PROCESS
                 IF resetn = '0' THEN                -- asynchronous reset (active low)

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +23 -5

               SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
-            --  SIGNAL run_dma : STD_LOGIC;
+              SIGNAL sample_time        :  STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f0_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f1_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f2_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f3_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
               debug_vector <= apb_reg_debug_vector;
               sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
               sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
+              sample_time <= coarse_time & fine_time;
               --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
               --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
+                  sample_time      => sample_time,
                   clk              => clk,
                   rstn             => rstn,
                   data_shaping_SP0 => data_shaping_SP0,
                   sample_f0_wdata  => sample_f0_data,
                   sample_f1_wdata  => sample_f1_data,
                   sample_f2_wdata  => sample_f2_data,
-                  sample_f3_wdata  => sample_f3_data);
+                  sample_f3_wdata  => sample_f3_data,
+                  sample_f0_time   => sample_f0_time,
+                  sample_f1_time   => sample_f1_time,
+                  sample_f2_time   => sample_f2_time,
+                  sample_f3_time   => sample_f3_time
+                  );
               -----------------------------------------------------------------------------
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                   error_buffer_full   => wfp_error_buffer_full,
                   coarse_time => coarse_time,
-                  fine_time   => fine_time,
+            --      fine_time   => fine_time,
                   --f0
                   data_f0_in_valid             => sample_f0_val,
                   data_f0_in                   => sample_f0_data,
+                  data_f0_time                 => sample_f0_time,
                   --f1
                   data_f1_in_valid             => sample_f1_val,
                   data_f1_in                   => sample_f1_data,
+                  data_f1_time                 => sample_f1_time,
                   --f2
                   data_f2_in_valid             => sample_f2_val,
                   data_f2_in                   => sample_f2_data,
+                  data_f2_time                 => sample_f2_time,
                   --f3
                   data_f3_in_valid             => sample_f3_val,
                   data_f3_in                   => sample_f3_data,
+                  data_f3_time                 => sample_f3_time,
                   -- OUTPUT -- DMA interface
                   dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
                   start_date => start_date,
                   coarse_time => coarse_time,
-                  fine_time   => fine_time,
                   sample_f0_wen   => sample_f0_wen,
                   sample_f0_wdata => sample_f0_wdata,
+                  sample_f0_time  => sample_f0_time,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
+                  sample_f1_time  => sample_f1_time,
                   sample_f2_wen   => sample_f2_wen,
                   sample_f2_wdata => sample_f2_wdata,
+                  sample_f2_time  => sample_f2_time,
                   --DMA
                   dma_fifo_burst_valid => dma_fifo_burst_valid(4),                  -- OUT
                   buffer_full_err => dma_buffer_full_err,  --buffer_full_err,
                   grant_error     => dma_grant_error);     --grant_error);
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +94 -4

@@ -50,6 +50,7 ENTITY lpp_lfr_filter IS
50	PORT (	50	PORT (
51	sample : IN Samples(7 DOWNTO 0);	51	sample : IN Samples(7 DOWNTO 0);
52	sample_val : IN STD_LOGIC;	52	sample_val : IN STD_LOGIC;
		53	sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
53	--	54	--
54	clk : IN STD_LOGIC;	55	clk : IN STD_LOGIC;
55	rstn : IN STD_LOGIC;	56	rstn : IN STD_LOGIC;
@@ -68,7 +69,12 ENTITY lpp_lfr_filter IS
68	sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	69	sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69	sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	70	sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70	sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	71	sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71	sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)	72	sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		73	--
		74	sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
		75	sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
		76	sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
		77	sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
72	);	78	);
73	END lpp_lfr_filter;	79	END lpp_lfr_filter;
74		80
@@ -159,6 +165,9 ARCHITECTURE tb OF lpp_lfr_filter IS
159		165
160	SIGNAL sample_f0_val_s : STD_LOGIC;	166	SIGNAL sample_f0_val_s : STD_LOGIC;
161	SIGNAL sample_f1_val_s : STD_LOGIC;	167	SIGNAL sample_f1_val_s : STD_LOGIC;
		168	SIGNAL sample_f1_val_ss : STD_LOGIC;
		169	SIGNAL sample_f2_val_s : STD_LOGIC;
		170	SIGNAL sample_f3_val_s : STD_LOGIC;
162		171
163	-----------------------------------------------------------------------------	172	-----------------------------------------------------------------------------
164	-- CONFIG FILTER IIR f0 to f1	173	-- CONFIG FILTER IIR f0 to f1
@@ -214,6 +223,16 ARCHITECTURE tb OF lpp_lfr_filter IS
214	f2_f3_gain);	223	f2_f3_gain);
215	-----------------------------------------------------------------------------	224	-----------------------------------------------------------------------------
216		225
		226	SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
		227	SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
		228	SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
		229	SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
		230	SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
		231	SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
		232	SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
		233	-- SIGNAL sample_f2_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
		234	-- SIGNAL sample_f3_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
		235	SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
217		236
218	BEGIN	237	BEGIN
219		238
@@ -259,6 +278,24 BEGIN
259	sample_out_val => sample_filter_v2_out_val,	278	sample_out_val => sample_filter_v2_out_val,
260	sample_out => sample_filter_v2_out);	279	sample_out => sample_filter_v2_out);
261		280
		281	-- TIME --
		282	PROCESS (clk, rstn)
		283	BEGIN -- PROCESS
		284	IF rstn = '0' THEN -- asynchronous reset (active low)
		285	sample_time_reg <= (OTHERS => '0');
		286	sample_filter_v2_out_time <= (OTHERS => '0');
		287	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		288	IF sample_val = '1' THEN
		289	sample_time_reg <= sample_time;
		290	END IF;
		291	IF sample_filter_v2_out_val = '1' THEN
		292	sample_filter_v2_out_time <= sample_time_reg;
		293	END IF;
		294	END IF;
		295	END PROCESS;
		296	----------
		297
		298
262	-----------------------------------------------------------------------------	299	-----------------------------------------------------------------------------
263	-- DATA_SHAPING	300	-- DATA_SHAPING
264	-----------------------------------------------------------------------------	301	-----------------------------------------------------------------------------
@@ -336,6 +373,21 BEGIN
336	sample_out_val => sample_f0_val_s,	373	sample_out_val => sample_f0_val_s,
337	sample_out => sample_f0);	374	sample_out => sample_f0);
338		375
		376	-- TIME --
		377	PROCESS (clk, rstn)
		378	BEGIN
		379	IF rstn = '0' THEN
		380	sample_f0_time_reg <= (OTHERS => '0');
		381	ELSIF clk'event AND clk = '1' THEN
		382	IF sample_f0_val_s = '1' THEN
		383	sample_f0_time_reg <= sample_filter_v2_out_time;
		384	END IF;
		385	END IF;
		386	END PROCESS;
		387	sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg;
		388	sample_f0_time <= sample_f0_time_s;
		389	----------
		390
339	sample_f0_val <= sample_f0_val_s;	391	sample_f0_val <= sample_f0_val_s;
340		392
341	all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE	393	all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
@@ -401,9 +453,27 BEGIN
401	rstn => rstn,	453	rstn => rstn,
402	sample_in_val => sample_f1_val_s,	454	sample_in_val => sample_f1_val_s,
403	sample_in => sample_f1_s,	455	sample_in => sample_f1_s,
404	sample_out_val => sample_f1_val,	456	sample_out_val => sample_f1_val_ss,
405	sample_out => sample_f1);	457	sample_out => sample_f1);
406		458
		459	sample_f1_val <= sample_f1_val_ss;
		460
		461	-- TIME --
		462	PROCESS (clk, rstn)
		463	BEGIN
		464	IF rstn = '0' THEN
		465	sample_f1_time_reg <= (OTHERS => '0');
		466	ELSIF clk'event AND clk = '1' THEN
		467	IF sample_f1_val_ss = '1' THEN
		468	sample_f1_time_reg <= sample_f0_time_s;
		469	END IF;
		470	END IF;
		471	END PROCESS;
		472	sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg;
		473	sample_f1_time <= sample_f1_time_s;
		474	----------
		475
		476
407	all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE	477	all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
408	all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE	478	all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
409	sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);	479	sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
@@ -509,9 +579,11 BEGIN
509	rstn => rstn,	579	rstn => rstn,
510	sample_in_val => sample_f2_filter_val ,	580	sample_in_val => sample_f2_filter_val ,
511	sample_in => sample_f2_cic_s,	581	sample_in => sample_f2_cic_s,
512	sample_out_val => sample_f2_val,	582	sample_out_val => sample_f2_val_s,
513	sample_out => sample_f2);	583	sample_out => sample_f2);
514		584
		585	sample_f2_val <= sample_f2_val_s;
		586
515	all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE	587	all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
516	all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE	588	all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
517	sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);	589	sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
@@ -530,8 +602,9 BEGIN
530	rstn => rstn,	602	rstn => rstn,
531	sample_in_val => sample_f3_filter_val ,	603	sample_in_val => sample_f3_filter_val ,
532	sample_in => sample_f3_cic_s,	604	sample_in => sample_f3_cic_s,
533	sample_out_val => sample_f3_val,	605	sample_out_val => sample_f3_val_s,
534	sample_out => sample_f3);	606	sample_out => sample_f3);
		607	sample_f3_val <= sample_f3_val_s;
535		608
536	all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE	609	all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
537	all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE	610	all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
@@ -540,6 +613,23 BEGIN
540	END GENERATE all_bit_sample_f3;	613	END GENERATE all_bit_sample_f3;
541		614
542	-----------------------------------------------------------------------------	615	-----------------------------------------------------------------------------
		616
		617	-- TIME --
		618	PROCESS (clk, rstn)
		619	BEGIN
		620	IF rstn = '0' THEN
		621	sample_f2_time_reg <= (OTHERS => '0');
		622	sample_f3_time_reg <= (OTHERS => '0');
		623	ELSIF clk'event AND clk = '1' THEN
		624	IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF;
		625	IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF;
		626	END IF;
		627	END PROCESS;
		628	sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg;
		629	sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg;
		630	----------
		631
		632	-----------------------------------------------------------------------------
543	--	633	--
544	-----------------------------------------------------------------------------	634	-----------------------------------------------------------------------------
545	sample_f0_wdata <= sample_f0_wdata_s;	635	sample_f0_wdata <= sample_f0_wdata_s;

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +9 -6

                 -- DATA INPUT
                 ---------------------------------------------------------------------------
                 start_date      : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
-                -- TIME
+                coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-                coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
+                --fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
-                fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                sample_f0_time  : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --
                 sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                sample_f1_time  : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --
                 sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                sample_f2_time  : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA
               -----------------------------------------------------------------------------
               -- TIME REG & INFOs
               -----------------------------------------------------------------------------
-              SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL f_empty       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL f_empty_reg   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- TIME MANAGMENT
               -----------------------------------------------------------------------------
-              all_time         <= coarse_time & fine_time;
+              all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
+              --all_time         <= coarse_time & fine_time;
               --
               f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
               f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
                   PORT MAP (
                     clk      => clk,
                     rstn     => rstn,
-                    time_in  => all_time,
+                    time_in  => all_time((I+1)*48-1 DOWNTO I*48),
                     update_1 => time_update_f(I),
                     time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
                     );

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +11 -3

                   run                    : IN  STD_LOGIC;
                   start_date             : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   coarse_time            : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  fine_time              : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   sample_f0_wen          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f0_wdata        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                  sample_f0_time         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   sample_f1_wen          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f1_wdata        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                  sample_f1_time         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   sample_f2_wen          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f2_wdata        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                  sample_f2_time         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   dma_fifo_burst_valid   : OUT STD_LOGIC;
                   dma_fifo_data          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_fifo_ren           : IN  STD_LOGIC;
                 PORT (
                   sample           : IN  Samples(7 DOWNTO 0);
                   sample_val       : IN  STD_LOGIC;
+                  sample_time      : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                   data_shaping_SP0 : IN  STD_LOGIC;
                   sample_f0_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f1_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f2_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-                  sample_f3_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
+                  sample_f3_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+                  sample_f0_time   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                  sample_f1_time   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                  sample_f2_time   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                  sample_f3_time   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+                  );
               END COMPONENT;
               COMPONENT lpp_lfr
                   out_full        : OUT STD_LOGIC);
               END COMPONENT;
-            END lpp_lfr_pkg;
+            END lpp_lfr_pkg;
  No newline at end of file

lib/lpp/lpp_waveform/lpp_waveform.vhd +12 -5

                 ---------------------------------------------------------------------------
                 -- INPUT
                 coarse_time       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                fine_time         : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+            --    fine_time         : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                 --f0
                 data_f0_in_valid : IN STD_LOGIC;
                 data_f0_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                data_f0_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --f1
                 data_f1_in_valid : IN STD_LOGIC;
                 data_f1_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                data_f1_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --f2
                 data_f2_in_valid : IN STD_LOGIC;
                 data_f2_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                data_f2_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --f3
                 data_f3_in_valid : IN STD_LOGIC;
                 data_f3_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                data_f3_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA --------------------------------------------------------------------
               SIGNAL time_out_2                 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
               SIGNAL time_out                   : TIME_VECTOR(3 DOWNTO 0);
               SIGNAL time_out_debug             : TIME_VECTOR(3 DOWNTO 0);  -- TODO : debug
-              SIGNAL time_reg1                  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL time_reg1                  : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
-              SIGNAL time_reg2                  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL time_reg2                  : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               --
               SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);  --occupancy is lesser than 16 * 32b
                   time_reg1 <= (OTHERS => '0');
                   time_reg2 <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-                  time_reg1 <= fine_time & coarse_time;
+                  time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);
+                  time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);
+                  time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);
+                  time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);
                   time_reg2 <= time_reg1;
                 END IF;
               END PROCESS;
                     run       => run,
                     valid_in  => valid_in(I),
                     ack_in    => valid_ack(I),
-                    time_in   => time_reg2,         -- Todo
+                    time_in   => time_reg2(48*(I+1)-1 DOWNTO 48*I),         -- Todo
                     valid_out => valid_out(I),
                     time_out  => time_out(I),       -- Todo
                     error     => status_new_err(I));

lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +5 -1

                   buffer_time         : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
                   error_buffer_full   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   coarse_time                  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  fine_time                    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  --fine_time                    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_f0_in_valid             : IN  STD_LOGIC;
                   data_f0_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                  data_f0_time                 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   data_f1_in_valid             : IN  STD_LOGIC;
                   data_f1_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                  data_f1_time                 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   data_f2_in_valid             : IN  STD_LOGIC;
                   data_f2_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                  data_f2_time                 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   data_f3_in_valid             : IN  STD_LOGIC;
                   data_f3_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                  data_f3_time                 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   dma_fifo_data        : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);

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