##// END OF EJS Templates
Update methodology of data dating into LFR
pellion -
r527:32bdf5e8de1b (MINI-LFR) WFP_MS-0-1-59 (LFR-EM) WFP_MS_1-1-59 JC
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@@ -380,7 +380,7 BEGIN -- beh
380 pirq_ms => 6,
380 pirq_ms => 6,
381 pirq_wfp => 14,
381 pirq_wfp => 14,
382 hindex => 2,
382 hindex => 2,
383 top_lfr_version => X"010139") -- aa.bb.cc version
383 top_lfr_version => X"01013A") -- aa.bb.cc version
384 -- AA : BOARD NUMBER
384 -- AA : BOARD NUMBER
385 -- 0 => MINI_LFR
385 -- 0 => MINI_LFR
386 -- 1 => EM
386 -- 1 => EM
@@ -342,7 +342,7 BEGIN -- beh
342 dbguart => 0,
342 dbguart => 0,
343 pclow => 2,
343 pclow => 2,
344 clk_freq => 25000,
344 clk_freq => 25000,
345 IS_RADHARD => 1,
345 IS_RADHARD => 0,
346 NB_CPU => 1,
346 NB_CPU => 1,
347 ENABLE_FPU => 1,
347 ENABLE_FPU => 1,
348 FPU_NETLIST => 0,
348 FPU_NETLIST => 0,
@@ -517,7 +517,7 BEGIN -- beh
517 pirq_ms => 6,
517 pirq_ms => 6,
518 pirq_wfp => 14,
518 pirq_wfp => 14,
519 hindex => 2,
519 hindex => 2,
520 top_lfr_version => X"000138") -- aa.bb.cc version
520 top_lfr_version => X"00013A") -- aa.bb.cc version
521 PORT MAP (
521 PORT MAP (
522 clk => clk_25,
522 clk => clk_25,
523 rstn => LFR_rstn,
523 rstn => LFR_rstn,
@@ -75,8 +75,6 ARCHITECTURE beh OF cic_lfr_r2 IS
75 --
75 --
76 CONSTANT S_parameter : INTEGER := 3;
76 CONSTANT S_parameter : INTEGER := 3;
77 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
77 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
78 SIGNAL CARRY_PUSH : STD_LOGIC;
79 SIGNAL CARRY_POP : STD_LOGIC;
80 --
78 --
81
79
82 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
80 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -397,4 +395,3 BEGIN
397 END GENERATE all_channel_out_v;
395 END GENERATE all_channel_out_v;
398
396
399 END beh;
397 END beh;
400
@@ -115,9 +115,6 ARCHITECTURE Behavioral OF apb_lfr_manag
115 SIGNAL soft_reset : STD_LOGIC;
115 SIGNAL soft_reset : STD_LOGIC;
116 SIGNAL soft_reset_sync : STD_LOGIC;
116 SIGNAL soft_reset_sync : STD_LOGIC;
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
122
119
123 SIGNAL previous_fine_time_bit : STD_LOGIC;
120 SIGNAL previous_fine_time_bit : STD_LOGIC;
@@ -360,9 +357,13 BEGIN
360 -----------------------------------------------------------------------------
357 -----------------------------------------------------------------------------
361
358
362 PROCESS (clk25MHz, resetn)
359 PROCESS (clk25MHz, resetn)
363 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 11; -- freq = 2^(16-BIT)
360 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
364 -- for 11, the update frequency is 32Hz
365 -- for each HK, the update frequency is freq/3
361 -- for each HK, the update frequency is freq/3
362 --
363 -- for 14, the update frequency is
364 -- 4Hz and update for each
365 -- HK is 1.33Hz
366
366 BEGIN -- PROCESS
367 BEGIN -- PROCESS
367 IF resetn = '0' THEN -- asynchronous reset (active low)
368 IF resetn = '0' THEN -- asynchronous reset (active low)
368
369
@@ -228,7 +228,12 ARCHITECTURE beh OF lpp_lfr IS
228
228
229 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
229 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
230 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
231 -- SIGNAL run_dma : STD_LOGIC;
231 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
236
232 BEGIN
237 BEGIN
233
238
234 debug_vector <= apb_reg_debug_vector;
239 debug_vector <= apb_reg_debug_vector;
@@ -236,6 +241,7 BEGIN
236
241
237 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
242 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
238 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
243 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
244 sample_time <= coarse_time & fine_time;
239
245
240 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
246 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
241 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
247 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
@@ -248,6 +254,7 BEGIN
248 PORT MAP (
254 PORT MAP (
249 sample => sample_s,
255 sample => sample_s,
250 sample_val => sample_val,
256 sample_val => sample_val,
257 sample_time => sample_time,
251 clk => clk,
258 clk => clk,
252 rstn => rstn,
259 rstn => rstn,
253 data_shaping_SP0 => data_shaping_SP0,
260 data_shaping_SP0 => data_shaping_SP0,
@@ -262,7 +269,12 BEGIN
262 sample_f0_wdata => sample_f0_data,
269 sample_f0_wdata => sample_f0_data,
263 sample_f1_wdata => sample_f1_data,
270 sample_f1_wdata => sample_f1_data,
264 sample_f2_wdata => sample_f2_data,
271 sample_f2_wdata => sample_f2_data,
265 sample_f3_wdata => sample_f3_data);
272 sample_f3_wdata => sample_f3_data,
273 sample_f0_time => sample_f0_time,
274 sample_f1_time => sample_f1_time,
275 sample_f2_time => sample_f2_time,
276 sample_f3_time => sample_f3_time
277 );
266
278
267 -----------------------------------------------------------------------------
279 -----------------------------------------------------------------------------
268 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
280 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
@@ -393,20 +405,24 BEGIN
393 error_buffer_full => wfp_error_buffer_full,
405 error_buffer_full => wfp_error_buffer_full,
394
406
395 coarse_time => coarse_time,
407 coarse_time => coarse_time,
396 fine_time => fine_time,
408 -- fine_time => fine_time,
397
409
398 --f0
410 --f0
399 data_f0_in_valid => sample_f0_val,
411 data_f0_in_valid => sample_f0_val,
400 data_f0_in => sample_f0_data,
412 data_f0_in => sample_f0_data,
413 data_f0_time => sample_f0_time,
401 --f1
414 --f1
402 data_f1_in_valid => sample_f1_val,
415 data_f1_in_valid => sample_f1_val,
403 data_f1_in => sample_f1_data,
416 data_f1_in => sample_f1_data,
417 data_f1_time => sample_f1_time,
404 --f2
418 --f2
405 data_f2_in_valid => sample_f2_val,
419 data_f2_in_valid => sample_f2_val,
406 data_f2_in => sample_f2_data,
420 data_f2_in => sample_f2_data,
421 data_f2_time => sample_f2_time,
407 --f3
422 --f3
408 data_f3_in_valid => sample_f3_val,
423 data_f3_in_valid => sample_f3_val,
409 data_f3_in => sample_f3_data,
424 data_f3_in => sample_f3_data,
425 data_f3_time => sample_f3_time,
410 -- OUTPUT -- DMA interface
426 -- OUTPUT -- DMA interface
411
427
412 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
428 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
@@ -452,14 +468,16 BEGIN
452 start_date => start_date,
468 start_date => start_date,
453
469
454 coarse_time => coarse_time,
470 coarse_time => coarse_time,
455 fine_time => fine_time,
456
471
457 sample_f0_wen => sample_f0_wen,
472 sample_f0_wen => sample_f0_wen,
458 sample_f0_wdata => sample_f0_wdata,
473 sample_f0_wdata => sample_f0_wdata,
474 sample_f0_time => sample_f0_time,
459 sample_f1_wen => sample_f1_wen,
475 sample_f1_wen => sample_f1_wen,
460 sample_f1_wdata => sample_f1_wdata,
476 sample_f1_wdata => sample_f1_wdata,
477 sample_f1_time => sample_f1_time,
461 sample_f2_wen => sample_f2_wen,
478 sample_f2_wen => sample_f2_wen,
462 sample_f2_wdata => sample_f2_wdata,
479 sample_f2_wdata => sample_f2_wdata,
480 sample_f2_time => sample_f2_time,
463
481
464 --DMA
482 --DMA
465 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
483 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
@@ -521,4 +539,4 BEGIN
521 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
539 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
522 grant_error => dma_grant_error); --grant_error);
540 grant_error => dma_grant_error); --grant_error);
523
541
524 END beh;
542 END beh; No newline at end of file
@@ -50,6 +50,7 ENTITY lpp_lfr_filter IS
50 PORT (
50 PORT (
51 sample : IN Samples(7 DOWNTO 0);
51 sample : IN Samples(7 DOWNTO 0);
52 sample_val : IN STD_LOGIC;
52 sample_val : IN STD_LOGIC;
53 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
53 --
54 --
54 clk : IN STD_LOGIC;
55 clk : IN STD_LOGIC;
55 rstn : IN STD_LOGIC;
56 rstn : IN STD_LOGIC;
@@ -68,7 +69,12 ENTITY lpp_lfr_filter IS
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
72 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
73 --
74 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
75 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
72 );
78 );
73 END lpp_lfr_filter;
79 END lpp_lfr_filter;
74
80
@@ -159,6 +165,9 ARCHITECTURE tb OF lpp_lfr_filter IS
159
165
160 SIGNAL sample_f0_val_s : STD_LOGIC;
166 SIGNAL sample_f0_val_s : STD_LOGIC;
161 SIGNAL sample_f1_val_s : STD_LOGIC;
167 SIGNAL sample_f1_val_s : STD_LOGIC;
168 SIGNAL sample_f1_val_ss : STD_LOGIC;
169 SIGNAL sample_f2_val_s : STD_LOGIC;
170 SIGNAL sample_f3_val_s : STD_LOGIC;
162
171
163 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
164 -- CONFIG FILTER IIR f0 to f1
173 -- CONFIG FILTER IIR f0 to f1
@@ -214,6 +223,16 ARCHITECTURE tb OF lpp_lfr_filter IS
214 f2_f3_gain);
223 f2_f3_gain);
215 -----------------------------------------------------------------------------
224 -----------------------------------------------------------------------------
216
225
226 SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
227 SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
228 SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
229 SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 -- SIGNAL sample_f2_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 -- SIGNAL sample_f3_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
217
236
218 BEGIN
237 BEGIN
219
238
@@ -259,6 +278,24 BEGIN
259 sample_out_val => sample_filter_v2_out_val,
278 sample_out_val => sample_filter_v2_out_val,
260 sample_out => sample_filter_v2_out);
279 sample_out => sample_filter_v2_out);
261
280
281 -- TIME --
282 PROCESS (clk, rstn)
283 BEGIN -- PROCESS
284 IF rstn = '0' THEN -- asynchronous reset (active low)
285 sample_time_reg <= (OTHERS => '0');
286 sample_filter_v2_out_time <= (OTHERS => '0');
287 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
288 IF sample_val = '1' THEN
289 sample_time_reg <= sample_time;
290 END IF;
291 IF sample_filter_v2_out_val = '1' THEN
292 sample_filter_v2_out_time <= sample_time_reg;
293 END IF;
294 END IF;
295 END PROCESS;
296 ----------
297
298
262 -----------------------------------------------------------------------------
299 -----------------------------------------------------------------------------
263 -- DATA_SHAPING
300 -- DATA_SHAPING
264 -----------------------------------------------------------------------------
301 -----------------------------------------------------------------------------
@@ -336,6 +373,21 BEGIN
336 sample_out_val => sample_f0_val_s,
373 sample_out_val => sample_f0_val_s,
337 sample_out => sample_f0);
374 sample_out => sample_f0);
338
375
376 -- TIME --
377 PROCESS (clk, rstn)
378 BEGIN
379 IF rstn = '0' THEN
380 sample_f0_time_reg <= (OTHERS => '0');
381 ELSIF clk'event AND clk = '1' THEN
382 IF sample_f0_val_s = '1' THEN
383 sample_f0_time_reg <= sample_filter_v2_out_time;
384 END IF;
385 END IF;
386 END PROCESS;
387 sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg;
388 sample_f0_time <= sample_f0_time_s;
389 ----------
390
339 sample_f0_val <= sample_f0_val_s;
391 sample_f0_val <= sample_f0_val_s;
340
392
341 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
393 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
@@ -401,9 +453,27 BEGIN
401 rstn => rstn,
453 rstn => rstn,
402 sample_in_val => sample_f1_val_s,
454 sample_in_val => sample_f1_val_s,
403 sample_in => sample_f1_s,
455 sample_in => sample_f1_s,
404 sample_out_val => sample_f1_val,
456 sample_out_val => sample_f1_val_ss,
405 sample_out => sample_f1);
457 sample_out => sample_f1);
406
458
459 sample_f1_val <= sample_f1_val_ss;
460
461 -- TIME --
462 PROCESS (clk, rstn)
463 BEGIN
464 IF rstn = '0' THEN
465 sample_f1_time_reg <= (OTHERS => '0');
466 ELSIF clk'event AND clk = '1' THEN
467 IF sample_f1_val_ss = '1' THEN
468 sample_f1_time_reg <= sample_f0_time_s;
469 END IF;
470 END IF;
471 END PROCESS;
472 sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg;
473 sample_f1_time <= sample_f1_time_s;
474 ----------
475
476
407 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
477 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
408 all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
478 all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
409 sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
479 sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
@@ -509,9 +579,11 BEGIN
509 rstn => rstn,
579 rstn => rstn,
510 sample_in_val => sample_f2_filter_val ,
580 sample_in_val => sample_f2_filter_val ,
511 sample_in => sample_f2_cic_s,
581 sample_in => sample_f2_cic_s,
512 sample_out_val => sample_f2_val,
582 sample_out_val => sample_f2_val_s,
513 sample_out => sample_f2);
583 sample_out => sample_f2);
514
584
585 sample_f2_val <= sample_f2_val_s;
586
515 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
587 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
516 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
588 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
517 sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
589 sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
@@ -530,8 +602,9 BEGIN
530 rstn => rstn,
602 rstn => rstn,
531 sample_in_val => sample_f3_filter_val ,
603 sample_in_val => sample_f3_filter_val ,
532 sample_in => sample_f3_cic_s,
604 sample_in => sample_f3_cic_s,
533 sample_out_val => sample_f3_val,
605 sample_out_val => sample_f3_val_s,
534 sample_out => sample_f3);
606 sample_out => sample_f3);
607 sample_f3_val <= sample_f3_val_s;
535
608
536 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
609 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
537 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
610 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
@@ -540,6 +613,23 BEGIN
540 END GENERATE all_bit_sample_f3;
613 END GENERATE all_bit_sample_f3;
541
614
542 -----------------------------------------------------------------------------
615 -----------------------------------------------------------------------------
616
617 -- TIME --
618 PROCESS (clk, rstn)
619 BEGIN
620 IF rstn = '0' THEN
621 sample_f2_time_reg <= (OTHERS => '0');
622 sample_f3_time_reg <= (OTHERS => '0');
623 ELSIF clk'event AND clk = '1' THEN
624 IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF;
625 IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF;
626 END IF;
627 END PROCESS;
628 sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg;
629 sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg;
630 ----------
631
632 -----------------------------------------------------------------------------
543 --
633 --
544 -----------------------------------------------------------------------------
634 -----------------------------------------------------------------------------
545 sample_f0_wdata <= sample_f0_wdata_s;
635 sample_f0_wdata <= sample_f0_wdata_s;
@@ -28,18 +28,20 ENTITY lpp_lfr_ms IS
28 -- DATA INPUT
28 -- DATA INPUT
29 ---------------------------------------------------------------------------
29 ---------------------------------------------------------------------------
30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 -- TIME
31 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
32 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
32 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
33 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
34 --
33 --
35 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
37 --
37 --
38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
40 --
41 --
41 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
43
45
44 ---------------------------------------------------------------------------
46 ---------------------------------------------------------------------------
45 -- DMA
47 -- DMA
@@ -217,7 +219,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
217 -----------------------------------------------------------------------------
219 -----------------------------------------------------------------------------
218 -- TIME REG & INFOs
220 -- TIME REG & INFOs
219 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
220 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
222 SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
221
223
222 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
224 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
223 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
225 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -1173,7 +1175,8 BEGIN
1173 -----------------------------------------------------------------------------
1175 -----------------------------------------------------------------------------
1174 -- TIME MANAGMENT
1176 -- TIME MANAGMENT
1175 -----------------------------------------------------------------------------
1177 -----------------------------------------------------------------------------
1176 all_time <= coarse_time & fine_time;
1178 all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
1179 --all_time <= coarse_time & fine_time;
1177 --
1180 --
1178 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1181 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1179 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1182 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
@@ -1197,7 +1200,7 BEGIN
1197 PORT MAP (
1200 PORT MAP (
1198 clk => clk,
1201 clk => clk,
1199 rstn => rstn,
1202 rstn => rstn,
1200 time_in => all_time,
1203 time_in => all_time((I+1)*48-1 DOWNTO I*48),
1201 update_1 => time_update_f(I),
1204 update_1 => time_update_f(I),
1202 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1205 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1203 );
1206 );
@@ -76,13 +76,15 PACKAGE lpp_lfr_pkg IS
76 run : IN STD_LOGIC;
76 run : IN STD_LOGIC;
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
84 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
86 dma_fifo_burst_valid : OUT STD_LOGIC;
88 dma_fifo_burst_valid : OUT STD_LOGIC;
87 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 dma_fifo_ren : IN STD_LOGIC;
90 dma_fifo_ren : IN STD_LOGIC;
@@ -169,6 +171,7 PACKAGE lpp_lfr_pkg IS
169 PORT (
171 PORT (
170 sample : IN Samples(7 DOWNTO 0);
172 sample : IN Samples(7 DOWNTO 0);
171 sample_val : IN STD_LOGIC;
173 sample_val : IN STD_LOGIC;
174 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
172 clk : IN STD_LOGIC;
175 clk : IN STD_LOGIC;
173 rstn : IN STD_LOGIC;
176 rstn : IN STD_LOGIC;
174 data_shaping_SP0 : IN STD_LOGIC;
177 data_shaping_SP0 : IN STD_LOGIC;
@@ -183,7 +186,12 PACKAGE lpp_lfr_pkg IS
183 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
186 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
187 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
185 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
188 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
186 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
189 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
190 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
191 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
192 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
193 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
194 );
187 END COMPONENT;
195 END COMPONENT;
188
196
189 COMPONENT lpp_lfr
197 COMPONENT lpp_lfr
@@ -392,4 +400,4 PACKAGE lpp_lfr_pkg IS
392 out_full : OUT STD_LOGIC);
400 out_full : OUT STD_LOGIC);
393 END COMPONENT;
401 END COMPONENT;
394
402
395 END lpp_lfr_pkg;
403 END lpp_lfr_pkg; No newline at end of file
@@ -94,20 +94,24 ENTITY lpp_waveform IS
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 -- INPUT
95 -- INPUT
96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
97 -- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
98
98
99 --f0
99 --f0
100 data_f0_in_valid : IN STD_LOGIC;
100 data_f0_in_valid : IN STD_LOGIC;
101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
102 --f1
103 --f1
103 data_f1_in_valid : IN STD_LOGIC;
104 data_f1_in_valid : IN STD_LOGIC;
104 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106 data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
105 --f2
107 --f2
106 data_f2_in_valid : IN STD_LOGIC;
108 data_f2_in_valid : IN STD_LOGIC;
107 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
109 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
110 data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
108 --f3
111 --f3
109 data_f3_in_valid : IN STD_LOGIC;
112 data_f3_in_valid : IN STD_LOGIC;
110 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
113 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
114 data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
111
115
112 ---------------------------------------------------------------------------
116 ---------------------------------------------------------------------------
113 -- DMA --------------------------------------------------------------------
117 -- DMA --------------------------------------------------------------------
@@ -172,8 +176,8 ARCHITECTURE beh OF lpp_waveform IS
172 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
176 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
173 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
177 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
174 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
178 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
177 --
181 --
178
182
179 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
183 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
@@ -301,7 +305,10 BEGIN -- beh
301 time_reg1 <= (OTHERS => '0');
305 time_reg1 <= (OTHERS => '0');
302 time_reg2 <= (OTHERS => '0');
306 time_reg2 <= (OTHERS => '0');
303 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
307 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
304 time_reg1 <= fine_time & coarse_time;
308 time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);
309 time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);
310 time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);
311 time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);
305 time_reg2 <= time_reg1;
312 time_reg2 <= time_reg1;
306 END IF;
313 END IF;
307 END PROCESS;
314 END PROCESS;
@@ -315,7 +322,7 BEGIN -- beh
315 run => run,
322 run => run,
316 valid_in => valid_in(I),
323 valid_in => valid_in(I),
317 ack_in => valid_ack(I),
324 ack_in => valid_ack(I),
318 time_in => time_reg2, -- Todo
325 time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo
319 valid_out => valid_out(I),
326 valid_out => valid_out(I),
320 time_out => time_out(I), -- Todo
327 time_out => time_out(I), -- Todo
321 error => status_new_err(I));
328 error => status_new_err(I));
@@ -135,15 +135,19 PACKAGE lpp_waveform_pkg IS
135 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
135 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
136 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
137 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
138 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
139 data_f0_in_valid : IN STD_LOGIC;
139 data_f0_in_valid : IN STD_LOGIC;
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
141 data_f1_in_valid : IN STD_LOGIC;
142 data_f1_in_valid : IN STD_LOGIC;
142 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
143 data_f2_in_valid : IN STD_LOGIC;
145 data_f2_in_valid : IN STD_LOGIC;
144 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
145 data_f3_in_valid : IN STD_LOGIC;
148 data_f3_in_valid : IN STD_LOGIC;
146 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
147
151
148 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
152 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
149 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
153 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
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