diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd --- a/designs/LFR-em-WFP_MS/LFR-em.vhd +++ b/designs/LFR-em-WFP_MS/LFR-em.vhd @@ -380,7 +380,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"010139") -- aa.bb.cc version + top_lfr_version => X"01013A") -- aa.bb.cc version -- AA : BOARD NUMBER -- 0 => MINI_LFR -- 1 => EM diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -342,7 +342,7 @@ BEGIN -- beh dbguart => 0, pclow => 2, clk_freq => 25000, - IS_RADHARD => 1, + IS_RADHARD => 0, NB_CPU => 1, ENABLE_FPU => 1, FPU_NETLIST => 0, @@ -517,7 +517,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000138") -- aa.bb.cc version + top_lfr_version => X"00013A") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, diff --git a/lib/lpp/dsp/cic/cic_lfr_r2.vhd b/lib/lpp/dsp/cic/cic_lfr_r2.vhd --- a/lib/lpp/dsp/cic/cic_lfr_r2.vhd +++ b/lib/lpp/dsp/cic/cic_lfr_r2.vhd @@ -75,8 +75,6 @@ ARCHITECTURE beh OF cic_lfr_r2 IS -- CONSTANT S_parameter : INTEGER := 3; SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0); - SIGNAL CARRY_PUSH : STD_LOGIC; - SIGNAL CARRY_POP : STD_LOGIC; -- SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0); @@ -397,4 +395,3 @@ BEGIN END GENERATE all_channel_out_v; END beh; - diff --git a/lib/lpp/lfr_management/apb_lfr_management.vhd b/lib/lpp/lfr_management/apb_lfr_management.vhd --- a/lib/lpp/lfr_management/apb_lfr_management.vhd +++ b/lib/lpp/lfr_management/apb_lfr_management.vhd @@ -115,9 +115,6 @@ ARCHITECTURE Behavioral OF apb_lfr_manag SIGNAL soft_reset : STD_LOGIC; SIGNAL soft_reset_sync : STD_LOGIC; ----------------------------------------------------------------------------- - SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL previous_fine_time_bit : STD_LOGIC; @@ -360,9 +357,13 @@ BEGIN ----------------------------------------------------------------------------- PROCESS (clk25MHz, resetn) - CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 11; -- freq = 2^(16-BIT) - -- for 11, the update frequency is 32Hz + CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT) -- for each HK, the update frequency is freq/3 + -- + -- for 14, the update frequency is + -- 4Hz and update for each + -- HK is 1.33Hz + BEGIN -- PROCESS IF resetn = '0' THEN -- asynchronous reset (active low) diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -228,7 +228,12 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); ----------------------------------------------------------------------------- --- SIGNAL run_dma : STD_LOGIC; + SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + BEGIN debug_vector <= apb_reg_debug_vector; @@ -236,7 +241,8 @@ BEGIN sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); - + sample_time <= coarse_time & fine_time; + --all_channel : FOR i IN 7 DOWNTO 0 GENERATE -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); --END GENERATE all_channel; @@ -248,6 +254,7 @@ BEGIN PORT MAP ( sample => sample_s, sample_val => sample_val, + sample_time => sample_time, clk => clk, rstn => rstn, data_shaping_SP0 => data_shaping_SP0, @@ -262,7 +269,12 @@ BEGIN sample_f0_wdata => sample_f0_data, sample_f1_wdata => sample_f1_data, sample_f2_wdata => sample_f2_data, - sample_f3_wdata => sample_f3_data); + sample_f3_wdata => sample_f3_data, + sample_f0_time => sample_f0_time, + sample_f1_time => sample_f1_time, + sample_f2_time => sample_f2_time, + sample_f3_time => sample_f3_time + ); ----------------------------------------------------------------------------- lpp_lfr_apbreg_1 : lpp_lfr_apbreg @@ -393,20 +405,24 @@ BEGIN error_buffer_full => wfp_error_buffer_full, coarse_time => coarse_time, - fine_time => fine_time, +-- fine_time => fine_time, --f0 data_f0_in_valid => sample_f0_val, data_f0_in => sample_f0_data, + data_f0_time => sample_f0_time, --f1 data_f1_in_valid => sample_f1_val, data_f1_in => sample_f1_data, + data_f1_time => sample_f1_time, --f2 data_f2_in_valid => sample_f2_val, data_f2_in => sample_f2_data, + data_f2_time => sample_f2_time, --f3 data_f3_in_valid => sample_f3_val, data_f3_in => sample_f3_data, + data_f3_time => sample_f3_time, -- OUTPUT -- DMA interface dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0), @@ -452,14 +468,16 @@ BEGIN start_date => start_date, coarse_time => coarse_time, - fine_time => fine_time, sample_f0_wen => sample_f0_wen, sample_f0_wdata => sample_f0_wdata, + sample_f0_time => sample_f0_time, sample_f1_wen => sample_f1_wen, sample_f1_wdata => sample_f1_wdata, + sample_f1_time => sample_f1_time, sample_f2_wen => sample_f2_wen, sample_f2_wdata => sample_f2_wdata, + sample_f2_time => sample_f2_time, --DMA dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT @@ -521,4 +539,4 @@ BEGIN buffer_full_err => dma_buffer_full_err, --buffer_full_err, grant_error => dma_grant_error); --grant_error); -END beh; +END beh; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd @@ -50,6 +50,7 @@ ENTITY lpp_lfr_filter IS PORT ( sample : IN Samples(7 DOWNTO 0); sample_val : IN STD_LOGIC; + sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); -- clk : IN STD_LOGIC; rstn : IN STD_LOGIC; @@ -68,7 +69,12 @@ ENTITY lpp_lfr_filter IS sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0) + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) ); END lpp_lfr_filter; @@ -159,6 +165,9 @@ ARCHITECTURE tb OF lpp_lfr_filter IS SIGNAL sample_f0_val_s : STD_LOGIC; SIGNAL sample_f1_val_s : STD_LOGIC; + SIGNAL sample_f1_val_ss : STD_LOGIC; + SIGNAL sample_f2_val_s : STD_LOGIC; + SIGNAL sample_f3_val_s : STD_LOGIC; ----------------------------------------------------------------------------- -- CONFIG FILTER IIR f0 to f1 @@ -214,6 +223,16 @@ ARCHITECTURE tb OF lpp_lfr_filter IS f2_f3_gain); ----------------------------------------------------------------------------- + SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); +-- SIGNAL sample_f2_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); +-- SIGNAL sample_f3_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0); BEGIN @@ -259,6 +278,24 @@ BEGIN sample_out_val => sample_filter_v2_out_val, sample_out => sample_filter_v2_out); + -- TIME -- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_time_reg <= (OTHERS => '0'); + sample_filter_v2_out_time <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF sample_val = '1' THEN + sample_time_reg <= sample_time; + END IF; + IF sample_filter_v2_out_val = '1' THEN + sample_filter_v2_out_time <= sample_time_reg; + END IF; + END IF; + END PROCESS; + ---------- + + ----------------------------------------------------------------------------- -- DATA_SHAPING ----------------------------------------------------------------------------- @@ -336,6 +373,21 @@ BEGIN sample_out_val => sample_f0_val_s, sample_out => sample_f0); + -- TIME -- + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_f0_time_reg <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN + IF sample_f0_val_s = '1' THEN + sample_f0_time_reg <= sample_filter_v2_out_time; + END IF; + END IF; + END PROCESS; + sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg; + sample_f0_time <= sample_f0_time_s; + ---------- + sample_f0_val <= sample_f0_val_s; all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE @@ -401,8 +453,26 @@ BEGIN rstn => rstn, sample_in_val => sample_f1_val_s, sample_in => sample_f1_s, - sample_out_val => sample_f1_val, - sample_out => sample_f1); + sample_out_val => sample_f1_val_ss, + sample_out => sample_f1); + + sample_f1_val <= sample_f1_val_ss; + + -- TIME -- + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_f1_time_reg <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN + IF sample_f1_val_ss = '1' THEN + sample_f1_time_reg <= sample_f0_time_s; + END IF; + END IF; + END PROCESS; + sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg; + sample_f1_time <= sample_f1_time_s; + ---------- + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE @@ -509,8 +579,10 @@ BEGIN rstn => rstn, sample_in_val => sample_f2_filter_val , sample_in => sample_f2_cic_s, - sample_out_val => sample_f2_val, - sample_out => sample_f2); + sample_out_val => sample_f2_val_s, + sample_out => sample_f2); + + sample_f2_val <= sample_f2_val_s; all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE @@ -530,14 +602,32 @@ BEGIN rstn => rstn, sample_in_val => sample_f3_filter_val , sample_in => sample_f3_cic_s, - sample_out_val => sample_f3_val, + sample_out_val => sample_f3_val_s, sample_out => sample_f3); + sample_f3_val <= sample_f3_val_s; all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE sample_f3_wdata_s(16*J+I) <= sample_f3(J,I); END GENERATE all_channel_sample_f3; - END GENERATE all_bit_sample_f3; + END GENERATE all_bit_sample_f3; + + ----------------------------------------------------------------------------- + + -- TIME -- + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_f2_time_reg <= (OTHERS => '0'); + sample_f3_time_reg <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN + IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF; + IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF; + END IF; + END PROCESS; + sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg; + sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg; + ---------- ----------------------------------------------------------------------------- -- diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -28,18 +28,20 @@ ENTITY lpp_lfr_ms IS -- DATA INPUT --------------------------------------------------------------------------- start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); - -- TIME - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo -- sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); -- sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); -- sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); --------------------------------------------------------------------------- -- DMA @@ -217,7 +219,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS ----------------------------------------------------------------------------- -- TIME REG & INFOs ----------------------------------------------------------------------------- - SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -1173,7 +1175,8 @@ BEGIN ----------------------------------------------------------------------------- -- TIME MANAGMENT ----------------------------------------------------------------------------- - all_time <= coarse_time & fine_time; + all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time; + --all_time <= coarse_time & fine_time; -- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; @@ -1197,7 +1200,7 @@ BEGIN PORT MAP ( clk => clk, rstn => rstn, - time_in => all_time, + time_in => all_time((I+1)*48-1 DOWNTO I*48), update_1 => time_update_f(I), time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) ); diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -1,395 +1,403 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -PACKAGE lpp_lfr_pkg IS - ----------------------------------------------------------------------------- - -- TEMP - ----------------------------------------------------------------------------- - COMPONENT lpp_lfr_ms_test - GENERIC ( - Mem_use : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - -- TIME - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo - -- - sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - - - --------------------------------------------------------------------------- - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - - -- - --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); - - -- IN - MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - - ----------------------------------------------------------------------------- - - status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); - SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); - SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - - SM_correlation_start : OUT STD_LOGIC; - SM_correlation_auto : OUT STD_LOGIC; - SM_correlation_done : IN STD_LOGIC - ); - END COMPONENT; - - - ----------------------------------------------------------------------------- - COMPONENT lpp_lfr_ms - GENERIC ( - Mem_use : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - run : IN STD_LOGIC; - start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - dma_fifo_burst_valid : OUT STD_LOGIC; - dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_fifo_ren : IN STD_LOGIC; - dma_buffer_new : OUT STD_LOGIC; - dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - dma_buffer_full : IN STD_LOGIC; - dma_buffer_full_err : IN STD_LOGIC; - ready_matrix_f0 : OUT STD_LOGIC; - ready_matrix_f1 : OUT STD_LOGIC; - ready_matrix_f2 : OUT STD_LOGIC; - error_buffer_full : OUT STD_LOGIC; - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - status_ready_matrix_f0 : IN STD_LOGIC; - status_ready_matrix_f1 : IN STD_LOGIC; - status_ready_matrix_f2 : IN STD_LOGIC; - addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); - length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); - length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); - matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_lfr_ms_fsmdma - PORT ( - clk : IN STD_ULOGIC; - rstn : IN STD_ULOGIC; - run : IN STD_LOGIC; - fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fifo_empty : IN STD_LOGIC; - fifo_empty_threshold : IN STD_LOGIC; - fifo_ren : OUT STD_LOGIC; - dma_fifo_valid_burst : OUT STD_LOGIC; - dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_fifo_ren : IN STD_LOGIC; - dma_buffer_new : OUT STD_LOGIC; - dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - dma_buffer_full : IN STD_LOGIC; - dma_buffer_full_err : IN STD_LOGIC; - status_ready_matrix_f0 : IN STD_LOGIC; - status_ready_matrix_f1 : IN STD_LOGIC; - status_ready_matrix_f2 : IN STD_LOGIC; - addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); - length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); - length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); - ready_matrix_f0 : OUT STD_LOGIC; - ready_matrix_f1 : OUT STD_LOGIC; - ready_matrix_f2 : OUT STD_LOGIC; - matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - error_buffer_full : OUT STD_LOGIC); - END COMPONENT; - - COMPONENT lpp_lfr_ms_FFT - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_valid : IN STD_LOGIC; - fft_read : IN STD_LOGIC; - sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - sample_load : OUT STD_LOGIC; - fft_pong : OUT STD_LOGIC; - fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - fft_data_valid : OUT STD_LOGIC; - fft_ready : OUT STD_LOGIC); - END COMPONENT; - - COMPONENT lpp_lfr_filter - GENERIC ( - Mem_use : INTEGER); - PORT ( - sample : IN Samples(7 DOWNTO 0); - sample_val : IN STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - data_shaping_SP0 : IN STD_LOGIC; - data_shaping_SP1 : IN STD_LOGIC; - data_shaping_R0 : IN STD_LOGIC; - data_shaping_R1 : IN STD_LOGIC; - data_shaping_R2 : IN STD_LOGIC; - sample_f0_val : OUT STD_LOGIC; - sample_f1_val : OUT STD_LOGIC; - sample_f2_val : OUT STD_LOGIC; - sample_f3_val : OUT STD_LOGIC; - sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_lfr - GENERIC ( - Mem_use : INTEGER; - nb_data_by_buffer_size : INTEGER; --- nb_word_by_buffer_size : INTEGER; - nb_snapshot_param_size : INTEGER; - delta_vector_size : INTEGER; - delta_vector_size_f0_2 : INTEGER; - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq_ms : INTEGER; - pirq_wfp : INTEGER; - hindex : INTEGER; - top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_B : IN Samples(2 DOWNTO 0); - sample_E : IN Samples(4 DOWNTO 0); - sample_val : IN STD_LOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - ahbi : IN AHB_Mst_In_Type; - ahbo : OUT AHB_Mst_Out_Type; - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data_shaping_BW : OUT STD_LOGIC ; - debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) - ); - END COMPONENT; - - ----------------------------------------------------------------------------- - -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) - ----------------------------------------------------------------------------- - COMPONENT lpp_lfr_WFP_nMS - GENERIC ( - Mem_use : INTEGER; - nb_data_by_buffer_size : INTEGER; - nb_word_by_buffer_size : INTEGER; - nb_snapshot_param_size : INTEGER; - delta_vector_size : INTEGER; - delta_vector_size_f0_2 : INTEGER; - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq_ms : INTEGER; - pirq_wfp : INTEGER; - hindex : INTEGER; - top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_B : IN Samples(2 DOWNTO 0); - sample_E : IN Samples(4 DOWNTO 0); - sample_val : IN STD_LOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - ahbi : IN AHB_Mst_In_Type; - ahbo : OUT AHB_Mst_Out_Type; - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data_shaping_BW : OUT STD_LOGIC; - observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - END COMPONENT; - ----------------------------------------------------------------------------- - - COMPONENT lpp_lfr_apbreg - GENERIC ( - nb_data_by_buffer_size : INTEGER; - nb_snapshot_param_size : INTEGER; - delta_vector_size : INTEGER; - delta_vector_size_f0_2 : INTEGER; - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq_ms : INTEGER; - pirq_wfp : INTEGER; - top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); - PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - run_ms : OUT STD_LOGIC; - ready_matrix_f0 : IN STD_LOGIC; - ready_matrix_f1 : IN STD_LOGIC; - ready_matrix_f2 : IN STD_LOGIC; - error_buffer_full : IN STD_LOGIC; - error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); - status_ready_matrix_f0 : OUT STD_LOGIC; - status_ready_matrix_f1 : OUT STD_LOGIC; - status_ready_matrix_f2 : OUT STD_LOGIC; - addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - data_shaping_BW : OUT STD_LOGIC; - data_shaping_SP0 : OUT STD_LOGIC; - data_shaping_SP1 : OUT STD_LOGIC; - data_shaping_R0 : OUT STD_LOGIC; - data_shaping_R1 : OUT STD_LOGIC; - data_shaping_R2 : OUT STD_LOGIC; - delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); - delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - enable_f0 : OUT STD_LOGIC; - enable_f1 : OUT STD_LOGIC; - enable_f2 : OUT STD_LOGIC; - enable_f3 : OUT STD_LOGIC; - burst_f0 : OUT STD_LOGIC; - burst_f1 : OUT STD_LOGIC; - burst_f2 : OUT STD_LOGIC; - run : OUT STD_LOGIC; - start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); - wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); - wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - sample_f3_valid : IN STD_LOGIC; - debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_top_ms - GENERIC ( - Mem_use : INTEGER; - nb_burst_available_size : INTEGER; - nb_snapshot_param_size : INTEGER; - delta_snapshot_size : INTEGER; - delta_f2_f0_size : INTEGER; - delta_f2_f1_size : INTEGER; - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq_ms : INTEGER; - pirq_wfp : INTEGER; - hindex_wfp : INTEGER; - hindex_ms : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_B : IN Samples14v(2 DOWNTO 0); - sample_E : IN Samples14v(4 DOWNTO 0); - sample_val : IN STD_LOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - ahbi_ms : IN AHB_Mst_In_Type; - ahbo_ms : OUT AHB_Mst_Out_Type; - data_shaping_BW : OUT STD_LOGIC; - matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpp_apbreg_ms_pointer - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - run : IN STD_LOGIC; - reg0_status_ready_matrix : IN STD_LOGIC; - reg0_ready_matrix : OUT STD_LOGIC; - reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - reg1_status_ready_matrix : IN STD_LOGIC; - reg1_ready_matrix : OUT STD_LOGIC; - reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - ready_matrix : IN STD_LOGIC; - status_ready_matrix : OUT STD_LOGIC; - addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_lfr_ms_reg_head - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - in_wen : IN STD_LOGIC; - in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - in_full : IN STD_LOGIC; - in_empty : IN STD_LOGIC; - out_write_error : OUT STD_LOGIC; - out_wen : OUT STD_LOGIC; - out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - out_full : OUT STD_LOGIC); - END COMPONENT; - -END lpp_lfr_pkg; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +PACKAGE lpp_lfr_pkg IS + ----------------------------------------------------------------------------- + -- TEMP + ----------------------------------------------------------------------------- + COMPONENT lpp_lfr_ms_test + GENERIC ( + Mem_use : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + -- TIME + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo + -- + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + + + --------------------------------------------------------------------------- + error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- + --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); + + -- IN + MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- + + status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); + SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); + SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + SM_correlation_start : OUT STD_LOGIC; + SM_correlation_auto : OUT STD_LOGIC; + SM_correlation_done : IN STD_LOGIC + ); + END COMPONENT; + + + ----------------------------------------------------------------------------- + COMPONENT lpp_lfr_ms + GENERIC ( + Mem_use : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + dma_fifo_burst_valid : OUT STD_LOGIC; + dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC; + dma_buffer_new : OUT STD_LOGIC; + dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC; + dma_buffer_full_err : IN STD_LOGIC; + ready_matrix_f0 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_buffer_full : OUT STD_LOGIC; + error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + status_ready_matrix_f0 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_lfr_ms_fsmdma + PORT ( + clk : IN STD_ULOGIC; + rstn : IN STD_ULOGIC; + run : IN STD_LOGIC; + fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fifo_empty : IN STD_LOGIC; + fifo_empty_threshold : IN STD_LOGIC; + fifo_ren : OUT STD_LOGIC; + dma_fifo_valid_burst : OUT STD_LOGIC; + dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC; + dma_buffer_new : OUT STD_LOGIC; + dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC; + dma_buffer_full_err : IN STD_LOGIC; + status_ready_matrix_f0 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + ready_matrix_f0 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + error_buffer_full : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_lfr_ms_FFT + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_valid : IN STD_LOGIC; + fft_read : IN STD_LOGIC; + sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_load : OUT STD_LOGIC; + fft_pong : OUT STD_LOGIC; + fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fft_data_valid : OUT STD_LOGIC; + fft_ready : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_lfr_filter + GENERIC ( + Mem_use : INTEGER); + PORT ( + sample : IN Samples(7 DOWNTO 0); + sample_val : IN STD_LOGIC; + sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + data_shaping_R2 : IN STD_LOGIC; + sample_f0_val : OUT STD_LOGIC; + sample_f1_val : OUT STD_LOGIC; + sample_f2_val : OUT STD_LOGIC; + sample_f3_val : OUT STD_LOGIC; + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpp_lfr + GENERIC ( + Mem_use : INTEGER; + nb_data_by_buffer_size : INTEGER; +-- nb_word_by_buffer_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_vector_size : INTEGER; + delta_vector_size_f0_2 : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq_ms : INTEGER; + pirq_wfp : INTEGER; + hindex : INTEGER; + top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_B : IN Samples(2 DOWNTO 0); + sample_E : IN Samples(4 DOWNTO 0); + sample_val : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ahbi : IN AHB_Mst_In_Type; + ahbo : OUT AHB_Mst_Out_Type; + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data_shaping_BW : OUT STD_LOGIC; + debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) + ); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) + ----------------------------------------------------------------------------- + COMPONENT lpp_lfr_WFP_nMS + GENERIC ( + Mem_use : INTEGER; + nb_data_by_buffer_size : INTEGER; + nb_word_by_buffer_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_vector_size : INTEGER; + delta_vector_size_f0_2 : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq_ms : INTEGER; + pirq_wfp : INTEGER; + hindex : INTEGER; + top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_B : IN Samples(2 DOWNTO 0); + sample_E : IN Samples(4 DOWNTO 0); + sample_val : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ahbi : IN AHB_Mst_In_Type; + ahbo : OUT AHB_Mst_Out_Type; + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data_shaping_BW : OUT STD_LOGIC; + observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + ----------------------------------------------------------------------------- + + COMPONENT lpp_lfr_apbreg + GENERIC ( + nb_data_by_buffer_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_vector_size : INTEGER; + delta_vector_size_f0_2 : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq_ms : INTEGER; + pirq_wfp : INTEGER; + top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + run_ms : OUT STD_LOGIC; + ready_matrix_f0 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_buffer_full : IN STD_LOGIC; + error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + status_ready_matrix_f0 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + data_shaping_R2 : OUT STD_LOGIC; + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + run : OUT STD_LOGIC; + start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); + wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_valid : IN STD_LOGIC; + debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_top_ms + GENERIC ( + Mem_use : INTEGER; + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq_ms : INTEGER; + pirq_wfp : INTEGER; + hindex_wfp : INTEGER; + hindex_ms : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_B : IN Samples14v(2 DOWNTO 0); + sample_E : IN Samples14v(4 DOWNTO 0); + sample_val : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ahbi_ms : IN AHB_Mst_In_Type; + ahbo_ms : OUT AHB_Mst_Out_Type; + data_shaping_BW : OUT STD_LOGIC; + matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpp_apbreg_ms_pointer + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + reg0_status_ready_matrix : IN STD_LOGIC; + reg0_ready_matrix : OUT STD_LOGIC; + reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + reg1_status_ready_matrix : IN STD_LOGIC; + reg1_ready_matrix : OUT STD_LOGIC; + reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + ready_matrix : IN STD_LOGIC; + status_ready_matrix : OUT STD_LOGIC; + addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_lfr_ms_reg_head + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + in_wen : IN STD_LOGIC; + in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + in_full : IN STD_LOGIC; + in_empty : IN STD_LOGIC; + out_write_error : OUT STD_LOGIC; + out_wen : OUT STD_LOGIC; + out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + out_full : OUT STD_LOGIC); + END COMPONENT; + +END lpp_lfr_pkg; \ No newline at end of file diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -94,20 +94,24 @@ ENTITY lpp_waveform IS --------------------------------------------------------------------------- -- INPUT coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); +-- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); --f0 data_f0_in_valid : IN STD_LOGIC; data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); --f1 data_f1_in_valid : IN STD_LOGIC; data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); --f2 data_f2_in_valid : IN STD_LOGIC; data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); --f3 data_f3_in_valid : IN STD_LOGIC; data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); --------------------------------------------------------------------------- -- DMA -------------------------------------------------------------------- @@ -172,8 +176,8 @@ ARCHITECTURE beh OF lpp_waveform IS SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug - SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); -- SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b @@ -301,7 +305,10 @@ BEGIN -- beh time_reg1 <= (OTHERS => '0'); time_reg2 <= (OTHERS => '0'); ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - time_reg1 <= fine_time & coarse_time; + time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16); + time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16); + time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16); + time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16); time_reg2 <= time_reg1; END IF; END PROCESS; @@ -315,7 +322,7 @@ BEGIN -- beh run => run, valid_in => valid_in(I), ack_in => valid_ack(I), - time_in => time_reg2, -- Todo + time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo valid_out => valid_out(I), time_out => time_out(I), -- Todo error => status_new_err(I)); diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -135,15 +135,19 @@ PACKAGE lpp_waveform_pkg IS buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); data_f0_in_valid : IN STD_LOGIC; data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); data_f1_in_valid : IN STD_LOGIC; data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); data_f2_in_valid : IN STD_LOGIC; data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); data_f3_in_valid : IN STD_LOGIC; data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);