HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r527:32bdf5e8de1b

Update methodology of data dating into LFR

pellion -

parent child

Context file:

r527:32bdf5e8de1b

Collapse all files

designs/LFR-em-WFP_MS/LFR-em.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY LFR_em IS
               PORT (
                 clk100MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 -- TAG --------------------------------------------------------------------
                 TAG1           : IN    STD_ULOGIC;  -- DSU rx data
                 TAG3           : OUT   STD_ULOGIC;  -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 TAG2           : IN    STD_ULOGIC;  -- UART1 rx data
                 TAG4           : OUT   STD_ULOGIC;  -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address        : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data           : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0      : OUT   STD_LOGIC;
                 nSRAM_BE1      : OUT   STD_LOGIC;
                 nSRAM_BE2      : OUT   STD_LOGIC;
                 nSRAM_BE3      : OUT   STD_LOGIC;
                 nSRAM_WE       : OUT   STD_LOGIC;
                 nSRAM_CE       : OUT   STD_LOGIC;
                 nSRAM_OE       : OUT   STD_LOGIC;
                 -- SPW --------------------------------------------------------------------
                 spw1_din       : IN    STD_LOGIC;
                 spw1_sin       : IN    STD_LOGIC;
                 spw1_dout      : OUT   STD_LOGIC;
                 spw1_sout      : OUT   STD_LOGIC;
                 spw2_din       : IN    STD_LOGIC;
                 spw2_sin       : IN    STD_LOGIC;
                 spw2_dout      : OUT   STD_LOGIC;
                 spw2_sout      : OUT   STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT   STD_LOGIC;
                 ADC_OEB_bar_CH : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT   STD_LOGIC;
                 ADC_data       : IN    STD_LOGIC_VECTOR(13 DOWNTO 0);
                 -- HK ---------------------------------------------------------------------
                 HK_smpclk      : OUT   STD_LOGIC;
                 ADC_OEB_bar_HK : OUT   STD_LOGIC;
                 HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 TAG8           : OUT   STD_LOGIC;
                 led            : OUT   STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
             END LFR_em;
             ARCHITECTURE beh OF LFR_em IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(8 DOWNTO 0);
               SIGNAL sample_s    : Samples(8 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL  ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn : STD_LOGIC;
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
               PROCESS(clk100MHz)
               BEGIN
                 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
                   clk_50_s <= NOT clk_50_s;
                 END IF;
               END PROCESS;
               PROCESS(clk_50_s)
               BEGIN
                 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   led(0) <= '0';
                   led(1) <= '0';
                   led(2) <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   led(0) <= '0';
                   led(1) <= '1';
                   led(2) <= '1';
                 END IF;
               END PROCESS;
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   IS_RADHARD      => 0,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => 0)
                 PORT MAP (
                   clk    => clk_25,
                   reset  => rstn,
                   errorn => OPEN,
                   ahbrxd => TAG1,
                   ahbtxd => TAG3,
                   urxd1  => TAG2,
                   utxd1  => TAG4,
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => nSRAM_BE0,
                   nSRAM_BE1 => nSRAM_BE1,
                   nSRAM_BE2 => nSRAM_BE2,
                   nSRAM_BE3 => nSRAM_BE3,
                   nSRAM_WE  => nSRAM_WE,
                   nSRAM_CE  => nSRAM_CE_s,
                   nSRAM_OE  => nSRAM_OE,
                   nSRAM_READY => '0',
                   SRAM_MBE    => OPEN,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               nSRAM_CE <= nSRAM_CE_s(0);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz      => clk_25,
                   clk24_576MHz  => clk_24,          -- 49.152MHz/2
                   resetn        => rstn,
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                   HK_sample     => sample_s(8),
                   HK_val        => sample_val,
                   HK_sel        => HK_SEL,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
             --  SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"010139")  -- aa.bb.cc version
+                  top_lfr_version        => X"01013A")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw,
                   debug_vector    => OPEN,
                   debug_vector_ms => OPEN);     --,
               --observation_vector_0 => OPEN,
               --observation_vector_1 => OPEN,
               --observation_reg => observation_reg);
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I) & '0' & '0';
               END GENERATE all_sample;
               sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
                 GENERIC MAP (
                   ChanelCount     => 9,
                   ncycle_cnv_high => 13,
                   ncycle_cnv      => 25,
                   FILTER_ENABLED  => 16#FF#)
                 PORT MAP (
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
                   rstn       => rstn,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH_s,
                   sample     => sample,
                   sample_val => sample_val);
               ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
               ADC_smpclk <= ADC_smpclk_s;
               HK_smpclk  <= ADC_smpclk_s;
               TAG8 <= ADC_smpclk_s;
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
             END beh;

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +2 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY MINI_LFR_top IS
               PORT (
                 clk_50 : IN  STD_LOGIC;
                 clk_49 : IN  STD_LOGIC;
                 reset  : IN  STD_LOGIC;
                 --BPs
                 BP0    : IN  STD_LOGIC;
                 BP1    : IN  STD_LOGIC;
                 --LEDs
                 LED0   : OUT STD_LOGIC;
                 LED1   : OUT STD_LOGIC;
                 LED2   : OUT STD_LOGIC;
                 --UARTs
                 TXD1   : IN  STD_LOGIC;
                 RXD1   : OUT STD_LOGIC;
                 nCTS1  : OUT STD_LOGIC;
                 nRTS1  : IN  STD_LOGIC;
                 TXD2  : IN  STD_LOGIC;
                 RXD2  : OUT STD_LOGIC;
                 nCTS2 : OUT STD_LOGIC;
                 nDTR2 : IN  STD_LOGIC;
                 nRTS2 : IN  STD_LOGIC;
                 nDCD2 : OUT STD_LOGIC;
                 --EXT CONNECTOR
                 IO0  : INOUT STD_LOGIC;
                 IO1  : INOUT STD_LOGIC;
                 IO2  : INOUT STD_LOGIC;
                 IO3  : INOUT STD_LOGIC;
                 IO4  : INOUT STD_LOGIC;
                 IO5  : INOUT STD_LOGIC;
                 IO6  : INOUT STD_LOGIC;
                 IO7  : INOUT STD_LOGIC;
                 IO8  : INOUT STD_LOGIC;
                 IO9  : INOUT STD_LOGIC;
                 IO10 : INOUT STD_LOGIC;
                 IO11 : INOUT STD_LOGIC;
                 --SPACE WIRE
                 SPW_EN       : OUT STD_LOGIC;       -- 0 => off
                 SPW_NOM_DIN  : IN  STD_LOGIC;       -- NOMINAL LINK
                 SPW_NOM_SIN  : IN  STD_LOGIC;
                 SPW_NOM_DOUT : OUT STD_LOGIC;
                 SPW_NOM_SOUT : OUT STD_LOGIC;
                 SPW_RED_DIN  : IN  STD_LOGIC;       -- REDUNDANT LINK
                 SPW_RED_SIN  : IN  STD_LOGIC;
                 SPW_RED_DOUT : OUT STD_LOGIC;
                 SPW_RED_SOUT : OUT STD_LOGIC;
                 -- MINI LFR ADC INPUTS
                 ADC_nCS      : OUT STD_LOGIC;
                 ADC_CLK      : OUT STD_LOGIC;
                 ADC_SDO      : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 -- SRAM
                 SRAM_nWE : OUT   STD_LOGIC;
                 SRAM_CE  : OUT   STD_LOGIC;
                 SRAM_nOE : OUT   STD_LOGIC;
                 SRAM_nBE : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
                 SRAM_A   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 SRAM_DQ  : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END MINI_LFR_top;
             ARCHITECTURE beh OF MINI_LFR_top IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL errorn      : STD_LOGIC;
               -- UART AHB ---------------------------------------------------------------
             --  SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data
             --  SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
               -- UART APB ---------------------------------------------------------------
             --  SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
             --  SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
               --
               SIGNAL I00_s : STD_LOGIC;
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               --
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);  --  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);  --  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);  -- := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --  SIGNAL clkmn                : STD_ULOGIC;
             --  SIGNAL txclk                : STD_ULOGIC;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
               SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL bias_fail_sw_sig : STD_LOGIC;
               SIGNAL observation_reg      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL rstn_25    : STD_LOGIC;
               SIGNAL rstn_25_d1 : STD_LOGIC;
               SIGNAL rstn_25_d2 : STD_LOGIC;
               SIGNAL rstn_25_d3 : STD_LOGIC;
               SIGNAL rstn_50    : STD_LOGIC;
               SIGNAL rstn_50_d1 : STD_LOGIC;
               SIGNAL rstn_50_d2 : STD_LOGIC;
               SIGNAL rstn_50_d3 : STD_LOGIC;
               SIGNAL lfr_debug_vector    : STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
               --
               SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
               --
               SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL HK_SEL    : STD_LOGIC_VECTOR( 1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               --PROCESS(clk_50)
               --BEGIN
               --  IF clk_50'EVENT AND clk_50 = '1' THEN
               --    clk_50_s <= NOT clk_50_s;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_50_s)
               --BEGIN
               --  IF clk_50_s'EVENT AND clk_50_s = '1' THEN
               --    clk_25 <= NOT clk_25;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_49)
               --BEGIN
               --  IF clk_49'EVENT AND clk_49 = '1' THEN
               --    clk_24 <= NOT clk_24;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_25)
               --BEGIN
               --  IF clk_25'EVENT AND clk_25 = '1' THEN
               --    rstn_25 <= reset;
               --  END IF;
               --END PROCESS;
               PROCESS (clk_50, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_50_s   <= '0';
                   rstn_50    <= '0';
                   rstn_50_d1 <= '0';
                   rstn_50_d2 <= '0';
                   rstn_50_d3 <= '0';
                 ELSIF clk_50'EVENT AND clk_50 = '1' THEN  -- rising clock edge
                   clk_50_s   <= NOT clk_50_s;
                   rstn_50_d1 <= '1';
                   rstn_50_d2 <= rstn_50_d1;
                   rstn_50_d3 <= rstn_50_d2;
                   rstn_50    <= rstn_50_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_50_s, rstn_50)
               BEGIN  -- PROCESS
                 IF rstn_50 = '0' THEN               -- asynchronous reset (active low)
                   clk_25     <= '0';
                   rstn_25    <= '0';
                   rstn_25_d1 <= '0';
                   rstn_25_d2 <= '0';
                   rstn_25_d3 <= '0';
                 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN  -- rising clock edge
                   clk_25     <= NOT clk_25;
                   rstn_25_d1 <= '1';
                   rstn_25_d2 <= rstn_25_d1;
                   rstn_25_d3 <= rstn_25_d2;
                   rstn_25    <= rstn_25_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_49, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_24 <= '0';
                 ELSIF clk_49'EVENT AND clk_49 = '1' THEN  -- rising clock edge
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   LED0 <= '0';
                   LED1 <= '0';
                   LED2 <= '0';
                   --IO1  <= '0';
                   --IO2  <= '1';
                   --IO3  <= '0';
                   --IO4  <= '0';
                   --IO5  <= '0';
                   --IO6  <= '0';
                   --IO7  <= '0';
                   --IO8  <= '0';
                   --IO9  <= '0';
                   --IO10 <= '0';
                   --IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   LED0 <= '0';
                   LED1 <= '1';
                   LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                   --IO1  <= '1';
                   --IO2  <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
                   --IO3  <= ADC_SDO(0);
                   --IO4  <= ADC_SDO(1);
                   --IO5  <= ADC_SDO(2);
                   --IO6  <= ADC_SDO(3);
                   --IO7  <= ADC_SDO(4);
                   --IO8  <= ADC_SDO(5);
                   --IO9  <= ADC_SDO(6);
                   --IO10 <= ADC_SDO(7);
                   --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                 END IF;
               END PROCESS;
               PROCESS (clk_24, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   I00_s <= '0';
                 ELSIF clk_24'EVENT AND clk_24 = '1' THEN  -- rising clock edge
                   I00_s <= NOT I00_s;
                 END IF;
               END PROCESS;
             --  IO0 <= I00_s;
               --UARTs
               nCTS1 <= '1';
               nCTS2 <= '1';
               nDCD2 <= '1';
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
-                  IS_RADHARD      => 1,
+                  IS_RADHARD      => 0,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => 0)
                 PORT MAP (
                   clk       => clk_25,
                   reset     => rstn_25,
                   errorn    => errorn,
                   ahbrxd    => TXD1,
                   ahbtxd    => RXD1,
                   urxd1     => TXD2,
                   utxd1     => RXD2,
                   address   => SRAM_A,
                   data      => SRAM_DQ,
                   nSRAM_BE0 => SRAM_nBE(0),
                   nSRAM_BE1 => SRAM_nBE(1),
                   nSRAM_BE2 => SRAM_nBE(2),
                   nSRAM_BE3 => SRAM_nBE(3),
                   nSRAM_WE  => SRAM_nWE,
                   nSRAM_CE  => SRAM_CE_s,
                   nSRAM_OE  => SRAM_nOE,
                   nSRAM_READY => '0',
                   SRAM_MBE    => OPEN,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               SRAM_CE <= SRAM_CE_s(0);
             -------------------------------------------------------------------------------
             -- APB_LFR_MANAGEMENT ---------------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz      => clk_25,
                   clk24_576MHz  => clk_24,          -- 49.152MHz/2
                   resetn        => rstn_25,
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                   HK_sample     => sample_hk,
                   HK_val        => sample_val,
                   HK_sel        => HK_SEL,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
               SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DIN, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SIN, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DOUT, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SOUT, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_SIN, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_DIN, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_DOUT, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_SOUT, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               swni.rmapnodeaddr <= (OTHERS => '0');
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn_25;
               --LFR_rstn <= rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000138")  -- aa.bb.cc version
+                  top_lfr_version        => X"00013A")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw_sig,
                   debug_vector    => lfr_debug_vector,
                   debug_vector_ms => lfr_debug_vector_ms
                   );
               observation_reg(11 DOWNTO 0)      <= lfr_debug_vector;
               observation_reg(31 DOWNTO 12)     <= (OTHERS => '0');
               observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
               observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
               IO0                               <= rstn_25;
               IO1                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT data_valid
               IO2                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT ready
               IO3                               <= lfr_debug_vector(0);  -- LFR APBREG error_buffer_full
               IO4                               <= lfr_debug_vector(1);  -- LFR APBREG reg_sp.status_error_buffer_full
               IO5                               <= lfr_debug_vector(8);  -- LFR APBREG  ready_matrix_f2
               IO6                               <= lfr_debug_vector(9);  -- LFR APBREG reg0_ready_matrix_f2
               IO7                               <= lfr_debug_vector(10);  -- LFR APBREG reg0_ready_matrix_f2
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
               END GENERATE all_sample;
               top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
                 GENERIC MAP(
                   ChannelCount    => 8,
                   SampleNbBits    => 14,
                   ncycle_cnv_high => 40,  -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
                   ncycle_cnv      => 249)           -- 49 152 000 / 98304 /2
                 PORT MAP (
                   -- CONV
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn_25,
                   cnv        => ADC_nCS_sig,
                   -- DATA
                   clk        => clk_25,
                   rstn       => rstn_25,
                   sck        => ADC_CLK_sig,
                   sdo        => ADC_SDO_sig,
                   -- SAMPLE
                   sample     => sample,
                   sample_val => sample_val);
               --IO10 <= ADC_SDO_sig(5);
               --IO9  <= ADC_SDO_sig(4);
               --IO8  <= ADC_SDO_sig(3);
               ADC_nCS     <= ADC_nCS_sig;
               ADC_CLK     <= ADC_CLK_sig;
               ADC_SDO_sig <= ADC_SDO;
               sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
                            "0010001000100010" WHEN HK_SEL = "01" ELSE
                            "0100010001000100" WHEN HK_SEL = "10" ELSE
                            (OTHERS => '0');
             ----------------------------------------------------------------------
             ---  GPIO  -----------------------------------------------------------
             ----------------------------------------------------------------------
               grgpio0 : grgpio
                 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
                 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
               gpioi.sig_en <= (OTHERS => '0');
               gpioi.sig_in <= (OTHERS => '0');
               gpioi.din    <= (OTHERS => '0');
               --pio_pad_0 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
               --pio_pad_1 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
               --pio_pad_2 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
               --pio_pad_3 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
               --pio_pad_4 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
               --pio_pad_5 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
               --pio_pad_6 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
               --pio_pad_7 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   --    --IO0  <= '0';
                   --    IO1  <= '0';
                   --    IO2  <= '0';
                   --    IO3  <= '0';
                   --    IO4  <= '0';
                   --    IO5  <= '0';
                   --    IO6  <= '0';
                   --    IO7  <= '0';
                   IO8  <= '0';
                   IO9  <= '0';
                   IO10 <= '0';
                   IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   CASE gpioo.dout(2 DOWNTO 0) IS
                     WHEN "011" =>
                       --        --IO0  <= observation_reg(0 );
                       --        IO1  <= observation_reg(1 );
                       --        IO2  <= observation_reg(2 );
                       --        IO3  <= observation_reg(3 );
                       --        IO4  <= observation_reg(4 );
                       --        IO5  <= observation_reg(5 );
                       --        IO6  <= observation_reg(6 );
                       --        IO7  <= observation_reg(7 );
                       IO8  <= observation_reg(8);
                       IO9  <= observation_reg(9);
                       IO10 <= observation_reg(10);
                       IO11 <= observation_reg(11);
                     WHEN "001" =>
                       --        --IO0  <= observation_reg(0  + 12);
                       --        IO1  <= observation_reg(1  + 12);
                       --        IO2  <= observation_reg(2  + 12);
                       --        IO3  <= observation_reg(3  + 12);
                       --        IO4  <= observation_reg(4  + 12);
                       --        IO5  <= observation_reg(5  + 12);
                       --        IO6  <= observation_reg(6  + 12);
                       --        IO7  <= observation_reg(7  + 12);
                       IO8  <= observation_reg(8 + 12);
                       IO9  <= observation_reg(9 + 12);
                       IO10 <= observation_reg(10 + 12);
                       IO11 <= observation_reg(11 + 12);
                     WHEN "010" =>
                       --        --IO0  <= observation_reg(0  + 12 + 12);
                       --        IO1  <= observation_reg(1  + 12 + 12);
                       --        IO2  <= observation_reg(2  + 12 + 12);
                       --        IO3  <= observation_reg(3  + 12 + 12);
                       --        IO4  <= observation_reg(4  + 12 + 12);
                       --        IO5  <= observation_reg(5  + 12 + 12);
                       --        IO6  <= observation_reg(6  + 12 + 12);
                       --        IO7  <= observation_reg(7  + 12 + 12);
                       IO8  <= '0';
                       IO9  <= '0';
                       IO10 <= '0';
                       IO11 <= '0';
                     WHEN "000" =>
                       --        --IO0  <= observation_vector_0(0 );
                       --        IO1  <= observation_vector_0(1 );
                       --        IO2  <= observation_vector_0(2 );
                       --        IO3  <= observation_vector_0(3 );
                       --        IO4  <= observation_vector_0(4 );
                       --        IO5  <= observation_vector_0(5 );
                       --        IO6  <= observation_vector_0(6 );
                       --        IO7  <= observation_vector_0(7 );
                       IO8  <= observation_vector_0(8);
                       IO9  <= observation_vector_0(9);
                       IO10 <= observation_vector_0(10);
                       IO11 <= observation_vector_0(11);
                     WHEN "100" =>
                       --        --IO0  <= observation_vector_1(0 );
                       --        IO1  <= observation_vector_1(1 );
                       --        IO2  <= observation_vector_1(2 );
                       --        IO3  <= observation_vector_1(3 );
                       --        IO4  <= observation_vector_1(4 );
                       --        IO5  <= observation_vector_1(5 );
                       --        IO6  <= observation_vector_1(6 );
                       --        IO7  <= observation_vector_1(7 );
                       IO8  <= observation_vector_1(8);
                       IO9  <= observation_vector_1(9);
                       IO10 <= observation_vector_1(10);
                       IO11 <= observation_vector_1(11);
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
                 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
                   apbo_ext(I) <= apb_none;
                 END GENERATE apbo_ext_not_used;
               END GENERATE all_apbo_ext;
               all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
                 ahbo_s_ext(I) <= ahbs_none;
               END GENERATE all_ahbo_ext;
               all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
                 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
                   ahbo_m_ext(I) <= ahbm_none;
                 END GENERATE ahbo_m_ext_not_used;
               END GENERATE all_ahbo_m_ext;
             END beh;

lib/lpp/dsp/cic/cic_lfr_r2.vhd 0 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --                             jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.all;
             LIBRARY lpp;
             USE lpp.cic_pkg.ALL;
             USE lpp.data_type_pkg.ALL;
             USE lpp.iir_filter.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY cic_lfr_r2 IS
               GENERIC(
                 tech         : INTEGER := 0;
                 use_RAM_nCEL : INTEGER := 0         -- 1 => RAM(tech) , 0 => RAM_CEL
                 );
               PORT (
                 clk            : IN  STD_LOGIC;
                 rstn           : IN  STD_LOGIC;
                 run            : IN  STD_LOGIC;
                 param_r2       : IN  STD_LOGIC;
                 data_in        : IN  sample_vector(7 DOWNTO 0,15 DOWNTO 0);
                 data_in_valid  : IN  STD_LOGIC;
                 data_out_16        : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
                 data_out_16_valid  : OUT STD_LOGIC;
                 data_out_256       : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
                 data_out_256_valid : OUT STD_LOGIC
                 );
             END cic_lfr_r2;
             ARCHITECTURE beh OF cic_lfr_r2 IS
               --
               SIGNAL sel_sample  : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
               SIGNAL sample      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL sel_A  : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
               SIGNAL data_A  : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL data_B      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_B_reg      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_out      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_in_Carry  : STD_LOGIC;
               SIGNAL data_out_Carry : STD_LOGIC;
               --
               CONSTANT S_parameter : INTEGER := 3;
               SIGNAL carry_reg  : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
-              SIGNAL CARRY_PUSH : STD_LOGIC;
-              SIGNAL CARRY_POP  : STD_LOGIC;
               --
               SIGNAL OPERATION    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE ARRAY_OF_ADDR IS ARRAY (7 DOWNTO 0) OF STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL   base_addr_INT   : ARRAY_OF_ADDR;
               CONSTANT base_addr_delta : INTEGER := 40;
               SIGNAL addr_base_sel : STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_write_mux: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL data_we: STD_LOGIC;
               SIGNAL data_we_s: STD_LOGIC;
               SIGNAL data_wen       : STD_LOGIC;
             --  SIGNAL data_write     : STD_LOGIC_VECTOR(15 DOWNTO 0);
             --  SIGNAL data_read      : STD_LOGIC_VECTOR(15 DOWNTO 0);
             --  SIGNAL data_read_pre      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_out_reg16   : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_out_reg256  : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(8*2 DOWNTO 0);
               SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
               SIGNAL  data_out_16_valid_s  : STD_LOGIC;
               SIGNAL  data_out_256_valid_s : STD_LOGIC;
               SIGNAL  data_out_16_valid_s1  : STD_LOGIC;
               SIGNAL  data_out_256_valid_s1 : STD_LOGIC;
               SIGNAL  data_out_16_valid_s2  : STD_LOGIC;
               SIGNAL  data_out_256_valid_s2 : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL sample_out_reg16_s   : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
               SIGNAL sample_out_reg256_s  : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
               -----------------------------------------------------------------------------
             BEGIN
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_B_reg <=  (OTHERS => '0');
                   OPERATION_reg <= (OTHERS => '0');
                   OPERATION_reg2 <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   OPERATION_reg <= OPERATION;
                   OPERATION_reg2 <= OPERATION_reg;
                   data_B_reg <= data_B;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SEL_SAMPLE
               -----------------------------------------------------------------------------
               sel_sample <= OPERATION_reg(2 DOWNTO 0);
               all_bit: FOR I IN 15 DOWNTO 0 GENERATE
                 sample_temp(0,I) <= data_in(0,I)     WHEN sel_sample(0) = '0' ELSE data_in(1,I);
                 sample_temp(1,I) <= data_in(2,I)     WHEN sel_sample(0) = '0' ELSE data_in(3,I);
                 sample_temp(2,I) <= data_in(4,I)     WHEN sel_sample(0) = '0' ELSE data_in(5,I);
                 sample_temp(3,I) <= data_in(6,I)     WHEN sel_sample(0) = '0' ELSE data_in(7,I);
                 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
                 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I);
                 sample(I)        <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
               END GENERATE all_bit;
               -----------------------------------------------------------------------------
               -- SEL_DATA_IN_A
               -----------------------------------------------------------------------------
               sel_A <= OPERATION_reg(4 DOWNTO 3);
               all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
                 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
                 data_A_temp(1,I) <= '0'       WHEN sel_A(0) = '0' ELSE sample(15);
                 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
                 data_A(I)        <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
               END GENERATE all_data_mux_A;
               -----------------------------------------------------------------------------
               -- ALU
               -----------------------------------------------------------------------------
               ALU_OP <= OPERATION_reg(6 DOWNTO 5);
               ALU: cic_lfr_add_sub
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   run            => run,
                   OP             => ALU_OP,
                   data_in_A      => data_A,
                   data_in_B      => data_B,
                   data_in_Carry  => data_in_Carry,
                   data_out       => data_out,
                   data_out_Carry => data_out_Carry);
               -----------------------------------------------------------------------------
               -- CARRY_MANAGER
               -----------------------------------------------------------------------------
               data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
             --  CARRY_PUSH <= OPERATION_reg(7);
             --  CARRY_POP  <= OPERATION_reg(6);
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   carry_reg <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
                     carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
                     carry_reg(0)                      <= data_out_Carry;
                   --END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- MEMORY
               -----------------------------------------------------------------------------
               all_bit_base_ADDR: FOR J IN 8 DOWNTO 0 GENERATE
                 all_channel: FOR I IN 7 DOWNTO 0 GENERATE
                   base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
                 END GENERATE all_channel;
               END GENERATE all_bit_base_ADDR;
               addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
               cic_lfr_address_gen_1: cic_lfr_address_gen
                 GENERIC MAP (
                   ADDR_SIZE => 9)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   addr_base         => addr_base_sel,
                   addr_init         => OPERATION(8),
                   addr_add_1        => OPERATION(9),
                   addr              => addr_gen);
               addr_read <= addr_gen                                                               WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,9)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,9)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,9)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen     ))+6,9)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen     ))+15,9));
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   addr_write   <= (OTHERS => '0');
                   data_we      <= '0';
                   addr_write_s <= (OTHERS => '0');
                   data_we_s    <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   addr_write_s <= addr_read;
                   data_we_s    <= OPERATION(13);
                   IF OPERATION_reg(15) = '0' THEN
                     addr_write   <= addr_write_s;
                   ELSE
                     addr_write <= addr_read;
                   END IF;
                   data_we      <= data_we_s;
                 END IF;
               END PROCESS;
               memCEL : IF use_RAM_nCEL = 0 GENERATE
                 data_wen <= NOT data_we;
                 RAMblk : RAM_CEL
                   GENERIC MAP(16, 9)
                   PORT MAP(
                     WD    => data_out,
                     RD    => data_B,
                     WEN   => data_wen,
                     REN   => '0',
                     WADDR => addr_write,
                     RADDR => addr_read,
                     RWCLK => clk,
                     RESET => rstn
                     ) ;
               END GENERATE;
               memRAM : IF use_RAM_nCEL = 1 GENERATE
                 SRAM : syncram_2p
                   GENERIC MAP(tech, 9, 16)
                   PORT MAP(clk, '1', addr_read,  data_B,
                            clk, data_we, addr_write, data_out);
               END GENERATE;
               -----------------------------------------------------------------------------
               -- CONTROL
               -----------------------------------------------------------------------------
               cic_lfr_control_1: cic_lfr_control_r2
                 PORT MAP (
                   clk                => clk,
                   rstn               => rstn,
                   run                => run,
                   data_in_valid      => data_in_valid,
                   data_out_16_valid  => data_out_16_valid_s,
                   data_out_256_valid => data_out_256_valid_s,
                   OPERATION          => OPERATION);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_out_16_valid_s1 <= '0';
                   data_out_256_valid_s1 <= '0';
                   data_out_16_valid_s2 <= '0';
                   data_out_256_valid_s2 <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   data_out_16_valid_s1 <= data_out_16_valid_s;
                   data_out_256_valid_s1 <= data_out_256_valid_s;
                   data_out_16_valid_s2  <= data_out_16_valid_s1;
                   data_out_256_valid_s2 <= data_out_256_valid_s1;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_valid_reg16  <= "00000" & "000000" & "000001";
                   sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF run = '0' THEN
                     sample_valid_reg16  <= "00000" & "000000" & "000001";
                     sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
                   ELSE
                     IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(8*2) = '1' THEN
                       sample_valid_reg16  <= sample_valid_reg16(8*2-1 DOWNTO 0)  & sample_valid_reg16(8*2);
                     END IF;
                     IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
                       sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               data_out_16_valid  <= sample_valid_reg16(8*2);
               data_out_256_valid <= sample_valid_reg256(6*3);
               -----------------------------------------------------------------------------
               all_bits: FOR J IN 15 DOWNTO 0 GENERATE
                 all_channel_out16: FOR I IN 8*2-1 DOWNTO 0 GENERATE
                   PROCESS (clk, rstn)
                   BEGIN  -- PROCESS
                     IF rstn = '0' THEN              -- asynchronous reset (active low)
                       sample_out_reg16(I,J)  <= '0';
                     ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                       IF run = '0' THEN
                         sample_out_reg16(I,J)  <= '0';
                       ELSE
                         IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
                           sample_out_reg16(I,J) <= data_out(J);
                         END IF;
                       END IF;
                     END IF;
                   END PROCESS;
                 END GENERATE all_channel_out16;
                 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
                   PROCESS (clk, rstn)
                   BEGIN  -- PROCESS
                     IF rstn = '0' THEN              -- asynchronous reset (active low)
                       sample_out_reg256(I,J) <= '0';
                     ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                       IF run = '0' THEN
                         sample_out_reg256(I,J) <= '0';
                       ELSE
                         IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
                           sample_out_reg256(I,J) <= data_out(J);
                         END IF;
                       END IF;
                     END IF;
                   END PROCESS;
                 END GENERATE all_channel_out256;
               END GENERATE all_bits;
               all_bits_16: FOR J IN 15 DOWNTO 0 GENERATE
                 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
                   sample_out_reg16_s(0,J+(K*16)) <= sample_out_reg16(2*0+K,J);
                   sample_out_reg16_s(1,J+(K*16)) <= sample_out_reg16(2*1+K,J) WHEN param_r2 = '1' ELSE  sample_out_reg16(2*6+K,J);
                   sample_out_reg16_s(2,J+(K*16)) <= sample_out_reg16(2*2+K,J) WHEN param_r2 = '1' ELSE  sample_out_reg16(2*7+K,J);
                   sample_out_reg16_s(3,J+(K*16)) <= sample_out_reg16(2*3+K,J);
                   sample_out_reg16_s(4,J+(K*16)) <= sample_out_reg16(2*4+K,J);
                   sample_out_reg16_s(5,J+(K*16)) <= sample_out_reg16(2*5+K,J);
                 END GENERATE all_reg_16;
               END GENERATE all_bits_16;
               all_channel_out_256: FOR I IN 5 DOWNTO 0 GENERATE
                 all_bits_256: FOR J IN 15 DOWNTO 0 GENERATE
                   all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
                     sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
                   END GENERATE all_reg_256;
                 END GENERATE all_bits_256;
               END GENERATE all_channel_out_256;
               all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
                 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
                   data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27);
                   data_out_16(I,J)  <= sample_out_reg16_s (I,J+16  -16+15);
                 END GENERATE all_bits;
               END GENERATE all_channel_out_v;
             END beh;

lib/lpp/lfr_management/apb_lfr_management.vhd +6 -5

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    11:17:05 07/02/2012
             -- Design Name:
             -- Module Name:    apb_lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY lpp;
             USE lpp.apb_devices_list.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
             ENTITY apb_lfr_management IS
               GENERIC(
                 pindex           : INTEGER := 0;        --! APB slave index
                 paddr            : INTEGER := 0;        --! ADDR field of the APB BAR
                 pmask            : INTEGER := 16#fff#;  --! MASK field of the APB BAR
                 FIRST_DIVISION   : INTEGER := 374;
                 NB_SECOND_DESYNC : INTEGER := 60
                 );
               PORT (
                 clk25MHz     : IN STD_LOGIC;        --! Clock
                 clk24_576MHz : IN STD_LOGIC;        --! secondary clock
                 resetn       : IN STD_LOGIC;        --! Reset
                 grspw_tick : IN STD_LOGIC;  --! grspw signal asserted when a valid time-code is received
                 apbi          : IN  apb_slv_in_type;   --! APB slave input signals
                 apbo          : OUT apb_slv_out_type;  --! APB slave output signals
                 ---------------------------------------------------------------------------
                 HK_sample     : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                 HK_val        : IN  STD_LOGIC;
                 HK_sel        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --! coarse time
                 fine_time     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);  --! fine TIME
                 ---------------------------------------------------------------------------
                 LFR_soft_rstn : OUT STD_LOGIC
                 );
             END apb_lfr_management;
             ARCHITECTURE Behavioral OF apb_lfr_management IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
 => apb_iobar(paddr, pmask)
                 );
               TYPE apb_lfr_time_management_Reg IS RECORD
                 ctrl             : STD_LOGIC;
                 soft_reset       : STD_LOGIC;
                 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
                 coarse_time      : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 fine_time        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 LFR_soft_reset   : STD_LOGIC;
                 HK_temp_0        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 HK_temp_1        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 HK_temp_2        : STD_LOGIC_VECTOR(15 DOWNTO 0);
               END RECORD;
               SIGNAL r : apb_lfr_time_management_Reg;
               SIGNAL Rdata               : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL force_tick          : STD_LOGIC;
               SIGNAL previous_force_tick : STD_LOGIC;
               SIGNAL soft_tick           : STD_LOGIC;
               SIGNAL coarsetime_reg_updated : STD_LOGIC;
               SIGNAL coarsetime_reg         : STD_LOGIC_VECTOR(30 DOWNTO 0);
               --SIGNAL coarse_time_new    : STD_LOGIC;
               SIGNAL coarse_time_new_49 : STD_LOGIC;
               SIGNAL coarse_time_49     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL coarse_time_s      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               --SIGNAL fine_time_new      : STD_LOGIC;
               --SIGNAL fine_time_new_temp : STD_LOGIC;
               SIGNAL fine_time_new_49 : STD_LOGIC;
               SIGNAL fine_time_49     : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fine_time_s      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL tick             : STD_LOGIC;
               SIGNAL new_timecode     : STD_LOGIC;
               SIGNAL new_coarsetime   : STD_LOGIC;
               SIGNAL time_new_49 : STD_LOGIC;
               SIGNAL time_new    : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL force_reset          : STD_LOGIC;
               SIGNAL previous_force_reset : STD_LOGIC;
               SIGNAL soft_reset           : STD_LOGIC;
               SIGNAL soft_reset_sync      : STD_LOGIC;
               -----------------------------------------------------------------------------
-              SIGNAL HK_temp_0_s          : STD_LOGIC_VECTOR(15 DOWNTO 0);
-              SIGNAL HK_temp_1_s          : STD_LOGIC_VECTOR(15 DOWNTO 0);
-              SIGNAL HK_temp_2_s          : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL HK_sel_s             : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL previous_fine_time_bit : STD_LOGIC;
               SIGNAL rstn_LFR_TM : STD_LOGIC;
             BEGIN
               LFR_soft_rstn <= NOT r.LFR_soft_reset;
               PROCESS(resetn, clk25MHz)
                 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
               BEGIN
                 IF resetn = '0' THEN
                   Rdata              <= (OTHERS => '0');
                   r.coarse_time_load <= (OTHERS => '0');
                   r.soft_reset       <= '0';
                   r.ctrl             <= '0';
                   r.LFR_soft_reset   <= '1';
                   force_tick          <= '0';
                   previous_force_tick <= '0';
                   soft_tick           <= '0';
                   coarsetime_reg_updated <= '0';
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
                   coarsetime_reg_updated <= '0';
                   force_tick          <= r.ctrl;
                   previous_force_tick <= force_tick;
                   IF (previous_force_tick = '0') AND (force_tick = '1') THEN
                     soft_tick <= '1';
                   ELSE
                     soft_tick <= '0';
                   END IF;
                   force_reset          <= r.soft_reset;
                   previous_force_reset <= force_reset;
                   IF (previous_force_reset = '0') AND (force_reset = '1') THEN
                     soft_reset <= '1';
                   ELSE
                     soft_reset <= '0';
                   END IF;
                   paddr             := "000000";
                   paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
                   Rdata             <= (OTHERS => '0');
                   IF apbi.psel(pindex) = '1' THEN
                     --APB READ OP
                     CASE paddr(7 DOWNTO 2) IS
                       WHEN ADDR_LFR_MANAGMENT_CONTROL =>
                         Rdata(0)           <= r.ctrl;
                         Rdata(1)           <= r.soft_reset;
                         Rdata(2)           <= r.LFR_soft_reset;
                         Rdata(31 DOWNTO 3) <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
                         Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
                       WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
                         Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
                       WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.fine_time(15 DOWNTO 0);
                       WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.HK_temp_0;
                       WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.HK_temp_1;
                       WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.HK_temp_2;
                       WHEN OTHERS =>
                         Rdata(31 DOWNTO 0) <= (OTHERS => '0');
                     END CASE;
                     --APB Write OP
                     IF (apbi.pwrite AND apbi.penable) = '1' THEN
                       CASE paddr(7 DOWNTO 2) IS
                         WHEN ADDR_LFR_MANAGMENT_CONTROL =>
                           r.ctrl           <= apbi.pwdata(0);
                           r.soft_reset     <= apbi.pwdata(1);
                           r.LFR_soft_reset <= apbi.pwdata(2);
                         WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
                           r.coarse_time_load     <= apbi.pwdata(30 DOWNTO 0);
                           coarsetime_reg_updated <= '1';
                         WHEN OTHERS =>
                           NULL;
                       END CASE;
                     ELSE
                       IF r.ctrl = '1' THEN
                         r.ctrl <= '0';
                       END IF;
                       IF r.soft_reset = '1' THEN
                         r.soft_reset <= '0';
                       END IF;
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               apbo.pirq    <= (OTHERS => '0');
               apbo.prdata  <= Rdata;
               apbo.pconfig <= pconfig;
               apbo.pindex  <= pindex;
               -----------------------------------------------------------------------------
               -- IN
               coarse_time    <= r.coarse_time;
               fine_time      <= r.fine_time;
               coarsetime_reg <= r.coarse_time_load;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- OUT
               r.coarse_time <= coarse_time_s;
               r.fine_time   <= fine_time_s;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               tick <= grspw_tick OR soft_tick;
               SYNC_VALID_BIT_1 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => tick,
                   sout    => new_timecode);
               SYNC_VALID_BIT_2 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => coarsetime_reg_updated,
                   sout    => new_coarsetime);
               SYNC_VALID_BIT_3 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => soft_reset,
                   sout    => soft_reset_sync);
               -----------------------------------------------------------------------------
               --SYNC_FF_1 : SYNC_FF
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk    => clk25MHz,
               --    rstn   => resetn,
               --    A      => fine_time_new_49,
               --    A_sync => fine_time_new_temp);
               --lpp_front_detection_1 : lpp_front_detection
               --  PORT MAP (
               --    clk  => clk25MHz,
               --    rstn => resetn,
               --    sin  => fine_time_new_temp,
               --    sout => fine_time_new);
               --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk_in  => clk24_576MHz,
               --    clk_out => clk25MHz,
               --    rstn    => resetn,
               --    sin     => coarse_time_new_49,
               --    sout    => coarse_time_new);
               time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
               SYNC_VALID_BIT_4 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk24_576MHz,
                   clk_out => clk25MHz,
                   rstn    => resetn,
                   sin     => time_new_49,
                   sout    => time_new);
               PROCESS (clk25MHz, resetn)
               BEGIN  -- PROCESS
                 IF resetn = '0' THEN                -- asynchronous reset (active low)
                   fine_time_s   <= (OTHERS => '0');
                   coarse_time_s <= (OTHERS => '0');
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
                   IF time_new = '1' THEN
                     fine_time_s   <= fine_time_49;
                     coarse_time_s <= coarse_time_49;
                   END IF;
                 END IF;
               END PROCESS;
               rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
                              '0' WHEN soft_reset_sync = '1' ELSE
                              '1';
               -----------------------------------------------------------------------------
               -- LFR_TIME_MANAGMENT
               -----------------------------------------------------------------------------
               lfr_time_management_1 : lfr_time_management
                 GENERIC MAP (
                   FIRST_DIVISION   => FIRST_DIVISION,
                   NB_SECOND_DESYNC => NB_SECOND_DESYNC)
                 PORT MAP (
                   clk  => clk24_576MHz,
                   rstn => rstn_LFR_TM,
                   tick           => new_timecode,
                   new_coarsetime => new_coarsetime,
                   coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
                   fine_time       => fine_time_49,
                   fine_time_new   => fine_time_new_49,
                   coarse_time     => coarse_time_49,
                   coarse_time_new => coarse_time_new_49);
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               PROCESS (clk25MHz, resetn)
-                CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 11;  -- freq = 2^(16-BIT)
+                CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14;  -- freq = 2^(16-BIT)
-                                                                -- for 11, the update frequency is 32Hz
                                                                 -- for each HK, the update frequency is freq/3
+                                                                --
+                                                                -- for 14, the update frequency is
+                                                                -- 4Hz and update for each
+                                                                -- HK is 1.33Hz
               BEGIN  -- PROCESS
                 IF resetn = '0' THEN                -- asynchronous reset (active low)
                   r.HK_temp_0 <= (OTHERS => '0');
                   r.HK_temp_1 <= (OTHERS => '0');
                   r.HK_temp_2 <= (OTHERS => '0');
                   HK_sel_s <= "00";
                   previous_fine_time_bit <= '0';
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
                   IF HK_val = '1' THEN
                     IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
                       previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
                       CASE HK_sel_s IS
                         WHEN "00"   => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
                         WHEN "01"   => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
                         WHEN "10"   => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
                         WHEN OTHERS => NULL;
                       END CASE;
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               HK_sel <= HK_sel_s;
             END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +24 -6

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr IS
               GENERIC (
                 Mem_use                : INTEGER := use_RAM;
                 nb_data_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 7;
                 pindex   : INTEGER := 4;
                 paddr    : INTEGER := 4;
                 pmask    : INTEGER := 16#fff#;
                 pirq_ms  : INTEGER := 0;
                 pirq_wfp : INTEGER := 1;
                 hindex : INTEGER := 2;
                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
                 );
               PORT (
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
                 sample_B        : IN  Samples(2 DOWNTO 0);
                 sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
                 apbo            : OUT apb_slv_out_type;
                 -- AHB
                 ahbi            : IN  AHB_Mst_In_Type;
                 ahbo            : OUT AHB_Mst_Out_Type;
                 -- TIME
                 coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 data_shaping_BW : OUT STD_LOGIC;
                 --
                 debug_vector    : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                 );
             END lpp_lfr;
             ARCHITECTURE beh OF lpp_lfr IS
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
               SIGNAL data_shaping_SP1 : STD_LOGIC;
               SIGNAL data_shaping_R0  : STD_LOGIC;
               SIGNAL data_shaping_R1  : STD_LOGIC;
               SIGNAL data_shaping_R2  : STD_LOGIC;
               --
               SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_val    : STD_LOGIC;
               SIGNAL sample_f1_val    : STD_LOGIC;
               SIGNAL sample_f2_val    : STD_LOGIC;
               SIGNAL sample_f3_val    : STD_LOGIC;
               --
               SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -- SM
               SIGNAL ready_matrix_f0          : STD_LOGIC;
             --  SIGNAL ready_matrix_f0_1        : STD_LOGIC;
               SIGNAL ready_matrix_f1          : STD_LOGIC;
               SIGNAL ready_matrix_f2          : STD_LOGIC;
               SIGNAL status_ready_matrix_f0   : STD_LOGIC;
             --  SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
               SIGNAL status_ready_matrix_f1   : STD_LOGIC;
               SIGNAL status_ready_matrix_f2   : STD_LOGIC;
               SIGNAL addr_matrix_f0           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL length_matrix_f0         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f1         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f2         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               -- WFP
               SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
               SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0         : STD_LOGIC;
               SIGNAL enable_f1         : STD_LOGIC;
               SIGNAL enable_f2         : STD_LOGIC;
               SIGNAL enable_f3         : STD_LOGIC;
               SIGNAL burst_f0          : STD_LOGIC;
               SIGNAL burst_f1          : STD_LOGIC;
               SIGNAL burst_f2          : STD_LOGIC;
               --SIGNAL run        : STD_LOGIC;
               SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
             --  SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
               --f1
             --  SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
               --f2
             --  SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
               --f3
             --  SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
               SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               SIGNAL wfp_length_buffer       : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL wfp_ready_buffer        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_buffer_time         : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL wfp_error_buffer_full   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA RR
               -----------------------------------------------------------------------------
             --  SIGNAL dma_sel_valid   : STD_LOGIC;
             --  SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
             --  SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA_REG
               -----------------------------------------------------------------------------
             --  SIGNAL ongoing_reg         : STD_LOGIC;
             --  SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_send_reg        : STD_LOGIC;
             --  SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
             --  SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
             --  SIGNAL dma_send        : STD_LOGIC;
             --  SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
             --  SIGNAL dma_done        : STD_LOGIC;
             --  SIGNAL dma_ren         : STD_LOGIC;
             --  SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- MS
               -----------------------------------------------------------------------------
             --  SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_ms_valid       : STD_LOGIC;
             --  SIGNAL data_ms_valid_burst : STD_LOGIC;
             --  SIGNAL data_ms_ren         : STD_LOGIC;
             --  SIGNAL data_ms_done        : STD_LOGIC;
             --  SIGNAL dma_ms_ongoing      : STD_LOGIC;
             --  SIGNAL run_ms              : STD_LOGIC;
             --  SIGNAL ms_softandhard_rstn : STD_LOGIC;
               SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL error_buffer_full      : STD_LOGIC;
               SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
             --  SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_fifo_data        : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_fifo_ren         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_new       : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_addr      : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_buffer_length    : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
               SIGNAL dma_buffer_full      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_full_err  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_grant_error      : STD_LOGIC;
               SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
-            --  SIGNAL run_dma : STD_LOGIC;
+              SIGNAL sample_time        :  STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f0_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f1_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f2_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f3_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
               debug_vector <= apb_reg_debug_vector;
               -----------------------------------------------------------------------------
               sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
               sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
+              sample_time <= coarse_time & fine_time;
               --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
               --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
               --END GENERATE all_channel;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
+                  sample_time      => sample_time,
                   clk              => clk,
                   rstn             => rstn,
                   data_shaping_SP0 => data_shaping_SP0,
                   data_shaping_SP1 => data_shaping_SP1,
                   data_shaping_R0  => data_shaping_R0,
                   data_shaping_R1  => data_shaping_R1,
                   data_shaping_R2  => data_shaping_R2,
                   sample_f0_val    => sample_f0_val,
                   sample_f1_val    => sample_f1_val,
                   sample_f2_val    => sample_f2_val,
                   sample_f3_val    => sample_f3_val,
                   sample_f0_wdata  => sample_f0_data,
                   sample_f1_wdata  => sample_f1_data,
                   sample_f2_wdata  => sample_f2_data,
-                  sample_f3_wdata  => sample_f3_data);
+                  sample_f3_wdata  => sample_f3_data,
+                  sample_f0_time   => sample_f0_time,
+                  sample_f1_time   => sample_f1_time,
+                  sample_f2_time   => sample_f2_time,
+                  sample_f3_time   => sample_f3_time
+                  );
               -----------------------------------------------------------------------------
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                 GENERIC MAP (
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
             --      nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2,
                   pindex                 => pindex,
                   paddr                  => paddr,
                   pmask                  => pmask,
                   pirq_ms                => pirq_ms,
                   pirq_wfp               => pirq_wfp,
                   top_lfr_version        => top_lfr_version)
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   apbi    => apbi,
                   apbo    => apbo,
                   run_ms => OPEN,--run_ms,
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,       -- TODO
                   error_input_fifo_write => error_input_fifo_write,  -- TODO
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2,
                   addr_matrix_f0 => addr_matrix_f0,
                   addr_matrix_f1 => addr_matrix_f1,
                   addr_matrix_f2 => addr_matrix_f2,
                   length_matrix_f0  => length_matrix_f0,
                   length_matrix_f1  => length_matrix_f1,
                   length_matrix_f2  => length_matrix_f2,
                   -------------------------------------------------------------------------
                   --status_full       => status_full,       --      TODo
                   --status_full_ack   => status_full_ack,   --      TODo
                   --status_full_err   => status_full_err,   --      TODo
                   status_new_err    => status_new_err,
                   data_shaping_BW   => data_shaping_BW,
                   data_shaping_SP0  => data_shaping_SP0,
                   data_shaping_SP1  => data_shaping_SP1,
                   data_shaping_R0   => data_shaping_R0,
                   data_shaping_R1   => data_shaping_R1,
                   data_shaping_R2   => data_shaping_R2,
                   delta_snapshot    => delta_snapshot,
                   delta_f0          => delta_f0,
                   delta_f0_2        => delta_f0_2,
                   delta_f1          => delta_f1,
                   delta_f2          => delta_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
             --      nb_word_by_buffer => nb_word_by_buffer, -- TODO
                   nb_snapshot_param => nb_snapshot_param,
                   enable_f0         => enable_f0,
                   enable_f1         => enable_f1,
                   enable_f2         => enable_f2,
                   enable_f3         => enable_f3,
                   burst_f0          => burst_f0,
                   burst_f1          => burst_f1,
                   burst_f2          => burst_f2,
                   run               => OPEN, --run,
                   start_date        => start_date,
             --      debug_signal      => debug_signal,
                   wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
                   wfp_addr_buffer         => wfp_addr_buffer,-- TODO
                   wfp_length_buffer       => wfp_length_buffer,-- TODO
                   wfp_ready_buffer        => wfp_ready_buffer,-- TODO
                   wfp_buffer_time         => wfp_buffer_time,-- TODO
                   wfp_error_buffer_full   => wfp_error_buffer_full, -- TODO
                   -------------------------------------------------------------------------
                   sample_f3_v     => sample_f3_data(1*16-1 DOWNTO 0*16),
                   sample_f3_e1    => sample_f3_data(2*16-1 DOWNTO 1*16),
                   sample_f3_e2    => sample_f3_data(3*16-1 DOWNTO 2*16),
                   sample_f3_valid => sample_f3_val,
                   debug_vector => apb_reg_debug_vector
                   );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   tech                   => inferred,
                   data_size              => 6*16,
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   reg_run            => '1',--run,
                   reg_start_date     => start_date,
                   reg_delta_snapshot => delta_snapshot,
                   reg_delta_f0       => delta_f0,
                   reg_delta_f0_2     => delta_f0_2,
                   reg_delta_f1       => delta_f1,
                   reg_delta_f2       => delta_f2,
                   enable_f0 => enable_f0,
                   enable_f1 => enable_f1,
                   enable_f2 => enable_f2,
                   enable_f3 => enable_f3,
                   burst_f0  => burst_f0,
                   burst_f1  => burst_f1,
                   burst_f2  => burst_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   status_new_err    => status_new_err,
                   status_buffer_ready => wfp_status_buffer_ready,
                   addr_buffer         => wfp_addr_buffer,
                   length_buffer       => wfp_length_buffer,
                   ready_buffer        => wfp_ready_buffer,
                   buffer_time         => wfp_buffer_time,
                   error_buffer_full   => wfp_error_buffer_full,
                   coarse_time => coarse_time,
-                  fine_time   => fine_time,
+            --      fine_time   => fine_time,
                   --f0
                   data_f0_in_valid             => sample_f0_val,
                   data_f0_in                   => sample_f0_data,
+                  data_f0_time                 => sample_f0_time,
                   --f1
                   data_f1_in_valid             => sample_f1_val,
                   data_f1_in                   => sample_f1_data,
+                  data_f1_time                 => sample_f1_time,
                   --f2
                   data_f2_in_valid             => sample_f2_val,
                   data_f2_in                   => sample_f2_data,
+                  data_f2_time                 => sample_f2_time,
                   --f3
                   data_f3_in_valid             => sample_f3_val,
                   data_f3_in                   => sample_f3_data,
+                  data_f3_time                 => sample_f3_time,
                   -- OUTPUT -- DMA interface
                   dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
                   dma_fifo_data        => dma_fifo_data(32*4-1 DOWNTO 0),
                   dma_fifo_ren         => dma_fifo_ren(3 DOWNTO 0),
                   dma_buffer_new       => dma_buffer_new(3 DOWNTO 0),
                   dma_buffer_addr      => dma_buffer_addr(32*4-1 DOWNTO 0),
                   dma_buffer_length    => dma_buffer_length(26*4-1 DOWNTO 0),
                   dma_buffer_full      => dma_buffer_full(3 DOWNTO 0),
                   dma_buffer_full_err  => dma_buffer_full_err(3 DOWNTO 0)
                   );
               -----------------------------------------------------------------------------
               -- Matrix Spectral
               -----------------------------------------------------------------------------
               sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
                                NOT(sample_f0_val) & NOT(sample_f0_val);
               sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
                                NOT(sample_f1_val) & NOT(sample_f1_val);
               sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
                                NOT(sample_f2_val) & NOT(sample_f2_val);
               sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
               sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
               sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
               -------------------------------------------------------------------------------
               --ms_softandhard_rstn <= rstn AND run_ms AND run;
               -----------------------------------------------------------------------------
               lpp_lfr_ms_1 : lpp_lfr_ms
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   clk  => clk,
                   --rstn => ms_softandhard_rstn,      --rstn,
                   rstn => rstn,
                   run  => '1',--run_ms,
                   start_date => start_date,
                   coarse_time => coarse_time,
-                  fine_time   => fine_time,
                   sample_f0_wen   => sample_f0_wen,
                   sample_f0_wdata => sample_f0_wdata,
+                  sample_f0_time  => sample_f0_time,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
+                  sample_f1_time  => sample_f1_time,
                   sample_f2_wen   => sample_f2_wen,
                   sample_f2_wdata => sample_f2_wdata,
+                  sample_f2_time  => sample_f2_time,
                   --DMA
                   dma_fifo_burst_valid => dma_fifo_burst_valid(4),                  -- OUT
                   dma_fifo_data        => dma_fifo_data((4+1)*32-1 DOWNTO 4*32),    -- OUT
                   dma_fifo_ren         => dma_fifo_ren(4),                          -- IN
                   dma_buffer_new       => dma_buffer_new(4),                        -- OUT
                   dma_buffer_addr      => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32),  -- OUT
                   dma_buffer_length    => dma_buffer_length((4+1)*26-1 DOWNTO 4*26),  -- OUT
                   dma_buffer_full      => dma_buffer_full(4),                       -- IN
                   dma_buffer_full_err  => dma_buffer_full_err(4),                   -- IN
                   --REG
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,
                   error_input_fifo_write => error_input_fifo_write,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   addr_matrix_f0         => addr_matrix_f0,
                   addr_matrix_f1         => addr_matrix_f1,
                   addr_matrix_f2         => addr_matrix_f2,
                   length_matrix_f0 => length_matrix_f0,
                   length_matrix_f1 => length_matrix_f1,
                   length_matrix_f2 => length_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2,
                   debug_vector   => debug_vector_ms);
               -----------------------------------------------------------------------------
               --run_dma <= run_ms OR run;
               DMA_SubSystem_1 : DMA_SubSystem
                 GENERIC MAP (
                   hindex => hindex)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   run  => '1',--run_dma,
                   ahbi => ahbi,
                   ahbo => ahbo,
                   fifo_burst_valid => dma_fifo_burst_valid,  --fifo_burst_valid,
                   fifo_data        => dma_fifo_data,         --fifo_data,
                   fifo_ren         => dma_fifo_ren,          --fifo_ren,
                   buffer_new      => dma_buffer_new,       --buffer_new,
                   buffer_addr     => dma_buffer_addr,      --buffer_addr,
                   buffer_length   => dma_buffer_length,    --buffer_length,
                   buffer_full     => dma_buffer_full,      --buffer_full,
                   buffer_full_err => dma_buffer_full_err,  --buffer_full_err,
                   grant_error     => dma_grant_error);     --grant_error);
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +97 -7

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --                             jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.cic_pkg.ALL;
             USE lpp.data_type_pkg.ALL;
             USE lpp.lpp_lfr_filter_coeff.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr_filter IS
               GENERIC(
                 Mem_use                 : INTEGER := use_RAM
                 );
               PORT (
                 sample           : IN Samples(7 DOWNTO 0);
                 sample_val       : IN STD_LOGIC;
+                sample_time      : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 --
                 data_shaping_SP0 : IN STD_LOGIC;
                 data_shaping_SP1 : IN STD_LOGIC;
                 data_shaping_R0  : IN STD_LOGIC;
                 data_shaping_R1  : IN STD_LOGIC;
                 data_shaping_R2  : IN STD_LOGIC;
                 --
                 sample_f0_val   : OUT STD_LOGIC;
                 sample_f1_val   : OUT STD_LOGIC;
                 sample_f2_val   : OUT STD_LOGIC;
                 sample_f3_val   : OUT STD_LOGIC;
                 --
                 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-                sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
+                sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+                --
+                sample_f0_time  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                sample_f1_time  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                sample_f2_time  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                sample_f3_time  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
                 );
             END lpp_lfr_filter;
             ARCHITECTURE tb OF lpp_lfr_filter IS
               COMPONENT Downsampling
                 GENERIC (
                   ChanelCount : INTEGER;
                   SampleSize  : INTEGER;
                   DivideParam : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   sample_in_val  : IN  STD_LOGIC;
                   sample_in      : IN  samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
                   sample_out_val : OUT STD_LOGIC;
                   sample_out     : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               CONSTANT ChanelCount     : INTEGER := 8;
               -----------------------------------------------------------------------------
               SIGNAL   sample_val_delay : STD_LOGIC;
               -----------------------------------------------------------------------------
               CONSTANT Coef_SZ          : INTEGER := 9;
               CONSTANT CoefCntPerCel    : INTEGER := 6;
               CONSTANT CoefPerCel       : INTEGER := 5;
               CONSTANT Cels_count       : INTEGER := 5;
               --SIGNAL coefs                    : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
               SIGNAL coefs_v2                 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
               SIGNAL sample_filter_in         : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               --SIGNAL sample_filter_out        : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               --
               SIGNAL sample_filter_v2_out_val : STD_LOGIC;
               SIGNAL sample_filter_v2_out     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_data_shaping_out_val     : STD_LOGIC;
               SIGNAL sample_data_shaping_out         : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_data_shaping_f0_s        : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f1_s        : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f2_s        : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f1_f0_s     : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f2_f1_s     : STD_LOGIC_VECTOR(17 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_filter_v2_out_val_s      : STD_LOGIC;
               SIGNAL sample_filter_v2_out_s          : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
               -----------------------------------------------------------------------------
             --  SIGNAL sample_f0_val                   : STD_LOGIC;
               SIGNAL sample_f0                       : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f0_s                     : sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
               --
             --  SIGNAL sample_f1_val                   : STD_LOGIC;
               SIGNAL sample_f0_f1_s                  : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f1_s                     : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f1                       : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               --
             --  SIGNAL sample_f2_val                   : STD_LOGIC;
               SIGNAL sample_f2                       : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f2_cic_s                 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f2_cic_filter            : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f2_filter                : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f2_cic                   : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f2_cic_val               : STD_LOGIC;
               SIGNAL sample_f2_filter_val            : STD_LOGIC;
               SIGNAL sample_f3                       : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f3_cic_s                 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f3_cic_filter            : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f3_filter                : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f3_cic                   : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f3_cic_val               : STD_LOGIC;
               SIGNAL sample_f3_filter_val            : STD_LOGIC;
               -----------------------------------------------------------------------------
               --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               -----------------------------------------------------------------------------
               SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f0_val_s : STD_LOGIC;
               SIGNAL sample_f1_val_s : STD_LOGIC;
+              SIGNAL sample_f1_val_ss : STD_LOGIC;
+              SIGNAL sample_f2_val_s : STD_LOGIC;
+              SIGNAL sample_f3_val_s : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- CONFIG FILTER IIR f0 to f1
               -----------------------------------------------------------------------------
               CONSTANT f0_to_f1_CEL_NUMBER           : INTEGER := 5;
               CONSTANT f0_to_f1_COEFFICIENT_SIZE     : INTEGER := 10;
               CONSTANT f0_to_f1_POINT_POSITION       : INTEGER := 8;
               CONSTANT f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
                 (
                   (1.0, -1.61171504942096,  1.0, 1.0, -1.68876443778669,  0.908610171614583),
                   (1.0, -1.53324505744412,  1.0, 1.0, -1.51088513595779,  0.732564401274351),
                   (1.0, -1.30646173160060,  1.0, 1.0, -1.30571711968384,  0.546869268827102),
                   (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406,  0.358436944718464),
                   (1.0,  1.24322747034001,  1.0, 1.0, -0.929530176676438, 0.224862726961691)
                 );
               CONSTANT f0_to_f1_gain : COEFF_CEL_REAL :=
                 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
               CONSTANT coefs_iir_cel_f0_to_f1 : STD_LOGIC_VECTOR((f0_to_f1_CEL_NUMBER*f0_to_f1_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
                 :=  get_IIR_CEL_FILTER_CONFIG(
                   f0_to_f1_COEFFICIENT_SIZE,
                   f0_to_f1_POINT_POSITION,
                   f0_to_f1_CEL_NUMBER,
                   f0_to_f1_sos,
                   f0_to_f1_gain);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- CONFIG FILTER IIR f2 and f3
               -----------------------------------------------------------------------------
               CONSTANT f2_f3_CEL_NUMBER           : INTEGER := 5;
               CONSTANT f2_f3_COEFFICIENT_SIZE     : INTEGER := 10;
               CONSTANT f2_f3_POINT_POSITION       : INTEGER := 8;
               CONSTANT f2_f3_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
                 (
                   (1.0, -1.61171504942096,  1.0, 1.0, -1.68876443778669,  0.908610171614583),
                   (1.0, -1.53324505744412,  1.0, 1.0, -1.51088513595779,  0.732564401274351),
                   (1.0, -1.30646173160060,  1.0, 1.0, -1.30571711968384,  0.546869268827102),
                   (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406,  0.358436944718464),
                   (1.0,  1.24322747034001,  1.0, 1.0, -0.929530176676438, 0.224862726961691)
                 );
               CONSTANT f2_f3_gain : COEFF_CEL_REAL :=
                 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
               CONSTANT coefs_iir_cel_f2_f3 : STD_LOGIC_VECTOR((f2_f3_CEL_NUMBER*f2_f3_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
                 :=  get_IIR_CEL_FILTER_CONFIG(
                   f2_f3_COEFFICIENT_SIZE,
                   f2_f3_POINT_POSITION,
                   f2_f3_CEL_NUMBER,
                   f2_f3_sos,
                   f2_f3_gain);
               -----------------------------------------------------------------------------
+              SIGNAL sample_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f0_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f1_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f2_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f3_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f0_time_s           : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_f1_time_s           : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL sample_f2_time_s           : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL sample_f3_time_s           : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN              -- asynchronous reset (active low)
                   sample_val_delay <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   sample_val_delay <= sample_val;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
                 SampleLoop : FOR j IN 0 TO 15 GENERATE
                   sample_filter_in(i, j) <= sample(i)(j);
                 END GENERATE;
                 sample_filter_in(i, 16) <= sample(i)(15);
                 sample_filter_in(i, 17) <= sample(i)(15);
               END GENERATE;
               coefs_v2 <= CoefsInitValCst_v2;
               IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,          -- use_RAM
                   Sample_SZ    => 18,
                   Coef_SZ      => Coef_SZ,
                   Coef_Nb      => 25,
                   Coef_sel_SZ  => 5,
                   Cels_count   => Cels_count,
                   ChanelsCount => ChanelCount)
                 PORT MAP (
                   rstn           => rstn,
                   clk            => clk,
                   virg_pos       => 7,
                   coefs          => coefs_v2,
                   sample_in_val  => sample_val_delay,
                   sample_in      => sample_filter_in,
                   sample_out_val => sample_filter_v2_out_val,
                   sample_out     => sample_filter_v2_out);
+              -- TIME --
+              PROCESS (clk, rstn)
+              BEGIN  -- PROCESS
+                IF rstn = '0' THEN                  -- asynchronous reset (active low)
+                  sample_time_reg           <= (OTHERS => '0');
+                  sample_filter_v2_out_time <= (OTHERS => '0');
+                ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                  IF sample_val = '1' THEN
+                    sample_time_reg <= sample_time;
+                  END IF;
+                  IF sample_filter_v2_out_val = '1' THEN
+                    sample_filter_v2_out_time <= sample_time_reg;
+                  END IF;
+                END IF;
+              END PROCESS;
+              ----------
               -----------------------------------------------------------------------------
               -- DATA_SHAPING
               -----------------------------------------------------------------------------
               all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
                 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
                 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
                 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
               END GENERATE all_data_shaping_in_loop;
               sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
               sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_data_shaping_out_val <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   sample_data_shaping_out_val <= sample_filter_v2_out_val;
                 END IF;
               END PROCESS;
               SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     sample_data_shaping_out(0, j) <= '0';
                     sample_data_shaping_out(1, j) <= '0';
                     sample_data_shaping_out(2, j) <= '0';
                     sample_data_shaping_out(3, j) <= '0';
                     sample_data_shaping_out(4, j) <= '0';
                     sample_data_shaping_out(5, j) <= '0';
                     sample_data_shaping_out(6, j) <= '0';
                     sample_data_shaping_out(7, j) <= '0';
                   ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                     sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
                     IF data_shaping_SP0 = '1' THEN
                       sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
                     ELSE
                       sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
                     END IF;
                     IF data_shaping_SP1 = '1' THEN
                       sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
                     ELSE
                       sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
                     END IF;
                     sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
                     sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
                     sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
                     sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
                     sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
                   END IF;
                 END PROCESS;
               END GENERATE;
               sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
               ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
                 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
                   sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
                 END GENERATE;
               END GENERATE;
               -----------------------------------------------------------------------------
               -- F0 -- @24.576 kHz
               -----------------------------------------------------------------------------
               Downsampling_f0 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 8,
                   SampleSize  => 16,
                   DivideParam => 4)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_filter_v2_out_val_s,
                   sample_in      => sample_filter_v2_out_s,
                   sample_out_val => sample_f0_val_s,
                   sample_out     => sample_f0);
+              -- TIME --
+              PROCESS (clk, rstn)
+              BEGIN
+                IF rstn = '0' THEN
+                  sample_f0_time_reg <= (OTHERS => '0');
+                ELSIF clk'event AND clk = '1' THEN
+                  IF sample_f0_val_s = '1' THEN
+                    sample_f0_time_reg <= sample_filter_v2_out_time;
+                  END IF;
+                END IF;
+              END PROCESS;
+              sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg;
+              sample_f0_time   <= sample_f0_time_s;
+              ----------
               sample_f0_val <= sample_f0_val_s;
               all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f0_wdata_s(I)      <= sample_f0(0, I);  -- V
                 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I);  -- E1
                 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I);  -- E2
                 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I);  -- B1
                 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I);  -- B2
                 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I);  -- B3
               END GENERATE all_bit_sample_f0;
               -----------------------------------------------------------------------------
               -- F1 -- @4096 Hz
               -----------------------------------------------------------------------------
               all_bit_sample_f0_f1 : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f0_f1_s(0,I) <=  sample_f0(0,I);  --V
                 sample_f0_f1_s(1,I) <=  sample_f0(1,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,I); --E1
                 sample_f0_f1_s(2,I) <=  sample_f0(2,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,I); --E2
                 sample_f0_f1_s(3,I) <=  sample_f0(5,I);  --B1
                 sample_f0_f1_s(4,I) <=  sample_f0(6,I);  --B2
                 sample_f0_f1_s(5,I) <=  sample_f0(7,I);  --B3
               END GENERATE all_bit_sample_f0_f1;
               all_bit_sample_f0_f1_extended : FOR I IN 17 DOWNTO 16 GENERATE
                 sample_f0_f1_s(0,I) <= sample_f0(0,15);
                 sample_f0_f1_s(1,I) <= sample_f0(1,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,15); --E1
                 sample_f0_f1_s(2,I) <= sample_f0(2,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,15); --E2
                 sample_f0_f1_s(3,I) <= sample_f0(5,15);  --B1
                 sample_f0_f1_s(4,I) <= sample_f0(6,15);  --B2
                 sample_f0_f1_s(5,I) <= sample_f0(7,15);  --B3
               END GENERATE all_bit_sample_f0_f1_extended;
               IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,          -- use_RAM
                   Sample_SZ    => 18,
                   Coef_SZ      => f0_to_f1_COEFFICIENT_SIZE,
                   Coef_Nb      => f0_to_f1_CEL_NUMBER*5,
                   Coef_sel_SZ  => 5,
                   Cels_count   => f0_to_f1_CEL_NUMBER,
                   ChanelsCount => 6)
                 PORT MAP (
                   rstn           => rstn,
                   clk            => clk,
                   virg_pos       => f0_to_f1_POINT_POSITION,
                   coefs          => coefs_iir_cel_f0_to_f1,
                   sample_in_val  => sample_f0_val_s,
                   sample_in      => sample_f0_f1_s,
                   sample_out_val => sample_f1_val_s,
                   sample_out     => sample_f1_s);
               Downsampling_f1 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 6,
                   SampleSize  => 18,
                   DivideParam => 6)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_f1_val_s,
                   sample_in      => sample_f1_s,
-                  sample_out_val => sample_f1_val,
+                  sample_out_val => sample_f1_val_ss,
                   sample_out     => sample_f1);
+              sample_f1_val <= sample_f1_val_ss;
+              -- TIME --
+              PROCESS (clk, rstn)
+              BEGIN
+                IF rstn = '0' THEN
+                  sample_f1_time_reg <= (OTHERS => '0');
+                ELSIF clk'event AND clk = '1' THEN
+                  IF sample_f1_val_ss = '1' THEN
+                    sample_f1_time_reg <= sample_f0_time_s;
+                  END IF;
+                END IF;
+              END PROCESS;
+              sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg;
+              sample_f1_time   <= sample_f1_time_s;
+              ----------
               all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
                 all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
                   sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
                 END GENERATE all_channel_sample_f1;
               END GENERATE all_bit_sample_f1;
               -----------------------------------------------------------------------------
               -- F2 -- @256 Hz
               -- F3 -- @16 Hz
               -----------------------------------------------------------------------------
               all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f0_s(0, I) <= sample_f0(0, I);  -- V
                 sample_f0_s(1, I) <= sample_f0(1, I);  -- E1
                 sample_f0_s(2, I) <= sample_f0(2, I);  -- E2
                 sample_f0_s(3, I) <= sample_f0(5, I);  -- B1
                 sample_f0_s(4, I) <= sample_f0(6, I);  -- B2
                 sample_f0_s(5, I) <= sample_f0(7, I);  -- B3
                 sample_f0_s(6, I) <= sample_f0(3, I);  --
                 sample_f0_s(7, I) <= sample_f0(4, I);  --
               END GENERATE all_bit_sample_f0_s;
               cic_lfr_1: cic_lfr_r2
                 GENERIC MAP (
                   tech         => 0,
                   use_RAM_nCEL => Mem_use)
                 PORT MAP (
                   clk                => clk,
                   rstn               => rstn,
                   run                => '1',
                   param_r2           => data_shaping_R2,
                   data_in            => sample_f0_s,
                   data_in_valid      => sample_f0_val_s,
                   data_out_16        => sample_f2_cic,
                   data_out_16_valid  => sample_f2_cic_val,
                   data_out_256       => sample_f3_cic,
                   data_out_256_valid => sample_f3_cic_val);
               all_channel_sample_f_cic : FOR J IN 5 DOWNTO 0 GENERATE
                 all_bit_sample_f_cic : FOR I IN 15 DOWNTO 0 GENERATE
                   sample_f2_cic_filter(J,I) <= sample_f2_cic(J,I);
                   sample_f3_cic_filter(J,I) <= sample_f3_cic(J,I);
                 END GENERATE all_bit_sample_f_cic;
                 sample_f2_cic_filter(J,16) <= sample_f2_cic(J,15);
                 sample_f2_cic_filter(J,17) <= sample_f2_cic(J,15);
                 sample_f3_cic_filter(J,16) <= sample_f3_cic(J,15);
                 sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15);
               END GENERATE all_channel_sample_f_cic;
               IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,
                   Sample_SZ    => 18,
                   Coef_SZ      => f2_f3_COEFFICIENT_SIZE,
                   Coef_Nb      => f2_f3_CEL_NUMBER*5,
                   Coef_sel_SZ  => 5,
                   Cels_count   => f2_f3_CEL_NUMBER,
                   ChanelsCount => 6)
                 PORT MAP (
                   rstn            => rstn,
                   clk             => clk,
                   virg_pos        => f2_f3_POINT_POSITION,
                   coefs           => coefs_iir_cel_f2_f3,
                   sample_in1_val  => sample_f2_cic_val,
                   sample_in1      => sample_f2_cic_filter,
                   sample_in2_val  => sample_f3_cic_val,
                   sample_in2      => sample_f3_cic_filter,
                   sample_out1_val => sample_f2_filter_val,
                   sample_out1     => sample_f2_filter,
                   sample_out2_val => sample_f3_filter_val,
                   sample_out2     => sample_f3_filter);
               all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE
                 all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE
                   sample_f2_cic_s(J,I) <= sample_f2_filter(J,I);
                   sample_f3_cic_s(J,I) <= sample_f3_filter(J,I);
                 END GENERATE all_bit_sample_f_filter;
               END GENERATE all_channel_sample_f_filter;
               -----------------------------------------------------------------------------
               Downsampling_f2 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 6,
                   SampleSize  => 16,
                   DivideParam => 6)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_f2_filter_val ,
                   sample_in      => sample_f2_cic_s,
-                  sample_out_val => sample_f2_val,
+                  sample_out_val => sample_f2_val_s,
                   sample_out     => sample_f2);
+              sample_f2_val <= sample_f2_val_s;
               all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
                 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
                   sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
                 END GENERATE all_channel_sample_f2;
               END GENERATE all_bit_sample_f2;
               -----------------------------------------------------------------------------
               Downsampling_f3 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 6,
                   SampleSize  => 16,
                   DivideParam => 6)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_f3_filter_val ,
                   sample_in      => sample_f3_cic_s,
-                  sample_out_val => sample_f3_val,
+                  sample_out_val => sample_f3_val_s,
                   sample_out     => sample_f3);
+              sample_f3_val <= sample_f3_val_s;
               all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
                 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
                   sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
                 END GENERATE all_channel_sample_f3;
               END GENERATE all_bit_sample_f3;
+              -----------------------------------------------------------------------------
+              -- TIME --
+              PROCESS (clk, rstn)
+              BEGIN
+                IF rstn = '0' THEN
+                  sample_f2_time_reg <= (OTHERS => '0');
+                  sample_f3_time_reg <= (OTHERS => '0');
+                ELSIF clk'event AND clk = '1' THEN
+                  IF sample_f2_val_s = '1' THEN  sample_f2_time_reg <= sample_f0_time_s; END IF;
+                  IF sample_f3_val_s = '1' THEN  sample_f3_time_reg <= sample_f0_time_s; END IF;
+                END IF;
+              END PROCESS;
+              sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg;
+              sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg;
+              ----------
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               sample_f0_wdata <= sample_f0_wdata_s;
               sample_f1_wdata <= sample_f1_wdata_s;
               sample_f2_wdata <= sample_f2_wdata_s;
               sample_f3_wdata <= sample_f3_wdata_s;
             END tb;

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +9 -6

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.spectral_matrix_package.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_Header.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.lpp_fft.ALL;
             USE lpp.fft_components.ALL;
             ENTITY lpp_lfr_ms IS
               GENERIC (
                 Mem_use : INTEGER := use_RAM
                 );
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 run  : IN STD_LOGIC;
                 ---------------------------------------------------------------------------
                 -- DATA INPUT
                 ---------------------------------------------------------------------------
                 start_date      : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
-                -- TIME
+                coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-                coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
+                --fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
-                fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                sample_f0_time  : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --
                 sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                sample_f1_time  : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --
                 sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                sample_f2_time  : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA
                 ---------------------------------------------------------------------------
                 dma_fifo_burst_valid: OUT STD_LOGIC;                      --TODO
                 dma_fifo_data       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
                 dma_fifo_ren        : IN  STD_LOGIC;                      --TODO
                 dma_buffer_new      : OUT STD_LOGIC;                      --TODOx
                 dma_buffer_addr     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
                 dma_buffer_length   : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);  --TODO
                 dma_buffer_full     : IN  STD_LOGIC;                      --TODO
                 dma_buffer_full_err : IN  STD_LOGIC;                      --TODO
                 -- Reg out
                 ready_matrix_f0           : OUT STD_LOGIC;                  -- TODO
                 ready_matrix_f1           : OUT STD_LOGIC;                  -- TODO
                 ready_matrix_f2           : OUT STD_LOGIC;                  -- TODO
             --    error_bad_component_error : OUT STD_LOGIC;                  -- TODO
                 error_buffer_full         : OUT STD_LOGIC;                  -- TODO
                 error_input_fifo_write    : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                 -- Reg In
                 status_ready_matrix_f0 : IN STD_LOGIC;                      -- TODO
                 status_ready_matrix_f1 : IN STD_LOGIC;                      -- TODO
                 status_ready_matrix_f2 : IN STD_LOGIC;                      -- TODO
                 addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 length_matrix_f0                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 length_matrix_f1                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 length_matrix_f2                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
                 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
                 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);  -- TODO
                 ---------------------------------------------------------------------------
                 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_lfr_ms IS
               SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_A_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_B_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL error_wen_f0 : STD_LOGIC;
               SIGNAL error_wen_f1 : STD_LOGIC;
               SIGNAL error_wen_f2 : STD_LOGIC;
               SIGNAL one_sample_f1_full : STD_LOGIC;
               SIGNAL one_sample_f1_wen  : STD_LOGIC;
               SIGNAL one_sample_f2_full : STD_LOGIC;
               SIGNAL one_sample_f2_wen  : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- FSM / SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               TYPE   fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
               SIGNAL state_fsm_select_channel     : fsm_select_channel;
             --  SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
               SIGNAL select_channel     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               TYPE   fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
               SIGNAL state_fsm_load_FFT      : fsm_load_FFT;
             --  SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
               SIGNAL select_fifo     : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL sample_ren_s   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_load    : STD_LOGIC;
               SIGNAL sample_valid   : STD_LOGIC;
               SIGNAL sample_valid_r : STD_LOGIC;
               SIGNAL sample_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               SIGNAL fft_read                 : STD_LOGIC;
               SIGNAL fft_pong                 : STD_LOGIC;
               SIGNAL fft_data_im              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_re              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_valid           : STD_LOGIC;
               SIGNAL fft_ready                : STD_LOGIC;
               -----------------------------------------------------------------------------
             --  SIGNAL fft_linker_ReUse    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE   fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
               SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
               SIGNAL current_fifo_load        : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL current_fifo_empty       : STD_LOGIC;
               SIGNAL current_fifo_locked      : STD_LOGIC;
               SIGNAL current_fifo_full        : STD_LOGIC;
               SIGNAL MEM_IN_SM_locked         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_Full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL SM_in_data      : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
               SIGNAL SM_in_ren       : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_in_empty     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_correlation_start     : STD_LOGIC;
               SIGNAL SM_correlation_auto      : STD_LOGIC;
               SIGNAL SM_correlation_done      : STD_LOGIC;
               SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
               SIGNAL SM_correlation_begin     : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Full_s    : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Write_s   : STD_LOGIC;
               SIGNAL current_matrix_write      : STD_LOGIC;
               SIGNAL current_matrix_wait_empty : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fifo_0_ready              : STD_LOGIC;
               SIGNAL fifo_1_ready              : STD_LOGIC;
               SIGNAL fifo_ongoing              : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_ren    : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty_threshold  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_data   : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
               -----------------------------------------------------------------------------
               SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_in  : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Full     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty_Threshold    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- TIME REG & INFOs
               -----------------------------------------------------------------------------
-              SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL f_empty       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL f_empty_reg   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_reg_f    : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f1   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f2   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               --SIGNAL time_update_f0_A : STD_LOGIC;
               --SIGNAL time_update_f0_B : STD_LOGIC;
               --SIGNAL time_update_f1   : STD_LOGIC;
               --SIGNAL time_update_f2   : STD_LOGIC;
               --
               SIGNAL status_channel   : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_MS_input  : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
               SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 4);
               SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 4);
               SIGNAL status_component_fifo_0_end : STD_LOGIC;
               SIGNAL status_component_fifo_1_end : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
               SIGNAL fft_ready_reg         : STD_LOGIC;
               SIGNAL fft_ready_rising_down : STD_LOGIC;
               SIGNAL sample_load_reg         : STD_LOGIC;
               SIGNAL sample_load_rising_down : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL sample_f1_wen_head     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen_head_in  : STD_LOGIC;
               SIGNAL sample_f1_wen_head_out : STD_LOGIC;
               SIGNAL sample_f1_full_head_in : STD_LOGIC;
               SIGNAL sample_f1_full_head_out : STD_LOGIC;
               SIGNAL sample_f1_empty_head_in : STD_LOGIC;
               SIGNAL sample_f1_wdata_head   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL ongoing : STD_LOGIC;
             BEGIN
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_f0_wen_s <= (OTHERS => '1');
                   sample_f1_wen_s <= (OTHERS => '1');
                   sample_f2_wen_s <= (OTHERS => '1');
                   ongoing <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF ongoing = '1' THEN
                     sample_f0_wen_s <= sample_f0_wen;
                     sample_f1_wen_s <= sample_f1_wen;
                     sample_f2_wen_s <= sample_f2_wen;
                   ELSE
                     IF start_date = coarse_time(30 DOWNTO 0) THEN
                       ongoing <= '1';
                     END IF;
                     sample_f0_wen_s <= (OTHERS => '1');
                     sample_f1_wen_s <= (OTHERS => '1');
                     sample_f2_wen_s <= (OTHERS => '1');
                   END IF;
                 END IF;
               END PROCESS;
               error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
               switch_f0_inst : spectral_matrix_switch_f0
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   sample_wen => sample_f0_wen_s,
                   fifo_A_empty => sample_f0_A_empty,
                   fifo_A_full  => sample_f0_A_full,
                   fifo_A_wen   => sample_f0_A_wen,
                   fifo_B_empty => sample_f0_B_empty,
                   fifo_B_full  => sample_f0_B_full,
                   fifo_B_wen   => sample_f0_B_wen,
                   error_wen => error_wen_f0);       -- TODO
               -----------------------------------------------------------------------------
               -- FIFO IN
               -----------------------------------------------------------------------------
               lppFIFOxN_f0_a : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen   => sample_f0_A_wen,
                   wdata => sample_f0_wdata,
                   ren   => sample_f0_A_ren,
                   rdata => sample_f0_A_rdata,
                   empty       => sample_f0_A_empty,
                   full        => sample_f0_A_full,
                   almost_full => OPEN);
               lppFIFOxN_f0_b : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f0_B_wen,
                   wdata       => sample_f0_wdata,
                   ren         => sample_f0_B_ren,
                   rdata       => sample_f0_B_rdata,
                   empty       => sample_f0_B_empty,
                   full        => sample_f0_B_full,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               -- sample_f1_wen   in
               -- sample_f1_wdata in
               -- sample_f1_full  OUT
               sample_f1_wen_head_in   <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
               sample_f1_full_head_in  <= '0' WHEN sample_f1_full  = "00000" ELSE '1';
               sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
               lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
                 PORT MAP (
                   clk      => clk,
                   rstn     => rstn,
                   in_wen   => sample_f1_wen_head_in,
                   in_data  => sample_f1_wdata,
                   in_full  => sample_f1_full_head_in,
                   in_empty => sample_f1_empty_head_in,
                   out_write_error => error_wen_f1,
                   out_wen  => sample_f1_wen_head_out,
                   out_data => sample_f1_wdata_head,
                   out_full => sample_f1_full_head_out);
               sample_f1_wen_head    <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
               lppFIFOxN_f1 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f1_wen_head,
                   wdata       => sample_f1_wdata_head,
                   ren         => sample_f1_ren,
                   rdata       => sample_f1_rdata,
                   empty       => sample_f1_empty,
                   full        => sample_f1_full,
                   almost_full => sample_f1_almost_full);
               one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f1_full <= '0';
                   --error_wen_f1       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f1_full_head_out = '0' THEN
                     one_sample_f1_full <= '0';
                   ELSE
                     one_sample_f1_full <= '1';
                   END IF;
                   --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               lppFIFOxN_f2 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f2_wen_s,
                   wdata       => sample_f2_wdata,
                   ren         => sample_f2_ren,
                   rdata       => sample_f2_rdata,
                   empty       => sample_f2_empty,
                   full        => sample_f2_full,
                   almost_full => OPEN);
               one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f2_full <= '0';
                   error_wen_f2       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f2_full = "00000" THEN
                     one_sample_f2_full <= '0';
                   ELSE
                     one_sample_f2_full <= '1';
                   END IF;
                   error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- FSM SELECT CHANNEL
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_select_channel <= IDLE;
                   select_channel <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_select_channel IS
                     WHEN IDLE =>
                       IF sample_f1_full = "11111" THEN
                         state_fsm_select_channel <= SWITCH_F1;
                         select_channel <= "10";
                       ELSIF sample_f1_almost_full = "00000" THEN
                         IF sample_f0_A_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_A;
                           select_channel <= "00";
                         ELSIF sample_f0_B_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_B;
                           select_channel <= "01";
                         ELSIF sample_f2_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F2;
                           select_channel <= "11";
                         END IF;
                       END IF;
                     WHEN SWITCH_F0_A =>
                       IF sample_f0_A_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F0_B =>
                       IF sample_f0_B_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F1 =>
                       IF sample_f1_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F2 =>
                       IF sample_f2_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   select_channel_reg <= (OTHERS => '0');
                   --pre_state_fsm_select_channel <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   select_channel_reg <= select_channel;
                   --pre_state_fsm_select_channel <= state_fsm_select_channel;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                               sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                               sample_f1_empty   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                               sample_f2_empty   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                               (OTHERS => '1');
               sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                              sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                              sample_f1_full   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                              sample_f2_full   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                              (OTHERS => '0');
               --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
               --                sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
               --                sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
               --                sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
               sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
                               sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
                               sample_f1_rdata   WHEN select_channel_reg = "10"   ELSE
                               sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
               sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
               sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
               sample_f1_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1   ELSE (OTHERS => '1');
               sample_f2_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2   ELSE (OTHERS => '1');
               status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                                 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                                 time_reg_f1 & "01"   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                                 time_reg_f2 & "10";  -- WHEN state_fsm_select_channel = SWITCH_F2
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
                             sample_ren_s    WHEN sample_load = '1' ELSE
                             (OTHERS => '1');
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_ren_s       <= (OTHERS => '1');
                   state_fsm_load_FFT <= IDLE;
                   status_MS_input    <= (OTHERS => '0');
                   select_fifo        <= "000";
                   --next_state_fsm_load_FFT <= IDLE;
                   --sample_valid              <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_FFT IS
                     WHEN IDLE =>
                       --sample_valid <= '0';
                       sample_ren_s <= (OTHERS => '1');
                       IF sample_full = "11111" AND sample_load = '1' THEN
                         state_fsm_load_FFT <= FIFO_1;
                         status_MS_input    <= status_channel;
                         select_fifo <= "000";
                       END IF;
                     WHEN FIFO_1 =>
                       sample_ren_s <= "1111" & NOT(sample_load);
                       IF sample_empty(0) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_2;
                         select_fifo <= "001";
                       END IF;
                     WHEN FIFO_2 =>
                       sample_ren_s <= "111" & NOT(sample_load) & '1';
                       IF sample_empty(1) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_3;
                         select_fifo <= "010";
                       END IF;
                     WHEN FIFO_3 =>
                       sample_ren_s <= "11" & NOT(sample_load) & "11";
                       IF sample_empty(2) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_4;
                         select_fifo <= "011";
                       END IF;
                     WHEN FIFO_4 =>
                       sample_ren_s <= '1' & NOT(sample_load) & "111";
                       IF sample_empty(3) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_5;
                         select_fifo <= "100";
                       END IF;
                     WHEN FIFO_5 =>
                       sample_ren_s <= NOT(sample_load) & "1111";
                       IF sample_empty(4) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= IDLE;
                         select_fifo <= "000";
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_valid_r          <= '0';
                   select_fifo_reg <= (OTHERS => '0');
                   --next_state_fsm_load_FFT <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   select_fifo_reg <= select_fifo;
                   --next_state_fsm_load_FFT <= state_fsm_load_FFT;
                   IF sample_ren_s = "11111" THEN
                     sample_valid_r <= '0';
                   ELSE
                     sample_valid_r <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
               --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
               --               sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
               --               sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
               --               sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
               --               sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
                              sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
                              sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
                              sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011"  ELSE
                              sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_valid   => sample_valid,
                   fft_read       => fft_read,
                   sample_data    => sample_data,
                   sample_load    => sample_load,
                   fft_pong       => fft_pong,
                   fft_data_im    => fft_data_im,
                   fft_data_re    => fft_data_re,
                   fft_data_valid => fft_data_valid,
                   fft_ready      => fft_ready);
               debug_vector(0) <= fft_data_valid;
               debug_vector(1) <= fft_ready;
               debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
               -----------------------------------------------------------------------------
               fft_ready_rising_down   <= fft_ready_reg AND NOT fft_ready;
               sample_load_rising_down <= sample_load_reg AND NOT sample_load;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fft_ready_reg     <= '0';
                   sample_load_reg   <= '0';
                   fft_ongoing_counter <= '0';
                 ELSIF clk'event AND clk = '1' THEN
                   fft_ready_reg    <= fft_ready;
                   sample_load_reg  <= sample_load;
                   IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
                     fft_ongoing_counter <= '0';
             --        CASE fft_ongoing_counter IS
             --          WHEN "01" => fft_ongoing_counter <= "00";
             ----          WHEN "10" => fft_ongoing_counter <= "01";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
                     fft_ongoing_counter <= '1';
             --        CASE fft_ongoing_counter IS
             --          WHEN "00" => fft_ongoing_counter <= "01";
             ----          WHEN "01" => fft_ongoing_counter <= "10";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_load_MS_memory <= IDLE;
                   current_fifo_load        <= "00001";
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_MS_memory IS
                     WHEN IDLE =>
                       IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
                         state_fsm_load_MS_memory <= LOAD_FIFO;
                       END IF;
                     WHEN LOAD_FIFO =>
                       IF current_fifo_full = '1' THEN
                         state_fsm_load_MS_memory <= TRASH_FFT;
                       END IF;
                     WHEN TRASH_FFT =>
                       IF fft_ready = '0' THEN
                         state_fsm_load_MS_memory <= IDLE;
                         current_fifo_load        <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
                                     MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
                                     MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
                                     MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
                                     MEM_IN_SM_Empty(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
                                    MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
                                    MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
                                    MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
                                    MEM_IN_SM_Full(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
                                      MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
                                      MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
                                      MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
                                      MEM_IN_SM_locked(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
               all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
                 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
                                       AND state_fsm_load_MS_memory = LOAD_FIFO
                                       AND current_fifo_load(I) = '1'
                                       ELSE '1';
               END GENERATE all_fifo;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   MEM_IN_SM_wen <= (OTHERS => '1');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
                 END IF;
               END PROCESS;
               MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               Mem_In_SpectralMatrix : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 32,                    --16,
                   Addr_sz => 7,                     --8
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => MEM_IN_SM_ReUse,
                   run   => (OTHERS => '1'),
                   wen   => MEM_IN_SM_wen,
                   wdata => MEM_IN_SM_wData,
                   ren         => MEM_IN_SM_ren,
                   rdata       => MEM_IN_SM_rData,
                   full        => MEM_IN_SM_Full,
                   empty       => MEM_IN_SM_Empty,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               MS_control_1 : MS_control
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   current_status_ms => status_MS_input,
                   fifo_in_lock  => MEM_IN_SM_locked,
                   fifo_in_data  => MEM_IN_SM_rdata,
                   fifo_in_full  => MEM_IN_SM_Full,
                   fifo_in_empty => MEM_IN_SM_Empty,
                   fifo_in_ren   => MEM_IN_SM_ren,
                   fifo_in_reuse => MEM_IN_SM_ReUse,
                   fifo_out_data  => SM_in_data,
                   fifo_out_ren   => SM_in_ren,
                   fifo_out_empty => SM_in_empty,
                   current_status_component => status_component,
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_done  => SM_correlation_done);
               MS_calculation_1 : MS_calculation
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   fifo_in_data  => SM_in_data,
                   fifo_in_ren   => SM_in_ren,
                   fifo_in_empty => SM_in_empty,
                   fifo_out_data => MEM_OUT_SM_Data_in_s,  --    TODO
                   fifo_out_wen  => MEM_OUT_SM_Write_s,    --      TODO
                   fifo_out_full => MEM_OUT_SM_Full_s,     --       TODO
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_begin => SM_correlation_begin,
                   correlation_done  => SM_correlation_done);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   current_matrix_write        <= '0';
                   current_matrix_wait_empty   <= '1';
                   status_component_fifo_0     <= (OTHERS => '0');
                   status_component_fifo_1     <= (OTHERS => '0');
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   SM_correlation_done_reg1    <= '0';
                   SM_correlation_done_reg2    <= '0';
                   SM_correlation_done_reg3    <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   SM_correlation_done_reg1    <= SM_correlation_done;
                   SM_correlation_done_reg2    <= SM_correlation_done_reg1;
                   SM_correlation_done_reg3    <= SM_correlation_done_reg2;
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   IF SM_correlation_begin = '1' THEN
                     IF current_matrix_write = '0' THEN
                       status_component_fifo_0 <= status_component(53 DOWNTO 4);
                     ELSE
                       status_component_fifo_1 <= status_component(53 DOWNTO 4);
                     END IF;
                   END IF;
                   IF SM_correlation_done_reg3 = '1' THEN
                     IF current_matrix_write = '0' THEN
                       status_component_fifo_0_end <= '1';
                     ELSE
                       status_component_fifo_1_end <= '1';
                     END IF;
                     current_matrix_wait_empty <= '1';
                     current_matrix_write      <= NOT current_matrix_write;
                   END IF;
                   IF current_matrix_wait_empty <= '1' THEN
                     IF current_matrix_write = '0' THEN
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
                     ELSE
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
                                    '1'                WHEN SM_correlation_done_reg1 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg2 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg3 = '1'  ELSE
                                    '1'                WHEN current_matrix_wait_empty = '1' ELSE
                                    MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0'      ELSE
                                    MEM_OUT_SM_Full(1);
               MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
               MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
               MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
               -----------------------------------------------------------------------------
               --Mem_Out_SpectralMatrix : lppFIFOxN
               --  GENERIC MAP (
               --    tech    => 0,
               --    Mem_use => Mem_use,
               --    Data_sz => 32,
               --    Addr_sz => 8,
               --    FifoCnt => 2)
               --  PORT MAP (
               --    clk  => clk,
               --    rstn => rstn,
               --    ReUse => (OTHERS => '0'),
               --    run   => (OTHERS => '1'),
               --    wen   => MEM_OUT_SM_Write,
               --    wdata => MEM_OUT_SM_Data_in,
               --    ren   => MEM_OUT_SM_Read,
               --    rdata => MEM_OUT_SM_Data_out,
               --    full        => MEM_OUT_SM_Full,
               --    empty       => MEM_OUT_SM_Empty,
               --    almost_full => OPEN);
               all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
                 Mem_Out_SpectralMatrix_I: lpp_fifo
                   GENERIC MAP (
                     tech                  => 0,
                     Mem_use               => Mem_use,
                     EMPTY_THRESHOLD_LIMIT => 15,
                     FULL_THRESHOLD_LIMIT  => 1,
                     DataSz                => 32,
                     AddrSz                => 8)
                   PORT MAP (
                     clk             => clk,
                     rstn            => rstn,
                     reUse           => '0',
                     run             => run,
                     ren             => MEM_OUT_SM_Read(I),
                     rdata           => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
                     wen             => MEM_OUT_SM_Write(I),
                     wdata           => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
                     empty           => MEM_OUT_SM_Empty(I),
                     full            => MEM_OUT_SM_Full(I),
                     full_almost     => OPEN,
                     empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
                     full_threshold  => OPEN);
               END GENERATE all_Mem_Out_SpectralMatrix;
               -----------------------------------------------------------------------------
             --  MEM_OUT_SM_Read <= "00";
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fifo_0_ready <= '0';
                   fifo_1_ready <= '0';
                   fifo_ongoing <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
                     fifo_ongoing <= '1';
                     fifo_0_ready <= '0';
                   ELSIF status_component_fifo_0_end = '1' THEN
                     fifo_0_ready <= '1';
                   END IF;
                   IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
                     fifo_ongoing <= '0';
                     fifo_1_ready <= '0';
                   ELSIF status_component_fifo_1_end = '1' THEN
                     fifo_1_ready <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
                                     '1' WHEN fifo_0_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
                                     '1' WHEN fifo_1_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
                                     MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
                                     '1';
               FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
                                      status_component_fifo_1;
               FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
                                    MEM_OUT_SM_Data_out(63 DOWNTO 32);
               FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1'  ELSE
                                               MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1'  ELSE
                                               '1';
               -----------------------------------------------------------------------------
               --    fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),       --IN
               --    fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),       --IN
               --    fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),      --IN
               --    fifo_data             => FSM_DMA_fifo_data,                     --IN
               --    fifo_empty            => FSM_DMA_fifo_empty,                    --IN
               --    fifo_empty_threshold  => FSM_DMA_fifo_empty_threshold,          --IN
               --    fifo_ren              => FSM_DMA_fifo_ren,                      --OUT
               lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
                 PORT MAP (
                   clk                    => clk,
                   rstn                   => rstn,
                   run                    => run,
                   fifo_matrix_type       => FSM_DMA_fifo_status(5 DOWNTO 4),
                   fifo_matrix_time       => FSM_DMA_fifo_status(53 DOWNTO 6),
                   fifo_data              => FSM_DMA_fifo_data,
                   fifo_empty             => FSM_DMA_fifo_empty,
                   fifo_empty_threshold   => FSM_DMA_fifo_empty_threshold,
                   fifo_ren               => FSM_DMA_fifo_ren,
                   dma_fifo_valid_burst   => dma_fifo_burst_valid,
                   dma_fifo_data          => dma_fifo_data,
                   dma_fifo_ren           => dma_fifo_ren,
                   dma_buffer_new         => dma_buffer_new,
                   dma_buffer_addr        => dma_buffer_addr,
                   dma_buffer_length      => dma_buffer_length,
                   dma_buffer_full        => dma_buffer_full,
                   dma_buffer_full_err    => dma_buffer_full_err,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   addr_matrix_f0         => addr_matrix_f0,
                   addr_matrix_f1         => addr_matrix_f1,
                   addr_matrix_f2         => addr_matrix_f2,
                   length_matrix_f0       => length_matrix_f0,
                   length_matrix_f1       => length_matrix_f1,
                   length_matrix_f2       => length_matrix_f2,
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   matrix_time_f0         => matrix_time_f0,
                   matrix_time_f1         => matrix_time_f1,
                   matrix_time_f2         => matrix_time_f2,
                   error_buffer_full      => error_buffer_full);
               --dma_fifo_burst_valid: OUT STD_LOGIC;                      --TODO
               --dma_fifo_data       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
               --dma_fifo_ren        : IN  STD_LOGIC;                      --TODO
               --dma_buffer_new      : OUT STD_LOGIC;                      --TODO
               --dma_buffer_addr     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
               --dma_buffer_length   : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);  --TODO
               --dma_buffer_full     : IN  STD_LOGIC;                      --TODO
               --dma_buffer_full_err : IN  STD_LOGIC;                      --TODO
               ---- Reg out
               --ready_matrix_f0           : OUT STD_LOGIC;                  -- TODO
               --ready_matrix_f1           : OUT STD_LOGIC;                  -- TODO
               --ready_matrix_f2           : OUT STD_LOGIC;                  -- TODO
               --error_bad_component_error : OUT STD_LOGIC;                  -- TODO
               --error_buffer_full         : OUT STD_LOGIC;                  -- TODO
               ---- Reg In
               --status_ready_matrix_f0 : IN STD_LOGIC;                      -- TODO
               --status_ready_matrix_f1 : IN STD_LOGIC;                      -- TODO
               --status_ready_matrix_f2 : IN STD_LOGIC;                      -- TODO
               --addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
               --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
               --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)  -- TODO
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
               --  PORT MAP (
               --    HCLK    => clk,
               --    HRESETn => rstn,
               --    fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),
               --    fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
               --    fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),
               --    fifo_data             => FSM_DMA_fifo_data,
               --    fifo_empty            => FSM_DMA_fifo_empty,
               --    fifo_ren              => FSM_DMA_fifo_ren,
               --    dma_addr        => dma_addr,
               --    dma_data        => dma_data,
               --    dma_valid       => dma_valid,
               --    dma_valid_burst => dma_valid_burst,
               --    dma_ren         => dma_ren,
               --    dma_done        => dma_done,
               --    ready_matrix_f0 => ready_matrix_f0,
               --    ready_matrix_f1 => ready_matrix_f1,
               --    ready_matrix_f2 => ready_matrix_f2,
               --    error_bad_component_error => error_bad_component_error,
               --    error_buffer_full         => error_buffer_full,
               --    debug_reg              => debug_reg,
               --    status_ready_matrix_f0 => status_ready_matrix_f0,
               --    status_ready_matrix_f1 => status_ready_matrix_f1,
               --    status_ready_matrix_f2 => status_ready_matrix_f2,
               --    config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
               --    config_active_interruption_onError     => config_active_interruption_onError,
               --    addr_matrix_f0 => addr_matrix_f0,
               --    addr_matrix_f1 => addr_matrix_f1,
               --    addr_matrix_f2 => addr_matrix_f2,
               --    matrix_time_f0 => matrix_time_f0,
               --    matrix_time_f1 => matrix_time_f1,
               --    matrix_time_f2 => matrix_time_f2
               --    );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- TIME MANAGMENT
               -----------------------------------------------------------------------------
-              all_time         <= coarse_time & fine_time;
+              all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
+              --all_time         <= coarse_time & fine_time;
               --
               f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
               f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
               f_empty(2) <= '1' WHEN sample_f1_empty   = "11111" ELSE '0';
               f_empty(3) <= '1' WHEN sample_f2_empty   = "11111" ELSE '0';
               all_time_reg: FOR I IN 0 TO 3 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     f_empty_reg(I) <= '1';
                   ELSIF clk'event AND clk = '1' THEN
                     f_empty_reg(I) <= f_empty(I);
                   END IF;
                 END PROCESS;
                 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
                 s_m_t_m_f0_A : spectral_matrix_time_managment
                   PORT MAP (
                     clk      => clk,
                     rstn     => rstn,
-                    time_in  => all_time,
+                    time_in  => all_time((I+1)*48-1 DOWNTO I*48),
                     update_1 => time_update_f(I),
                     time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
                     );
               END GENERATE all_time_reg;
               time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
               time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
               time_reg_f1   <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
               time_reg_f2   <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
               -----------------------------------------------------------------------------
             END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +403 -395

This diff has been collapsed as it changes many lines, (798 lines changed) Show them Hide them
	@@ -1,395 +1,403
	1	LIBRARY ieee;	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;	2	USE ieee.std_logic_1164.ALL;
	3		3
	4	LIBRARY grlib;	4	LIBRARY grlib;
	5	USE grlib.amba.ALL;	5	USE grlib.amba.ALL;
	6		6
	7	LIBRARY lpp;	7	LIBRARY lpp;
	8	USE lpp.lpp_ad_conv.ALL;	8	USE lpp.lpp_ad_conv.ALL;
	9	USE lpp.iir_filter.ALL;	9	USE lpp.iir_filter.ALL;
	10	USE lpp.FILTERcfg.ALL;	10	USE lpp.FILTERcfg.ALL;
	11	USE lpp.lpp_memory.ALL;	11	USE lpp.lpp_memory.ALL;
	12	LIBRARY techmap;	12	LIBRARY techmap;
	13	USE techmap.gencomp.ALL;	13	USE techmap.gencomp.ALL;
	14		14
	15	PACKAGE lpp_lfr_pkg IS	15	PACKAGE lpp_lfr_pkg IS
	16	-----------------------------------------------------------------------------	16	-----------------------------------------------------------------------------
	17	-- TEMP	17	-- TEMP
	18	-----------------------------------------------------------------------------	18	-----------------------------------------------------------------------------
	19	COMPONENT lpp_lfr_ms_test	19	COMPONENT lpp_lfr_ms_test
	20	GENERIC (	20	GENERIC (
	21	Mem_use : INTEGER);	21	Mem_use : INTEGER);
	22	PORT (	22	PORT (
	23	clk : IN STD_LOGIC;	23	clk : IN STD_LOGIC;
	24	rstn : IN STD_LOGIC;	24	rstn : IN STD_LOGIC;
	25		25
	26	-- TIME	26	-- TIME
	27	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo	27	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
	28	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo	28	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
	29	--	29	--
	30	sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	30	sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	31	sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	31	sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	32	--	32	--
	33	sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	33	sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	34	sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	34	sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	35	--	35	--
	36	sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	36	sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	37	sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	37	sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	38		38
	39		39
	40		40
	41	---------------------------------------------------------------------------	41	---------------------------------------------------------------------------
	42	error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);	42	error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
	43		43
	44	--	44	--
	45	--sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);	45	--sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	46	--sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	46	--sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	47	--sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	47	--sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	48	--sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	48	--sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	49		49
	50	--status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);	50	--status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
	51		51
	52	-- IN	52	-- IN
	53	MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	53	MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	54		54
	55	-----------------------------------------------------------------------------	55	-----------------------------------------------------------------------------
	56		56
	57	status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);	57	status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
	58	SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);	58	SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
	59	SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);	59	SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	60	SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);	60	SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	61		61
	62	SM_correlation_start : OUT STD_LOGIC;	62	SM_correlation_start : OUT STD_LOGIC;
	63	SM_correlation_auto : OUT STD_LOGIC;	63	SM_correlation_auto : OUT STD_LOGIC;
	64	SM_correlation_done : IN STD_LOGIC	64	SM_correlation_done : IN STD_LOGIC
	65	);	65	);
	66	END COMPONENT;	66	END COMPONENT;
	67		67
	68		68
	69	-----------------------------------------------------------------------------	69	-----------------------------------------------------------------------------
	70	COMPONENT lpp_lfr_ms	70	COMPONENT lpp_lfr_ms
	71	GENERIC (	71	GENERIC (
	72	Mem_use : INTEGER);	72	Mem_use : INTEGER);
	73	PORT (	73	PORT (
	74	clk : IN STD_LOGIC;	74	clk : IN STD_LOGIC;
	75	rstn : IN STD_LOGIC;	75	rstn : IN STD_LOGIC;
	76	run : IN STD_LOGIC;	76	run : IN STD_LOGIC;
	77	start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);	77	start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
	78	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	78	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	79	~~fine_time~~ : IN STD_LOGIC_VECTOR(15 DOWNTO 0);	79	sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	80	sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	80	sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	81	sample_f0_~~wdata~~ : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	81	sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	82	sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	82	sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	83	sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	83	sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	84	sample_f~~2_wen~~ : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	84	sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	85	sample_f2_w~~data~~ : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	85	sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	86	dma_fifo_burst_valid : OUT STD_LOGIC;	86	sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	87	~~dma_fifo_data~~ : ~~OUT~~ STD_LOGIC_VECTOR(31 DOWNTO 0);	87	sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	88	dma_fifo_~~ren~~ : IN STD_LOGIC;	88	dma_fifo_burst_valid : OUT STD_LOGIC;
	89	dma_~~buffer_new~~ : OUT STD_LOGIC;	89	dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	90	dma_~~buffer_addr~~ : ~~OUT~~ STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	90	dma_fifo_ren : IN STD_LOGIC;
	91	dma_buffer_~~length~~ : OUT STD_LOGIC~~_VECTOR~~(25 ~~DOWNTO~~ 0);	91	dma_buffer_new : OUT STD_LOGIC;
	92	dma_buffer_~~full~~ : IN STD_LOGIC;	92	dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	93	dma_buffer_~~full_err~~ : IN STD_LOGIC;	93	dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
	94	~~ready_matrix_f0~~ : ~~OUT~~ STD_LOGIC;	94	dma_buffer_full : IN STD_LOGIC;
	95	~~ready_matrix_f1~~ : ~~OUT~~ STD_LOGIC;	95	dma_buffer_full_err : IN STD_LOGIC;
	96	ready_matrix_f2 : OUT STD_LOGIC;	96	ready_matrix_f0 : OUT STD_LOGIC;
	97	~~error_buffer_full~~ : OUT STD_LOGIC;	97	ready_matrix_f1 : OUT STD_LOGIC;
	98	error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);	98	ready_matrix_f2 : OUT STD_LOGIC;
	99	status_ready_matrix_f0 : IN STD_LOGIC;	99	error_buffer_full : OUT STD_LOGIC;
	100	status_ready_matrix_f1 : IN STD_LOGIC;	100	error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
	101	status_ready_matrix_f2 : IN STD_LOGIC;	101	status_ready_matrix_f0 : IN STD_LOGIC;
	102	~~addr_matrix_f0~~ : IN STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	102	status_ready_matrix_f1 : IN STD_LOGIC;
	103	~~addr_matrix_f1~~ : IN STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	103	status_ready_matrix_f2 : IN STD_LOGIC;
	104	addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	104	addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	105	~~length_matrix_f0~~ : IN STD_LOGIC_VECTOR(25 DOWNTO 0);	105	addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	106	~~length_matrix_f1~~ : IN STD_LOGIC_VECTOR(25 DOWNTO 0);	106	addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	107	length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);	107	length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
	108	matrix_~~time_f0~~ : ~~OUT~~ STD_LOGIC_VECTOR(47 DOWNTO 0);	108	length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
	109	matrix_~~time_f1~~ : ~~OUT~~ STD_LOGIC_VECTOR(47 DOWNTO 0);	109	length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
	110	matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	110	matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	111	~~debug_vector~~ : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));	111	matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	112	END COMPONENT;	112	matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	113		113	debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
	114	COMPONENT lpp_lfr_ms_fsmdma	114	END COMPONENT;
	115	PORT (	115
	116	clk : IN STD_ULOGIC;	116	COMPONENT lpp_lfr_ms_fsmdma
	117	rstn : IN STD_ULOGIC;	117	PORT (
	118	~~run~~ : IN STD_LOGIC;	118	clk : IN STD_ULOGIC;
	119	fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);	119	rstn : IN STD_ULOGIC;
	120	fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	120	run : IN STD_LOGIC;
	121	fifo_~~data~~ : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	121	fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	122	fifo_~~empty~~ : IN STD_LOGIC;	122	fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	123	fifo_empty_threshold : IN STD_LOGIC;	123	fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	124	fifo_~~ren~~ : ~~OUT~~ STD_LOGIC;	124	fifo_empty : IN STD_LOGIC;
	125	~~dma_fifo_valid_burst~~ : ~~OUT~~ STD_LOGIC;	125	fifo_empty_threshold : IN STD_LOGIC;
	126	~~dma_fifo_data~~ : OUT STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	126	fifo_ren : OUT STD_LOGIC;
	127	dma_fifo_~~ren~~ : IN STD_LOGIC;	127	dma_fifo_valid_burst : OUT STD_LOGIC;
	128	dma_~~buffer_new~~ : OUT STD_LOGIC;	128	dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	129	dma_~~buffer_addr~~ : ~~OUT~~ STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	129	dma_fifo_ren : IN STD_LOGIC;
	130	dma_buffer_~~length~~ : OUT STD_LOGIC~~_VECTOR~~(25 ~~DOWNTO~~ 0);	130	dma_buffer_new : OUT STD_LOGIC;
	131	dma_buffer_~~full~~ : IN STD_LOGIC;	131	dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	132	dma_buffer_~~full_err~~ : IN STD_LOGIC;	132	dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
	133	~~status_ready_matrix_f0~~ : IN STD_LOGIC;	133	dma_buffer_full : IN STD_LOGIC;
	134	~~status_ready_matrix_f1~~ : IN STD_LOGIC;	134	dma_buffer_full_err : IN STD_LOGIC;
	135	status_ready_matrix_f2 : IN STD_LOGIC;	135	status_ready_matrix_f0 : IN STD_LOGIC;
	136	~~addr_matrix_f0~~ : IN STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	136	status_ready_matrix_f1 : IN STD_LOGIC;
	137	~~addr_matrix_f1~~ : IN STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	137	status_ready_matrix_f2 : IN STD_LOGIC;
	138	addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	138	addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	139	~~length_matrix_f0~~ : IN STD_LOGIC_VECTOR(25 DOWNTO 0);	139	addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	140	~~length_matrix_f1~~ : IN STD_LOGIC_VECTOR(25 DOWNTO 0);	140	addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	141	length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);	141	length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
	142	~~ready_matrix_f0~~ : ~~OUT~~ ~~STD_LOGIC~~;	142	length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
	143	~~ready_matrix_f1~~ : ~~OUT~~ ~~STD_LOGIC~~;	143	length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
	144	ready_matrix_f2 : OUT STD_LOGIC;	144	ready_matrix_f0 : OUT STD_LOGIC;
	145	matrix_~~time_f0~~ : OUT STD_LOGIC~~_VECTOR~~(47 ~~DOWNTO~~ 0);	145	ready_matrix_f1 : OUT STD_LOGIC;
	146	matrix_~~time_f1~~ : OUT STD_LOGIC~~_VECTOR~~(47 ~~DOWNTO~~ 0);	146	ready_matrix_f2 : OUT STD_LOGIC;
	147	matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	147	matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	148	error_buffer_full : OUT STD_LOGIC);	148	matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	149	END COMPONENT;	149	matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	150		150	error_buffer_full : OUT STD_LOGIC);
	151	COMPONENT lpp_lfr_ms_FFT	151	END COMPONENT;
	152	PORT (	152
	153	clk : IN STD_LOGIC;	153	COMPONENT lpp_lfr_ms_FFT
	154	rstn : IN STD_LOGIC;	154	PORT (
	155	~~sample_valid~~ : IN STD_LOGIC;	155	clk : IN STD_LOGIC;
	156	~~fft_read~~ : IN STD_LOGIC;	156	rstn : IN STD_LOGIC;
	157	sample_~~data~~ : IN STD_LOGIC~~_VECTOR~~(15 ~~DOWNTO~~ 0);	157	sample_valid : IN STD_LOGIC;
	158	~~sample_load~~ : ~~OUT~~ STD_LOGIC;	158	fft_read : IN STD_LOGIC;
	159	fft_pong : OUT STD_LOGIC;	159	sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	160	fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);	160	sample_load : OUT STD_LOGIC;
	161	fft_~~data_re~~ : OUT STD_LOGIC~~_VECTOR~~(15 ~~DOWNTO~~ 0);	161	fft_pong : OUT STD_LOGIC;
	162	fft_data_~~valid~~ : OUT STD_LOGIC;	162	fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
	163	fft_re~~ady~~ : OUT STD_LOGIC);	163	fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
	164	END COMPONENT;	164	fft_data_valid : OUT STD_LOGIC;
	165		165	fft_ready : OUT STD_LOGIC);
	166	COMPONENT lpp_lfr_filter	166	END COMPONENT;
	167	GENERIC (	167
	168	Mem_use : INTEGER);	168	COMPONENT lpp_lfr_filter
	169	~~PORT~~ (	169	GENERIC (
	170	sample : IN Samples(7 DOWNTO 0);	170	Mem_use : INTEGER);
	171	sample_val : IN STD_LOGIC;	171	PORT (
	172	~~clk~~ : IN S~~TD_LOGIC~~;	172	sample : IN Samples(7 DOWNTO 0);
	173	~~rstn~~ : IN STD_LOGIC;	173	sample_val : IN STD_LOGIC;
	174	data_shaping_SP0 : IN STD_LOGIC;	174	sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	175	data_shaping_SP1 : IN STD_LOGIC;	175	clk : IN STD_LOGIC;
	176	~~data_shaping_R0~~ : IN STD_LOGIC;	176	rstn : IN STD_LOGIC;
	177	data_shaping_R1 : IN STD_LOGIC;	177	data_shaping_SP0 : IN STD_LOGIC;
	178	data_shaping_R2 : IN STD_LOGIC;	178	data_shaping_SP1 : IN STD_LOGIC;
	179	~~sample_f0_val~~ : ~~OUT~~ STD_LOGIC;	179	data_shaping_R0 : IN STD_LOGIC;
	180	~~sample_f1_val~~ : ~~OUT~~ STD_LOGIC;	180	data_shaping_R1 : IN STD_LOGIC;
	181	~~sample_f2_val~~ : ~~OUT~~ STD_LOGIC;	181	data_shaping_R2 : IN STD_LOGIC;
	182	sample_f3_val : OUT STD_LOGIC;	182	sample_f0_val : OUT STD_LOGIC;
	183	sample_f~~0_wdata~~ : OUT STD_LOGIC~~_VECTOR~~((6*16)-1 ~~DOWNTO~~ 0);	183	sample_f1_val : OUT STD_LOGIC;
	184	sample_f~~1_wdata~~ : OUT STD_LOGIC~~_VECTOR~~((6*16)-1 ~~DOWNTO~~ 0);	184	sample_f2_val : OUT STD_LOGIC;
	185	sample_f~~2_wdata~~ : OUT STD_LOGIC~~_VECTOR~~((6*16)-1 ~~DOWNTO~~ 0);	185	sample_f3_val : OUT STD_LOGIC;
	186	sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));	186	sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
	187	END COMPONENT;	187	sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
	188		188	sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
	189	COMPONENT lpp_lfr	189	sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
	190	GENERIC (	190	sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	191	Mem_use : INTEGER;	191	sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	192	nb_data_by_buffer_size : INTEGER;	192	sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	193	-- nb_word_by_buffer_size : INTEGER;	193	sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
	194	nb_snapshot_param_size : INTEGER;	194	);
	195	delta_vector_size : INTEGER;	195	END COMPONENT;
	196	delta_vector_size_f0_2 : INTEGER;	196
	197	pindex : INTEGER;	197	COMPONENT lpp_lfr
	198	paddr : INTEGER;	198	GENERIC (
	199	~~pmask~~ : INTEGER;	199	Mem_use : INTEGER;
	200	pirq_ms : INTEGER;	200	nb_data_by_buffer_size : INTEGER;
	201	pirq_wfp : INTEGER;	201	-- nb_word_by_buffer_size : INTEGER;
	202	hindex : INTEGER;	202	nb_snapshot_param_size : INTEGER;
	203	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)	203	delta_vector_size : INTEGER;
	204	);	204	delta_vector_size_f0_2 : INTEGER;
	205	PORT (	205	pindex : INTEGER;
	206	~~clk~~ : IN ~~STD_LOGIC~~;	206	paddr : INTEGER;
	207	~~rstn~~ : IN ~~STD_LOGIC~~;	207	pmask : INTEGER;
	208	sample_B : IN Samples(2 DOWNTO 0);	208	pirq_ms : INTEGER;
	209	sample_E : IN Samples(4 DOWNTO 0);	209	pirq_wfp : INTEGER;
	210	sample_val : IN STD_LOGIC;	210	hindex : INTEGER;
	211	apbi : IN apb_slv_in_type;	211	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
	212	apbo : OUT apb_slv_out_type;	212	);
	213	ahbi : IN AHB_Mst_In_Type;	213	PORT (
	214	ahbo : OUT AHB_Mst_Out_Type;	214	clk : IN STD_LOGIC;
	215	~~coarse_time~~ : IN STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	215	rstn : IN STD_LOGIC;
	216	~~fine_time~~ : IN S~~TD_LOGIC_VECTOR~~(15 DOWNTO 0);	216	sample_B : IN Samples(2 DOWNTO 0);
	217	data_shaping_BW : OUT STD_LOGIC ;	217	sample_E : IN Samples(4 DOWNTO 0);
	218	debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);	218	sample_val : IN STD_LOGIC;
	219	debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)	219	apbi : IN apb_slv_in_type;
	220	);	220	apbo : OUT apb_slv_out_type;
	221	END COMPONENT;	221	ahbi : IN AHB_Mst_In_Type;
	222		222	ahbo : OUT AHB_Mst_Out_Type;
	223	-----------------------------------------------------------------------------	223	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	224	-- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)	224	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	225	-----------------------------------------------------------------------------	225	data_shaping_BW : OUT STD_LOGIC;
	226	COMPONENT lpp_lfr_WFP_nMS	226	debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
	227	GENERIC (	227	debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
	228	Mem_use : INTEGER;	228	);
	229	nb_data_by_buffer_size : INTEGER;	229	END COMPONENT;
	230	nb_word_by_buffer_size : INTEGER;	230
	231	nb_snapshot_param_size : INTEGER;	231	-----------------------------------------------------------------------------
	232	delta_vector_size : INTEGER;	232	-- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
	233	delta_vector_size_f0_2 : INTEGER;	233	-----------------------------------------------------------------------------
	234	pindex : INTEGER;	234	COMPONENT lpp_lfr_WFP_nMS
	235	paddr : INTEGER;	235	GENERIC (
	236	~~pmask~~ : INTEGER;	236	Mem_use : INTEGER;
	237	pirq_ms : INTEGER;	237	nb_data_by_buffer_size : INTEGER;
	238	pirq_wfp : INTEGER;	238	nb_word_by_buffer_size : INTEGER;
	239	hindex : INTEGER;	239	nb_snapshot_param_size : INTEGER;
	240	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));	240	delta_vector_size : INTEGER;
	241	PORT (	241	delta_vector_size_f0_2 : INTEGER;
	242	~~clk~~ : IN ~~STD_LOGIC~~;	242	pindex : INTEGER;
	243	~~rstn~~ : IN ~~STD_LOGIC~~;	243	paddr : INTEGER;
	244	sample_B : IN Samples(2 DOWNTO 0);	244	pmask : INTEGER;
	245	sample_E : IN Samples(4 DOWNTO 0);	245	pirq_ms : INTEGER;
	246	sample_val : IN STD_LOGIC;	246	pirq_wfp : INTEGER;
	247	apbi : IN apb_slv_in_type;	247	hindex : INTEGER;
	248	apbo : OUT apb_slv_out_type;	248	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
	249	ahbi : IN AHB_Mst_In_Type;	249	PORT (
	250	ahbo : OUT AHB_Mst_Out_Type;	250	clk : IN STD_LOGIC;
	251	~~coarse_time~~ : IN STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	251	rstn : IN STD_LOGIC;
	252	~~fine_time~~ : IN S~~TD_LOGIC_VECTOR~~(15 DOWNTO 0);	252	sample_B : IN Samples(2 DOWNTO 0);
	253	data_shaping_BW : OUT STD_LOGIC;	253	sample_E : IN Samples(4 DOWNTO 0);
	254	observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));	254	sample_val : IN STD_LOGIC;
	255	END COMPONENT;	255	apbi : IN apb_slv_in_type;
	256	-----------------------------------------------------------------------------	256	apbo : OUT apb_slv_out_type;
	257		257	ahbi : IN AHB_Mst_In_Type;
	258	COMPONENT lpp_lfr_apbreg	258	ahbo : OUT AHB_Mst_Out_Type;
	259	GENERIC (	259	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	260	nb_data_by_buffer_size : INTEGER;	260	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	261	nb_snapshot_param_size : INTEGER;	261	data_shaping_BW : OUT STD_LOGIC;
	262	delta_vector_size : INTEGER;	262	observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
	263	delta_vector_size_f0_2 : INTEGER;	263	END COMPONENT;
	264	pindex : INTEGER;	264	-----------------------------------------------------------------------------
	265	paddr : INTEGER;	265
	266	pmask : INTEGER;	266	COMPONENT lpp_lfr_apbreg
	267	pirq_ms : INTEGER;	267	GENERIC (
	268	pirq_wfp : INTEGER;	268	nb_data_by_buffer_size : INTEGER;
	269	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));	269	nb_snapshot_param_size : INTEGER;
	270	PORT (	270	delta_vector_size : INTEGER;
	271	HCLK : IN STD_ULOGIC;	271	delta_vector_size_f0_2 : INTEGER;
	272	~~HRESETn~~ : IN ~~STD_ULOGIC~~;	272	pindex : INTEGER;
	273	~~apbi~~ : IN ~~apb_slv_in_type~~;	273	paddr : INTEGER;
	274	~~apbo~~ : ~~OUT~~ ~~apb_slv_out_type~~;	274	pmask : INTEGER;
	275	~~run_ms~~ : ~~OUT~~ ~~STD_LOGIC~~;	275	pirq_ms : INTEGER;
	276	ready_matrix_f0 : IN STD_LOGIC;	276	pirq_wfp : INTEGER;
	277	ready_matrix_f1 : IN STD_LOGIC;	277	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
	278	ready_matrix_f2 : IN STD_LOGIC;	278	PORT (
	279	~~error_buffer_full~~ : IN STD_LOGIC;	279	HCLK : IN STD_ULOGIC;
	280	error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);	280	HRESETn : IN STD_ULOGIC;
	281	status_ready_matrix_f0 : OUT STD_LOGIC;	281	apbi : IN apb_slv_in_type;
	282	status_ready_matrix_f1 : OUT STD_LOGIC;	282	apbo : OUT apb_slv_out_type;
	283	status_ready_matrix_f2 : OUT STD_LOGIC;	283	run_ms : OUT STD_LOGIC;
	284	~~addr~~_matrix_f0 : ~~OUT~~ STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	284	ready_matrix_f0 : IN STD_LOGIC;
	285	~~addr~~_matrix_f1 : ~~OUT~~ STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	285	ready_matrix_f1 : IN STD_LOGIC;
	286	~~addr~~_matrix_f2 : ~~OUT~~ STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	286	ready_matrix_f2 : IN STD_LOGIC;
	287	length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);	287	error_buffer_full : IN STD_LOGIC;
	288	~~length_matrix_f1~~ : ~~OUT~~ STD_LOGIC_VECTOR(25 DOWNTO 0);	288	error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	289	~~length_matrix_f2~~ : OUT STD_LOGIC~~_VECTOR~~(25 ~~DOWNTO~~ 0);	289	status_ready_matrix_f0 : OUT STD_LOGIC;
	290	matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	290	status_ready_matrix_f1 : OUT STD_LOGIC;
	291	matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	291	status_ready_matrix_f2 : OUT STD_LOGIC;
	292	matrix_~~time_f2~~ : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	292	addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	293	~~status_new_err~~ : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	293	addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	294	~~data_shaping_BW~~ : OUT STD_LOGIC;	294	addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	295	~~data_shaping_SP~~0 : OUT STD_LOGIC;	295	length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
	296	~~data_shaping_SP~~1 : OUT STD_LOGIC;	296	length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
	297	data_shaping_R0 : OUT STD_LOGIC;	297	length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
	298	data_shaping_R1 : OUT STD_LOGIC;	298	matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	299	data_shaping_R2 : OUT STD_LOGIC;	299	matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	300	~~delta_snapshot~~ : ~~OUT~~ STD_LOGIC_VECTOR(~~delta_vector_size~~-1 DOWNTO 0);	300	matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	301	~~delta_f0~~ : ~~OUT~~ STD_LOGIC_VECTOR(~~delta_vector_size~~-1 DOWNTO 0);	301	status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	302	delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);	302	data_shaping_BW : OUT STD_LOGIC;
	303	delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	303	data_shaping_SP0 : OUT STD_LOGIC;
	304	delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	304	data_shaping_SP1 : OUT STD_LOGIC;
	305	nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);	305	data_shaping_R0 : OUT STD_LOGIC;
	306	nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);	306	data_shaping_R1 : OUT STD_LOGIC;
	307	~~enable_f0~~ : OUT STD_LOGIC;	307	data_shaping_R2 : OUT STD_LOGIC;
	308	enable_f1 : OUT STD_LOGIC;	308	delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	309	~~enable_f2~~ : OUT STD_LOGIC;	309	delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	310	enable_f3 : OUT STD_LOGIC;	310	delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
	311	~~burst_f0~~ : OUT STD_LOGIC;	311	delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	312	~~burst_f1~~ : OUT STD_LOGIC;	312	delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	313	burst_f2 : OUT STD_LOGIC;	313	nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
	314	run : OUT STD_LOGIC;	314	nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
	315	~~start_date~~ : OUT STD_LOGIC~~_VECTOR~~(30 ~~DOWNTO~~ 0);	315	enable_f0 : OUT STD_LOGIC;
	316	wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	316	enable_f1 : OUT STD_LOGIC;
	317	wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);	317	enable_f2 : OUT STD_LOGIC;
	318	wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);	318	enable_f3 : OUT STD_LOGIC;
	319	wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	319	burst_f0 : OUT STD_LOGIC;
	320	wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);	320	burst_f1 : OUT STD_LOGIC;
	321	wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	321	burst_f2 : OUT STD_LOGIC;
	322	sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);	322	run : OUT STD_LOGIC;
	323	s~~ample_f3_e1~~ : IN STD_LOGIC_VECTOR(15 DOWNTO 0);	323	start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
	324	~~sample_f3_e2~~ : IN STD_LOGIC_VECTOR(15 DOWNTO 0);	324	wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	325	sample_f3_valid : IN STD_LOGIC;	325	wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
	326	~~debug_vector~~ : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));	326	wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
	327	END COMPONENT;	327	wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	328		328	wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
	329	COMPONENT lpp_top_ms	329	wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	330	GENERIC (	330	sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	331	Mem_use : INTEGER;	331	sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	332	nb_burst_available_size : INTEGER;	332	sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	333	nb_snapshot_param_size : INTEGER;	333	sample_f3_valid : IN STD_LOGIC;
	334	delta_snapshot_size : INTEGER;	334	debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
	335	delta_f2_f0_size : INTEGER;	335	END COMPONENT;
	336	delta_f2_f1_size : INTEGER;	336
	337	pindex : INTEGER;	337	COMPONENT lpp_top_ms
	338	paddr : INTEGER;	338	GENERIC (
	339	~~pmask~~ : INTEGER;	339	Mem_use : INTEGER;
	340	pirq_ms : INTEGER;	340	nb_burst_available_size : INTEGER;
	341	pirq_wfp : INTEGER;	341	nb_snapshot_param_size : INTEGER;
	342	~~hindex_wfp~~ : INTEGER;	342	delta_snapshot_size : INTEGER;
	343	~~hindex_ms~~ : INTEGER);	343	delta_f2_f0_size : INTEGER;
	344	PORT (	344	delta_f2_f1_size : INTEGER;
	345	~~clk~~ : IN ~~STD_LOGIC~~;	345	pindex : INTEGER;
	346	~~rstn~~ : IN ~~STD_LOGIC~~;	346	paddr : INTEGER;
	347	sample_B : IN Samples14v(2 DOWNTO 0);	347	pmask : INTEGER;
	348	sample_E : IN Samples14v(4 DOWNTO 0);	348	pirq_ms : INTEGER;
	349	sample_val : IN STD_LOGIC;	349	pirq_wfp : INTEGER;
	350	apbi : IN apb_slv_in_type;	350	hindex_wfp : INTEGER;
	351	apbo : OUT apb_slv_out_type;	351	hindex_ms : INTEGER);
	352	ahbi_ms : IN AHB_Mst_In_Type;	352	PORT (
	353	ahbo_ms : OUT AHB_Mst_Out_Type;	353	clk : IN STD_LOGIC;
	354	data_shaping_BW : OUT STD_LOGIC;	354	rstn : IN STD_LOGIC;
	355	matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	355	sample_B : IN Samples14v(2 DOWNTO 0);
	356	matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	356	sample_E : IN Samples14v(4 DOWNTO 0);
	357	matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	357	sample_val : IN STD_LOGIC;
	358	matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)	358	apbi : IN apb_slv_in_type;
	359	);	359	apbo : OUT apb_slv_out_type;
	360	END COMPONENT;	360	ahbi_ms : IN AHB_Mst_In_Type;
	361		361	ahbo_ms : OUT AHB_Mst_Out_Type;
	362	COMPONENT lpp_apbreg_ms_pointer	362	data_shaping_BW : OUT STD_LOGIC;
	363	PORT (	363	matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	364	clk : IN STD_LOGIC;	364	matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	365	rstn : IN STD_LOGIC;	365	matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	366	run : IN STD_LOGIC;	366	matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
	367	reg0_status_ready_matrix : IN STD_LOGIC;	367	);
	368	reg0_ready_matrix : OUT STD_LOGIC;	368	END COMPONENT;
	369	reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	369
	370	reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	370	COMPONENT lpp_apbreg_ms_pointer
	371	reg1_status_ready_matrix : IN STD_LOGIC;	371	PORT (
	372	reg1_ready_matrix : OUT STD_LOGIC;	372	clk : IN STD_LOGIC;
	373	reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	373	rstn : IN STD_LOGIC;
	374	reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	374	run : IN STD_LOGIC;
	375	ready_matrix : IN STD_LOGIC;	375	reg0_status_ready_matrix : IN STD_LOGIC;
	376	~~status~~_ready_matrix : OUT STD_LOGIC;	376	reg0_ready_matrix : OUT STD_LOGIC;
	377	addr_matrix : ~~OUT~~ STD_LOGIC_VECTOR(31 DOWNTO 0);	377	reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	378	matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));	378	reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	379	END COMPONENT;	379	reg1_status_ready_matrix : IN STD_LOGIC;
	380		380	reg1_ready_matrix : OUT STD_LOGIC;
	381	COMPONENT lpp_lfr_ms_reg_head	381	reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	382	PORT (	382	reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	383	~~clk~~ : IN STD_LOGIC;	383	ready_matrix : IN STD_LOGIC;
	384	~~rstn~~ : IN STD_LOGIC;	384	status_ready_matrix : OUT STD_LOGIC;
	385	in_wen : IN STD_LOGIC;	385	addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	386	~~in_data~~ : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);	386	matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
	387	in_full : IN STD_LOGIC;	387	END COMPONENT;
	388	in_empty : IN STD_LOGIC;	388
	389	out_write_error : OUT STD_LOGIC;	389	COMPONENT lpp_lfr_ms_reg_head
	390	out_wen : OUT STD_LOGIC;	390	PORT (
	391	out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);	391	clk : IN STD_LOGIC;
	392	~~out_full~~ : ~~OUT~~ STD_LOGIC);	392	rstn : IN STD_LOGIC;
	393	END COMPONENT;	393	in_wen : IN STD_LOGIC;
	394		394	in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
	395	END lpp_lfr_pkg;	395	in_full : IN STD_LOGIC;
			396	in_empty : IN STD_LOGIC;
			397	out_write_error : OUT STD_LOGIC;
			398	out_wen : OUT STD_LOGIC;
			399	out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
			400	out_full : OUT STD_LOGIC);
			401	END COMPONENT;
			402
			403	END lpp_lfr_pkg; No newline at end of file

lib/lpp/lpp_waveform/lpp_waveform.vhd +12 -5

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY lpp;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_waveform IS
               GENERIC (
                 tech                   : INTEGER := inferred;
                 data_size              : INTEGER := 96;  --16*6
                 nb_data_by_buffer_size : INTEGER := 11;
             --    nb_word_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 3);
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 ---- AMBA AHB Master Interface
                 --AHB_Master_In  : IN  AHB_Mst_In_Type;   -- TODO
                 --AHB_Master_Out : OUT AHB_Mst_Out_Type;  -- TODO
                 --config
                 reg_run            : IN STD_LOGIC;
                 reg_start_date     : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
                 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 reg_delta_f0       : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 reg_delta_f0_2     : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                 reg_delta_f1       : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 reg_delta_f2       : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 enable_f0 : IN STD_LOGIC;
                 enable_f1 : IN STD_LOGIC;
                 enable_f2 : IN STD_LOGIC;
                 enable_f3 : IN STD_LOGIC;
                 burst_f0 : IN STD_LOGIC;
                 burst_f1 : IN STD_LOGIC;
                 burst_f2 : IN STD_LOGIC;
                 nb_data_by_buffer : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
             --    nb_word_by_buffer : IN  STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                 nb_snapshot_param : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                 status_new_err    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  -- New data f(i) before the current data is write by dma
                 -- REG DMA
                 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                 addr_buffer         : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                 length_buffer       : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
                 ready_buffer        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 buffer_time         : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
                 error_buffer_full   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- INPUT
                 coarse_time       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                fine_time         : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+            --    fine_time         : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                 --f0
                 data_f0_in_valid : IN STD_LOGIC;
                 data_f0_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                data_f0_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --f1
                 data_f1_in_valid : IN STD_LOGIC;
                 data_f1_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                data_f1_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --f2
                 data_f2_in_valid : IN STD_LOGIC;
                 data_f2_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                data_f2_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --f3
                 data_f3_in_valid : IN STD_LOGIC;
                 data_f3_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                data_f3_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA --------------------------------------------------------------------
                 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 dma_fifo_data        : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                 dma_fifo_ren         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 dma_buffer_new       : OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 dma_buffer_addr      : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                 dma_buffer_length    : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
                 dma_buffer_full      : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 dma_buffer_full_err  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0)
                 );
             END lpp_waveform;
             ARCHITECTURE beh OF lpp_waveform IS
               SIGNAL start_snapshot_f0 : STD_LOGIC;
               SIGNAL start_snapshot_f1 : STD_LOGIC;
               SIGNAL start_snapshot_f2 : STD_LOGIC;
               SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f0_out_valid          : STD_LOGIC;
               SIGNAL data_f1_out_valid          : STD_LOGIC;
               SIGNAL data_f2_out_valid          : STD_LOGIC;
               SIGNAL data_f3_out_valid          : STD_LOGIC;
               SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
               --
               SIGNAL valid_in                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL valid_out                  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL valid_ack                  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_ready                 : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL data_ready                 : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL ready_arb                  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL data_wen                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_wen                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wdata                      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL full_almost                : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL full                       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL empty_almost               : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL empty                      : STD_LOGIC_VECTOR(3 DOWNTO 0);
               --
               SIGNAL data_ren                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_ren                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL rdata                      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL enable                     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               --
               SIGNAL run                        : STD_LOGIC;
               --
               TYPE   TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL data_out                   : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
               SIGNAL time_out_2                 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
               SIGNAL time_out                   : TIME_VECTOR(3 DOWNTO 0);
               SIGNAL time_out_debug             : TIME_VECTOR(3 DOWNTO 0);  -- TODO : debug
-              SIGNAL time_reg1                  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL time_reg1                  : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
-              SIGNAL time_reg2                  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL time_reg2                  : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               --
               SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);  --occupancy is lesser than 16 * 32b
               SIGNAL s_empty        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL s_data_ren     : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL s_rdata        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL s_rdata_v        : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               --
               SIGNAL arbiter_time_out      : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL arbiter_time_out_new  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
                 GENERIC MAP (
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk                => clk,
                   rstn               => rstn,
                   reg_run            => reg_run,
                   reg_start_date     => reg_start_date,
                   reg_delta_snapshot => reg_delta_snapshot,
                   reg_delta_f0       => reg_delta_f0,
                   reg_delta_f0_2     => reg_delta_f0_2,
                   reg_delta_f1       => reg_delta_f1,
                   reg_delta_f2       => reg_delta_f2,
                   coarse_time        => coarse_time(30 DOWNTO 0),
                   data_f0_valid      => data_f0_in_valid,
                   data_f2_valid      => data_f2_in_valid,
                   start_snapshot_f0  => start_snapshot_f0,
                   start_snapshot_f1  => start_snapshot_f1,
                   start_snapshot_f2  => start_snapshot_f2,
                   wfp_on             => run);
               lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
                 GENERIC MAP (
                   data_size              => data_size,
                   nb_snapshot_param_size => nb_snapshot_param_size)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   enable            => enable_f0,
                   burst_enable      => burst_f0,
                   nb_snapshot_param => nb_snapshot_param,
                   start_snapshot    => start_snapshot_f0,
                   data_in           => data_f0_in,
                   data_in_valid     => data_f0_in_valid,
                   data_out          => data_f0_out,
                   data_out_valid    => data_f0_out_valid);
               nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
               lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
                 GENERIC MAP (
                   data_size              => data_size,
                   nb_snapshot_param_size => nb_snapshot_param_size+1)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   enable            => enable_f1,
                   burst_enable      => burst_f1,
                   nb_snapshot_param => nb_snapshot_param_more_one,
                   start_snapshot    => start_snapshot_f1,
                   data_in           => data_f1_in,
                   data_in_valid     => data_f1_in_valid,
                   data_out          => data_f1_out,
                   data_out_valid    => data_f1_out_valid);
               lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
                 GENERIC MAP (
                   data_size              => data_size,
                   nb_snapshot_param_size => nb_snapshot_param_size+1)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   enable            => enable_f2,
                   burst_enable      => burst_f2,
                   nb_snapshot_param => nb_snapshot_param_more_one,
                   start_snapshot    => start_snapshot_f2,
                   data_in           => data_f2_in,
                   data_in_valid     => data_f2_in_valid,
                   data_out          => data_f2_out,
                   data_out_valid    => data_f2_out_valid);
               lpp_waveform_burst_f3 : lpp_waveform_burst
                 GENERIC MAP (
                   data_size => data_size)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   run            => run,
                   enable         => enable_f3,
                   data_in        => data_f3_in,
                   data_in_valid  => data_f3_in_valid,
                   data_out       => data_f3_out,
                   data_out_valid => data_f3_out_valid);
               -----------------------------------------------------------------------------
               -- DEBUG -- SNAPSHOT OUT
               --debug_f0_data_valid <= data_f0_out_valid;
               --debug_f0_data       <= data_f0_out;
               --debug_f1_data_valid <= data_f1_out_valid;
               --debug_f1_data       <= data_f1_out;
               --debug_f2_data_valid <= data_f2_out_valid;
               --debug_f2_data       <= data_f2_out;
               --debug_f3_data_valid <= data_f3_out_valid;
               --debug_f3_data       <= data_f3_out;
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   time_reg1 <= (OTHERS => '0');
                   time_reg2 <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-                  time_reg1 <= fine_time & coarse_time;
+                  time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);
+                  time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);
+                  time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);
+                  time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);
                   time_reg2 <= time_reg1;
                 END IF;
               END PROCESS;
               valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
               all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
                 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
                   PORT MAP (
                     HCLK      => clk,
                     HRESETn   => rstn,
                     run       => run,
                     valid_in  => valid_in(I),
                     ack_in    => valid_ack(I),
-                    time_in   => time_reg2,         -- Todo
+                    time_in   => time_reg2(48*(I+1)-1 DOWNTO 48*I),         -- Todo
                     valid_out => valid_out(I),
                     time_out  => time_out(I),       -- Todo
                     error     => status_new_err(I));
               END GENERATE all_input_valid;
               data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
                                   data_f0_out((16*6)-1 DOWNTO 16*5) &
                                   data_f0_out((16*3)-1 DOWNTO 16*2) &
                                   data_f0_out((16*4)-1 DOWNTO 16*3) &
                                   data_f0_out((16*1)-1 DOWNTO 16*0) &
                                   data_f0_out((16*2)-1 DOWNTO 16*1) ;
               data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
                                   data_f1_out((16*6)-1 DOWNTO 16*5) &
                                   data_f1_out((16*3)-1 DOWNTO 16*2) &
                                   data_f1_out((16*4)-1 DOWNTO 16*3) &
                                   data_f1_out((16*1)-1 DOWNTO 16*0) &
                                   data_f1_out((16*2)-1 DOWNTO 16*1) ;
               data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
                                   data_f2_out((16*6)-1 DOWNTO 16*5) &
                                   data_f2_out((16*3)-1 DOWNTO 16*2) &
                                   data_f2_out((16*4)-1 DOWNTO 16*3) &
                                   data_f2_out((16*1)-1 DOWNTO 16*0) &
                                   data_f2_out((16*2)-1 DOWNTO 16*1) ;
               data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
                                   data_f3_out((16*6)-1 DOWNTO 16*5) &
                                   data_f3_out((16*3)-1 DOWNTO 16*2) &
                                   data_f3_out((16*4)-1 DOWNTO 16*3) &
                                   data_f3_out((16*1)-1 DOWNTO 16*0) &
                                   data_f3_out((16*2)-1 DOWNTO 16*1) ;
               all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
                 data_out(0, I) <= data_f0_out_swap(I);
                 data_out(1, I) <= data_f1_out_swap(I);
                 data_out(2, I) <= data_f2_out_swap(I);
                 data_out(3, I) <= data_f3_out_swap(I);
               END GENERATE all_bit_of_data_out;
               -----------------------------------------------------------------------------
               -- TODO : debug
               -----------------------------------------------------------------------------
               all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
                 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
                   time_out_2(J, I) <= time_out(J)(I);
                 END GENERATE all_sample_of_time_out;
               END GENERATE all_bit_of_time_out;
               lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
                 GENERIC MAP (tech                   => tech,
                              nb_data_by_buffer_size => nb_data_by_buffer_size)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   nb_data_by_buffer => nb_data_by_buffer,
                   data_in_valid     => valid_out,
                   data_in_ack       => valid_ack,
                   data_in           => data_out,
                   time_in           => time_out_2,
                   data_out     => wdata,
                   data_out_wen => data_wen,
                   full_almost  => full_almost,
                   full         => full,
                   time_out          => arbiter_time_out,
                   time_out_new      => arbiter_time_out_new
                   );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               generate_all_fifo: FOR I IN 0 TO 3 GENERATE
                 lpp_fifo_1: lpp_fifo
                   GENERIC MAP (
                     tech                  => tech,
                     Mem_use               => use_RAM,
                     EMPTY_THRESHOLD_LIMIT => 15,
                     FULL_THRESHOLD_LIMIT  => 3,
                     DataSz                => 32,
                     AddrSz                => 7)
                   PORT MAP (
                     clk             => clk,
                     rstn            => rstn,
                     reUse           => '0',
                     run             => run,
                     ren             => data_ren(I),
                     rdata           => s_rdata_v((I+1)*32-1 downto I*32),
                     wen             => data_wen(I),
                     wdata           => wdata,
                     empty           => empty(I),
                     full            => full(I),
                     full_almost     => OPEN,
                     empty_threshold => empty_almost(I),
                     full_threshold  => full_almost(I) );
               END GENERATE generate_all_fifo;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               all_channel: FOR I IN 3 DOWNTO 0 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
                   ELSIF clk'event AND clk = '1' THEN
                     IF run = '0' THEN
                       fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
                     ELSE
                       IF arbiter_time_out_new(I) = '1' THEN  -- modif JC 15-01-2015
                         fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
                       END IF;
                     END IF;
                   END IF;
                 END PROCESS;
                 fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
                                                               fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
                 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
                   PORT MAP (
                     clk                  => clk,
                     rstn                 => rstn,
                     run                  => run,
                     fifo_buffer_time     => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I),
                     fifo_data            => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
                     fifo_empty           => empty(I),
                     fifo_empty_threshold => empty_almost(I),
                     fifo_ren             => data_ren(I),
                     dma_fifo_valid_burst => dma_fifo_valid_burst(I),
                     dma_fifo_data        => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
                     dma_fifo_ren         => dma_fifo_ren(I),
                     dma_buffer_new       => dma_buffer_new(I),
                     dma_buffer_addr      => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
                     dma_buffer_length    => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
                     dma_buffer_full      => dma_buffer_full(I),
                     dma_buffer_full_err  => dma_buffer_full_err(I),
                     status_buffer_ready  => status_buffer_ready(I),                 -- TODO
                     addr_buffer          => addr_buffer(32*(I+1)-1 DOWNTO 32*I),    -- TODO
                     length_buffer        => length_buffer,--(26*(I+1)-1 DOWNTO 26*I),  -- TODO
                     ready_buffer         => ready_buffer(I),                        -- TODO
                     buffer_time          => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I),    -- TODO
                     error_buffer_full    => error_buffer_full(I));                  -- TODO
                 buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
               END GENERATE all_channel;
             END beh;

lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +5 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             PACKAGE lpp_waveform_pkg IS
               TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
               TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
               -----------------------------------------------------------------------------
               -- SNAPSHOT
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform_snapshot
                 GENERIC (
                   data_size              : INTEGER;
                   nb_snapshot_param_size : INTEGER);
                 PORT (
                   clk               : IN  STD_LOGIC;
                   rstn              : IN  STD_LOGIC;
                   run               : IN  STD_LOGIC;
                   enable            : IN  STD_LOGIC;
                   burst_enable      : IN  STD_LOGIC;
                   nb_snapshot_param : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   start_snapshot    : IN  STD_LOGIC;
                   data_in           : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_in_valid     : IN  STD_LOGIC;
                   data_out          : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_out_valid    : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_waveform_burst
                 GENERIC (
                   data_size : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   run            : IN  STD_LOGIC;
                   enable         : IN  STD_LOGIC;
                   data_in        : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_in_valid  : IN  STD_LOGIC;
                   data_out       : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_out_valid : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_waveform_snapshot_controler
                 GENERIC (
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER);
                 PORT (
                   clk                : IN  STD_LOGIC;
                   rstn               : IN  STD_LOGIC;
                   reg_run            : IN  STD_LOGIC;
                   reg_start_date     : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   reg_delta_snapshot : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0       : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0_2     : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f1       : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f2       : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   coarse_time        : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   data_f0_valid      : IN  STD_LOGIC;
                   data_f2_valid      : IN  STD_LOGIC;
                   start_snapshot_f0  : OUT STD_LOGIC;
                   start_snapshot_f1  : OUT STD_LOGIC;
                   start_snapshot_f2  : OUT STD_LOGIC;
                   wfp_on             : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform
                 GENERIC (
                   tech                   : INTEGER;
                   data_size              : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER);
                 PORT (
                   clk                          : IN  STD_LOGIC;
                   rstn                         : IN  STD_LOGIC;
                   reg_run                      : IN  STD_LOGIC;
                   reg_start_date               : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   reg_delta_snapshot           : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0                 : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0_2               : IN  STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                   reg_delta_f1                 : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f2                 : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   enable_f0                    : IN  STD_LOGIC;
                   enable_f1                    : IN  STD_LOGIC;
                   enable_f2                    : IN  STD_LOGIC;
                   enable_f3                    : IN  STD_LOGIC;
                   burst_f0                     : IN  STD_LOGIC;
                   burst_f1                     : IN  STD_LOGIC;
                   burst_f2                     : IN  STD_LOGIC;
                   nb_data_by_buffer            : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   nb_snapshot_param            : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   status_new_err               : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                   addr_buffer         : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   length_buffer       : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
                   ready_buffer        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   buffer_time         : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
                   error_buffer_full   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   coarse_time                  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  fine_time                    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  --fine_time                    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_f0_in_valid             : IN  STD_LOGIC;
                   data_f0_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                  data_f0_time                 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   data_f1_in_valid             : IN  STD_LOGIC;
                   data_f1_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                  data_f1_time                 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   data_f2_in_valid             : IN  STD_LOGIC;
                   data_f2_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                  data_f2_time                 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   data_f3_in_valid             : IN  STD_LOGIC;
                   data_f3_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+                  data_f3_time                 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   dma_fifo_data        : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   dma_fifo_ren         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   dma_buffer_new       : OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   dma_buffer_addr      : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   dma_buffer_length    : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
                   dma_buffer_full      : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   dma_buffer_full_err  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_waveform_dma_genvalid
                 PORT (
                   HCLK      : IN  STD_LOGIC;
                   HRESETn   : IN  STD_LOGIC;
                   run       : IN  STD_LOGIC;
                   valid_in  : IN  STD_LOGIC;
                   ack_in    : IN  STD_LOGIC;
                   time_in   : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   valid_out : OUT STD_LOGIC;
                   time_out  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   error     : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- FIFO
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform_fifo_ctrl
                 GENERIC (
                   offset : INTEGER;
                   length : INTEGER);
                 PORT (
                   clk          : IN  STD_LOGIC;
                   rstn         : IN  STD_LOGIC;
                   run          : IN  STD_LOGIC;
                   ren          : IN  STD_LOGIC;
                   wen          : IN  STD_LOGIC;
                   mem_re       : OUT STD_LOGIC;
                   mem_we       : OUT STD_LOGIC;
                   mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
                   mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
                   empty_almost : OUT STD_LOGIC;
                   empty        : OUT STD_LOGIC;
                   full_almost  : OUT STD_LOGIC;
                   full         : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_waveform_fifo_arbiter
                 GENERIC (
                   tech                   : INTEGER;
                   nb_data_by_buffer_size : INTEGER);
                 PORT (
                   clk               : IN  STD_LOGIC;
                   rstn              : IN  STD_LOGIC;
                   run               : IN  STD_LOGIC;
                   nb_data_by_buffer : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
                   data_in_valid     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_in_ack       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_in           : IN  Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
                   time_in           : IN  Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
                   data_out          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_out_wen      : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   full_almost       : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   full              : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   time_out     : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_waveform_fifo
                 GENERIC (
                   tech : INTEGER);
                 PORT (
                   clk          : IN  STD_LOGIC;
                   rstn         : IN  STD_LOGIC;
                   run          : IN  STD_LOGIC;
                   empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   empty        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_ren     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   rdata        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   full_almost  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   full         : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_wen     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   wdata        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_waveform_fifo_headreg
                 GENERIC (
                   tech : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   run            : IN  STD_LOGIC;
                   o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   o_empty        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   o_data_ren     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   o_rdata_0      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   o_rdata_1      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   o_rdata_2      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   o_rdata_3      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   i_empty_almost : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   i_empty        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   i_data_ren     : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   i_rdata        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_waveform_fifo_latencyCorrection
                 GENERIC (
                   tech : INTEGER);
                 PORT (
                   clk               : IN  STD_LOGIC;
                   rstn              : IN  STD_LOGIC;
                   run               : IN  STD_LOGIC;
                   empty_almost      : OUT STD_LOGIC;
                   empty             : OUT STD_LOGIC;
                   data_ren          : IN  STD_LOGIC;
                   rdata             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   empty_almost_fifo : IN  STD_LOGIC;
                   empty_fifo        : IN  STD_LOGIC;
                   data_ren_fifo     : OUT STD_LOGIC;
                   rdata_fifo        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_waveform_fifo_withoutLatency
                 GENERIC (
                   tech : INTEGER);
                 PORT (
                   clk          : IN  STD_LOGIC;
                   rstn         : IN  STD_LOGIC;
                   run          : IN  STD_LOGIC;
                   empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   empty        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_ren     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   rdata_0      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   rdata_1      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   rdata_2      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   rdata_3      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   full_almost  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   full         : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_wen     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   wdata        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- GEN ADDRESS
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform_genaddress
                 GENERIC (
                   nb_data_by_buffer_size : INTEGER);
                 PORT (
                   clk                          : IN  STD_LOGIC;
                   rstn                         : IN  STD_LOGIC;
                   run                          : IN  STD_LOGIC;
                   nb_data_by_buffer            : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   addr_data_f0                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   empty                        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   empty_almost                 : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_ren                     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full                  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack              : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err              : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_f0_data_out_valid_burst : OUT STD_LOGIC;
                   data_f1_data_out_valid_burst : OUT STD_LOGIC;
                   data_f2_data_out_valid_burst : OUT STD_LOGIC;
                   data_f3_data_out_valid_burst : OUT STD_LOGIC;
                   data_f0_data_out_valid       : OUT STD_LOGIC;
                   data_f1_data_out_valid       : OUT STD_LOGIC;
                   data_f2_data_out_valid       : OUT STD_LOGIC;
                   data_f3_data_out_valid       : OUT STD_LOGIC;
                   data_f0_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f1_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f2_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f3_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- lpp_waveform_fifo_arbiter_reg
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform_fifo_arbiter_reg
                 GENERIC (
                   data_size : INTEGER;
                   data_nb   : INTEGER);
                 PORT (
                   clk       : IN  STD_LOGIC;
                   rstn      : IN  STD_LOGIC;
                   run       : IN  STD_LOGIC;
                   max_count : IN  STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
                   enable    : IN  STD_LOGIC;
                   sel       : IN  STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
                   data      : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_s    : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_waveform_fsmdma
                 PORT (
                   clk                  : IN  STD_ULOGIC;
                   rstn                 : IN  STD_ULOGIC;
                   run                  : IN  STD_LOGIC;
                   fifo_buffer_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   fifo_data            : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty           : IN  STD_LOGIC;
                   fifo_empty_threshold : IN  STD_LOGIC;
                   fifo_ren             : OUT STD_LOGIC;
                   dma_fifo_valid_burst : OUT STD_LOGIC;
                   dma_fifo_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_fifo_ren         : IN  STD_LOGIC;
                   dma_buffer_new       : OUT STD_LOGIC;
                   dma_buffer_addr      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_buffer_length    : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   dma_buffer_full      : IN  STD_LOGIC;
                   dma_buffer_full_err  : IN  STD_LOGIC;
                   status_buffer_ready  : IN  STD_LOGIC;
                   addr_buffer          : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   length_buffer        : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   ready_buffer         : OUT STD_LOGIC;
                   buffer_time          : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   error_buffer_full    : OUT STD_LOGIC);
               END COMPONENT;
             END lpp_waveform_pkg;

General Comments 0

Write
Preview

You need to be logged in to leave comments. Login now

No TODOs yet

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages