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Update methodology of data dating into LFR
pellion -
r527:32bdf5e8de1b (MINI-LFR) WFP_MS-0-1-59 (LFR-EM) WFP_MS_1-1-59 JC
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@@ -380,7 +380,7 BEGIN -- beh
380 380 pirq_ms => 6,
381 381 pirq_wfp => 14,
382 382 hindex => 2,
383 top_lfr_version => X"010139") -- aa.bb.cc version
383 top_lfr_version => X"01013A") -- aa.bb.cc version
384 384 -- AA : BOARD NUMBER
385 385 -- 0 => MINI_LFR
386 386 -- 1 => EM
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@@ -342,7 +342,7 BEGIN -- beh
342 342 dbguart => 0,
343 343 pclow => 2,
344 344 clk_freq => 25000,
345 IS_RADHARD => 1,
345 IS_RADHARD => 0,
346 346 NB_CPU => 1,
347 347 ENABLE_FPU => 1,
348 348 FPU_NETLIST => 0,
@@ -517,7 +517,7 BEGIN -- beh
517 517 pirq_ms => 6,
518 518 pirq_wfp => 14,
519 519 hindex => 2,
520 top_lfr_version => X"000138") -- aa.bb.cc version
520 top_lfr_version => X"00013A") -- aa.bb.cc version
521 521 PORT MAP (
522 522 clk => clk_25,
523 523 rstn => LFR_rstn,
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@@ -75,8 +75,6 ARCHITECTURE beh OF cic_lfr_r2 IS
75 75 --
76 76 CONSTANT S_parameter : INTEGER := 3;
77 77 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
78 SIGNAL CARRY_PUSH : STD_LOGIC;
79 SIGNAL CARRY_POP : STD_LOGIC;
80 78 --
81 79
82 80 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -397,4 +395,3 BEGIN
397 395 END GENERATE all_channel_out_v;
398 396
399 397 END beh;
400
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@@ -115,9 +115,6 ARCHITECTURE Behavioral OF apb_lfr_manag
115 115 SIGNAL soft_reset : STD_LOGIC;
116 116 SIGNAL soft_reset_sync : STD_LOGIC;
117 117 -----------------------------------------------------------------------------
118 SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 118 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 119
123 120 SIGNAL previous_fine_time_bit : STD_LOGIC;
@@ -360,9 +357,13 BEGIN
360 357 -----------------------------------------------------------------------------
361 358
362 359 PROCESS (clk25MHz, resetn)
363 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 11; -- freq = 2^(16-BIT)
364 -- for 11, the update frequency is 32Hz
360 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
365 361 -- for each HK, the update frequency is freq/3
362 --
363 -- for 14, the update frequency is
364 -- 4Hz and update for each
365 -- HK is 1.33Hz
366
366 367 BEGIN -- PROCESS
367 368 IF resetn = '0' THEN -- asynchronous reset (active low)
368 369
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@@ -228,7 +228,12 ARCHITECTURE beh OF lpp_lfr IS
228 228
229 229 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
230 230 -----------------------------------------------------------------------------
231 -- SIGNAL run_dma : STD_LOGIC;
231 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
236
232 237 BEGIN
233 238
234 239 debug_vector <= apb_reg_debug_vector;
@@ -236,7 +241,8 BEGIN
236 241
237 242 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
238 243 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
239
244 sample_time <= coarse_time & fine_time;
245
240 246 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
241 247 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
242 248 --END GENERATE all_channel;
@@ -248,6 +254,7 BEGIN
248 254 PORT MAP (
249 255 sample => sample_s,
250 256 sample_val => sample_val,
257 sample_time => sample_time,
251 258 clk => clk,
252 259 rstn => rstn,
253 260 data_shaping_SP0 => data_shaping_SP0,
@@ -262,7 +269,12 BEGIN
262 269 sample_f0_wdata => sample_f0_data,
263 270 sample_f1_wdata => sample_f1_data,
264 271 sample_f2_wdata => sample_f2_data,
265 sample_f3_wdata => sample_f3_data);
272 sample_f3_wdata => sample_f3_data,
273 sample_f0_time => sample_f0_time,
274 sample_f1_time => sample_f1_time,
275 sample_f2_time => sample_f2_time,
276 sample_f3_time => sample_f3_time
277 );
266 278
267 279 -----------------------------------------------------------------------------
268 280 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
@@ -393,20 +405,24 BEGIN
393 405 error_buffer_full => wfp_error_buffer_full,
394 406
395 407 coarse_time => coarse_time,
396 fine_time => fine_time,
408 -- fine_time => fine_time,
397 409
398 410 --f0
399 411 data_f0_in_valid => sample_f0_val,
400 412 data_f0_in => sample_f0_data,
413 data_f0_time => sample_f0_time,
401 414 --f1
402 415 data_f1_in_valid => sample_f1_val,
403 416 data_f1_in => sample_f1_data,
417 data_f1_time => sample_f1_time,
404 418 --f2
405 419 data_f2_in_valid => sample_f2_val,
406 420 data_f2_in => sample_f2_data,
421 data_f2_time => sample_f2_time,
407 422 --f3
408 423 data_f3_in_valid => sample_f3_val,
409 424 data_f3_in => sample_f3_data,
425 data_f3_time => sample_f3_time,
410 426 -- OUTPUT -- DMA interface
411 427
412 428 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
@@ -452,14 +468,16 BEGIN
452 468 start_date => start_date,
453 469
454 470 coarse_time => coarse_time,
455 fine_time => fine_time,
456 471
457 472 sample_f0_wen => sample_f0_wen,
458 473 sample_f0_wdata => sample_f0_wdata,
474 sample_f0_time => sample_f0_time,
459 475 sample_f1_wen => sample_f1_wen,
460 476 sample_f1_wdata => sample_f1_wdata,
477 sample_f1_time => sample_f1_time,
461 478 sample_f2_wen => sample_f2_wen,
462 479 sample_f2_wdata => sample_f2_wdata,
480 sample_f2_time => sample_f2_time,
463 481
464 482 --DMA
465 483 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
@@ -521,4 +539,4 BEGIN
521 539 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
522 540 grant_error => dma_grant_error); --grant_error);
523 541
524 END beh;
542 END beh; No newline at end of file
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@@ -50,6 +50,7 ENTITY lpp_lfr_filter IS
50 50 PORT (
51 51 sample : IN Samples(7 DOWNTO 0);
52 52 sample_val : IN STD_LOGIC;
53 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
53 54 --
54 55 clk : IN STD_LOGIC;
55 56 rstn : IN STD_LOGIC;
@@ -68,7 +69,12 ENTITY lpp_lfr_filter IS
68 69 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 70 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 71 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
72 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
73 --
74 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
75 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
72 78 );
73 79 END lpp_lfr_filter;
74 80
@@ -159,6 +165,9 ARCHITECTURE tb OF lpp_lfr_filter IS
159 165
160 166 SIGNAL sample_f0_val_s : STD_LOGIC;
161 167 SIGNAL sample_f1_val_s : STD_LOGIC;
168 SIGNAL sample_f1_val_ss : STD_LOGIC;
169 SIGNAL sample_f2_val_s : STD_LOGIC;
170 SIGNAL sample_f3_val_s : STD_LOGIC;
162 171
163 172 -----------------------------------------------------------------------------
164 173 -- CONFIG FILTER IIR f0 to f1
@@ -214,6 +223,16 ARCHITECTURE tb OF lpp_lfr_filter IS
214 223 f2_f3_gain);
215 224 -----------------------------------------------------------------------------
216 225
226 SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
227 SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
228 SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
229 SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 -- SIGNAL sample_f2_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 -- SIGNAL sample_f3_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
217 236
218 237 BEGIN
219 238
@@ -259,6 +278,24 BEGIN
259 278 sample_out_val => sample_filter_v2_out_val,
260 279 sample_out => sample_filter_v2_out);
261 280
281 -- TIME --
282 PROCESS (clk, rstn)
283 BEGIN -- PROCESS
284 IF rstn = '0' THEN -- asynchronous reset (active low)
285 sample_time_reg <= (OTHERS => '0');
286 sample_filter_v2_out_time <= (OTHERS => '0');
287 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
288 IF sample_val = '1' THEN
289 sample_time_reg <= sample_time;
290 END IF;
291 IF sample_filter_v2_out_val = '1' THEN
292 sample_filter_v2_out_time <= sample_time_reg;
293 END IF;
294 END IF;
295 END PROCESS;
296 ----------
297
298
262 299 -----------------------------------------------------------------------------
263 300 -- DATA_SHAPING
264 301 -----------------------------------------------------------------------------
@@ -336,6 +373,21 BEGIN
336 373 sample_out_val => sample_f0_val_s,
337 374 sample_out => sample_f0);
338 375
376 -- TIME --
377 PROCESS (clk, rstn)
378 BEGIN
379 IF rstn = '0' THEN
380 sample_f0_time_reg <= (OTHERS => '0');
381 ELSIF clk'event AND clk = '1' THEN
382 IF sample_f0_val_s = '1' THEN
383 sample_f0_time_reg <= sample_filter_v2_out_time;
384 END IF;
385 END IF;
386 END PROCESS;
387 sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg;
388 sample_f0_time <= sample_f0_time_s;
389 ----------
390
339 391 sample_f0_val <= sample_f0_val_s;
340 392
341 393 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
@@ -401,8 +453,26 BEGIN
401 453 rstn => rstn,
402 454 sample_in_val => sample_f1_val_s,
403 455 sample_in => sample_f1_s,
404 sample_out_val => sample_f1_val,
405 sample_out => sample_f1);
456 sample_out_val => sample_f1_val_ss,
457 sample_out => sample_f1);
458
459 sample_f1_val <= sample_f1_val_ss;
460
461 -- TIME --
462 PROCESS (clk, rstn)
463 BEGIN
464 IF rstn = '0' THEN
465 sample_f1_time_reg <= (OTHERS => '0');
466 ELSIF clk'event AND clk = '1' THEN
467 IF sample_f1_val_ss = '1' THEN
468 sample_f1_time_reg <= sample_f0_time_s;
469 END IF;
470 END IF;
471 END PROCESS;
472 sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg;
473 sample_f1_time <= sample_f1_time_s;
474 ----------
475
406 476
407 477 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
408 478 all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
@@ -509,8 +579,10 BEGIN
509 579 rstn => rstn,
510 580 sample_in_val => sample_f2_filter_val ,
511 581 sample_in => sample_f2_cic_s,
512 sample_out_val => sample_f2_val,
513 sample_out => sample_f2);
582 sample_out_val => sample_f2_val_s,
583 sample_out => sample_f2);
584
585 sample_f2_val <= sample_f2_val_s;
514 586
515 587 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
516 588 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
@@ -530,14 +602,32 BEGIN
530 602 rstn => rstn,
531 603 sample_in_val => sample_f3_filter_val ,
532 604 sample_in => sample_f3_cic_s,
533 sample_out_val => sample_f3_val,
605 sample_out_val => sample_f3_val_s,
534 606 sample_out => sample_f3);
607 sample_f3_val <= sample_f3_val_s;
535 608
536 609 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
537 610 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
538 611 sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
539 612 END GENERATE all_channel_sample_f3;
540 END GENERATE all_bit_sample_f3;
613 END GENERATE all_bit_sample_f3;
614
615 -----------------------------------------------------------------------------
616
617 -- TIME --
618 PROCESS (clk, rstn)
619 BEGIN
620 IF rstn = '0' THEN
621 sample_f2_time_reg <= (OTHERS => '0');
622 sample_f3_time_reg <= (OTHERS => '0');
623 ELSIF clk'event AND clk = '1' THEN
624 IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF;
625 IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF;
626 END IF;
627 END PROCESS;
628 sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg;
629 sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg;
630 ----------
541 631
542 632 -----------------------------------------------------------------------------
543 633 --
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@@ -28,18 +28,20 ENTITY lpp_lfr_ms IS
28 28 -- DATA INPUT
29 29 ---------------------------------------------------------------------------
30 30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 -- TIME
32 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
33 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
32 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
34 33 --
35 34 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 35 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
37 37 --
38 38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
40 41 --
41 42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
43 45
44 46 ---------------------------------------------------------------------------
45 47 -- DMA
@@ -217,7 +219,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
217 219 -----------------------------------------------------------------------------
218 220 -- TIME REG & INFOs
219 221 -----------------------------------------------------------------------------
220 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
222 SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
221 223
222 224 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
223 225 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -1173,7 +1175,8 BEGIN
1173 1175 -----------------------------------------------------------------------------
1174 1176 -- TIME MANAGMENT
1175 1177 -----------------------------------------------------------------------------
1176 all_time <= coarse_time & fine_time;
1178 all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
1179 --all_time <= coarse_time & fine_time;
1177 1180 --
1178 1181 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1179 1182 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
@@ -1197,7 +1200,7 BEGIN
1197 1200 PORT MAP (
1198 1201 clk => clk,
1199 1202 rstn => rstn,
1200 time_in => all_time,
1203 time_in => all_time((I+1)*48-1 DOWNTO I*48),
1201 1204 update_1 => time_update_f(I),
1202 1205 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1203 1206 );
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@@ -1,395 +1,403
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
14
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
17 -- TEMP
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
21 Mem_use : INTEGER);
22 PORT (
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
39
40
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
55 -----------------------------------------------------------------------------
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
65 );
66 END COMPONENT;
67
68
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
71 GENERIC (
72 Mem_use : INTEGER);
73 PORT (
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 run : IN STD_LOGIC;
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 dma_fifo_burst_valid : OUT STD_LOGIC;
87 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 dma_fifo_ren : IN STD_LOGIC;
89 dma_buffer_new : OUT STD_LOGIC;
90 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92 dma_buffer_full : IN STD_LOGIC;
93 dma_buffer_full_err : IN STD_LOGIC;
94 ready_matrix_f0 : OUT STD_LOGIC;
95 ready_matrix_f1 : OUT STD_LOGIC;
96 ready_matrix_f2 : OUT STD_LOGIC;
97 error_buffer_full : OUT STD_LOGIC;
98 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
99 status_ready_matrix_f0 : IN STD_LOGIC;
100 status_ready_matrix_f1 : IN STD_LOGIC;
101 status_ready_matrix_f2 : IN STD_LOGIC;
102 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
111 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
112 END COMPONENT;
113
114 COMPONENT lpp_lfr_ms_fsmdma
115 PORT (
116 clk : IN STD_ULOGIC;
117 rstn : IN STD_ULOGIC;
118 run : IN STD_LOGIC;
119 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
120 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
121 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
122 fifo_empty : IN STD_LOGIC;
123 fifo_empty_threshold : IN STD_LOGIC;
124 fifo_ren : OUT STD_LOGIC;
125 dma_fifo_valid_burst : OUT STD_LOGIC;
126 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 dma_fifo_ren : IN STD_LOGIC;
128 dma_buffer_new : OUT STD_LOGIC;
129 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
131 dma_buffer_full : IN STD_LOGIC;
132 dma_buffer_full_err : IN STD_LOGIC;
133 status_ready_matrix_f0 : IN STD_LOGIC;
134 status_ready_matrix_f1 : IN STD_LOGIC;
135 status_ready_matrix_f2 : IN STD_LOGIC;
136 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
141 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
142 ready_matrix_f0 : OUT STD_LOGIC;
143 ready_matrix_f1 : OUT STD_LOGIC;
144 ready_matrix_f2 : OUT STD_LOGIC;
145 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
147 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
148 error_buffer_full : OUT STD_LOGIC);
149 END COMPONENT;
150
151 COMPONENT lpp_lfr_ms_FFT
152 PORT (
153 clk : IN STD_LOGIC;
154 rstn : IN STD_LOGIC;
155 sample_valid : IN STD_LOGIC;
156 fft_read : IN STD_LOGIC;
157 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
158 sample_load : OUT STD_LOGIC;
159 fft_pong : OUT STD_LOGIC;
160 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
161 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
162 fft_data_valid : OUT STD_LOGIC;
163 fft_ready : OUT STD_LOGIC);
164 END COMPONENT;
165
166 COMPONENT lpp_lfr_filter
167 GENERIC (
168 Mem_use : INTEGER);
169 PORT (
170 sample : IN Samples(7 DOWNTO 0);
171 sample_val : IN STD_LOGIC;
172 clk : IN STD_LOGIC;
173 rstn : IN STD_LOGIC;
174 data_shaping_SP0 : IN STD_LOGIC;
175 data_shaping_SP1 : IN STD_LOGIC;
176 data_shaping_R0 : IN STD_LOGIC;
177 data_shaping_R1 : IN STD_LOGIC;
178 data_shaping_R2 : IN STD_LOGIC;
179 sample_f0_val : OUT STD_LOGIC;
180 sample_f1_val : OUT STD_LOGIC;
181 sample_f2_val : OUT STD_LOGIC;
182 sample_f3_val : OUT STD_LOGIC;
183 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
185 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
186 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
187 END COMPONENT;
188
189 COMPONENT lpp_lfr
190 GENERIC (
191 Mem_use : INTEGER;
192 nb_data_by_buffer_size : INTEGER;
193 -- nb_word_by_buffer_size : INTEGER;
194 nb_snapshot_param_size : INTEGER;
195 delta_vector_size : INTEGER;
196 delta_vector_size_f0_2 : INTEGER;
197 pindex : INTEGER;
198 paddr : INTEGER;
199 pmask : INTEGER;
200 pirq_ms : INTEGER;
201 pirq_wfp : INTEGER;
202 hindex : INTEGER;
203 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
204 );
205 PORT (
206 clk : IN STD_LOGIC;
207 rstn : IN STD_LOGIC;
208 sample_B : IN Samples(2 DOWNTO 0);
209 sample_E : IN Samples(4 DOWNTO 0);
210 sample_val : IN STD_LOGIC;
211 apbi : IN apb_slv_in_type;
212 apbo : OUT apb_slv_out_type;
213 ahbi : IN AHB_Mst_In_Type;
214 ahbo : OUT AHB_Mst_Out_Type;
215 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
217 data_shaping_BW : OUT STD_LOGIC ;
218 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
219 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
220 );
221 END COMPONENT;
222
223 -----------------------------------------------------------------------------
224 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
225 -----------------------------------------------------------------------------
226 COMPONENT lpp_lfr_WFP_nMS
227 GENERIC (
228 Mem_use : INTEGER;
229 nb_data_by_buffer_size : INTEGER;
230 nb_word_by_buffer_size : INTEGER;
231 nb_snapshot_param_size : INTEGER;
232 delta_vector_size : INTEGER;
233 delta_vector_size_f0_2 : INTEGER;
234 pindex : INTEGER;
235 paddr : INTEGER;
236 pmask : INTEGER;
237 pirq_ms : INTEGER;
238 pirq_wfp : INTEGER;
239 hindex : INTEGER;
240 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
241 PORT (
242 clk : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
244 sample_B : IN Samples(2 DOWNTO 0);
245 sample_E : IN Samples(4 DOWNTO 0);
246 sample_val : IN STD_LOGIC;
247 apbi : IN apb_slv_in_type;
248 apbo : OUT apb_slv_out_type;
249 ahbi : IN AHB_Mst_In_Type;
250 ahbo : OUT AHB_Mst_Out_Type;
251 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
252 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
253 data_shaping_BW : OUT STD_LOGIC;
254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
255 END COMPONENT;
256 -----------------------------------------------------------------------------
257
258 COMPONENT lpp_lfr_apbreg
259 GENERIC (
260 nb_data_by_buffer_size : INTEGER;
261 nb_snapshot_param_size : INTEGER;
262 delta_vector_size : INTEGER;
263 delta_vector_size_f0_2 : INTEGER;
264 pindex : INTEGER;
265 paddr : INTEGER;
266 pmask : INTEGER;
267 pirq_ms : INTEGER;
268 pirq_wfp : INTEGER;
269 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
270 PORT (
271 HCLK : IN STD_ULOGIC;
272 HRESETn : IN STD_ULOGIC;
273 apbi : IN apb_slv_in_type;
274 apbo : OUT apb_slv_out_type;
275 run_ms : OUT STD_LOGIC;
276 ready_matrix_f0 : IN STD_LOGIC;
277 ready_matrix_f1 : IN STD_LOGIC;
278 ready_matrix_f2 : IN STD_LOGIC;
279 error_buffer_full : IN STD_LOGIC;
280 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
281 status_ready_matrix_f0 : OUT STD_LOGIC;
282 status_ready_matrix_f1 : OUT STD_LOGIC;
283 status_ready_matrix_f2 : OUT STD_LOGIC;
284 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
287 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
288 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
289 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
290 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
291 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
292 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
293 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
294 data_shaping_BW : OUT STD_LOGIC;
295 data_shaping_SP0 : OUT STD_LOGIC;
296 data_shaping_SP1 : OUT STD_LOGIC;
297 data_shaping_R0 : OUT STD_LOGIC;
298 data_shaping_R1 : OUT STD_LOGIC;
299 data_shaping_R2 : OUT STD_LOGIC;
300 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
302 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
303 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
304 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
305 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
306 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
307 enable_f0 : OUT STD_LOGIC;
308 enable_f1 : OUT STD_LOGIC;
309 enable_f2 : OUT STD_LOGIC;
310 enable_f3 : OUT STD_LOGIC;
311 burst_f0 : OUT STD_LOGIC;
312 burst_f1 : OUT STD_LOGIC;
313 burst_f2 : OUT STD_LOGIC;
314 run : OUT STD_LOGIC;
315 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
316 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
317 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
318 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
322 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
323 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
324 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
325 sample_f3_valid : IN STD_LOGIC;
326 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
327 END COMPONENT;
328
329 COMPONENT lpp_top_ms
330 GENERIC (
331 Mem_use : INTEGER;
332 nb_burst_available_size : INTEGER;
333 nb_snapshot_param_size : INTEGER;
334 delta_snapshot_size : INTEGER;
335 delta_f2_f0_size : INTEGER;
336 delta_f2_f1_size : INTEGER;
337 pindex : INTEGER;
338 paddr : INTEGER;
339 pmask : INTEGER;
340 pirq_ms : INTEGER;
341 pirq_wfp : INTEGER;
342 hindex_wfp : INTEGER;
343 hindex_ms : INTEGER);
344 PORT (
345 clk : IN STD_LOGIC;
346 rstn : IN STD_LOGIC;
347 sample_B : IN Samples14v(2 DOWNTO 0);
348 sample_E : IN Samples14v(4 DOWNTO 0);
349 sample_val : IN STD_LOGIC;
350 apbi : IN apb_slv_in_type;
351 apbo : OUT apb_slv_out_type;
352 ahbi_ms : IN AHB_Mst_In_Type;
353 ahbo_ms : OUT AHB_Mst_Out_Type;
354 data_shaping_BW : OUT STD_LOGIC;
355 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
356 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
357 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
358 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
359 );
360 END COMPONENT;
361
362 COMPONENT lpp_apbreg_ms_pointer
363 PORT (
364 clk : IN STD_LOGIC;
365 rstn : IN STD_LOGIC;
366 run : IN STD_LOGIC;
367 reg0_status_ready_matrix : IN STD_LOGIC;
368 reg0_ready_matrix : OUT STD_LOGIC;
369 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
370 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
371 reg1_status_ready_matrix : IN STD_LOGIC;
372 reg1_ready_matrix : OUT STD_LOGIC;
373 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
374 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
375 ready_matrix : IN STD_LOGIC;
376 status_ready_matrix : OUT STD_LOGIC;
377 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
378 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
379 END COMPONENT;
380
381 COMPONENT lpp_lfr_ms_reg_head
382 PORT (
383 clk : IN STD_LOGIC;
384 rstn : IN STD_LOGIC;
385 in_wen : IN STD_LOGIC;
386 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
387 in_full : IN STD_LOGIC;
388 in_empty : IN STD_LOGIC;
389 out_write_error : OUT STD_LOGIC;
390 out_wen : OUT STD_LOGIC;
391 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
392 out_full : OUT STD_LOGIC);
393 END COMPONENT;
394
395 END lpp_lfr_pkg;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
14
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
17 -- TEMP
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
21 Mem_use : INTEGER);
22 PORT (
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
39
40
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
55 -----------------------------------------------------------------------------
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
65 );
66 END COMPONENT;
67
68
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
71 GENERIC (
72 Mem_use : INTEGER);
73 PORT (
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 run : IN STD_LOGIC;
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
85 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
86 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 dma_fifo_burst_valid : OUT STD_LOGIC;
89 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_fifo_ren : IN STD_LOGIC;
91 dma_buffer_new : OUT STD_LOGIC;
92 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
94 dma_buffer_full : IN STD_LOGIC;
95 dma_buffer_full_err : IN STD_LOGIC;
96 ready_matrix_f0 : OUT STD_LOGIC;
97 ready_matrix_f1 : OUT STD_LOGIC;
98 ready_matrix_f2 : OUT STD_LOGIC;
99 error_buffer_full : OUT STD_LOGIC;
100 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
101 status_ready_matrix_f0 : IN STD_LOGIC;
102 status_ready_matrix_f1 : IN STD_LOGIC;
103 status_ready_matrix_f2 : IN STD_LOGIC;
104 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
109 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
110 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
111 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
112 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
113 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
114 END COMPONENT;
115
116 COMPONENT lpp_lfr_ms_fsmdma
117 PORT (
118 clk : IN STD_ULOGIC;
119 rstn : IN STD_ULOGIC;
120 run : IN STD_LOGIC;
121 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
123 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
124 fifo_empty : IN STD_LOGIC;
125 fifo_empty_threshold : IN STD_LOGIC;
126 fifo_ren : OUT STD_LOGIC;
127 dma_fifo_valid_burst : OUT STD_LOGIC;
128 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 dma_fifo_ren : IN STD_LOGIC;
130 dma_buffer_new : OUT STD_LOGIC;
131 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
133 dma_buffer_full : IN STD_LOGIC;
134 dma_buffer_full_err : IN STD_LOGIC;
135 status_ready_matrix_f0 : IN STD_LOGIC;
136 status_ready_matrix_f1 : IN STD_LOGIC;
137 status_ready_matrix_f2 : IN STD_LOGIC;
138 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
142 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
143 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
144 ready_matrix_f0 : OUT STD_LOGIC;
145 ready_matrix_f1 : OUT STD_LOGIC;
146 ready_matrix_f2 : OUT STD_LOGIC;
147 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
148 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
149 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
150 error_buffer_full : OUT STD_LOGIC);
151 END COMPONENT;
152
153 COMPONENT lpp_lfr_ms_FFT
154 PORT (
155 clk : IN STD_LOGIC;
156 rstn : IN STD_LOGIC;
157 sample_valid : IN STD_LOGIC;
158 fft_read : IN STD_LOGIC;
159 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
160 sample_load : OUT STD_LOGIC;
161 fft_pong : OUT STD_LOGIC;
162 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
163 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
164 fft_data_valid : OUT STD_LOGIC;
165 fft_ready : OUT STD_LOGIC);
166 END COMPONENT;
167
168 COMPONENT lpp_lfr_filter
169 GENERIC (
170 Mem_use : INTEGER);
171 PORT (
172 sample : IN Samples(7 DOWNTO 0);
173 sample_val : IN STD_LOGIC;
174 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
175 clk : IN STD_LOGIC;
176 rstn : IN STD_LOGIC;
177 data_shaping_SP0 : IN STD_LOGIC;
178 data_shaping_SP1 : IN STD_LOGIC;
179 data_shaping_R0 : IN STD_LOGIC;
180 data_shaping_R1 : IN STD_LOGIC;
181 data_shaping_R2 : IN STD_LOGIC;
182 sample_f0_val : OUT STD_LOGIC;
183 sample_f1_val : OUT STD_LOGIC;
184 sample_f2_val : OUT STD_LOGIC;
185 sample_f3_val : OUT STD_LOGIC;
186 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
187 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
188 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
189 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
190 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
191 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
192 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
193 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
194 );
195 END COMPONENT;
196
197 COMPONENT lpp_lfr
198 GENERIC (
199 Mem_use : INTEGER;
200 nb_data_by_buffer_size : INTEGER;
201 -- nb_word_by_buffer_size : INTEGER;
202 nb_snapshot_param_size : INTEGER;
203 delta_vector_size : INTEGER;
204 delta_vector_size_f0_2 : INTEGER;
205 pindex : INTEGER;
206 paddr : INTEGER;
207 pmask : INTEGER;
208 pirq_ms : INTEGER;
209 pirq_wfp : INTEGER;
210 hindex : INTEGER;
211 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
212 );
213 PORT (
214 clk : IN STD_LOGIC;
215 rstn : IN STD_LOGIC;
216 sample_B : IN Samples(2 DOWNTO 0);
217 sample_E : IN Samples(4 DOWNTO 0);
218 sample_val : IN STD_LOGIC;
219 apbi : IN apb_slv_in_type;
220 apbo : OUT apb_slv_out_type;
221 ahbi : IN AHB_Mst_In_Type;
222 ahbo : OUT AHB_Mst_Out_Type;
223 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
224 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
225 data_shaping_BW : OUT STD_LOGIC;
226 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
227 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
228 );
229 END COMPONENT;
230
231 -----------------------------------------------------------------------------
232 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
233 -----------------------------------------------------------------------------
234 COMPONENT lpp_lfr_WFP_nMS
235 GENERIC (
236 Mem_use : INTEGER;
237 nb_data_by_buffer_size : INTEGER;
238 nb_word_by_buffer_size : INTEGER;
239 nb_snapshot_param_size : INTEGER;
240 delta_vector_size : INTEGER;
241 delta_vector_size_f0_2 : INTEGER;
242 pindex : INTEGER;
243 paddr : INTEGER;
244 pmask : INTEGER;
245 pirq_ms : INTEGER;
246 pirq_wfp : INTEGER;
247 hindex : INTEGER;
248 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
249 PORT (
250 clk : IN STD_LOGIC;
251 rstn : IN STD_LOGIC;
252 sample_B : IN Samples(2 DOWNTO 0);
253 sample_E : IN Samples(4 DOWNTO 0);
254 sample_val : IN STD_LOGIC;
255 apbi : IN apb_slv_in_type;
256 apbo : OUT apb_slv_out_type;
257 ahbi : IN AHB_Mst_In_Type;
258 ahbo : OUT AHB_Mst_Out_Type;
259 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
260 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
261 data_shaping_BW : OUT STD_LOGIC;
262 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
263 END COMPONENT;
264 -----------------------------------------------------------------------------
265
266 COMPONENT lpp_lfr_apbreg
267 GENERIC (
268 nb_data_by_buffer_size : INTEGER;
269 nb_snapshot_param_size : INTEGER;
270 delta_vector_size : INTEGER;
271 delta_vector_size_f0_2 : INTEGER;
272 pindex : INTEGER;
273 paddr : INTEGER;
274 pmask : INTEGER;
275 pirq_ms : INTEGER;
276 pirq_wfp : INTEGER;
277 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
278 PORT (
279 HCLK : IN STD_ULOGIC;
280 HRESETn : IN STD_ULOGIC;
281 apbi : IN apb_slv_in_type;
282 apbo : OUT apb_slv_out_type;
283 run_ms : OUT STD_LOGIC;
284 ready_matrix_f0 : IN STD_LOGIC;
285 ready_matrix_f1 : IN STD_LOGIC;
286 ready_matrix_f2 : IN STD_LOGIC;
287 error_buffer_full : IN STD_LOGIC;
288 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
289 status_ready_matrix_f0 : OUT STD_LOGIC;
290 status_ready_matrix_f1 : OUT STD_LOGIC;
291 status_ready_matrix_f2 : OUT STD_LOGIC;
292 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
293 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
294 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
295 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
296 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
297 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
298 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
299 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
300 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
301 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
302 data_shaping_BW : OUT STD_LOGIC;
303 data_shaping_SP0 : OUT STD_LOGIC;
304 data_shaping_SP1 : OUT STD_LOGIC;
305 data_shaping_R0 : OUT STD_LOGIC;
306 data_shaping_R1 : OUT STD_LOGIC;
307 data_shaping_R2 : OUT STD_LOGIC;
308 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
309 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
310 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
311 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
312 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
313 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
314 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
315 enable_f0 : OUT STD_LOGIC;
316 enable_f1 : OUT STD_LOGIC;
317 enable_f2 : OUT STD_LOGIC;
318 enable_f3 : OUT STD_LOGIC;
319 burst_f0 : OUT STD_LOGIC;
320 burst_f1 : OUT STD_LOGIC;
321 burst_f2 : OUT STD_LOGIC;
322 run : OUT STD_LOGIC;
323 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
324 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
325 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
326 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
327 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
328 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
329 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
330 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
331 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
332 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
333 sample_f3_valid : IN STD_LOGIC;
334 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
335 END COMPONENT;
336
337 COMPONENT lpp_top_ms
338 GENERIC (
339 Mem_use : INTEGER;
340 nb_burst_available_size : INTEGER;
341 nb_snapshot_param_size : INTEGER;
342 delta_snapshot_size : INTEGER;
343 delta_f2_f0_size : INTEGER;
344 delta_f2_f1_size : INTEGER;
345 pindex : INTEGER;
346 paddr : INTEGER;
347 pmask : INTEGER;
348 pirq_ms : INTEGER;
349 pirq_wfp : INTEGER;
350 hindex_wfp : INTEGER;
351 hindex_ms : INTEGER);
352 PORT (
353 clk : IN STD_LOGIC;
354 rstn : IN STD_LOGIC;
355 sample_B : IN Samples14v(2 DOWNTO 0);
356 sample_E : IN Samples14v(4 DOWNTO 0);
357 sample_val : IN STD_LOGIC;
358 apbi : IN apb_slv_in_type;
359 apbo : OUT apb_slv_out_type;
360 ahbi_ms : IN AHB_Mst_In_Type;
361 ahbo_ms : OUT AHB_Mst_Out_Type;
362 data_shaping_BW : OUT STD_LOGIC;
363 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
364 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
365 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
366 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
367 );
368 END COMPONENT;
369
370 COMPONENT lpp_apbreg_ms_pointer
371 PORT (
372 clk : IN STD_LOGIC;
373 rstn : IN STD_LOGIC;
374 run : IN STD_LOGIC;
375 reg0_status_ready_matrix : IN STD_LOGIC;
376 reg0_ready_matrix : OUT STD_LOGIC;
377 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
378 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
379 reg1_status_ready_matrix : IN STD_LOGIC;
380 reg1_ready_matrix : OUT STD_LOGIC;
381 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
382 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
383 ready_matrix : IN STD_LOGIC;
384 status_ready_matrix : OUT STD_LOGIC;
385 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
386 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
387 END COMPONENT;
388
389 COMPONENT lpp_lfr_ms_reg_head
390 PORT (
391 clk : IN STD_LOGIC;
392 rstn : IN STD_LOGIC;
393 in_wen : IN STD_LOGIC;
394 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
395 in_full : IN STD_LOGIC;
396 in_empty : IN STD_LOGIC;
397 out_write_error : OUT STD_LOGIC;
398 out_wen : OUT STD_LOGIC;
399 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
400 out_full : OUT STD_LOGIC);
401 END COMPONENT;
402
403 END lpp_lfr_pkg; No newline at end of file
Show file before | Show file after | Hide comments
@@ -94,20 +94,24 ENTITY lpp_waveform IS
94 94 ---------------------------------------------------------------------------
95 95 -- INPUT
96 96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
97 -- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
98 98
99 99 --f0
100 100 data_f0_in_valid : IN STD_LOGIC;
101 101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
102 103 --f1
103 104 data_f1_in_valid : IN STD_LOGIC;
104 105 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106 data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
105 107 --f2
106 108 data_f2_in_valid : IN STD_LOGIC;
107 109 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
110 data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
108 111 --f3
109 112 data_f3_in_valid : IN STD_LOGIC;
110 113 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
114 data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
111 115
112 116 ---------------------------------------------------------------------------
113 117 -- DMA --------------------------------------------------------------------
@@ -172,8 +176,8 ARCHITECTURE beh OF lpp_waveform IS
172 176 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
173 177 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
174 178 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
180 SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
177 181 --
178 182
179 183 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
@@ -301,7 +305,10 BEGIN -- beh
301 305 time_reg1 <= (OTHERS => '0');
302 306 time_reg2 <= (OTHERS => '0');
303 307 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
304 time_reg1 <= fine_time & coarse_time;
308 time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);
309 time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);
310 time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);
311 time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);
305 312 time_reg2 <= time_reg1;
306 313 END IF;
307 314 END PROCESS;
@@ -315,7 +322,7 BEGIN -- beh
315 322 run => run,
316 323 valid_in => valid_in(I),
317 324 ack_in => valid_ack(I),
318 time_in => time_reg2, -- Todo
325 time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo
319 326 valid_out => valid_out(I),
320 327 time_out => time_out(I), -- Todo
321 328 error => status_new_err(I));
Show file before | Show file after | Hide comments
@@ -135,15 +135,19 PACKAGE lpp_waveform_pkg IS
135 135 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
136 136 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
137 137 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
138 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
139 139 data_f0_in_valid : IN STD_LOGIC;
140 140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
141 142 data_f1_in_valid : IN STD_LOGIC;
142 143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
143 145 data_f2_in_valid : IN STD_LOGIC;
144 146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
145 148 data_f3_in_valid : IN STD_LOGIC;
146 149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
147 151
148 152 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
149 153 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
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