HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r347:326fa6e96475

Update Sample transformation from ADC to IIR_FILTER

pellion -

r347:326fa6e96475 JC

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designs/LFR-em-WFP_MS/LFR-em.vhd +9 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;      -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_time_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY LFR_em IS
               PORT (
                 clk100MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 -- TAG --------------------------------------------------------------------
                 TAG1 : IN  STD_ULOGIC;            -- DSU rx data
                 TAG3 : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 TAG2 : IN  STD_ULOGIC;            -- UART1 rx data
                 TAG4 : OUT STD_ULOGIC;            -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data      : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0 : OUT   STD_LOGIC;
                 nSRAM_BE1 : OUT   STD_LOGIC;
                 nSRAM_BE2 : OUT   STD_LOGIC;
                 nSRAM_BE3 : OUT   STD_LOGIC;
                 nSRAM_WE  : OUT   STD_LOGIC;
                 nSRAM_CE  : OUT   STD_LOGIC;
                 nSRAM_OE  : OUT   STD_LOGIC;
                 -- SPW --------------------------------------------------------------------
                 spw1_din  : IN  STD_LOGIC;
                 spw1_sin  : IN  STD_LOGIC;
                 spw1_dout : OUT STD_LOGIC;
                 spw1_sout : OUT STD_LOGIC;
                 spw2_din  : IN  STD_LOGIC;
                 spw2_sin  : IN  STD_LOGIC;
                 spw2_dout : OUT STD_LOGIC;
                 spw2_sout : OUT STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT STD_LOGIC;
                 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT STD_LOGIC;
                 ADC_data       : IN  STD_LOGIC_VECTOR(13 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 TAG8 : OUT STD_LOGIC;
                 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
             END LFR_em;
             ARCHITECTURE beh OF LFR_em IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
+              SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
               SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn : STD_LOGIC;
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
               PROCESS(clk100MHz)
               BEGIN
                 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
                   clk_50_s <= NOT clk_50_s;
                 END IF;
               END PROCESS;
               PROCESS(clk_50_s)
               BEGIN
                 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                 -- asynchronous reset (active low)
                   led(0) <= '0';
                   led(1) <= '0';
                   led(2) <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   led(0) <= '0';
                   led(1) <= '1';
                   led(2) <= '1';
                 END IF;
               END PROCESS;
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE)
                 PORT MAP (
                   clk       => clk_25,
                   reset     => rstn,
                   errorn    => OPEN,
                   ahbrxd    => TAG1,
                   ahbtxd    => TAG3,
                   urxd1     => TAG2,
                   utxd1     => TAG4,
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => nSRAM_BE0,
                   nSRAM_BE1 => nSRAM_BE1,
                   nSRAM_BE2 => nSRAM_BE2,
                   nSRAM_BE3 => nSRAM_BE3,
                   nSRAM_WE  => nSRAM_WE,
                   nSRAM_CE  => nSRAM_CE,
                   nSRAM_OE  => nSRAM_OE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_time_management_1 : apb_lfr_time_management
                 GENERIC MAP (
                   pindex => 6,
                   paddr  => 6,
                   pmask  => 16#fff#,
                   FIRST_DIVISION   => 374, -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz     => clk_25,
                   clk24_576MHz => clk_24,           -- 49.152MHz/2
                   resetn       => rstn,
                   grspw_tick   => swno.tickout,
                   apbi         => apbi_ext,
                   apbo         => apbo_ext(6),
                   coarse_time  => coarse_time,
                   fine_time    => fine_time);
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
             --  SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               lpp_lfr_1 : lpp_lfr_WFP_nMS
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,      -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"00010A")  -- aa.bb.cc version
+                  top_lfr_version        => X"00010B")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         -- 0 => MINI_LFR
                                                         -- 1 => EM
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => rstn,
-                  sample_B        => sample(2 DOWNTO 0),
+                  sample_B        => sample_s(2 DOWNTO 0),
-                  sample_E        => sample(7 DOWNTO 3),
+                  sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw,
                   observation_reg => observation_reg);
+              all_sample: FOR I IN 7 DOWNTO 0 GENERATE
+                sample_s(I) <= sample(I) & '0' & '0';
+              END GENERATE all_sample;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
                 GENERIC MAP (
                   ChanelCount     => 8,
                   ncycle_cnv_high => 40,            -- TODO : 79
                   ncycle_cnv      => 250)           -- TODO : 500
                 PORT MAP (
                   cnv_clk    => clk_24,             -- TODO : 49.152
                   cnv_rstn   => rstn,               -- ok
                   cnv        => ADC_smpclk,         -- ok
                   clk        => clk_25,             -- ok
                   rstn       => rstn,               -- ok
                   ADC_data   => ADC_data,           -- ok
                   ADC_nOE    => ADC_OEB_bar_CH,     -- ok
                   sample     => sample,             -- ok
                   sample_val => sample_val);        -- ok
               TAG8 <= ADC_smpclk;
             END beh;

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +9 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;      -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_time_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY MINI_LFR_top IS
               PORT (
                 clk_50 : IN  STD_LOGIC;
                 clk_49 : IN  STD_LOGIC;
                 reset  : IN  STD_LOGIC;
                 --BPs
                 BP0    : IN  STD_LOGIC;
                 BP1    : IN  STD_LOGIC;
                 --LEDs
                 LED0   : OUT STD_LOGIC;
                 LED1   : OUT STD_LOGIC;
                 LED2   : OUT STD_LOGIC;
                 --UARTs
                 TXD1   : IN  STD_LOGIC;
                 RXD1   : OUT STD_LOGIC;
                 nCTS1  : OUT STD_LOGIC;
                 nRTS1  : IN  STD_LOGIC;
                 TXD2  : IN  STD_LOGIC;
                 RXD2  : OUT STD_LOGIC;
                 nCTS2 : OUT STD_LOGIC;
                 nDTR2 : IN  STD_LOGIC;
                 nRTS2 : IN  STD_LOGIC;
                 nDCD2 : OUT STD_LOGIC;
                 --EXT CONNECTOR
                 IO0  : INOUT STD_LOGIC;
                 IO1  : INOUT STD_LOGIC;
                 IO2  : INOUT STD_LOGIC;
                 IO3  : INOUT STD_LOGIC;
                 IO4  : INOUT STD_LOGIC;
                 IO5  : INOUT STD_LOGIC;
                 IO6  : INOUT STD_LOGIC;
                 IO7  : INOUT STD_LOGIC;
                 IO8  : INOUT STD_LOGIC;
                 IO9  : INOUT STD_LOGIC;
                 IO10 : INOUT STD_LOGIC;
                 IO11 : INOUT STD_LOGIC;
                 --SPACE WIRE
                 SPW_EN       : OUT STD_LOGIC;       -- 0 => off
                 SPW_NOM_DIN  : IN  STD_LOGIC;       -- NOMINAL LINK
                 SPW_NOM_SIN  : IN  STD_LOGIC;
                 SPW_NOM_DOUT : OUT STD_LOGIC;
                 SPW_NOM_SOUT : OUT STD_LOGIC;
                 SPW_RED_DIN  : IN  STD_LOGIC;       -- REDUNDANT LINK
                 SPW_RED_SIN  : IN  STD_LOGIC;
                 SPW_RED_DOUT : OUT STD_LOGIC;
                 SPW_RED_SOUT : OUT STD_LOGIC;
                 -- MINI LFR ADC INPUTS
                 ADC_nCS      : OUT STD_LOGIC;
                 ADC_CLK      : OUT STD_LOGIC;
                 ADC_SDO      : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 -- SRAM
                 SRAM_nWE : OUT   STD_LOGIC;
                 SRAM_CE  : OUT   STD_LOGIC;
                 SRAM_nOE : OUT   STD_LOGIC;
                 SRAM_nBE : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
                 SRAM_A   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 SRAM_DQ  : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END MINI_LFR_top;
             ARCHITECTURE beh OF MINI_LFR_top IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL errorn      : STD_LOGIC;
               -- UART AHB ---------------------------------------------------------------
               SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data
               SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
               -- UART APB ---------------------------------------------------------------
               SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
               SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
                                                     --
               SIGNAL I00_s : STD_LOGIC;
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               --
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --  SIGNAL clkmn                : STD_ULOGIC;
             --  SIGNAL txclk                : STD_ULOGIC;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
+              SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
               SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL bias_fail_sw_sig : STD_LOGIC;
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               PROCESS(clk_50)
               BEGIN
                 IF clk_50'EVENT AND clk_50 = '1' THEN
                   clk_50_s <= NOT clk_50_s;
                 END IF;
               END PROCESS;
               PROCESS(clk_50_s)
               BEGIN
                 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               PROCESS(clk_49)
               BEGIN
                 IF clk_49'EVENT AND clk_49 = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   LED0 <= '0';
                   LED1 <= '0';
                   LED2 <= '0';
                   --IO1  <= '0';
                   --IO2  <= '1';
                   --IO3  <= '0';
                   --IO4  <= '0';
                   --IO5  <= '0';
                   --IO6  <= '0';
                   --IO7  <= '0';
                   --IO8  <= '0';
                   --IO9  <= '0';
                   --IO10 <= '0';
                   --IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   LED0 <= '0';
                   LED1 <= '1';
                   LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                   --IO1  <= '1';
                   --IO2  <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
                   --IO3  <= ADC_SDO(0);
                   --IO4  <= ADC_SDO(1);
                   --IO5  <= ADC_SDO(2);
                   --IO6  <= ADC_SDO(3);
                   --IO7  <= ADC_SDO(4);
                   --IO8  <= ADC_SDO(5);
                   --IO9  <= ADC_SDO(6);
                   --IO10 <= ADC_SDO(7);
                   --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                 END IF;
               END PROCESS;
               PROCESS (clk_24, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   I00_s <= '0';
                 ELSIF clk_24'EVENT AND clk_24 = '1' THEN  -- rising clock edge
                   I00_s <= NOT I00_s ;
                 END IF;
               END PROCESS;
             --  IO0 <= I00_s;
               --UARTs
               nCTS1 <= '1';
               nCTS2 <= '1';
               nDCD2 <= '1';
               --EXT CONNECTOR
               --SPACE WIRE
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE)
                 PORT MAP (
                   clk       => clk_25,
                   reset     => reset,
                   errorn    => errorn,
                   ahbrxd    => TXD1,
                   ahbtxd    => RXD1,
                   urxd1     => TXD2,
                   utxd1     => RXD2,
                   address   => SRAM_A,
                   data      => SRAM_DQ,
                   nSRAM_BE0 => SRAM_nBE(0),
                   nSRAM_BE1 => SRAM_nBE(1),
                   nSRAM_BE2 => SRAM_nBE(2),
                   nSRAM_BE3 => SRAM_nBE(3),
                   nSRAM_WE  => SRAM_nWE,
                   nSRAM_CE  => SRAM_CE,
                   nSRAM_OE  => SRAM_nOE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_time_management_1 : apb_lfr_time_management
                 GENERIC MAP (
                   pindex => 6,
                   paddr  => 6,
                   pmask  => 16#fff#,
                   FIRST_DIVISION   => 374, -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz     => clk_25,
                   clk24_576MHz => clk_24,           -- 49.152MHz/2
                   resetn       => reset,
                   grspw_tick   => swno.tickout,
                   apbi         => apbi_ext,
                   apbo         => apbo_ext(6),
                   coarse_time  => coarse_time,
                   fine_time    => fine_time);
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
               SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DIN, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SIN, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DOUT, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SOUT, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_SIN, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_DIN, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_DOUT, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_SOUT, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(reset, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,      -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
                   top_lfr_version        => X"00010A")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => reset,
-                  sample_B        => sample(2 DOWNTO 0),
+                  sample_B        => sample_s(2 DOWNTO 0),
-                  sample_E        => sample(7 DOWNTO 3),
+                  sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw_sig,
                   observation_reg => observation_reg);
+              all_sample: FOR I IN 7 DOWNTO 0 GENERATE
+                sample_s(I) <= sample(I) & '0' & '0';
+              END GENERATE all_sample;
               top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
                 GENERIC MAP(
                   ChannelCount    => 8,
                   SampleNbBits    => 14,
                   ncycle_cnv_high => 40,  -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
                   ncycle_cnv      => 249) -- 49 152 000 / 98304 /2
                 PORT MAP (
                   -- CONV
                   cnv_clk    => clk_24,
                   cnv_rstn   => reset,
                   cnv        => ADC_nCS_sig,
                   -- DATA
                   clk        => clk_25,
                   rstn       => reset,
                   sck        => ADC_CLK_sig,
                   sdo        => ADC_SDO_sig,
                   -- SAMPLE
                   sample     => sample,
                   sample_val => sample_val);
               --IO10 <= ADC_SDO_sig(5);
               --IO9  <= ADC_SDO_sig(4);
               --IO8  <= ADC_SDO_sig(3);
               ADC_nCS     <= ADC_nCS_sig;
               ADC_CLK     <= ADC_CLK_sig;
               ADC_SDO_sig <= ADC_SDO;
             ----------------------------------------------------------------------
             ---  GPIO  -----------------------------------------------------------
             ----------------------------------------------------------------------
               grgpio0 : grgpio
                 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
                 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
               --pio_pad_0 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
               --pio_pad_1 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
               --pio_pad_2 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
               --pio_pad_3 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
               --pio_pad_4 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
               --pio_pad_5 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
               --pio_pad_6 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
               --pio_pad_7 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
               PROCESS (clk_25, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                  -- asynchronous reset (active low)
                   IO0  <= '0';
                   IO1  <= '0';
                   IO2  <= '0';
                   IO3  <= '0';
                   IO4  <= '0';
                   IO5  <= '0';
                   IO6  <= '0';
                   IO7  <= '0';
                   IO8  <= '0';
                   IO9  <= '0';
                   IO10 <= '0';
                   IO11 <= '0';
                 ELSIF clk_25'event AND clk_25 = '1' THEN  -- rising clock edge
                   CASE gpioo.dout(1 DOWNTO 0) IS
                     WHEN "00" =>
                       IO0  <= observation_reg(0 );
                       IO1  <= observation_reg(1 );
                       IO2  <= observation_reg(2 );
                       IO3  <= observation_reg(3 );
                       IO4  <= observation_reg(4 );
                       IO5  <= observation_reg(5 );
                       IO6  <= observation_reg(6 );
                       IO7  <= observation_reg(7 );
                       IO8  <= observation_reg(8 );
                       IO9  <= observation_reg(9 );
                       IO10 <= observation_reg(10);
                       IO11 <= observation_reg(11);
                     WHEN "01" =>
                       IO0  <= observation_reg(0  + 12);
                       IO1  <= observation_reg(1  + 12);
                       IO2  <= observation_reg(2  + 12);
                       IO3  <= observation_reg(3  + 12);
                       IO4  <= observation_reg(4  + 12);
                       IO5  <= observation_reg(5  + 12);
                       IO6  <= observation_reg(6  + 12);
                       IO7  <= observation_reg(7  + 12);
                       IO8  <= observation_reg(8  + 12);
                       IO9  <= observation_reg(9  + 12);
                       IO10 <= observation_reg(10 + 12);
                       IO11 <= observation_reg(11 + 12);
                     WHEN "10" =>
                       IO0  <= observation_reg(0  + 12 + 12);
                       IO1  <= observation_reg(1  + 12 + 12);
                       IO2  <= observation_reg(2  + 12 + 12);
                       IO3  <= observation_reg(3  + 12 + 12);
                       IO4  <= observation_reg(4  + 12 + 12);
                       IO5  <= observation_reg(5  + 12 + 12);
                       IO6  <= observation_reg(6  + 12 + 12);
                       IO7  <= observation_reg(7  + 12 + 12);
                       IO8  <= '0';
                       IO9  <= '0';
                       IO10 <= '0';
                       IO11 <= '0';
                     WHEN "11" =>
                       IO0  <= '0';
                       IO1  <= '0';
                       IO2  <= '0';
                       IO3  <= '0';
                       IO4  <= '0';
                       IO5  <= '0';
                       IO6  <= '0';
                       IO7  <= '0';
                       IO8  <= '0';
                       IO9  <= '0';
                       IO10 <= '0';
                       IO11 <= '0';
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +8 -8

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr IS
               GENERIC (
                 Mem_use                : INTEGER := use_RAM;
                 nb_data_by_buffer_size : INTEGER := 11;
                 nb_word_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 7;
                 pindex   : INTEGER := 4;
                 paddr    : INTEGER := 4;
                 pmask    : INTEGER := 16#fff#;
                 pirq_ms  : INTEGER := 0;
                 pirq_wfp : INTEGER := 1;
                 hindex : INTEGER := 2;
                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
                 );
               PORT (
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
-                sample_B        : IN  Samples14v(2 DOWNTO 0);
+                sample_B        : IN  Samples(2 DOWNTO 0);
-                sample_E        : IN  Samples14v(4 DOWNTO 0);
+                sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
                 apbo            : OUT apb_slv_out_type;
                 -- AHB
                 ahbi            : IN  AHB_Mst_In_Type;
                 ahbo            : OUT AHB_Mst_Out_Type;
                 -- TIME
                 coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 data_shaping_BW : OUT STD_LOGIC;
                 --
                 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 --debug
                 --debug_f0_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f0_data_valid : OUT STD_LOGIC;
                 --debug_f1_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f1_data_valid : OUT STD_LOGIC;
                 --debug_f2_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f2_data_valid : OUT STD_LOGIC;
                 --debug_f3_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f3_data_valid : OUT STD_LOGIC;
                 ---- debug FIFO_IN
                 --debug_f0_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
                 --debug_f1_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
                 --debug_f2_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
                 --debug_f3_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
                 ----debug FIFO OUT
                 --debug_f0_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug_f1_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug_f2_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug_f3_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
                 ----debug DMA IN
                 --debug_f0_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
                 --debug_f1_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
                 --debug_f2_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
                 --debug_f3_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
                 );
             END lpp_lfr;
             ARCHITECTURE beh OF lpp_lfr IS
-              SIGNAL sample           : Samples14v(7 DOWNTO 0);
+              --SIGNAL sample           : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
               SIGNAL data_shaping_SP1 : STD_LOGIC;
               SIGNAL data_shaping_R0  : STD_LOGIC;
               SIGNAL data_shaping_R1  : STD_LOGIC;
               --
               SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f3_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_val    : STD_LOGIC;
               SIGNAL sample_f1_val    : STD_LOGIC;
               SIGNAL sample_f2_val    : STD_LOGIC;
               SIGNAL sample_f3_val    : STD_LOGIC;
               --
               SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f3_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -- SM
               SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
               SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
               SIGNAL ready_matrix_f1                        : STD_LOGIC;
               SIGNAL ready_matrix_f2                        : STD_LOGIC;
               SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
               SIGNAL error_bad_component_error              : STD_LOGIC;
               SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
               SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
               SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
               SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
               SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
               SIGNAL status_error_bad_component_error       : STD_LOGIC;
               SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
               SIGNAL config_active_interruption_onError     : STD_LOGIC;
               SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -- WFP
               SIGNAL status_full     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
               SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0         : STD_LOGIC;
               SIGNAL enable_f1         : STD_LOGIC;
               SIGNAL enable_f2         : STD_LOGIC;
               SIGNAL enable_f3         : STD_LOGIC;
               SIGNAL burst_f0          : STD_LOGIC;
               SIGNAL burst_f1          : STD_LOGIC;
               SIGNAL burst_f2          : STD_LOGIC;
               SIGNAL addr_data_f0      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f1      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f3      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL run        : STD_LOGIC;
               SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
               SIGNAL data_f0_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out_valid       : STD_LOGIC;
               SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f0_data_out_ren         : STD_LOGIC;
               --f1
               SIGNAL data_f1_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out_valid       : STD_LOGIC;
               SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f1_data_out_ren         : STD_LOGIC;
               --f2
               SIGNAL data_f2_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out_valid       : STD_LOGIC;
               SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f2_data_out_ren         : STD_LOGIC;
               --f3
               SIGNAL data_f3_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out_valid       : STD_LOGIC;
               SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f3_data_out_ren         : STD_LOGIC;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
               --f1
               SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
               --f2
               SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
               --f3
               SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- DMA RR
               -----------------------------------------------------------------------------
               SIGNAL dma_sel_valid   : STD_LOGIC;
               SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA_REG
               -----------------------------------------------------------------------------
               SIGNAL ongoing_reg         : STD_LOGIC;
               SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_send_reg        : STD_LOGIC;
               SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
               SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
               SIGNAL dma_send        : STD_LOGIC;
               SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
               SIGNAL dma_done        : STD_LOGIC;
               SIGNAL dma_ren         : STD_LOGIC;
               SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DEBUG
               -----------------------------------------------------------------------------
               --
               SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- MS
               -----------------------------------------------------------------------------
               SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_ms_valid       : STD_LOGIC;
               SIGNAL data_ms_valid_burst : STD_LOGIC;
               SIGNAL data_ms_ren         : STD_LOGIC;
               SIGNAL data_ms_done        : STD_LOGIC;
               SIGNAL run_ms              : STD_LOGIC;
               SIGNAL ms_softandhard_rstn : STD_LOGIC;
               SIGNAL matrix_time_f0_0    : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1      : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2      : STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
-              sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
+              sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
-              sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
+              sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
-              all_channel : FOR i IN 7 DOWNTO 0 GENERATE
+              --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
-                sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
+              --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
-              END GENERATE all_channel;
+              --END GENERATE all_channel;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
                   clk              => clk,
                   rstn             => rstn,
                   data_shaping_SP0 => data_shaping_SP0,
                   data_shaping_SP1 => data_shaping_SP1,
                   data_shaping_R0  => data_shaping_R0,
                   data_shaping_R1  => data_shaping_R1,
                   sample_f0_val    => sample_f0_val,
                   sample_f1_val    => sample_f1_val,
                   sample_f2_val    => sample_f2_val,
                   sample_f3_val    => sample_f3_val,
                   sample_f0_wdata  => sample_f0_data,
                   sample_f1_wdata  => sample_f1_data,
                   sample_f2_wdata  => sample_f2_data,
                   sample_f3_wdata  => sample_f3_data);
               -----------------------------------------------------------------------------
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                 GENERIC MAP (
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_word_by_buffer_size => nb_word_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2,
                   pindex                 => pindex,
                   paddr                  => paddr,
                   pmask                  => pmask,
                   pirq_ms                => pirq_ms,
                   pirq_wfp               => pirq_wfp,
                   top_lfr_version        => top_lfr_version)
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   apbi    => apbi,
                   apbo    => apbo,
                   run_ms => run_ms,
                   ready_matrix_f0_0                      => ready_matrix_f0_0,
                   ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
                   debug_reg                              => debug_reg,
                   status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
                   status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
                   status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   matrix_time_f0_0 => matrix_time_f0_0,
                   matrix_time_f0_1 => matrix_time_f0_1,
                   matrix_time_f1   => matrix_time_f1,
                   matrix_time_f2   => matrix_time_f2,
                   addr_matrix_f0_0  => addr_matrix_f0_0,
                   addr_matrix_f0_1  => addr_matrix_f0_1,
                   addr_matrix_f1    => addr_matrix_f1,
                   addr_matrix_f2    => addr_matrix_f2,
                   status_full       => status_full,
                   status_full_ack   => status_full_ack,
                   status_full_err   => status_full_err,
                   status_new_err    => status_new_err,
                   data_shaping_BW   => data_shaping_BW,
                   data_shaping_SP0  => data_shaping_SP0,
                   data_shaping_SP1  => data_shaping_SP1,
                   data_shaping_R0   => data_shaping_R0,
                   data_shaping_R1   => data_shaping_R1,
                   delta_snapshot    => delta_snapshot,
                   delta_f0          => delta_f0,
                   delta_f0_2        => delta_f0_2,
                   delta_f1          => delta_f1,
                   delta_f2          => delta_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_word_by_buffer => nb_word_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   enable_f0         => enable_f0,
                   enable_f1         => enable_f1,
                   enable_f2         => enable_f2,
                   enable_f3         => enable_f3,
                   burst_f0          => burst_f0,
                   burst_f1          => burst_f1,
                   burst_f2          => burst_f2,
                   run               => run,
                   addr_data_f0      => addr_data_f0,
                   addr_data_f1      => addr_data_f1,
                   addr_data_f2      => addr_data_f2,
                   addr_data_f3      => addr_data_f3,
                   start_date        => start_date,
                   ---------------------------------------------------------------------------
                   debug_reg0        => debug_reg0,
                   debug_reg1        => debug_reg1,
                   debug_reg2        => debug_reg2,
                   debug_reg3        => debug_reg3,
                   debug_reg4        => debug_reg4,
                   debug_reg5        => debug_reg5,
                   debug_reg6        => debug_reg6,
                   debug_reg7        => debug_reg7);
               debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
               debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
               debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
               -----------------------------------------------------------------------------
               --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357";  -- TODO : debug
               --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB";  -- TODO : debug
               --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773";  -- TODO : debug
               --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612";  -- TODO : debug
               -----------------------------------------------------------------------------
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   tech                   => inferred,
                   data_size              => 6*16,
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_word_by_buffer_size => nb_word_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   reg_run            => run,
                   reg_start_date     => start_date,
                   reg_delta_snapshot => delta_snapshot,
                   reg_delta_f0       => delta_f0,
                   reg_delta_f0_2     => delta_f0_2,
                   reg_delta_f1       => delta_f1,
                   reg_delta_f2       => delta_f2,
                   enable_f0 => enable_f0,
                   enable_f1 => enable_f1,
                   enable_f2 => enable_f2,
                   enable_f3 => enable_f3,
                   burst_f0  => burst_f0,
                   burst_f1  => burst_f1,
                   burst_f2  => burst_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_word_by_buffer => nb_word_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   status_full       => status_full,
                   status_full_ack   => status_full_ack,
                   status_full_err   => status_full_err,
                   status_new_err    => status_new_err,
                   coarse_time => coarse_time,
                   fine_time   => fine_time,
                   --f0
                   addr_data_f0                 => addr_data_f0,
                   data_f0_in_valid             => sample_f0_val,
                   data_f0_in                   => sample_f0_data,  -- sample_f0_data_debug,  -- TODO : debug
                   --f1
                   addr_data_f1                 => addr_data_f1,
                   data_f1_in_valid             => sample_f1_val,
                   data_f1_in                   => sample_f1_data,  -- sample_f1_data_debug,  -- TODO : debug,
                   --f2
                   addr_data_f2                 => addr_data_f2,
                   data_f2_in_valid             => sample_f2_val,
                   data_f2_in                   => sample_f2_data,  -- sample_f2_data_debug,  -- TODO : debug,
                   --f3
                   addr_data_f3                 => addr_data_f3,
                   data_f3_in_valid             => sample_f3_val,
                   data_f3_in                   => sample_f3_data,  -- sample_f3_data_debug,  -- TODO : debug,
                   -- OUTPUT -- DMA interface
                   --f0
                   data_f0_addr_out             => data_f0_addr_out_s,
                   data_f0_data_out             => data_f0_data_out,
                   data_f0_data_out_valid       => data_f0_data_out_valid_s,
                   data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
                   data_f0_data_out_ren         => data_f0_data_out_ren,
                   --f1
                   data_f1_addr_out             => data_f1_addr_out_s,
                   data_f1_data_out             => data_f1_data_out,
                   data_f1_data_out_valid       => data_f1_data_out_valid_s,
                   data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
                   data_f1_data_out_ren         => data_f1_data_out_ren,
                   --f2
                   data_f2_addr_out             => data_f2_addr_out_s,
                   data_f2_data_out             => data_f2_data_out,
                   data_f2_data_out_valid       => data_f2_data_out_valid_s,
                   data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
                   data_f2_data_out_ren         => data_f2_data_out_ren,
                   --f3
                   data_f3_addr_out             => data_f3_addr_out_s,
                   data_f3_data_out             => data_f3_data_out,
                   data_f3_data_out_valid       => data_f3_data_out_valid_s,
                   data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
                   data_f3_data_out_ren         => data_f3_data_out_ren ,
                   -------------------------------------------------------------------------
                   observation_reg => OPEN
                   );
               -----------------------------------------------------------------------------
               -- TEMP
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_f0_data_out_valid       <= '0';
                   data_f0_data_out_valid_burst <= '0';
                   data_f1_data_out_valid       <= '0';
                   data_f1_data_out_valid_burst <= '0';
                   data_f2_data_out_valid       <= '0';
                   data_f2_data_out_valid_burst <= '0';
                   data_f3_data_out_valid       <= '0';
                   data_f3_data_out_valid_burst <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   data_f0_data_out_valid       <= data_f0_data_out_valid_s;
                   data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
                   data_f1_data_out_valid       <= data_f1_data_out_valid_s;
                   data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
                   data_f2_data_out_valid       <= data_f2_data_out_valid_s;
                   data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
                   data_f3_data_out_valid       <= data_f3_data_out_valid_s;
                   data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
                 END IF;
               END PROCESS;
               data_f0_addr_out <= data_f0_addr_out_s;
               data_f1_addr_out <= data_f1_addr_out_s;
               data_f2_addr_out <= data_f2_addr_out_s;
               data_f3_addr_out <= data_f3_addr_out_s;
               -----------------------------------------------------------------------------
               -- RoundRobin Selection For DMA
               -----------------------------------------------------------------------------
               dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
               dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
               dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
               dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
               RR_Arbiter_4_1 : RR_Arbiter_4
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   in_valid  => dma_rr_valid,
                   out_grant => dma_rr_grant_s);
               dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
               dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
               dma_rr_valid_ms(2) <= '0';
               dma_rr_valid_ms(3) <= '0';
               RR_Arbiter_4_2 : RR_Arbiter_4
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   in_valid  => dma_rr_valid_ms,
                   out_grant => dma_rr_grant_ms);
               dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
               -----------------------------------------------------------------------------
               -- in  : dma_rr_grant
               --       send
               -- out : dma_sel
               --       dma_valid_burst
               --       dma_sel_valid
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   dma_sel         <= (OTHERS => '0');
                   dma_send        <= '0';
                   dma_valid_burst <= '0';
                   data_ms_done    <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF run = '1' THEN
                     data_ms_done <= '0';
                     IF dma_sel = "00000" OR dma_done = '1' THEN
                       dma_sel <= dma_rr_grant;
                       IF dma_rr_grant(0) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f0_data_out_valid_burst;
                         dma_sel_valid   <= data_f0_data_out_valid;
                       ELSIF dma_rr_grant(1) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f1_data_out_valid_burst;
                         dma_sel_valid   <= data_f1_data_out_valid;
                       ELSIF dma_rr_grant(2) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f2_data_out_valid_burst;
                         dma_sel_valid   <= data_f2_data_out_valid;
                       ELSIF dma_rr_grant(3) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f3_data_out_valid_burst;
                         dma_sel_valid   <= data_f3_data_out_valid;
                       ELSIF dma_rr_grant(4) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_ms_valid_burst;
                         dma_sel_valid   <= data_ms_valid;
                       END IF;
                       IF dma_sel(4) = '1' THEN
                         data_ms_done <= '1';
                       END IF;
                     ELSE
                       dma_sel  <= dma_sel;
                       dma_send <= '0';
                     END IF;
                   ELSE
                     data_ms_done    <= '0';
                     dma_sel         <= (OTHERS => '0');
                     dma_send        <= '0';
                     dma_valid_burst <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
                              data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
                              data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
                              data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
                              data_ms_addr;
               dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
                           data_f1_data_out WHEN dma_sel(1) = '1' ELSE
                           data_f2_data_out WHEN dma_sel(2) = '1' ELSE
                           data_f3_data_out WHEN dma_sel(3) = '1' ELSE
                           data_ms_data;
               data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
               data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
               data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
               data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
               data_ms_ren          <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
               dma_data_2 <= dma_data;
               -----------------------------------------------------------------------------
               -- DEBUG -- DMA IN
               --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
               --debug_f0_data_dma_in       <= dma_data;
               --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
               --debug_f1_data_dma_in       <= dma_data;
               --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
               --debug_f2_data_dma_in       <= dma_data;
               --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
               --debug_f3_data_dma_in       <= dma_data;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
               lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
                 GENERIC MAP (
                   tech   => inferred,
                   hindex => hindex)
                 PORT MAP (
                   HCLK           => clk,
                   HRESETn        => rstn,
                   run            => run,
                   AHB_Master_In  => ahbi,
                   AHB_Master_Out => ahbo,
                   send        => dma_send,
                   valid_burst => dma_valid_burst,
                   done        => dma_done,
                   ren         => dma_ren,
                   address     => dma_address,
                   data        => dma_data_2);
               -----------------------------------------------------------------------------
               -- Matrix Spectral
               -----------------------------------------------------------------------------
               sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
                                NOT(sample_f0_val) & NOT(sample_f0_val);
               sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
                                NOT(sample_f1_val) & NOT(sample_f1_val);
               sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
                                NOT(sample_f3_val) & NOT(sample_f3_val);
               sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
               sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
               sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
               -------------------------------------------------------------------------------
               ms_softandhard_rstn <= rstn AND run_ms AND run;
               -----------------------------------------------------------------------------
               lpp_lfr_ms_1 : lpp_lfr_ms
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   clk  => clk,
                   rstn => ms_softandhard_rstn,      --rstn,
                   coarse_time => coarse_time,
                   fine_time   => fine_time,
                   sample_f0_wen   => sample_f0_wen,
                   sample_f0_wdata => sample_f0_wdata,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
                   sample_f3_wen   => sample_f3_wen,
                   sample_f3_wdata => sample_f3_wdata,
                   dma_addr        => data_ms_addr,         --
                   dma_data        => data_ms_data,         --
                   dma_valid       => data_ms_valid,        --
                   dma_valid_burst => data_ms_valid_burst,  --
                   dma_ren         => data_ms_ren,          --
                   dma_done        => data_ms_done,         --
                   ready_matrix_f0_0                      => ready_matrix_f0_0,
                   ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
                   debug_reg                              => observation_reg,  --debug_reg,
                   status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
                   status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
                   status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   addr_matrix_f0_0                       => addr_matrix_f0_0,
                   addr_matrix_f0_1                       => addr_matrix_f0_1,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2,
                   matrix_time_f0_0                       => matrix_time_f0_0,
                   matrix_time_f0_1                       => matrix_time_f0_1,
                   matrix_time_f1                         => matrix_time_f1,
                   matrix_time_f2                         => matrix_time_f2);
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_WFP_nMS.vhd +9 -8

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr_WFP_nMS IS
               GENERIC (
                 Mem_use                : INTEGER := use_RAM;
                 nb_data_by_buffer_size : INTEGER := 11;
                 nb_word_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 7;
                 pindex   : INTEGER := 4;
                 paddr    : INTEGER := 4;
                 pmask    : INTEGER := 16#fff#;
                 pirq_ms  : INTEGER := 0;
                 pirq_wfp : INTEGER := 1;
                 hindex : INTEGER := 2;
                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
                 );
               PORT (
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
-                sample_B        : IN  Samples14v(2 DOWNTO 0);
+                sample_B        : IN  Samples(2 DOWNTO 0);
-                sample_E        : IN  Samples14v(4 DOWNTO 0);
+                sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
                 apbo            : OUT apb_slv_out_type;
                 -- AHB
                 ahbi            : IN  AHB_Mst_In_Type;
                 ahbo            : OUT AHB_Mst_Out_Type;
                 -- TIME
                 coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 data_shaping_BW : OUT STD_LOGIC;
                 --
                 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 --debug
                 --debug_f0_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f0_data_valid : OUT STD_LOGIC;
                 --debug_f1_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f1_data_valid : OUT STD_LOGIC;
                 --debug_f2_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f2_data_valid : OUT STD_LOGIC;
                 --debug_f3_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f3_data_valid : OUT STD_LOGIC;
                 ---- debug FIFO_IN
                 --debug_f0_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
                 --debug_f1_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
                 --debug_f2_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
                 --debug_f3_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
                 ----debug FIFO OUT
                 --debug_f0_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug_f1_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug_f2_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug_f3_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
                 ----debug DMA IN
                 --debug_f0_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
                 --debug_f1_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
                 --debug_f2_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
                 --debug_f3_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
                 );
             END lpp_lfr_WFP_nMS;
             ARCHITECTURE beh OF lpp_lfr_WFP_nMS IS
-              SIGNAL sample           : Samples14v(7 DOWNTO 0);
+            --  SIGNAL sample           : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
               SIGNAL data_shaping_SP1 : STD_LOGIC;
               SIGNAL data_shaping_R0  : STD_LOGIC;
               SIGNAL data_shaping_R1  : STD_LOGIC;
               --
             --  SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
             --  SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
             --  SIGNAL sample_f3_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_val    : STD_LOGIC;
               SIGNAL sample_f1_val    : STD_LOGIC;
               SIGNAL sample_f2_val    : STD_LOGIC;
               SIGNAL sample_f3_val    : STD_LOGIC;
               --
               SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               --
               --SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               --SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               --SIGNAL sample_f3_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -- SM
               SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
               SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
               SIGNAL ready_matrix_f1                        : STD_LOGIC;
               SIGNAL ready_matrix_f2                        : STD_LOGIC;
               SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
               SIGNAL error_bad_component_error              : STD_LOGIC;
               SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
               SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
               SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
               SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
               SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
               SIGNAL status_error_bad_component_error       : STD_LOGIC;
               SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
               SIGNAL config_active_interruption_onError     : STD_LOGIC;
               SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -- WFP
               SIGNAL status_full     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
               SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0         : STD_LOGIC;
               SIGNAL enable_f1         : STD_LOGIC;
               SIGNAL enable_f2         : STD_LOGIC;
               SIGNAL enable_f3         : STD_LOGIC;
               SIGNAL burst_f0          : STD_LOGIC;
               SIGNAL burst_f1          : STD_LOGIC;
               SIGNAL burst_f2          : STD_LOGIC;
               SIGNAL addr_data_f0      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f1      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f3      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL run        : STD_LOGIC;
               SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
               SIGNAL data_f0_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out_valid       : STD_LOGIC;
               SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f0_data_out_ren         : STD_LOGIC;
               --f1
               SIGNAL data_f1_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out_valid       : STD_LOGIC;
               SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f1_data_out_ren         : STD_LOGIC;
               --f2
               SIGNAL data_f2_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out_valid       : STD_LOGIC;
               SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f2_data_out_ren         : STD_LOGIC;
               --f3
               SIGNAL data_f3_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out_valid       : STD_LOGIC;
               SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f3_data_out_ren         : STD_LOGIC;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
               --f1
               SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
               --f2
               SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
               --f3
               SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- DMA RR
               -----------------------------------------------------------------------------
               SIGNAL dma_sel_valid   : STD_LOGIC;
               SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA_REG
               -----------------------------------------------------------------------------
               SIGNAL ongoing_reg         : STD_LOGIC;
               SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_send_reg        : STD_LOGIC;
               SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
               SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
               SIGNAL dma_send        : STD_LOGIC;
               SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
               SIGNAL dma_done        : STD_LOGIC;
               SIGNAL dma_ren         : STD_LOGIC;
               SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DEBUG
               -----------------------------------------------------------------------------
               --
               SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- MS
               -----------------------------------------------------------------------------
               SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_ms_valid       : STD_LOGIC;
               SIGNAL data_ms_valid_burst : STD_LOGIC;
               SIGNAL data_ms_ren         : STD_LOGIC;
               SIGNAL data_ms_done        : STD_LOGIC;
               SIGNAL run_ms : STD_LOGIC;
               --SIGNAL ms_softandhard_rstn : STD_LOGIC;
               SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2   : STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
-              sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
+              sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
-              sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
+              sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
-              all_channel : FOR i IN 7 DOWNTO 0 GENERATE
+              --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
-                sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
+              --  --sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
-              END GENERATE all_channel;
+              --  sample_s(i) <= sample(i) & '0' & '0';
+              --END GENERATE all_channel;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
                   clk              => clk,
                   rstn             => rstn,
                   data_shaping_SP0 => data_shaping_SP0,
                   data_shaping_SP1 => data_shaping_SP1,
                   data_shaping_R0  => data_shaping_R0,
                   data_shaping_R1  => data_shaping_R1,
                   sample_f0_val    => sample_f0_val,
                   sample_f1_val    => sample_f1_val,
                   sample_f2_val    => sample_f2_val,
                   sample_f3_val    => sample_f3_val,
                   sample_f0_wdata  => sample_f0_data,
                   sample_f1_wdata  => sample_f1_data,
                   sample_f2_wdata  => sample_f2_data,
                   sample_f3_wdata  => sample_f3_data);
               -----------------------------------------------------------------------------
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                 GENERIC MAP (
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_word_by_buffer_size => nb_word_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2,
                   pindex                 => pindex,
                   paddr                  => paddr,
                   pmask                  => pmask,
                   pirq_ms                => pirq_ms,
                   pirq_wfp               => pirq_wfp,
                   top_lfr_version        => top_lfr_version)
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   apbi    => apbi,
                   apbo    => apbo,
                   run_ms => run_ms,
                   ready_matrix_f0_0                      => ready_matrix_f0_0,
                   ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
                   debug_reg                              => debug_reg,
                   status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
                   status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
                   status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   matrix_time_f0_0 => matrix_time_f0_0,
                   matrix_time_f0_1 => matrix_time_f0_1,
                   matrix_time_f1   => matrix_time_f1,
                   matrix_time_f2   => matrix_time_f2,
                   addr_matrix_f0_0  => addr_matrix_f0_0,
                   addr_matrix_f0_1  => addr_matrix_f0_1,
                   addr_matrix_f1    => addr_matrix_f1,
                   addr_matrix_f2    => addr_matrix_f2,
                   status_full       => status_full,
                   status_full_ack   => status_full_ack,
                   status_full_err   => status_full_err,
                   status_new_err    => status_new_err,
                   data_shaping_BW   => data_shaping_BW,
                   data_shaping_SP0  => data_shaping_SP0,
                   data_shaping_SP1  => data_shaping_SP1,
                   data_shaping_R0   => data_shaping_R0,
                   data_shaping_R1   => data_shaping_R1,
                   delta_snapshot    => delta_snapshot,
                   delta_f0          => delta_f0,
                   delta_f0_2        => delta_f0_2,
                   delta_f1          => delta_f1,
                   delta_f2          => delta_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_word_by_buffer => nb_word_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   enable_f0         => enable_f0,
                   enable_f1         => enable_f1,
                   enable_f2         => enable_f2,
                   enable_f3         => enable_f3,
                   burst_f0          => burst_f0,
                   burst_f1          => burst_f1,
                   burst_f2          => burst_f2,
                   run               => run,
                   addr_data_f0      => addr_data_f0,
                   addr_data_f1      => addr_data_f1,
                   addr_data_f2      => addr_data_f2,
                   addr_data_f3      => addr_data_f3,
                   start_date        => start_date,
                   ---------------------------------------------------------------------------
                   debug_reg0        => debug_reg0,
                   debug_reg1        => debug_reg1,
                   debug_reg2        => debug_reg2,
                   debug_reg3        => debug_reg3,
                   debug_reg4        => debug_reg4,
                   debug_reg5        => debug_reg5,
                   debug_reg6        => debug_reg6,
                   debug_reg7        => debug_reg7);
               debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
               debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
               debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
               -----------------------------------------------------------------------------
               --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357";  -- TODO : debug
               --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB";  -- TODO : debug
               --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773";  -- TODO : debug
               --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612";  -- TODO : debug
               -----------------------------------------------------------------------------
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   tech                   => inferred,
                   data_size              => 6*16,
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_word_by_buffer_size => nb_word_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   reg_run            => run,
                   reg_start_date     => start_date,
                   reg_delta_snapshot => delta_snapshot,
                   reg_delta_f0       => delta_f0,
                   reg_delta_f0_2     => delta_f0_2,
                   reg_delta_f1       => delta_f1,
                   reg_delta_f2       => delta_f2,
                   enable_f0 => enable_f0,
                   enable_f1 => enable_f1,
                   enable_f2 => enable_f2,
                   enable_f3 => enable_f3,
                   burst_f0  => burst_f0,
                   burst_f1  => burst_f1,
                   burst_f2  => burst_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_word_by_buffer => nb_word_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   status_full       => status_full,
                   status_full_ack   => status_full_ack,
                   status_full_err   => status_full_err,
                   status_new_err    => status_new_err,
                   coarse_time => coarse_time,
                   fine_time   => fine_time,
                   --f0
                   addr_data_f0                 => addr_data_f0,
                   data_f0_in_valid             => sample_f0_val,
                   data_f0_in                   => sample_f0_data,  -- sample_f0_data_debug,  -- TODO : debug
                   --f1
                   addr_data_f1                 => addr_data_f1,
                   data_f1_in_valid             => sample_f1_val,
                   data_f1_in                   => sample_f1_data,  -- sample_f1_data_debug,  -- TODO : debug,
                   --f2
                   addr_data_f2                 => addr_data_f2,
                   data_f2_in_valid             => sample_f2_val,
                   data_f2_in                   => sample_f2_data,  -- sample_f2_data_debug,  -- TODO : debug,
                   --f3
                   addr_data_f3                 => addr_data_f3,
                   data_f3_in_valid             => sample_f3_val,
                   data_f3_in                   => sample_f3_data,  -- sample_f3_data_debug,  -- TODO : debug,
                   -- OUTPUT -- DMA interface
                   --f0
                   data_f0_addr_out             => data_f0_addr_out_s,
                   data_f0_data_out             => data_f0_data_out,
                   data_f0_data_out_valid       => data_f0_data_out_valid_s,
                   data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
                   data_f0_data_out_ren         => data_f0_data_out_ren,
                   --f1
                   data_f1_addr_out             => data_f1_addr_out_s,
                   data_f1_data_out             => data_f1_data_out,
                   data_f1_data_out_valid       => data_f1_data_out_valid_s,
                   data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
                   data_f1_data_out_ren         => data_f1_data_out_ren,
                   --f2
                   data_f2_addr_out             => data_f2_addr_out_s,
                   data_f2_data_out             => data_f2_data_out,
                   data_f2_data_out_valid       => data_f2_data_out_valid_s,
                   data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
                   data_f2_data_out_ren         => data_f2_data_out_ren,
                   --f3
                   data_f3_addr_out             => data_f3_addr_out_s,
                   data_f3_data_out             => data_f3_data_out,
                   data_f3_data_out_valid       => data_f3_data_out_valid_s,
                   data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
                   data_f3_data_out_ren         => data_f3_data_out_ren ,
                   -------------------------------------------------------------------------
                   observation_reg => OPEN
                   );
               -----------------------------------------------------------------------------
               -- TEMP
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_f0_data_out_valid       <= '0';
                   data_f0_data_out_valid_burst <= '0';
                   data_f1_data_out_valid       <= '0';
                   data_f1_data_out_valid_burst <= '0';
                   data_f2_data_out_valid       <= '0';
                   data_f2_data_out_valid_burst <= '0';
                   data_f3_data_out_valid       <= '0';
                   data_f3_data_out_valid_burst <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   data_f0_data_out_valid       <= data_f0_data_out_valid_s;
                   data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
                   data_f1_data_out_valid       <= data_f1_data_out_valid_s;
                   data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
                   data_f2_data_out_valid       <= data_f2_data_out_valid_s;
                   data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
                   data_f3_data_out_valid       <= data_f3_data_out_valid_s;
                   data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
                 END IF;
               END PROCESS;
               data_f0_addr_out <= data_f0_addr_out_s;
               data_f1_addr_out <= data_f1_addr_out_s;
               data_f2_addr_out <= data_f2_addr_out_s;
               data_f3_addr_out <= data_f3_addr_out_s;
               -----------------------------------------------------------------------------
               -- RoundRobin Selection For DMA
               -----------------------------------------------------------------------------
               dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
               dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
               dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
               dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
               RR_Arbiter_4_1 : RR_Arbiter_4
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   in_valid  => dma_rr_valid,
                   out_grant => dma_rr_grant_s);
               dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
               dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
               dma_rr_valid_ms(2) <= '0';
               dma_rr_valid_ms(3) <= '0';
               RR_Arbiter_4_2 : RR_Arbiter_4
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   in_valid  => dma_rr_valid_ms,
                   out_grant => dma_rr_grant_ms);
               dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
               -----------------------------------------------------------------------------
               -- in  : dma_rr_grant
               --       send
               -- out : dma_sel
               --       dma_valid_burst
               --       dma_sel_valid
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   dma_sel         <= (OTHERS => '0');
                   dma_send        <= '0';
                   dma_valid_burst <= '0';
                   data_ms_done    <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF run = '1' THEN
                     data_ms_done <= '0';
                     IF dma_sel = "00000" OR dma_done = '1' THEN
                       dma_sel <= dma_rr_grant;
                       IF dma_rr_grant(0) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f0_data_out_valid_burst;
                         dma_sel_valid   <= data_f0_data_out_valid;
                       ELSIF dma_rr_grant(1) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f1_data_out_valid_burst;
                         dma_sel_valid   <= data_f1_data_out_valid;
                       ELSIF dma_rr_grant(2) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f2_data_out_valid_burst;
                         dma_sel_valid   <= data_f2_data_out_valid;
                       ELSIF dma_rr_grant(3) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f3_data_out_valid_burst;
                         dma_sel_valid   <= data_f3_data_out_valid;
                       ELSIF dma_rr_grant(4) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_ms_valid_burst;
                         dma_sel_valid   <= data_ms_valid;
                       END IF;
                       IF dma_sel(4) = '1' THEN
                         data_ms_done <= '1';
                       END IF;
                     ELSE
                       dma_sel  <= dma_sel;
                       dma_send <= '0';
                     END IF;
                   ELSE
                     data_ms_done    <= '0';
                     dma_sel         <= (OTHERS => '0');
                     dma_send        <= '0';
                     dma_valid_burst <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
                              data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
                              data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
                              data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
                              data_ms_addr;
               dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
                           data_f1_data_out WHEN dma_sel(1) = '1' ELSE
                           data_f2_data_out WHEN dma_sel(2) = '1' ELSE
                           data_f3_data_out WHEN dma_sel(3) = '1' ELSE
                           data_ms_data;
               data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
               data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
               data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
               data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
               data_ms_ren          <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
               dma_data_2 <= dma_data;
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
               lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
                 GENERIC MAP (
                   tech   => inferred,
                   hindex => hindex)
                 PORT MAP (
                   HCLK           => clk,
                   HRESETn        => rstn,
                   run            => run,
                   AHB_Master_In  => ahbi,
                   AHB_Master_Out => ahbo,
                   send        => dma_send,
                   valid_burst => dma_valid_burst,
                   done        => dma_done,
                   ren         => dma_ren,
                   address     => dma_address,
                   data        => dma_data_2);
               -----------------------------------------------------------------------------
               -- Matrix Spectral
               -----------------------------------------------------------------------------
               data_ms_addr        <= (OTHERS => '0');
               data_ms_data        <= (OTHERS => '0');
               data_ms_valid       <= '0';
               data_ms_valid_burst <= '0';
               ready_matrix_f0_0             <= '0';
               ready_matrix_f0_1             <= '0';
               ready_matrix_f1               <= '0';
               ready_matrix_f2               <= '0';
               error_anticipating_empty_fifo <= '0';
               error_bad_component_error     <= '0';
               observation_reg               <= (OTHERS => '0');
               matrix_time_f2   <= (OTHERS => '0');
               matrix_time_f1   <= (OTHERS => '0');
               matrix_time_f0_1 <= (OTHERS => '0');
               matrix_time_f0_0 <= (OTHERS => '0');
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +4 -4

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             PACKAGE lpp_lfr_pkg IS
               COMPONENT lpp_lfr_ms
                 GENERIC (
                   Mem_use : INTEGER
                   );
                 PORT (
                   clk                                    : IN  STD_LOGIC;
                   rstn                                   : IN  STD_LOGIC;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                   sample_f0_wen                          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f0_wdata                        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   sample_f1_wen                          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f1_wdata                        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   sample_f3_wen                          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f3_wdata                        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   dma_addr        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_valid       : OUT STD_LOGIC;
                   dma_valid_burst : OUT STD_LOGIC;
                   dma_ren         : IN STD_LOGIC;
                   dma_done        : IN STD_LOGIC;
                   ready_matrix_f0_0                      : OUT STD_LOGIC;
                   ready_matrix_f0_1                      : OUT STD_LOGIC;
                   ready_matrix_f1                        : OUT STD_LOGIC;
                   ready_matrix_f2                        : OUT STD_LOGIC;
                   error_anticipating_empty_fifo          : OUT STD_LOGIC;
                   error_bad_component_error              : OUT STD_LOGIC;
                   debug_reg                              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0_0               : IN  STD_LOGIC;
                   status_ready_matrix_f0_1               : IN  STD_LOGIC;
                   status_ready_matrix_f1                 : IN  STD_LOGIC;
                   status_ready_matrix_f2                 : IN  STD_LOGIC;
                   status_error_anticipating_empty_fifo   : IN  STD_LOGIC;
                   status_error_bad_component_error       : IN  STD_LOGIC;
                   config_active_interruption_onNewMatrix : IN  STD_LOGIC;
                   config_active_interruption_onError     : IN  STD_LOGIC;
                   addr_matrix_f0_0                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   matrix_time_f0_0                       : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f0_1                       : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_lfr_ms_fsmdma
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   data_time                              : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   fifo_data                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty                             : IN  STD_LOGIC;
                   fifo_ren                               : OUT STD_LOGIC;
                   header                                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val                             : IN  STD_LOGIC;
                   header_ack                             : OUT STD_LOGIC;
                   dma_addr                               : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_data                               : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_valid                              : OUT STD_LOGIC;
                   dma_valid_burst                        : OUT STD_LOGIC;
                   dma_ren                                : IN  STD_LOGIC;
                   dma_done                               : IN  STD_LOGIC;
                   ready_matrix_f0_0                      : OUT STD_LOGIC;
                   ready_matrix_f0_1                      : OUT STD_LOGIC;
                   ready_matrix_f1                        : OUT STD_LOGIC;
                   ready_matrix_f2                        : OUT STD_LOGIC;
                   error_anticipating_empty_fifo          : OUT STD_LOGIC;
                   error_bad_component_error              : OUT STD_LOGIC;
                   debug_reg                              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0_0               : IN  STD_LOGIC;
                   status_ready_matrix_f0_1               : IN  STD_LOGIC;
                   status_ready_matrix_f1                 : IN  STD_LOGIC;
                   status_ready_matrix_f2                 : IN  STD_LOGIC;
                   status_error_anticipating_empty_fifo   : IN  STD_LOGIC;
                   status_error_bad_component_error       : IN  STD_LOGIC;
                   config_active_interruption_onNewMatrix : IN  STD_LOGIC;
                   config_active_interruption_onError     : IN  STD_LOGIC;
                   addr_matrix_f0_0                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   matrix_time_f0_0                       : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f0_1                       : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_lfr_filter
                 GENERIC (
                   Mem_use : INTEGER);
                 PORT (
                   sample           : IN  Samples(7 DOWNTO 0);
                   sample_val       : IN  STD_LOGIC;
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                   data_shaping_SP0 : IN  STD_LOGIC;
                   data_shaping_SP1 : IN  STD_LOGIC;
                   data_shaping_R0  : IN  STD_LOGIC;
                   data_shaping_R1  : IN  STD_LOGIC;
                   sample_f0_val    : OUT STD_LOGIC;
                   sample_f1_val    : OUT STD_LOGIC;
                   sample_f2_val    : OUT STD_LOGIC;
                   sample_f3_val    : OUT STD_LOGIC;
                   sample_f0_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f1_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f2_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f3_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_lfr
                 GENERIC (
                   Mem_use                : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   hindex                 : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0)
                   );
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
-                  sample_B        : IN  Samples14v(2 DOWNTO 0);
+                  sample_B        : IN  Samples(2 DOWNTO 0);
-                  sample_E        : IN  Samples14v(4 DOWNTO 0);
+                  sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi            : IN  AHB_Mst_In_Type;
                   ahbo            : OUT AHB_Mst_Out_Type;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_shaping_BW : OUT STD_LOGIC;
                   observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                   );
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_WFP_nMS
                 GENERIC (
                   Mem_use                : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   hindex                 : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0));
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
-                  sample_B        : IN  Samples14v(2 DOWNTO 0);
+                  sample_B        : IN  Samples(2 DOWNTO 0);
-                  sample_E        : IN  Samples14v(4 DOWNTO 0);
+                  sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi            : IN  AHB_Mst_In_Type;
                   ahbo            : OUT AHB_Mst_Out_Type;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_shaping_BW : OUT STD_LOGIC;
                   observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_apbreg
                 GENERIC (
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0));
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   apbi                                   : IN  apb_slv_in_type;
                   apbo                                   : OUT apb_slv_out_type;
                   run_ms                                 : OUT STD_LOGIC;
                   ready_matrix_f0_0                      : IN  STD_LOGIC;
                   ready_matrix_f0_1                      : IN  STD_LOGIC;
                   ready_matrix_f1                        : IN  STD_LOGIC;
                   ready_matrix_f2                        : IN  STD_LOGIC;
                   error_anticipating_empty_fifo          : IN  STD_LOGIC;
                   error_bad_component_error              : IN  STD_LOGIC;
                   debug_reg                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0_0               : OUT STD_LOGIC;
                   status_ready_matrix_f0_1               : OUT STD_LOGIC;
                   status_ready_matrix_f1                 : OUT STD_LOGIC;
                   status_ready_matrix_f2                 : OUT STD_LOGIC;
                   status_error_anticipating_empty_fifo   : OUT STD_LOGIC;
                   status_error_bad_component_error       : OUT STD_LOGIC;
                   config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                   config_active_interruption_onError     : OUT STD_LOGIC;
                   addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   matrix_time_f0_0                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f0_1                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   status_full                            : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack                        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err                        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_new_err                         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_shaping_BW                        : OUT STD_LOGIC;
                   data_shaping_SP0                       : OUT STD_LOGIC;
                   data_shaping_SP1                       : OUT STD_LOGIC;
                   data_shaping_R0                        : OUT STD_LOGIC;
                   data_shaping_R1                        : OUT STD_LOGIC;
                   delta_snapshot                         : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0                               : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0_2                             : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                   delta_f1                               : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f2                               : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   nb_data_by_buffer                      : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   nb_word_by_buffer                      : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                   nb_snapshot_param                      : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   enable_f0                              : OUT STD_LOGIC;
                   enable_f1                              : OUT STD_LOGIC;
                   enable_f2                              : OUT STD_LOGIC;
                   enable_f3                              : OUT STD_LOGIC;
                   burst_f0                               : OUT STD_LOGIC;
                   burst_f1                               : OUT STD_LOGIC;
                   burst_f2                               : OUT STD_LOGIC;
                   run                                    : OUT STD_LOGIC;
                   addr_data_f0                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   start_date                             : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
                   ---------------------------------------------------------------------------
                   debug_reg0                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg1                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg2                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg3                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg4                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg5                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg6                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg7                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_top_ms
                 GENERIC (
                   Mem_use                 : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   pindex                  : INTEGER;
                   paddr                   : INTEGER;
                   pmask                   : INTEGER;
                   pirq_ms                 : INTEGER;
                   pirq_wfp                : INTEGER;
                   hindex_wfp              : INTEGER;
                   hindex_ms               : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   sample_B        : IN  Samples14v(2 DOWNTO 0);
                   sample_E        : IN  Samples14v(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi_ms         : IN  AHB_Mst_In_Type;
                   ahbo_ms         : OUT AHB_Mst_Out_Type;
                   data_shaping_BW : OUT STD_LOGIC;
                   matrix_time_f0_0                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f0_1                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
                   );
               END COMPONENT;
             END lpp_lfr_pkg;

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