HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r347:326fa6e96475

Update Sample transformation from ADC to IIR_FILTER

pellion -

r347:326fa6e96475 JC

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r347:326fa6e96475

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designs/LFR-em-WFP_MS/LFR-em.vhd +9 -3

             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
+              SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"00010A")  -- aa.bb.cc version
+                  top_lfr_version        => X"00010B")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         -- 0 => MINI_LFR
                                                         -- 1 => EM
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => rstn,
-                  sample_B        => sample(2 DOWNTO 0),
+                  sample_B        => sample_s(2 DOWNTO 0),
-                  sample_E        => sample(7 DOWNTO 3),
+                  sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   data_shaping_BW => bias_fail_sw,
                   observation_reg => observation_reg);
+              all_sample: FOR I IN 7 DOWNTO 0 GENERATE
+                sample_s(I) <= sample(I) & '0' & '0';
+              END GENERATE all_sample;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +9 -2

             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
+              SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => reset,
-                  sample_B        => sample(2 DOWNTO 0),
+                  sample_B        => sample_s(2 DOWNTO 0),
-                  sample_E        => sample(7 DOWNTO 3),
+                  sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   data_shaping_BW => bias_fail_sw_sig,
                   observation_reg => observation_reg);
+              all_sample: FOR I IN 7 DOWNTO 0 GENERATE
+                sample_s(I) <= sample(I) & '0' & '0';
+              END GENERATE all_sample;
               top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
                 GENERIC MAP(
                   ChannelCount    => 8,

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +8 -8

                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
-                sample_B        : IN  Samples14v(2 DOWNTO 0);
+                sample_B        : IN  Samples(2 DOWNTO 0);
-                sample_E        : IN  Samples14v(4 DOWNTO 0);
+                sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
             END lpp_lfr;
             ARCHITECTURE beh OF lpp_lfr IS
-              SIGNAL sample           : Samples14v(7 DOWNTO 0);
+              --SIGNAL sample           : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
             BEGIN
-              sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
+              sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
-              sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
+              sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
-              all_channel : FOR i IN 7 DOWNTO 0 GENERATE
+              --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
-                sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
+              --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
-              END GENERATE all_channel;
+              --END GENERATE all_channel;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter

lib/lpp/lpp_top_lfr/lpp_lfr_WFP_nMS.vhd +9 -8

                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
-                sample_B        : IN  Samples14v(2 DOWNTO 0);
+                sample_B        : IN  Samples(2 DOWNTO 0);
-                sample_E        : IN  Samples14v(4 DOWNTO 0);
+                sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
             END lpp_lfr_WFP_nMS;
             ARCHITECTURE beh OF lpp_lfr_WFP_nMS IS
-              SIGNAL sample           : Samples14v(7 DOWNTO 0);
+            --  SIGNAL sample           : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
             BEGIN
-              sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
+              sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
-              sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
+              sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
-              all_channel : FOR i IN 7 DOWNTO 0 GENERATE
+              --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
-                sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
+              --  --sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
-              END GENERATE all_channel;
+              --  sample_s(i) <= sample(i) & '0' & '0';
+              --END GENERATE all_channel;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +4 -4

                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
-                  sample_B        : IN  Samples14v(2 DOWNTO 0);
+                  sample_B        : IN  Samples(2 DOWNTO 0);
-                  sample_E        : IN  Samples14v(4 DOWNTO 0);
+                  sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
-                  sample_B        : IN  Samples14v(2 DOWNTO 0);
+                  sample_B        : IN  Samples(2 DOWNTO 0);
-                  sample_E        : IN  Samples14v(4 DOWNTO 0);
+                  sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;

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