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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
29
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33
34 ENTITY IIR_CEL_CTRLR_v2 IS
35 GENERIC (
36 tech : INTEGER := apa3;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
44 PORT (
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
51 sample_in_val : IN STD_LOGIC;
52 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53
54 sample_out_val : OUT STD_LOGIC;
55 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
56 END IIR_CEL_CTRLR_v2;
57
58 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
59
60 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
61 GENERIC (
62 tech : INTEGER;
63 Mem_use : INTEGER;
64 Sample_SZ : INTEGER;
65 Coef_SZ : INTEGER;
66 Coef_Nb : INTEGER;
67 Coef_sel_SZ : INTEGER);
68 PORT (
69 rstn : IN STD_LOGIC;
70 clk : IN STD_LOGIC;
71 virg_pos : IN INTEGER;
72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
74 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
75 ram_write : IN STD_LOGIC;
76 ram_read : IN STD_LOGIC;
77 raddr_rst : IN STD_LOGIC;
78 raddr_add1 : IN STD_LOGIC;
79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 alu_sel_input : IN STD_LOGIC;
81 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
82 alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
83 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
84 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
85 END COMPONENT;
86
87 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
88 GENERIC (
89 Coef_sel_SZ : INTEGER;
90 Cels_count : INTEGER;
91 ChanelsCount : INTEGER);
92 PORT (
93 rstn : IN STD_LOGIC;
94 clk : IN STD_LOGIC;
95 sample_in_val : IN STD_LOGIC;
96 sample_in_rot : OUT STD_LOGIC;
97 sample_out_val : OUT STD_LOGIC;
98 sample_out_rot : OUT STD_LOGIC;
99 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
100 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 ram_write : OUT STD_LOGIC;
102 ram_read : OUT STD_LOGIC;
103 raddr_rst : OUT STD_LOGIC;
104 raddr_add1 : OUT STD_LOGIC;
105 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
106 alu_sel_input : OUT STD_LOGIC;
107 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
108 alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
109 END COMPONENT;
110
111 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
112 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
113 SIGNAL ram_write : STD_LOGIC;
114 SIGNAL ram_read : STD_LOGIC;
115 SIGNAL raddr_rst : STD_LOGIC;
116 SIGNAL raddr_add1 : STD_LOGIC;
117 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL alu_sel_input : STD_LOGIC;
119 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
120 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(3 DOWNTO 0);
121
122 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
123 SIGNAL sample_in_rotate : STD_LOGIC;
124 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
125 SIGNAL sample_out_val_s : STD_LOGIC;
126 SIGNAL sample_out_val_s2 : STD_LOGIC;
127 SIGNAL sample_out_rot_s : STD_LOGIC;
128 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
129
130 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
131
132 BEGIN
133
134 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
135 GENERIC MAP (
136 tech => tech,
137 Mem_use => Mem_use,
138 Sample_SZ => Sample_SZ,
139 Coef_SZ => Coef_SZ,
140 Coef_Nb => Coef_Nb,
141 Coef_sel_SZ => Coef_sel_SZ)
142 PORT MAP (
143 rstn => rstn,
144 clk => clk,
145 virg_pos => virg_pos,
146 coefs => coefs,
147 --CTRL
148 in_sel_src => in_sel_src,
149 ram_sel_Wdata => ram_sel_Wdata,
150 ram_write => ram_write,
151 ram_read => ram_read,
152 raddr_rst => raddr_rst,
153 raddr_add1 => raddr_add1,
154 waddr_previous => waddr_previous,
155 alu_sel_input => alu_sel_input,
156 alu_sel_coeff => alu_sel_coeff,
157 alu_ctrl => alu_ctrl,
158 --DATA
159 sample_in => sample_in_s,
160 sample_out => sample_out_s);
161
162
163 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
164 GENERIC MAP (
165 Coef_sel_SZ => Coef_sel_SZ,
166 Cels_count => Cels_count,
167 ChanelsCount => ChanelsCount)
168 PORT MAP (
169 rstn => rstn,
170 clk => clk,
171 sample_in_val => sample_in_val,
172 sample_in_rot => sample_in_rotate,
173 sample_out_val => sample_out_val_s,
174 sample_out_rot => sample_out_rot_s,
175
176 in_sel_src => in_sel_src,
177 ram_sel_Wdata => ram_sel_Wdata,
178 ram_write => ram_write,
179 ram_read => ram_read,
180 raddr_rst => raddr_rst,
181 raddr_add1 => raddr_add1,
182 waddr_previous => waddr_previous,
183 alu_sel_input => alu_sel_input,
184 alu_sel_coeff => alu_sel_coeff,
185 alu_ctrl => alu_ctrl);
186
187 -----------------------------------------------------------------------------
188 -- SAMPLE IN
189 -----------------------------------------------------------------------------
190 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
191
192 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
193 PROCESS (clk, rstn)
194 BEGIN -- PROCESS
195 IF rstn = '0' THEN -- asynchronous reset (active low)
196 sample_in_buf(I, J) <= '0';
197 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 IF sample_in_val = '1' THEN
199 sample_in_buf(I, J) <= sample_in(I, J);
200 ELSIF sample_in_rotate = '1' THEN
201 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
202 END IF;
203 END IF;
204 END PROCESS;
205 END GENERATE loop_all_chanel;
206
207 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
208
209 END GENERATE loop_all_sample;
210
211 -----------------------------------------------------------------------------
212 -- SAMPLE OUT
213 -----------------------------------------------------------------------------
214 PROCESS (clk, rstn)
215 BEGIN -- PROCESS
216 IF rstn = '0' THEN -- asynchronous reset (active low)
217 sample_out_val <= '0';
218 sample_out_val_s2 <= '0';
219 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
220 sample_out_val <= sample_out_val_s2;
221 sample_out_val_s2 <= sample_out_val_s;
222 END IF;
223 END PROCESS;
224
225 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
226 PROCESS (clk, rstn)
227 BEGIN -- PROCESS
228 IF rstn = '0' THEN -- asynchronous reset (active low)
229 sample_out_s2(ChanelsCount-1, I) <= '0';
230 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
231 IF sample_out_rot_s = '1' THEN
232 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
233 END IF;
234 END IF;
235 END PROCESS;
236 END GENERATE chanel_HIGH;
237
238 chanel_more : IF ChanelsCount > 1 GENERATE
239 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
240 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
241 PROCESS (clk, rstn)
242 BEGIN -- PROCESS
243 IF rstn = '0' THEN -- asynchronous reset (active low)
244 sample_out_s2(J-1, I) <= '0';
245 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
246 IF sample_out_rot_s = '1' THEN
247 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
248 END IF;
249 END IF;
250 END PROCESS;
251 END GENERATE all_bit;
252 END GENERATE all_chanel;
253 END GENERATE chanel_more;
254
255 sample_out <= sample_out_s2;
256 END ar_IIR_CEL_CTRLR_v2;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more Cdetails.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26 LIBRARY lpp;
27 USE lpp.iir_filter.ALL;
28 USE lpp.general_purpose.ALL;
29
30 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
31 GENERIC (
32 Coef_sel_SZ : INTEGER;
33 Cels_count : INTEGER := 5;
34 ChanelsCount : INTEGER := 1);
35 PORT (
36 rstn : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
38
39 sample_in_val : IN STD_LOGIC;
40 sample_in_rot : OUT STD_LOGIC;
41 sample_out_val : OUT STD_LOGIC;
42 sample_out_rot : OUT STD_LOGIC;
43
44 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
45 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46 ram_write : OUT STD_LOGIC;
47 ram_read : OUT STD_LOGIC;
48 raddr_rst : OUT STD_LOGIC;
49 raddr_add1 : OUT STD_LOGIC;
50 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 alu_sel_input : OUT STD_LOGIC;
52 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
53 alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
54 );
55 END IIR_CEL_CTRLR_v2_CONTROL;
56
57 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
58
59 TYPE fsmIIR_CEL_T IS (waiting,
60 first_read,
61 compute_b0,
62 compute_b1,
63 compute_b2,
64 compute_a1,
65 compute_a2,
66 LAST_CEL,
67 wait_valid_last_output,
68 wait_valid_last_output_2);
69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
70
71 SIGNAL alu_selected_coeff : INTEGER;
72 SIGNAL Chanel_ongoing : INTEGER;
73 SIGNAL Cel_ongoing : INTEGER;
74
75 BEGIN
76
77 alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
78
79 PROCESS (clk, rstn)
80 BEGIN -- PROCESS
81 IF rstn = '0' THEN -- asynchronous reset (active low)
82 --REG -------------------------------------------------------------------
83 in_sel_src <= (OTHERS => '0'); --
84 --RAM_WRitE -------------------------------------------------------------
85 ram_sel_Wdata <= "00"; --
86 ram_write <= '0'; --
87 waddr_previous <= "00"; --
88 --RAM_READ --------------------------------------------------------------
89 ram_read <= '0'; --
90 raddr_rst <= '0'; --
91 raddr_add1 <= '0'; --
92 --ALU -------------------------------------------------------------------
93 alu_selected_coeff <= 0; --
94 alu_sel_input <= '0'; --
95 alu_ctrl <= (OTHERS => '0'); --
96 --OUT
97 sample_out_val <= '0'; --
98 sample_out_rot <= '0'; --
99
100 Chanel_ongoing <= 0; --
101 Cel_ongoing <= 0; --
102 sample_in_rot <= '0';
103
104 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
105
106 CASE IIR_CEL_STATE IS
107 WHEN waiting =>
108 sample_out_rot <= '0';
109 sample_in_rot <= '0';
110 sample_out_val <= '0';
111 alu_ctrl <= "0100";
112 alu_selected_coeff <= 0;
113 in_sel_src <= "01";
114 ram_read <= '0';
115 ram_sel_Wdata <= "00";
116 ram_write <= '0';
117 waddr_previous <= "00";
118 IF sample_in_val = '1' THEN
119 raddr_rst <= '0';
120 alu_sel_input <= '1';
121 ram_read <= '1';
122 raddr_add1 <= '1';
123 IIR_CEL_STATE <= first_read;
124 Chanel_ongoing <= Chanel_ongoing + 1;
125 Cel_ongoing <= 1;
126 ELSE
127 raddr_add1 <= '0';
128 raddr_rst <= '1';
129 Chanel_ongoing <= 0;
130 Cel_ongoing <= 0;
131 END IF;
132
133 WHEN first_read =>
134 IIR_CEL_STATE <= compute_b2;
135 ram_read <= '1';
136 raddr_add1 <= '1';
137 alu_ctrl <= "0010";
138 alu_sel_input <= '1';
139 in_sel_src <= "01";
140
141
142 WHEN compute_b2 =>
143 sample_out_rot <= '0';
144
145 sample_in_rot <= '0';
146 sample_out_val <= '0';
147
148 alu_sel_input <= '1';
149 --
150 ram_sel_Wdata <= "10";
151 ram_write <= '1';
152 waddr_previous <= "10";
153 --
154 ram_read <= '1';
155 raddr_rst <= '0';
156 raddr_add1 <= '0';
157 IF Cel_ongoing = 1 THEN
158 in_sel_src <= "00";
159 ELSE
160 in_sel_src <= "11";
161 END IF;
162 alu_selected_coeff <= alu_selected_coeff+1;
163 alu_ctrl <= "0001";
164 IIR_CEL_STATE <= compute_b1;
165
166 WHEN compute_b1 =>
167 sample_in_rot <= '0';
168 alu_sel_input <= '0';
169 --
170 ram_sel_Wdata <= "00";
171 ram_write <= '1';
172 waddr_previous <= "01";
173 --
174 ram_read <= '1';
175 raddr_rst <= '0';
176 raddr_add1 <= '1';
177 sample_out_rot <= '0';
178 IF Cel_ongoing = 1 THEN
179 in_sel_src <= "10";
180 sample_out_val <= '0';
181 ELSE
182 sample_out_val <= '0';
183 in_sel_src <= "00";
184 END IF;
185 alu_selected_coeff <= alu_selected_coeff+1;
186 alu_ctrl <= "0001";
187 IIR_CEL_STATE <= compute_b0;
188
189 WHEN compute_b0 =>
190 sample_out_rot <= '0';
191 sample_out_val <= '0';
192 sample_in_rot <= '0';
193 alu_sel_input <= '1';
194 ram_sel_Wdata <= "00";
195 ram_write <= '0';
196 waddr_previous <= "01";
197 ram_read <= '1';
198 raddr_rst <= '0';
199 raddr_add1 <= '0';
200 in_sel_src <= "10";
201 alu_selected_coeff <= alu_selected_coeff+1;
202 alu_ctrl <= "0001";
203 IIR_CEL_STATE <= compute_a2;
204 IF Cel_ongoing = Cels_count THEN
205 sample_in_rot <= '1';
206 ELSE
207 sample_in_rot <= '0';
208 END IF;
209
210 WHEN compute_a2 =>
211 sample_out_val <= '0';
212 sample_out_rot <= '0';
213 alu_sel_input <= '1';
214 ram_sel_Wdata <= "00";
215 ram_write <= '0';
216 waddr_previous <= "01";
217 ram_read <= '1';
218 raddr_rst <= '0';
219 IF Cel_ongoing = Cels_count THEN
220 raddr_add1 <= '1';
221 ELSE
222 raddr_add1 <= '0';
223 END IF;
224 in_sel_src <= "00";
225 alu_selected_coeff <= alu_selected_coeff+1;
226 alu_ctrl <= "0001";
227 IIR_CEL_STATE <= compute_a1;
228 sample_in_rot <= '0';
229
230 WHEN compute_a1 =>
231 sample_out_val <= '0';
232 sample_out_rot <= '0';
233 alu_sel_input <= '0';
234 ram_sel_Wdata <= "00";
235 ram_write <= '0';
236 waddr_previous <= "01";
237 ram_read <= '1';
238 raddr_rst <= '0';
239 alu_ctrl <= "0010";
240 sample_in_rot <= '0';
241 IF Cel_ongoing = Cels_count THEN
242 alu_selected_coeff <= 0;
243
244 ram_sel_Wdata <= "10";
245 raddr_add1 <= '1';
246 ram_write <= '1';
247 waddr_previous <= "10";
248
249 IF Chanel_ongoing = ChanelsCount THEN
250 IIR_CEL_STATE <= wait_valid_last_output;
251 ELSE
252 Chanel_ongoing <= Chanel_ongoing + 1;
253 Cel_ongoing <= 1;
254 IIR_CEL_STATE <= LAST_CEL;
255 in_sel_src <= "01";
256 END IF;
257 ELSE
258 raddr_add1 <= '1';
259 alu_selected_coeff <= alu_selected_coeff+1;
260 Cel_ongoing <= Cel_ongoing+1;
261 IIR_CEL_STATE <= compute_b2;
262 END IF;
263
264 WHEN LAST_CEL =>
265 alu_sel_input <= '1';
266 IIR_CEL_STATE <= compute_b2;
267 raddr_add1 <= '1';
268 ram_sel_Wdata <= "01";
269 ram_write <= '1';
270 waddr_previous <= "10";
271 sample_out_rot <= '1';
272
273
274 WHEN wait_valid_last_output =>
275 IIR_CEL_STATE <= wait_valid_last_output_2;
276 sample_in_rot <= '0';
277 alu_ctrl <= "0000";
278 alu_selected_coeff <= 0;
279 in_sel_src <= "01";
280 ram_read <= '0';
281 raddr_rst <= '1';
282 raddr_add1 <= '1';
283 ram_sel_Wdata <= "01";
284 ram_write <= '1';
285 waddr_previous <= "10";
286 Chanel_ongoing <= 0;
287 Cel_ongoing <= 0;
288 sample_out_val <= '0';
289 sample_out_rot <= '1';
290
291 WHEN wait_valid_last_output_2 =>
292 IIR_CEL_STATE <= waiting;
293 sample_in_rot <= '0';
294 alu_ctrl <= "0000";
295 alu_selected_coeff <= 0;
296 in_sel_src <= "01";
297 ram_read <= '0';
298 raddr_rst <= '1';
299 raddr_add1 <= '1';
300 ram_sel_Wdata <= "10";
301 ram_write <= '1';
302 waddr_previous <= "10";
303 Chanel_ongoing <= 0;
304 Cel_ongoing <= 0;
305 sample_out_val <= '1';
306 sample_out_rot <= '0';
307 WHEN OTHERS => NULL;
308 END CASE;
309
310 END IF;
311 END PROCESS;
312
313 END ar_IIR_CEL_CTRLR_v2_CONTROL;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
27 USE lpp.general_purpose.ALL;
28
29
30
31 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
32 GENERIC(
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
35 Sample_SZ : INTEGER := 16;
36 Coef_SZ : INTEGER := 9;
37 Coef_Nb : INTEGER := 30;
38 Coef_sel_SZ : INTEGER := 5
39 );
40 PORT(
41 rstn : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
43 -- PARAMETER
44 virg_pos : IN INTEGER;
45 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
46 -- CONTROL
47 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 --
49 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 ram_write : IN STD_LOGIC;
51 ram_read : IN STD_LOGIC;
52 raddr_rst : IN STD_LOGIC;
53 raddr_add1 : IN STD_LOGIC;
54 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
55 --
56 alu_sel_input : IN STD_LOGIC;
57 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
58 alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
59 -- DATA
60 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
61 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
62 );
63 END IIR_CEL_CTRLR_v2_DATAFLOW;
64
65 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
66
67 COMPONENT RAM_CTRLR_v2
68 GENERIC (
69 tech : INTEGER;
70 Input_SZ_1 : INTEGER;
71 Mem_use : INTEGER);
72 PORT (
73 rstn : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 ram_write : IN STD_LOGIC;
76 ram_read : IN STD_LOGIC;
77 raddr_rst : IN STD_LOGIC;
78 raddr_add1 : IN STD_LOGIC;
79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
81 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
82 END COMPONENT;
83
84 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
85 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
86 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
87 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
88 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
89 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
90
91 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
92 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
93
94 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
95
96 BEGIN
97
98 -----------------------------------------------------------------------------
99 -- INPUT
100 -----------------------------------------------------------------------------
101 PROCESS (clk, rstn)
102 BEGIN -- PROCESS
103 IF rstn = '0' THEN -- asynchronous reset (active low)
104 reg_sample_in <= (OTHERS => '0');
105 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
106 CASE in_sel_src IS
107 WHEN "00" => reg_sample_in <= reg_sample_in;
108 WHEN "01" => reg_sample_in <= sample_in;
109 WHEN "10" => reg_sample_in <= ram_output;
110 WHEN "11" => reg_sample_in <= alu_output;
111 WHEN OTHERS => NULL;
112 END CASE;
113 END IF;
114 END PROCESS;
115
116
117 -----------------------------------------------------------------------------
118 -- RAM + CTRL
119 -----------------------------------------------------------------------------
120
121 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
122 alu_output WHEN ram_sel_Wdata = "01" ELSE
123 ram_output;
124
125 RAM_CTRLR_v2_1: RAM_CTRLR_v2
126 GENERIC MAP (
127 tech => tech,
128 Input_SZ_1 => Sample_SZ,
129 Mem_use => Mem_use)
130 PORT MAP (
131 clk => clk,
132 rstn => rstn,
133 ram_write => ram_write,
134 ram_read => ram_read,
135 raddr_rst => raddr_rst,
136 raddr_add1 => raddr_add1,
137 waddr_previous => waddr_previous,
138 sample_in => ram_input,
139 sample_out => ram_output);
140
141 -----------------------------------------------------------------------------
142 -- MAC_ACC
143 -----------------------------------------------------------------------------
144 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
145 -- Data In : mac_sample, mac_coef
146 -- Data Out: mac_output
147
148 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
149
150 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
151 coeff_in: IF I < Coef_Nb GENERATE
152 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
153 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
154 END GENERATE all_bit;
155 END GENERATE coeff_in;
156 coeff_null: IF I > (Coef_Nb -1) GENERATE
157 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
158 arrayCoeff(I,J) <= '0';
159 END GENERATE all_bit;
160 END GENERATE coeff_null;
161 END GENERATE coefftable;
162
163 Coeff_Mux : MUXN
164 GENERIC MAP (
165 Input_SZ => Coef_SZ,
166 NbStage => Coef_sel_SZ)
167 PORT MAP (
168 sel => alu_sel_coeff,
169 INPUT => arrayCoeff,
170 RES => alu_coef_s);
171
172
173 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
174 alu_coef(J) <= alu_coef_s(J);
175 END GENERATE all_bit;
176
177 -----------------------------------------------------------------------------
178 -- TODO : just for Synthesis test
179
180 --PROCESS (clk, rstn)
181 --BEGIN
182 -- IF rstn = '0' THEN
183 -- alu_coef <= (OTHERS => '0');
184 -- ELSIF clk'event AND clk = '1' THEN
185 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
186 -- alu_coef(J) <= alu_coef_s(J);
187 -- END LOOP all_bit;
188 -- END IF;
189 --END PROCESS;
190
191 -----------------------------------------------------------------------------
192
193
194 ALU_1: ALU
195 GENERIC MAP (
196 Arith_en => 1,
197 Input_SZ_1 => Sample_SZ,
198 Input_SZ_2 => Coef_SZ)
199 PORT MAP (
200 clk => clk,
201 reset => rstn,
202 ctrl => alu_ctrl,
203 OP1 => alu_sample,
204 OP2 => alu_coef,
205 RES => alu_output_s);
206
207 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
208
209 sample_out <= alu_output;
210
211 END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
27 USE lpp.FILTERcfg.ALL;
28 USE lpp.general_purpose.ALL;
29 LIBRARY techmap;
30 USE techmap.gencomp.ALL;
31
32 ENTITY RAM_CTRLR_v2 IS
33 GENERIC(
34 tech : INTEGER := 0;
35 Input_SZ_1 : INTEGER := 16;
36 Mem_use : INTEGER := use_RAM
37 );
38 PORT(
39 rstn : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 -- R/W Ctrl
42 ram_write : IN STD_LOGIC;
43 ram_read : IN STD_LOGIC;
44 -- ADDR Ctrl
45 raddr_rst : IN STD_LOGIC;
46 raddr_add1 : IN STD_LOGIC;
47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 -- Data
49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
51 );
52 END RAM_CTRLR_v2;
53
54
55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
56
57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 SIGNAL WEN, REN : STD_LOGIC;
60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
63
64 BEGIN
65
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
68 -----------------------------------------------------------------------------
69 -- RAM
70 -----------------------------------------------------------------------------
71
72 memCEL : IF Mem_use = use_CEL GENERATE
73 WEN <= NOT ram_write;
74 REN <= NOT ram_read;
75 RAMblk : RAM_CEL
76 GENERIC MAP(Input_SZ_1)
77 PORT MAP(
78 WD => WD,
79 RD => RD,
80 WEN => WEN,
81 REN => REN,
82 WADDR => WADDR,
83 RADDR => RADDR,
84 RWCLK => clk,
85 RESET => rstn
86 ) ;
87 END GENERATE;
88
89 memRAM : IF Mem_use = use_RAM GENERATE
90 SRAM : syncram_2p
91 GENERIC MAP(tech, 8, Input_SZ_1)
92 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
93 END GENERATE;
94
95 -----------------------------------------------------------------------------
96 -- RADDR
97 -----------------------------------------------------------------------------
98 PROCESS (clk, rstn)
99 BEGIN -- PROCESS
100 IF rstn = '0' THEN -- asynchronous reset (active low)
101 counter <= (OTHERS => '0');
102 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
103 IF raddr_rst = '1' THEN
104 counter <= (OTHERS => '0');
105 ELSIF raddr_add1 = '1' THEN
106 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
107 END IF;
108 END IF;
109 END PROCESS;
110 RADDR <= counter;
111
112 -----------------------------------------------------------------------------
113 -- WADDR
114 -----------------------------------------------------------------------------
115 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
116 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
117 STD_LOGIC_VECTOR(UNSIGNED(counter));
118
119
120 END ar_RAM_CTRLR_v2;
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@@ -0,0 +1,86
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : Jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27
28 ENTITY MUXN IS
29 GENERIC(
30 Input_SZ : INTEGER := 16;
31 NbStage : INTEGER := 2);
32 PORT(
33 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
34 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
35 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
36 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
37 END ENTITY;
38
39 ARCHITECTURE ar_MUXN OF MUXN IS
40 COMPONENT MUXN
41 GENERIC (
42 Input_SZ : INTEGER;
43 NbStage : INTEGER);
44 PORT (
45 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
46 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
47 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
48 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
49 END COMPONENT;
50
51 --SIGNAL S : ARRAY (0 TO (2**(NbStage-1)-1)) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
52 SIGNAL S: MUX_INPUT_TYPE(0 TO (2**(NbStage-1))-1,Input_SZ-1 DOWNTO 0);
53
54
55 BEGIN
56
57 all_input : FOR I IN 0 TO (2**(NbStage-1))-1 GENERATE
58 all_input: FOR J IN Input_SZ-1 DOWNTO 0 GENERATE
59 S(I,J) <= INPUT(2*I,J) WHEN sel(0) = '0' ELSE INPUT(2*I+1,J);
60 END GENERATE all_input;
61 END GENERATE all_input;
62
63 NB_STAGE_1: IF NbStage = 1 GENERATE
64 all_input: FOR J IN Input_SZ-1 DOWNTO 0 GENERATE
65 RES(J) <= S(0,J);
66 END GENERATE all_input;
67 END GENERATE NB_STAGE_1;
68
69 NB_STAGE_2 : IF NbStage = 2 GENERATE
70 all_input: FOR I IN Input_SZ-1 DOWNTO 0 GENERATE
71 RES(I) <= S(0,I) WHEN sel(1) = '0' ELSE S(1,I);
72 END GENERATE all_input;
73 END GENERATE NB_STAGE_2;
74
75 NB_STAGE_PLUS : IF NbStage > 2 GENERATE
76 MUXN_1 : MUXN
77 GENERIC MAP (
78 Input_SZ => Input_SZ,
79 NbStage => NbStage-1)
80 PORT MAP (
81 sel => sel(NbStage-1 DOWNTO 1),
82 INPUT => S,
83 RES => RES);
84 END GENERATE NB_STAGE_PLUS;
85
86 END ar_MUXN;
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@@ -0,0 +1,57
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 ENTITY SYNC_FF IS
27
28 GENERIC (
29 NB_FF_OF_SYNC : INTEGER := 2);
30
31 PORT (
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 A : IN STD_LOGIC;
35 A_sync : OUT STD_LOGIC);
36
37 END SYNC_FF;
38
39 ARCHITECTURE beh OF SYNC_FF IS
40 SIGNAL A_temp : STD_LOGIC_VECTOR(NB_FF_OF_SYNC DOWNTO 0);
41 BEGIN -- beh
42
43 sync_loop : FOR I IN 0 TO NB_FF_OF_SYNC-1 GENERATE
44 PROCESS (clk, rstn)
45 BEGIN -- PROCESS
46 IF rstn = '0' THEN -- asynchronous reset (active low)
47 A_temp(I) <= '0';
48 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
49 A_temp(I) <= A_temp(I+1);
50 END IF;
51 END PROCESS;
52 END GENERATE sync_loop;
53
54 A_temp(NB_FF_OF_SYNC) <= A;
55 A_sync <= A_temp(0);
56
57 END beh;
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@@ -0,0 +1,70
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.std_logic_arith.ALL;
25 USE IEEE.std_logic_signed.ALL;
26 USE IEEE.MATH_real.ALL;
27
28 ENTITY TestModule_ADS7886 IS
29 GENERIC (
30 freq : INTEGER := 24;
31 amplitude : INTEGER := 3000;
32 impulsion : INTEGER := 0 -- 1 => impulsion generation
33 );
34 PORT (
35 -- CONV --
36 cnv_run : IN STD_LOGIC;
37 cnv : IN STD_LOGIC;
38
39 -- DATA --
40 sck : IN STD_LOGIC;
41 sdo : OUT STD_LOGIC
42 );
43 END TestModule_ADS7886;
44
45 ARCHITECTURE beh OF TestModule_ADS7886 IS
46 SIGNAL reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
47 SIGNAL n : INTEGER := 0;
48 BEGIN -- beh
49
50 PROCESS (cnv, sck)
51 BEGIN -- PROCESS
52 IF cnv = '0' AND cnv'EVENT THEN
53 n <= n + 1;
54 IF impulsion = 1 THEN
55 IF n = 1 THEN
56 reg <= conv_std_logic_vector(integer(REAL(amplitude)) , 16);
57 ELSE
58 reg <= conv_std_logic_vector(integer(REAL(0)) , 16);
59 END IF;
60 ELSE
61 reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16);
62 END IF;
63 ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge
64 reg(15) <= 'X';
65 reg(14 DOWNTO 0) <= reg(15 DOWNTO 1);
66 END IF;
67 END PROCESS;
68 sdo <= reg(0);
69
70 END beh;
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@@ -19,62 +19,60
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 LIBRARY IEEE;
23 use IEEE.numeric_std.all;
23 USE IEEE.numeric_std.ALL;
24 use IEEE.std_logic_1164.all;
24 USE IEEE.std_logic_1164.ALL;
25 library lpp;
25 LIBRARY lpp;
26 use lpp.iir_filter.all;
26 USE lpp.iir_filter.ALL;
27 use lpp.FILTERcfg.all;
27 USE lpp.FILTERcfg.ALL;
28 use lpp.general_purpose.all;
28 USE lpp.general_purpose.ALL;
29 library techmap;
29 LIBRARY techmap;
30 use techmap.gencomp.all;
30 USE techmap.gencomp.ALL;
31
31
32 --TODO amliorer la flexibilit de la config de la RAM.
32 --TODO amliorer la flexibilit de la config de la RAM.
33
33
34 entity RAM_CTRLR2 is
34 ENTITY RAM_CTRLR2 IS
35 generic(
35 GENERIC(
36 tech : integer := 0;
36 tech : INTEGER := 0;
37 Input_SZ_1 : integer := 16;
37 Input_SZ_1 : INTEGER := 16;
38 Mem_use : integer := use_RAM
38 Mem_use : INTEGER := use_RAM
39
39
40 );
40 );
41 port(
41 PORT(
42 reset : in std_logic;
42 reset : IN STD_LOGIC;
43 clk : in std_logic;
43 clk : IN STD_LOGIC;
44 WD_sel : in std_logic;
44 WD_sel : IN STD_LOGIC;
45 Read : in std_logic;
45 Read : IN STD_LOGIC;
46 WADDR_sel : in std_logic;
46 WADDR_sel : IN STD_LOGIC;
47 count : in std_logic;
47 count : IN STD_LOGIC;
48 SVG_ADDR : in std_logic;
48 SVG_ADDR : IN STD_LOGIC;
49 Write : in std_logic;
49 Write : IN STD_LOGIC;
50 GO_0 : in std_logic;
50 GO_0 : IN STD_LOGIC;
51 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
51 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
52 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
52 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
53 );
53 );
54 end RAM_CTRLR2;
54 END RAM_CTRLR2;
55
55
56
56
57 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
57 ARCHITECTURE ar_RAM_CTRLR2 OF RAM_CTRLR2 IS
58
58
59 signal WD : std_logic_vector(Input_SZ_1-1 downto 0);
59 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
60 signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0);
60 SIGNAL WD_D : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
61 signal RD : std_logic_vector(Input_SZ_1-1 downto 0);
61 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
62 signal WEN, REN : std_logic;
62 SIGNAL WEN, REN : STD_LOGIC;
63 signal WADDR_back : std_logic_vector(7 downto 0);
63 SIGNAL WADDR_back : STD_LOGIC_VECTOR(7 DOWNTO 0);
64 signal WADDR_back_D: std_logic_vector(7 downto 0);
64 SIGNAL WADDR_back_D : STD_LOGIC_VECTOR(7 DOWNTO 0);
65 signal RADDR : std_logic_vector(7 downto 0);
65 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
66 signal WADDR : std_logic_vector(7 downto 0);
66 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
67 signal WADDR_D : std_logic_vector(7 downto 0);
67 SIGNAL WADDR_D : STD_LOGIC_VECTOR(7 DOWNTO 0);
68
68
69 SIGNAL WADDR_back_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
69 SIGNAL WADDR_back_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
70
70
71 begin
71 BEGIN
72
72
73 sample_out <= RD(Input_SZ_1-1 downto 0);
73 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
74
74
75
75
76 WEN <= not Write;
77 REN <= not read;
78
76
79
77
80 --==============================================================
78 --==============================================================
@@ -98,29 +96,37 REN <= not read;
98 -- ) ;
96 -- ) ;
99 --end generate;
97 --end generate;
100
98
101 --memCEL : if Mem_use = use_CEL generate
99 memCEL : IF Mem_use = use_CEL GENERATE
102 --RAMblk :RAM_CEL
100 WEN <= not Write;
103 -- port map(
101 REN <= not read;
104 -- WD => WD_D,
102 RAMblk : RAM_CEL
105 -- RD => RD,
103 GENERIC MAP( Input_SZ_1)
106 -- WEN => WEN,
104 PORT MAP(
107 -- REN => REN,
105 WD => WD_D,
108 -- WADDR => WADDR,
106 RD => RD,
109 -- RADDR => RADDR,
107 WEN => WEN,
110 -- RWCLK => clk,
108 REN => REN,
111 -- RESET => reset
109 WADDR => WADDR,
112 -- ) ;
110 RADDR => RADDR,
113 --end generate;
111 RWCLK => clk,
112 RESET => reset
113 ) ;
114 END GENERATE;
114
115
116 memRAM : IF Mem_use = use_RAM GENERATE
115 SRAM : syncram_2p
117 SRAM : syncram_2p
116 generic map(tech,8,Input_SZ_1)
118 GENERIC MAP(tech, 8, Input_SZ_1)
117 port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D);
119 PORT MAP(clk, read, RADDR, RD, clk, write, WADDR, WD_D);
120 END GENERATE;
121
122 -- port map(clk,REN,RADDR,RD,clk,WEN,WADDR,WD_D);
123
118 --==============================================================
124 --==============================================================
119 --==============================================================
125 --==============================================================
120
126
121
127
122 ADDRcntr_inst : ADDRcntr
128 ADDRcntr_inst : ADDRcntr
123 port map(
129 PORT MAP(
124 clk => clk,
130 clk => clk,
125 reset => reset,
131 reset => reset,
126 count => count,
132 count => count,
@@ -128,115 +134,60 port map(
128 Q => RADDR
134 Q => RADDR
129 );
135 );
130
136
131
132
133 MUX2_inst1 :MUX2
137 MUX2_inst1 : MUX2
134 generic map(Input_SZ => Input_SZ_1)
138 GENERIC MAP(Input_SZ => Input_SZ_1)
135 port map(
139 PORT MAP(
136 sel => WD_sel,
140 sel => WD_sel,
137 IN1 => sample_in,
141 IN1 => sample_in,
138 IN2 => RD(Input_SZ_1-1 downto 0),
142 IN2 => RD(Input_SZ_1-1 DOWNTO 0),
139 RES => WD(Input_SZ_1-1 downto 0)
143 RES => WD(Input_SZ_1-1 DOWNTO 0)
140 );
144 );
141
145
142
143 MUX2_inst2 :MUX2
146 MUX2_inst2 : MUX2
144 generic map(Input_SZ => 8)
147 GENERIC MAP(Input_SZ => 8)
145 port map(
148 PORT MAP(
146 sel => WADDR_sel,
149 sel => WADDR_sel,
147 IN1 => WADDR_D,
150 IN1 => WADDR_D,
148 IN2 => WADDR_back_D,
151 IN2 => WADDR_back_D,
149 RES => WADDR
152 RES => WADDR
150 );
153 );
151
154
152
153 WADDR_backreg : REG
155 WADDR_backreg : REG
154 generic map(size => 8,initial_VALUE =>ChanelsCount*Cels_count*4-2)
156 GENERIC MAP(size => 8, initial_VALUE => ChanelsCount*Cels_count*4-2)
155 port map(
157 PORT MAP(
156 reset => reset,
158 reset => reset,
157 clk => clk, --SVG_ADDR,
159 clk => clk, --SVG_ADDR,
158 D => WADDR_back_s,--RADDR,
160 D => WADDR_back_s, --RADDR,
159 Q => WADDR_back
161 Q => WADDR_back
160 );
162 );
163
161 WADDR_back_s <= RADDR WHEN SVG_ADDR = '1' ELSE WADDR_back;
164 WADDR_back_s <= RADDR WHEN SVG_ADDR = '1' ELSE WADDR_back;
162
165
163 WADDR_backreg2 :entity work.REG
166 WADDR_backreg2 : REG
164 generic map(size => 8)
167 GENERIC MAP(size => 8)
165 port map(
168 PORT MAP(
166 reset => reset,
169 reset => reset,
167 clk => clk, --SVG_ADDR,
170 clk => clk, --SVG_ADDR,
168 D => WADDR_back,
171 D => WADDR_back,
169 Q => WADDR_back_D
172 Q => WADDR_back_D
170 );
173 );
171
174
172 --WADDR_backreg :REG
173 --generic map(size => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2)
174 --port map(
175 -- reset => reset,
176 -- clk => SVG_ADDR,
177 -- D => RADDR,
178 -- Q => WADDR_back
179 --);
180 --
181 --WADDR_backreg2 :REG
182 --generic map(size => 8)
183 --port map(
184 -- reset => reset,
185 -- clk => SVG_ADDR,
186 -- D => WADDR_back,
187 -- Q => WADDR_back_D
188 --
189
190 WDRreg :REG
175 WDRreg : REG
191 generic map(size => Input_SZ_1)
176 GENERIC MAP(size => Input_SZ_1)
192 port map(
177 PORT MAP(
193 reset => reset,
178 reset => reset,
194 clk => clk,
179 clk => clk,
195 D => WD(Input_SZ_1-1 downto 0),
180 D => WD(Input_SZ_1-1 DOWNTO 0),
196 Q => WD_D(Input_SZ_1-1 downto 0)
181 Q => WD_D(Input_SZ_1-1 DOWNTO 0)
197 );
182 );
198
183
199
200
201
202 ADDRreg :REG
184 ADDRreg : REG
203 generic map(size => 8)
185 GENERIC MAP(size => 8)
204 port map(
186 PORT MAP(
205 reset => reset,
187 reset => reset,
206 clk => clk,
188 clk => clk,
207 D => RADDR,
189 D => RADDR,
208 Q => WADDR_D
190 Q => WADDR_D
209 );
191 );
210
192
211
193 END ar_RAM_CTRLR2;
212
213 end ar_RAM_CTRLR2;
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