diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd @@ -0,0 +1,256 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; + +ENTITY IIR_CEL_CTRLR_v2 IS + GENERIC ( + tech : INTEGER := apa3; + Mem_use : INTEGER := use_RAM; + Sample_SZ : INTEGER := 18; + Coef_SZ : INTEGER := 9; + Coef_Nb : INTEGER := 25; + Coef_sel_SZ : INTEGER := 5; + Cels_count : INTEGER := 5; + ChanelsCount : INTEGER := 8); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + virg_pos : IN INTEGER; + coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); + + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); +END IIR_CEL_CTRLR_v2; + +ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS + + COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW + GENERIC ( + tech : INTEGER; + Mem_use : INTEGER; + Sample_SZ : INTEGER; + Coef_SZ : INTEGER; + Coef_Nb : INTEGER; + Coef_sel_SZ : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + virg_pos : IN INTEGER; + coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); + in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_write : IN STD_LOGIC; + ram_read : IN STD_LOGIC; + raddr_rst : IN STD_LOGIC; + raddr_add1 : IN STD_LOGIC; + waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + alu_sel_input : IN STD_LOGIC; + alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT IIR_CEL_CTRLR_v2_CONTROL + GENERIC ( + Coef_sel_SZ : INTEGER; + Cels_count : INTEGER; + ChanelsCount : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in_rot : OUT STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + sample_out_rot : OUT STD_LOGIC; + in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_write : OUT STD_LOGIC; + ram_read : OUT STD_LOGIC; + raddr_rst : OUT STD_LOGIC; + raddr_add1 : OUT STD_LOGIC; + waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + alu_sel_input : OUT STD_LOGIC; + alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); + END COMPONENT; + + SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ram_write : STD_LOGIC; + SIGNAL ram_read : STD_LOGIC; + SIGNAL raddr_rst : STD_LOGIC; + SIGNAL raddr_add1 : STD_LOGIC; + SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL alu_sel_input : STD_LOGIC; + SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + SIGNAL alu_ctrl : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + SIGNAL sample_in_rotate : STD_LOGIC; + SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL sample_out_val_s : STD_LOGIC; + SIGNAL sample_out_val_s2 : STD_LOGIC; + SIGNAL sample_out_rot_s : STD_LOGIC; + SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + + SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + +BEGIN + + IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW + GENERIC MAP ( + tech => tech, + Mem_use => Mem_use, + Sample_SZ => Sample_SZ, + Coef_SZ => Coef_SZ, + Coef_Nb => Coef_Nb, + Coef_sel_SZ => Coef_sel_SZ) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => virg_pos, + coefs => coefs, + --CTRL + in_sel_src => in_sel_src, + ram_sel_Wdata => ram_sel_Wdata, + ram_write => ram_write, + ram_read => ram_read, + raddr_rst => raddr_rst, + raddr_add1 => raddr_add1, + waddr_previous => waddr_previous, + alu_sel_input => alu_sel_input, + alu_sel_coeff => alu_sel_coeff, + alu_ctrl => alu_ctrl, + --DATA + sample_in => sample_in_s, + sample_out => sample_out_s); + + + IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL + GENERIC MAP ( + Coef_sel_SZ => Coef_sel_SZ, + Cels_count => Cels_count, + ChanelsCount => ChanelsCount) + PORT MAP ( + rstn => rstn, + clk => clk, + sample_in_val => sample_in_val, + sample_in_rot => sample_in_rotate, + sample_out_val => sample_out_val_s, + sample_out_rot => sample_out_rot_s, + + in_sel_src => in_sel_src, + ram_sel_Wdata => ram_sel_Wdata, + ram_write => ram_write, + ram_read => ram_read, + raddr_rst => raddr_rst, + raddr_add1 => raddr_add1, + waddr_previous => waddr_previous, + alu_sel_input => alu_sel_input, + alu_sel_coeff => alu_sel_coeff, + alu_ctrl => alu_ctrl); + + ----------------------------------------------------------------------------- + -- SAMPLE IN + ----------------------------------------------------------------------------- + loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE + + loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_in_buf(I, J) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_in_val = '1' THEN + sample_in_buf(I, J) <= sample_in(I, J); + ELSIF sample_in_rotate = '1' THEN + sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J); + END IF; + END IF; + END PROCESS; + END GENERATE loop_all_chanel; + + sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J); + + END GENERATE loop_all_sample; + + ----------------------------------------------------------------------------- + -- SAMPLE OUT + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_out_val <= '0'; + sample_out_val_s2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_out_val <= sample_out_val_s2; + sample_out_val_s2 <= sample_out_val_s; + END IF; + END PROCESS; + + chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_out_s2(ChanelsCount-1, I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_out_rot_s = '1' THEN + sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I); + END IF; + END IF; + END PROCESS; + END GENERATE chanel_HIGH; + + chanel_more : IF ChanelsCount > 1 GENERATE + all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE + all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_out_s2(J-1, I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_out_rot_s = '1' THEN + sample_out_s2(J-1, I) <= sample_out_s2(J, I); + END IF; + END IF; + END PROCESS; + END GENERATE all_bit; + END GENERATE all_chanel; + END GENERATE chanel_more; + + sample_out <= sample_out_s2; +END ar_IIR_CEL_CTRLR_v2; diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd @@ -0,0 +1,313 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more Cdetails. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; + +ENTITY IIR_CEL_CTRLR_v2_CONTROL IS + GENERIC ( + Coef_sel_SZ : INTEGER; + Cels_count : INTEGER := 5; + ChanelsCount : INTEGER := 1); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_in_rot : OUT STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + sample_out_rot : OUT STD_LOGIC; + + in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_write : OUT STD_LOGIC; + ram_read : OUT STD_LOGIC; + raddr_rst : OUT STD_LOGIC; + raddr_add1 : OUT STD_LOGIC; + waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + alu_sel_input : OUT STD_LOGIC; + alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); +END IIR_CEL_CTRLR_v2_CONTROL; + +ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS + + TYPE fsmIIR_CEL_T IS (waiting, + first_read, + compute_b0, + compute_b1, + compute_b2, + compute_a1, + compute_a2, + LAST_CEL, + wait_valid_last_output, + wait_valid_last_output_2); + SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T; + + SIGNAL alu_selected_coeff : INTEGER; + SIGNAL Chanel_ongoing : INTEGER; + SIGNAL Cel_ongoing : INTEGER; + +BEGIN + + alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ)); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + --REG ------------------------------------------------------------------- + in_sel_src <= (OTHERS => '0'); -- + --RAM_WRitE ------------------------------------------------------------- + ram_sel_Wdata <= "00"; -- + ram_write <= '0'; -- + waddr_previous <= "00"; -- + --RAM_READ -------------------------------------------------------------- + ram_read <= '0'; -- + raddr_rst <= '0'; -- + raddr_add1 <= '0'; -- + --ALU ------------------------------------------------------------------- + alu_selected_coeff <= 0; -- + alu_sel_input <= '0'; -- + alu_ctrl <= (OTHERS => '0'); -- + --OUT + sample_out_val <= '0'; -- + sample_out_rot <= '0'; -- + + Chanel_ongoing <= 0; -- + Cel_ongoing <= 0; -- + sample_in_rot <= '0'; + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + + CASE IIR_CEL_STATE IS + WHEN waiting => + sample_out_rot <= '0'; + sample_in_rot <= '0'; + sample_out_val <= '0'; + alu_ctrl <= "0100"; + alu_selected_coeff <= 0; + in_sel_src <= "01"; + ram_read <= '0'; + ram_sel_Wdata <= "00"; + ram_write <= '0'; + waddr_previous <= "00"; + IF sample_in_val = '1' THEN + raddr_rst <= '0'; + alu_sel_input <= '1'; + ram_read <= '1'; + raddr_add1 <= '1'; + IIR_CEL_STATE <= first_read; + Chanel_ongoing <= Chanel_ongoing + 1; + Cel_ongoing <= 1; + ELSE + raddr_add1 <= '0'; + raddr_rst <= '1'; + Chanel_ongoing <= 0; + Cel_ongoing <= 0; + END IF; + + WHEN first_read => + IIR_CEL_STATE <= compute_b2; + ram_read <= '1'; + raddr_add1 <= '1'; + alu_ctrl <= "0010"; + alu_sel_input <= '1'; + in_sel_src <= "01"; + + + WHEN compute_b2 => + sample_out_rot <= '0'; + + sample_in_rot <= '0'; + sample_out_val <= '0'; + + alu_sel_input <= '1'; + -- + ram_sel_Wdata <= "10"; + ram_write <= '1'; + waddr_previous <= "10"; + -- + ram_read <= '1'; + raddr_rst <= '0'; + raddr_add1 <= '0'; + IF Cel_ongoing = 1 THEN + in_sel_src <= "00"; + ELSE + in_sel_src <= "11"; + END IF; + alu_selected_coeff <= alu_selected_coeff+1; + alu_ctrl <= "0001"; + IIR_CEL_STATE <= compute_b1; + + WHEN compute_b1 => + sample_in_rot <= '0'; + alu_sel_input <= '0'; + -- + ram_sel_Wdata <= "00"; + ram_write <= '1'; + waddr_previous <= "01"; + -- + ram_read <= '1'; + raddr_rst <= '0'; + raddr_add1 <= '1'; + sample_out_rot <= '0'; + IF Cel_ongoing = 1 THEN + in_sel_src <= "10"; + sample_out_val <= '0'; + ELSE + sample_out_val <= '0'; + in_sel_src <= "00"; + END IF; + alu_selected_coeff <= alu_selected_coeff+1; + alu_ctrl <= "0001"; + IIR_CEL_STATE <= compute_b0; + + WHEN compute_b0 => + sample_out_rot <= '0'; + sample_out_val <= '0'; + sample_in_rot <= '0'; + alu_sel_input <= '1'; + ram_sel_Wdata <= "00"; + ram_write <= '0'; + waddr_previous <= "01"; + ram_read <= '1'; + raddr_rst <= '0'; + raddr_add1 <= '0'; + in_sel_src <= "10"; + alu_selected_coeff <= alu_selected_coeff+1; + alu_ctrl <= "0001"; + IIR_CEL_STATE <= compute_a2; + IF Cel_ongoing = Cels_count THEN + sample_in_rot <= '1'; + ELSE + sample_in_rot <= '0'; + END IF; + + WHEN compute_a2 => + sample_out_val <= '0'; + sample_out_rot <= '0'; + alu_sel_input <= '1'; + ram_sel_Wdata <= "00"; + ram_write <= '0'; + waddr_previous <= "01"; + ram_read <= '1'; + raddr_rst <= '0'; + IF Cel_ongoing = Cels_count THEN + raddr_add1 <= '1'; + ELSE + raddr_add1 <= '0'; + END IF; + in_sel_src <= "00"; + alu_selected_coeff <= alu_selected_coeff+1; + alu_ctrl <= "0001"; + IIR_CEL_STATE <= compute_a1; + sample_in_rot <= '0'; + + WHEN compute_a1 => + sample_out_val <= '0'; + sample_out_rot <= '0'; + alu_sel_input <= '0'; + ram_sel_Wdata <= "00"; + ram_write <= '0'; + waddr_previous <= "01"; + ram_read <= '1'; + raddr_rst <= '0'; + alu_ctrl <= "0010"; + sample_in_rot <= '0'; + IF Cel_ongoing = Cels_count THEN + alu_selected_coeff <= 0; + + ram_sel_Wdata <= "10"; + raddr_add1 <= '1'; + ram_write <= '1'; + waddr_previous <= "10"; + + IF Chanel_ongoing = ChanelsCount THEN + IIR_CEL_STATE <= wait_valid_last_output; + ELSE + Chanel_ongoing <= Chanel_ongoing + 1; + Cel_ongoing <= 1; + IIR_CEL_STATE <= LAST_CEL; + in_sel_src <= "01"; + END IF; + ELSE + raddr_add1 <= '1'; + alu_selected_coeff <= alu_selected_coeff+1; + Cel_ongoing <= Cel_ongoing+1; + IIR_CEL_STATE <= compute_b2; + END IF; + + WHEN LAST_CEL => + alu_sel_input <= '1'; + IIR_CEL_STATE <= compute_b2; + raddr_add1 <= '1'; + ram_sel_Wdata <= "01"; + ram_write <= '1'; + waddr_previous <= "10"; + sample_out_rot <= '1'; + + + WHEN wait_valid_last_output => + IIR_CEL_STATE <= wait_valid_last_output_2; + sample_in_rot <= '0'; + alu_ctrl <= "0000"; + alu_selected_coeff <= 0; + in_sel_src <= "01"; + ram_read <= '0'; + raddr_rst <= '1'; + raddr_add1 <= '1'; + ram_sel_Wdata <= "01"; + ram_write <= '1'; + waddr_previous <= "10"; + Chanel_ongoing <= 0; + Cel_ongoing <= 0; + sample_out_val <= '0'; + sample_out_rot <= '1'; + + WHEN wait_valid_last_output_2 => + IIR_CEL_STATE <= waiting; + sample_in_rot <= '0'; + alu_ctrl <= "0000"; + alu_selected_coeff <= 0; + in_sel_src <= "01"; + ram_read <= '0'; + raddr_rst <= '1'; + raddr_add1 <= '1'; + ram_sel_Wdata <= "10"; + ram_write <= '1'; + waddr_previous <= "10"; + Chanel_ongoing <= 0; + Cel_ongoing <= 0; + sample_out_val <= '1'; + sample_out_rot <= '0'; + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + +END ar_IIR_CEL_CTRLR_v2_CONTROL; diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd @@ -0,0 +1,248 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; + + + +ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS + GENERIC( + tech : INTEGER := 0; + Mem_use : INTEGER := use_RAM; + Sample_SZ : INTEGER := 16; + Coef_SZ : INTEGER := 9; + Coef_Nb : INTEGER := 30; + Coef_sel_SZ : INTEGER := 5 + ); + PORT( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + -- PARAMETER + virg_pos : IN INTEGER; + coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); + -- CONTROL + in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + -- + ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_write : IN STD_LOGIC; + ram_read : IN STD_LOGIC; + raddr_rst : IN STD_LOGIC; + raddr_add1 : IN STD_LOGIC; + waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + -- + alu_sel_input : IN STD_LOGIC; + alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) + -- DATA + sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0) + ); +END IIR_CEL_CTRLR_v2_DATAFLOW; + +ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS + + COMPONENT RAM_CTRLR_v2 + GENERIC ( + tech : INTEGER; + Input_SZ_1 : INTEGER; + Mem_use : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + ram_write : IN STD_LOGIC; + ram_read : IN STD_LOGIC; + raddr_rst : IN STD_LOGIC; + raddr_add1 : IN STD_LOGIC; + waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); + END COMPONENT; + + SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0); + + SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0); + SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0); + + SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + -- INPUT + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + reg_sample_in <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + CASE in_sel_src IS + WHEN "00" => reg_sample_in <= reg_sample_in; + WHEN "01" => reg_sample_in <= sample_in; + WHEN "10" => reg_sample_in <= ram_output; + WHEN "11" => reg_sample_in <= alu_output; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + + ----------------------------------------------------------------------------- + -- RAM + CTRL + ----------------------------------------------------------------------------- + + ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE + alu_output WHEN ram_sel_Wdata = "01" ELSE + ram_output; + + RAM_CTRLR_v2_1: RAM_CTRLR_v2 + GENERIC MAP ( + tech => tech, + Input_SZ_1 => Sample_SZ, + Mem_use => Mem_use) + PORT MAP ( + clk => clk, + rstn => rstn, + ram_write => ram_write, + ram_read => ram_read, + raddr_rst => raddr_rst, + raddr_add1 => raddr_add1, + waddr_previous => waddr_previous, + sample_in => ram_input, + sample_out => ram_output); + + ----------------------------------------------------------------------------- + -- MAC_ACC + ----------------------------------------------------------------------------- + -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE) + -- Data In : mac_sample, mac_coef + -- Data Out: mac_output + + alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output; + + coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE + coeff_in: IF I < Coef_Nb GENERATE + all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE + arrayCoeff(I,J) <= coefs(Coef_SZ*I+J); + END GENERATE all_bit; + END GENERATE coeff_in; + coeff_null: IF I > (Coef_Nb -1) GENERATE + all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE + arrayCoeff(I,J) <= '0'; + END GENERATE all_bit; + END GENERATE coeff_null; + END GENERATE coefftable; + + Coeff_Mux : MUXN + GENERIC MAP ( + Input_SZ => Coef_SZ, + NbStage => Coef_sel_SZ) + PORT MAP ( + sel => alu_sel_coeff, + INPUT => arrayCoeff, + RES => alu_coef_s); + + + all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE + alu_coef(J) <= alu_coef_s(J); + END GENERATE all_bit; + + ----------------------------------------------------------------------------- + -- TODO : just for Synthesis test + + --PROCESS (clk, rstn) + --BEGIN + -- IF rstn = '0' THEN + -- alu_coef <= (OTHERS => '0'); + -- ELSIF clk'event AND clk = '1' THEN + -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP + -- alu_coef(J) <= alu_coef_s(J); + -- END LOOP all_bit; + -- END IF; + --END PROCESS; + + ----------------------------------------------------------------------------- + + + ALU_1: ALU + GENERIC MAP ( + Arith_en => 1, + Input_SZ_1 => Sample_SZ, + Input_SZ_2 => Coef_SZ) + PORT MAP ( + clk => clk, + reset => rstn, + ctrl => alu_ctrl, + OP1 => alu_sample, + OP2 => alu_coef, + RES => alu_output_s); + + alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos); + + sample_out <= alu_output; + +END ar_IIR_CEL_CTRLR_v2_DATAFLOW; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd @@ -19,62 +19,60 @@ -- Author : Alexis Jeandet -- Mail : alexis.jeandet@lpp.polytechnique.fr ---------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -library lpp; -use lpp.iir_filter.all; -use lpp.FILTERcfg.all; -use lpp.general_purpose.all; -library techmap; -use techmap.gencomp.all; +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.general_purpose.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; --TODO amliorer la flexibilit de la config de la RAM. -entity RAM_CTRLR2 is -generic( - tech : integer := 0; - Input_SZ_1 : integer := 16; - Mem_use : integer := use_RAM +ENTITY RAM_CTRLR2 IS + GENERIC( + tech : INTEGER := 0; + Input_SZ_1 : INTEGER := 16; + Mem_use : INTEGER := use_RAM -); -port( - reset : in std_logic; - clk : in std_logic; - WD_sel : in std_logic; - Read : in std_logic; - WADDR_sel : in std_logic; - count : in std_logic; - SVG_ADDR : in std_logic; - Write : in std_logic; - GO_0 : in std_logic; - sample_in : in std_logic_vector(Input_SZ_1-1 downto 0); - sample_out : out std_logic_vector(Input_SZ_1-1 downto 0) -); -end RAM_CTRLR2; + ); + PORT( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + WD_sel : IN STD_LOGIC; + Read : IN STD_LOGIC; + WADDR_sel : IN STD_LOGIC; + count : IN STD_LOGIC; + SVG_ADDR : IN STD_LOGIC; + Write : IN STD_LOGIC; + GO_0 : IN STD_LOGIC; + sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) + ); +END RAM_CTRLR2; -architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is +ARCHITECTURE ar_RAM_CTRLR2 OF RAM_CTRLR2 IS -signal WD : std_logic_vector(Input_SZ_1-1 downto 0); -signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0); -signal RD : std_logic_vector(Input_SZ_1-1 downto 0); -signal WEN, REN : std_logic; -signal WADDR_back : std_logic_vector(7 downto 0); -signal WADDR_back_D: std_logic_vector(7 downto 0); -signal RADDR : std_logic_vector(7 downto 0); -signal WADDR : std_logic_vector(7 downto 0); -signal WADDR_D : std_logic_vector(7 downto 0); + SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + SIGNAL WD_D : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + SIGNAL WEN, REN : STD_LOGIC; + SIGNAL WADDR_back : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL WADDR_back_D : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL WADDR_D : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL WADDR_back_s : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL WADDR_back_s : STD_LOGIC_VECTOR(7 DOWNTO 0); -begin +BEGIN -sample_out <= RD(Input_SZ_1-1 downto 0); + sample_out <= RD(Input_SZ_1-1 DOWNTO 0); -WEN <= not Write; -REN <= not read; --============================================================== @@ -98,145 +96,98 @@ REN <= not read; -- ) ; --end generate; ---memCEL : if Mem_use = use_CEL generate ---RAMblk :RAM_CEL --- port map( --- WD => WD_D, --- RD => RD, --- WEN => WEN, --- REN => REN, --- WADDR => WADDR, --- RADDR => RADDR, --- RWCLK => clk, --- RESET => reset --- ) ; ---end generate; + memCEL : IF Mem_use = use_CEL GENERATE + WEN <= not Write; + REN <= not read; + RAMblk : RAM_CEL + GENERIC MAP( Input_SZ_1) + PORT MAP( + WD => WD_D, + RD => RD, + WEN => WEN, + REN => REN, + WADDR => WADDR, + RADDR => RADDR, + RWCLK => clk, + RESET => reset + ) ; + END GENERATE; + memRAM : IF Mem_use = use_RAM GENERATE SRAM : syncram_2p - generic map(tech,8,Input_SZ_1) - port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D); + GENERIC MAP(tech, 8, Input_SZ_1) + PORT MAP(clk, read, RADDR, RD, clk, write, WADDR, WD_D); + END GENERATE; + +-- port map(clk,REN,RADDR,RD,clk,WEN,WADDR,WD_D); + --============================================================== --============================================================== -ADDRcntr_inst : ADDRcntr -port map( - clk => clk, - reset => reset, - count => count, - clr => GO_0, - Q => RADDR -); - - - -MUX2_inst1 :MUX2 -generic map(Input_SZ => Input_SZ_1) -port map( - sel => WD_sel, - IN1 => sample_in, - IN2 => RD(Input_SZ_1-1 downto 0), - RES => WD(Input_SZ_1-1 downto 0) -); - + ADDRcntr_inst : ADDRcntr + PORT MAP( + clk => clk, + reset => reset, + count => count, + clr => GO_0, + Q => RADDR + ); -MUX2_inst2 :MUX2 -generic map(Input_SZ => 8) -port map( - sel => WADDR_sel, - IN1 => WADDR_D, - IN2 => WADDR_back_D, - RES => WADDR -); - + MUX2_inst1 : MUX2 + GENERIC MAP(Input_SZ => Input_SZ_1) + PORT MAP( + sel => WD_sel, + IN1 => sample_in, + IN2 => RD(Input_SZ_1-1 DOWNTO 0), + RES => WD(Input_SZ_1-1 DOWNTO 0) + ); - WADDR_backreg : REG - generic map(size => 8,initial_VALUE =>ChanelsCount*Cels_count*4-2) - port map( - reset => reset, - clk => clk, --SVG_ADDR, - D => WADDR_back_s,--RADDR, - Q => WADDR_back - ); - WADDR_back_s <= RADDR WHEN SVG_ADDR = '1' ELSE WADDR_back; - - WADDR_backreg2 :entity work.REG - generic map(size => 8) - port map( - reset => reset, - clk => clk, --SVG_ADDR, - D => WADDR_back, - Q => WADDR_back_D + MUX2_inst2 : MUX2 + GENERIC MAP(Input_SZ => 8) + PORT MAP( + sel => WADDR_sel, + IN1 => WADDR_D, + IN2 => WADDR_back_D, + RES => WADDR ); ---WADDR_backreg :REG ---generic map(size => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2) ---port map( --- reset => reset, --- clk => SVG_ADDR, --- D => RADDR, --- Q => WADDR_back ---); --- ---WADDR_backreg2 :REG ---generic map(size => 8) ---port map( --- reset => reset, --- clk => SVG_ADDR, --- D => WADDR_back, --- Q => WADDR_back_D --- + WADDR_backreg : REG + GENERIC MAP(size => 8, initial_VALUE => ChanelsCount*Cels_count*4-2) + PORT MAP( + reset => reset, + clk => clk, --SVG_ADDR, + D => WADDR_back_s, --RADDR, + Q => WADDR_back + ); -WDRreg :REG -generic map(size => Input_SZ_1) -port map( - reset => reset, - clk => clk, - D => WD(Input_SZ_1-1 downto 0), - Q => WD_D(Input_SZ_1-1 downto 0) -); + WADDR_back_s <= RADDR WHEN SVG_ADDR = '1' ELSE WADDR_back; - - + WADDR_backreg2 : REG + GENERIC MAP(size => 8) + PORT MAP( + reset => reset, + clk => clk, --SVG_ADDR, + D => WADDR_back, + Q => WADDR_back_D + ); -ADDRreg :REG -generic map(size => 8) -port map( - reset => reset, - clk => clk, - D => RADDR, - Q => WADDR_D -); - - - -end ar_RAM_CTRLR2; - - - - - - - - + WDRreg : REG + GENERIC MAP(size => Input_SZ_1) + PORT MAP( + reset => reset, + clk => clk, + D => WD(Input_SZ_1-1 DOWNTO 0), + Q => WD_D(Input_SZ_1-1 DOWNTO 0) + ); - - - - - - - - - + ADDRreg : REG + GENERIC MAP(size => 8) + PORT MAP( + reset => reset, + clk => clk, + D => RADDR, + Q => WADDR_D + ); - - - - - - - - - - +END ar_RAM_CTRLR2; diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd @@ -0,0 +1,120 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.general_purpose.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY RAM_CTRLR_v2 IS + GENERIC( + tech : INTEGER := 0; + Input_SZ_1 : INTEGER := 16; + Mem_use : INTEGER := use_RAM + ); + PORT( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + -- R/W Ctrl + ram_write : IN STD_LOGIC; + ram_read : IN STD_LOGIC; + -- ADDR Ctrl + raddr_rst : IN STD_LOGIC; + raddr_add1 : IN STD_LOGIC; + waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + -- Data + sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) + ); +END RAM_CTRLR_v2; + + +ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS + + SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + SIGNAL WEN, REN : STD_LOGIC; + SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); + +BEGIN + + sample_out <= RD(Input_SZ_1-1 DOWNTO 0); + WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; + ----------------------------------------------------------------------------- + -- RAM + ----------------------------------------------------------------------------- + + memCEL : IF Mem_use = use_CEL GENERATE + WEN <= NOT ram_write; + REN <= NOT ram_read; + RAMblk : RAM_CEL + GENERIC MAP(Input_SZ_1) + PORT MAP( + WD => WD, + RD => RD, + WEN => WEN, + REN => REN, + WADDR => WADDR, + RADDR => RADDR, + RWCLK => clk, + RESET => rstn + ) ; + END GENERATE; + + memRAM : IF Mem_use = use_RAM GENERATE + SRAM : syncram_2p + GENERIC MAP(tech, 8, Input_SZ_1) + PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); + END GENERATE; + + ----------------------------------------------------------------------------- + -- RADDR + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + counter <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF raddr_rst = '1' THEN + counter <= (OTHERS => '0'); + ELSIF raddr_add1 = '1' THEN + counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); + END IF; + END IF; + END PROCESS; + RADDR <= counter; + + ----------------------------------------------------------------------------- + -- WADDR + ----------------------------------------------------------------------------- + WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE + STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE + STD_LOGIC_VECTOR(UNSIGNED(counter)); + + +END ar_RAM_CTRLR_v2; diff --git a/lib/lpp/general_purpose/MUXN.vhd b/lib/lpp/general_purpose/MUXN.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/MUXN.vhd @@ -0,0 +1,86 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : Jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.general_purpose.ALL; + +ENTITY MUXN IS + GENERIC( + Input_SZ : INTEGER := 16; + NbStage : INTEGER := 2); + PORT( + sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); + --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); + INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); + RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); +END ENTITY; + +ARCHITECTURE ar_MUXN OF MUXN IS + COMPONENT MUXN + GENERIC ( + Input_SZ : INTEGER; + NbStage : INTEGER); + PORT ( + sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); + INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); + --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); + RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); + END COMPONENT; + + --SIGNAL S : ARRAY (0 TO (2**(NbStage-1)-1)) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); + SIGNAL S: MUX_INPUT_TYPE(0 TO (2**(NbStage-1))-1,Input_SZ-1 DOWNTO 0); + + +BEGIN + + all_input : FOR I IN 0 TO (2**(NbStage-1))-1 GENERATE + all_input: FOR J IN Input_SZ-1 DOWNTO 0 GENERATE + S(I,J) <= INPUT(2*I,J) WHEN sel(0) = '0' ELSE INPUT(2*I+1,J); + END GENERATE all_input; + END GENERATE all_input; + + NB_STAGE_1: IF NbStage = 1 GENERATE + all_input: FOR J IN Input_SZ-1 DOWNTO 0 GENERATE + RES(J) <= S(0,J); + END GENERATE all_input; + END GENERATE NB_STAGE_1; + + NB_STAGE_2 : IF NbStage = 2 GENERATE + all_input: FOR I IN Input_SZ-1 DOWNTO 0 GENERATE + RES(I) <= S(0,I) WHEN sel(1) = '0' ELSE S(1,I); + END GENERATE all_input; + END GENERATE NB_STAGE_2; + + NB_STAGE_PLUS : IF NbStage > 2 GENERATE + MUXN_1 : MUXN + GENERIC MAP ( + Input_SZ => Input_SZ, + NbStage => NbStage-1) + PORT MAP ( + sel => sel(NbStage-1 DOWNTO 1), + INPUT => S, + RES => RES); + END GENERATE NB_STAGE_PLUS; + +END ar_MUXN; diff --git a/lib/lpp/general_purpose/SYNC_FF.vhd b/lib/lpp/general_purpose/SYNC_FF.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/SYNC_FF.vhd @@ -0,0 +1,57 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +ENTITY SYNC_FF IS + + GENERIC ( + NB_FF_OF_SYNC : INTEGER := 2); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + A : IN STD_LOGIC; + A_sync : OUT STD_LOGIC); + +END SYNC_FF; + +ARCHITECTURE beh OF SYNC_FF IS + SIGNAL A_temp : STD_LOGIC_VECTOR(NB_FF_OF_SYNC DOWNTO 0); +BEGIN -- beh + + sync_loop : FOR I IN 0 TO NB_FF_OF_SYNC-1 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + A_temp(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + A_temp(I) <= A_temp(I+1); + END IF; + END PROCESS; + END GENERATE sync_loop; + + A_temp(NB_FF_OF_SYNC) <= A; + A_sync <= A_temp(0); + +END beh; diff --git a/lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd b/lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd @@ -0,0 +1,70 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.std_logic_arith.ALL; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +ENTITY TestModule_ADS7886 IS + GENERIC ( + freq : INTEGER := 24; + amplitude : INTEGER := 3000; + impulsion : INTEGER := 0 -- 1 => impulsion generation + ); + PORT ( + -- CONV -- + cnv_run : IN STD_LOGIC; + cnv : IN STD_LOGIC; + + -- DATA -- + sck : IN STD_LOGIC; + sdo : OUT STD_LOGIC + ); +END TestModule_ADS7886; + +ARCHITECTURE beh OF TestModule_ADS7886 IS + SIGNAL reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL n : INTEGER := 0; +BEGIN -- beh + + PROCESS (cnv, sck) + BEGIN -- PROCESS + IF cnv = '0' AND cnv'EVENT THEN + n <= n + 1; + IF impulsion = 1 THEN + IF n = 1 THEN + reg <= conv_std_logic_vector(integer(REAL(amplitude)) , 16); + ELSE + reg <= conv_std_logic_vector(integer(REAL(0)) , 16); + END IF; + ELSE + reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16); + END IF; + ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge + reg(15) <= 'X'; + reg(14 DOWNTO 0) <= reg(15 DOWNTO 1); + END IF; + END PROCESS; + sdo <= reg(0); + +END beh;