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@@ -58,6 +58,7 vcom_tb:
58 $(CMD_VCOM) lpp lpp_FIFO.vhd
58 $(CMD_VCOM) lpp lpp_FIFO.vhd
59 $(CMD_VCOM) lpp spectral_matrix_package.vhd
59 $(CMD_VCOM) lpp spectral_matrix_package.vhd
60 $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd
60 $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd
61 $(CMD_VCOM) lpp spectral_matrix_time_managment.vhd
61 $(CMD_VCOM) lpp lpp_lfr_ms.vhd
62 $(CMD_VCOM) lpp lpp_lfr_ms.vhd
62 $(CMD_VCOM) work TB.vhd
63 $(CMD_VCOM) work TB.vhd
63 @echo "vcom done"
64 @echo "vcom done"
@@ -344,7 +345,52 vcom_lpp:
344 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
345 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
345 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
346 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
346 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
347 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
348 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
349 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
350 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
351 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
352 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
353 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
354 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
355 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
356 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
357 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
358 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
359 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
360 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
361 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
362 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
363 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
364 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
365 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
366 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
367 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
368 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
369 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
370 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
371 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
372 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
373 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
374 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
375 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
376 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
377 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
378 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
379 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
380 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
381 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
382 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
383 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
384 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
385 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
386 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
387 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
388 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
389 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
390 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
347 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
391 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
392 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
348 @echo "vcom lpp done"
394 @echo "vcom lpp done"
349
395
350 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
396 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
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@@ -19,52 +19,64
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 LIBRARY IEEE;
23 use IEEE.std_logic_1164.all;
23 USE IEEE.std_logic_1164.ALL;
24 use IEEE.numeric_std.all;
24 USE IEEE.numeric_std.ALL;
25 library lpp;
25 LIBRARY lpp;
26 use lpp.lpp_memory.all;
26 USE lpp.lpp_memory.ALL;
27 use lpp.iir_filter.all;
27 USE lpp.iir_filter.ALL;
28 library techmap;
28 LIBRARY techmap;
29 use techmap.gencomp.all;
29 USE techmap.gencomp.ALL;
30
30
31 entity lppFIFOxN is
31 ENTITY lppFIFOxN IS
32 generic(
32 GENERIC(
33 tech : integer := 0;
33 tech : INTEGER := 0;
34 Mem_use : integer := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 Data_sz : integer range 1 to 32 := 8;
35 Data_sz : INTEGER RANGE 1 TO 32 := 8;
36 Addr_sz : integer range 2 to 12 := 8;
36 Addr_sz : INTEGER RANGE 2 TO 12 := 8;
37 FifoCnt : integer := 1;
37 FifoCnt : INTEGER := 1
38 Enable_ReUse : std_logic := '0'
39 );
38 );
40 port(
39 PORT(
41 rstn : in std_logic;
40 clk : IN STD_LOGIC;
42 wclk : in std_logic;
41 rstn : IN STD_LOGIC;
43 rclk : in std_logic;
42
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
43 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
44
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
46 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
47
49 full : out std_logic_vector(FifoCnt-1 downto 0);
48 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
50 almost_full : out std_logic_vector(FifoCnt-1 downto 0); -- TODO
49 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
51 empty : out std_logic_vector(FifoCnt-1 downto 0)
50
52 );
51 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
53 end entity;
52 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
53 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
54 );
55 END ENTITY;
54
56
55
57
56 architecture ar_lppFIFOxN of lppFIFOxN is
58 ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS
57
59
58 begin
60 BEGIN
59
61
60 fifos: for i in 0 to FifoCnt-1 generate
62 fifos : FOR i IN 0 TO FifoCnt-1 GENERATE
61 FIFO0 : lpp_fifo
63 lpp_fifo_1: lpp_fifo
62 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
64 GENERIC MAP (
63 port map(rstn,ReUse(i),
65 tech => tech,
64 rclk,
66 Mem_use => Mem_use,
65 ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,
67 DataSz => Data_sz,
66 wclk,
68 AddrSz => Addr_sz)
67 wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),almost_full(i),open);
69 PORT MAP (
68 end generate;
70 clk => clk,
71 rstn => rstn,
72 reUse => reUse(I),
73 ren => ren(I),
74 rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
75 wen => wen(I),
76 wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
77 empty => empty(I),
78 full => full(I),
79 almost_full => almost_full(I));
80 END GENERATE;
69
81
70 end architecture;
82 END ARCHITECTURE;
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@@ -32,24 +32,26 ENTITY lpp_fifo IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 Enable_ReUse : STD_LOGIC := '0';
36 DataSz : INTEGER RANGE 1 TO 32 := 8;
35 DataSz : INTEGER RANGE 1 TO 32 := 8;
37 AddrSz : INTEGER RANGE 2 TO 12 := 8
36 AddrSz : INTEGER RANGE 2 TO 12 := 8
38 );
37 );
39 PORT(
38 PORT(
39 clk : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
41 ReUse : IN STD_LOGIC;
41 --
42 rclk : IN STD_LOGIC;
42 reUse : IN STD_LOGIC;
43
44 --IN
43 ren : IN STD_LOGIC;
45 ren : IN STD_LOGIC;
44 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
46 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
45 empty : OUT STD_LOGIC;
47
46 raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
48 --OUT
47 wclk : IN STD_LOGIC;
48 wen : IN STD_LOGIC;
49 wen : IN STD_LOGIC;
49 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
50 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
51
52 empty : OUT STD_LOGIC;
50 full : OUT STD_LOGIC;
53 full : OUT STD_LOGIC;
51 almost_full : OUT STD_LOGIC; -- TODO
54 almost_full : OUT STD_LOGIC
52 waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
53 );
55 );
54 END ENTITY;
56 END ENTITY;
55
57
@@ -82,13 +84,13 BEGIN
82 memRAM : IF Mem_use = use_RAM GENERATE
84 memRAM : IF Mem_use = use_RAM GENERATE
83 SRAM : syncram_2p
85 SRAM : syncram_2p
84 GENERIC MAP(tech, AddrSz, DataSz)
86 GENERIC MAP(tech, AddrSz, DataSz)
85 PORT MAP(RCLK, sRE, Raddr_vect, rdata, WCLK, sWE, Waddr_vect, wdata);
87 PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata);
86 END GENERATE;
88 END GENERATE;
87 --==================================================================================
89 --==================================================================================
88 memCEL : IF Mem_use = use_CEL GENERATE
90 memCEL : IF Mem_use = use_CEL GENERATE
89 CRAM : RAM_CEL
91 CRAM : RAM_CEL
90 GENERIC MAP(DataSz, AddrSz)
92 GENERIC MAP(DataSz, AddrSz)
91 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
93 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
92 END GENERATE;
94 END GENERATE;
93 --==================================================================================
95 --==================================================================================
94
96
@@ -98,19 +100,19 BEGIN
98 sREN <= REN OR sEmpty;
100 sREN <= REN OR sEmpty;
99 sRE <= NOT sREN;
101 sRE <= NOT sREN;
100
102
101 sEmpty_s <= '0' WHEN ReUse = '1' AND Enable_ReUse = '1' else
103 sEmpty_s <= '0' WHEN ReUse = '1' else
102 '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
104 '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
103 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
105 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
104 '0';
106 '0';
105
107
106 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
108 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
107
109
108 PROCESS (rclk, rstn)
110 PROCESS (clk, rstn)
109 BEGIN
111 BEGIN
110 IF(rstn = '0')then
112 IF(rstn = '0')then
111 Raddr_vect <= (OTHERS => '0');
113 Raddr_vect <= (OTHERS => '0');
112 sempty <= '1';
114 sempty <= '1';
113 ELSIF(rclk'EVENT AND rclk = '1')then
115 ELSIF(clk'EVENT AND clk = '1')then
114 sEmpty <= sempty_s;
116 sEmpty <= sempty_s;
115
117
116 IF(sREN = '0' and sempty = '0')then
118 IF(sREN = '0' and sempty = '0')then
@@ -126,7 +128,7 BEGIN
126 sWEN <= WEN OR sFull;
128 sWEN <= WEN OR sFull;
127 sWE <= NOT sWEN;
129 sWE <= NOT sWEN;
128
130
129 sFull_s <= '1' WHEN ReUse = '1' AND Enable_ReUse = '1' else
131 sFull_s <= '1' WHEN ReUse = '1' else
130 '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
132 '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
131 '1' WHEN sFull = '1' AND REN = '1' ELSE
133 '1' WHEN sFull = '1' AND REN = '1' ELSE
132 '0';
134 '0';
@@ -137,13 +139,13 BEGIN
137
139
138 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
140 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
139
141
140 PROCESS (wclk, rstn)
142 PROCESS (clk, rstn)
141 BEGIN
143 BEGIN
142 IF(rstn = '0')then
144 IF(rstn = '0')then
143 Waddr_vect <= (OTHERS => '0');
145 Waddr_vect <= (OTHERS => '0');
144 sfull <= '0';
146 sfull <= '0';
145 almost_full_r <= '0';
147 almost_full_r <= '0';
146 ELSIF(wclk'EVENT AND wclk = '1')then
148 ELSIF(clk'EVENT AND clk = '1')then
147 sfull <= sfull_s;
149 sfull <= sfull_s;
148 almost_full_r <= almost_full_s;
150 almost_full_r <= almost_full_s;
149
151
@@ -157,8 +159,6 BEGIN
157 almost_full <= almost_full_s;
159 almost_full <= almost_full_s;
158 full <= sFull_s;
160 full <= sFull_s;
159 empty <= sEmpty_s;
161 empty <= sEmpty_s;
160 waddr <= Waddr_vect;
161 raddr <= Raddr_vect;
162
162
163 END ARCHITECTURE;
163 END ARCHITECTURE;
164
164
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@@ -6,9 +6,13 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9
9 USE lpp.lpp_dma_pkg.ALL;
10 use lpp.lpp_fft.all;
10 USE lpp.lpp_Header.ALL;
11 use lpp.fft_components.all;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
12
16
13 ENTITY lpp_lfr_ms IS
17 ENTITY lpp_lfr_ms IS
14 GENERIC (
18 GENERIC (
@@ -94,7 +98,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
94 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97
101
98 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99
103
100 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
@@ -105,17 +109,18 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
105 SIGNAL error_wen_f0 : STD_LOGIC;
109 SIGNAL error_wen_f0 : STD_LOGIC;
106 SIGNAL error_wen_f1 : STD_LOGIC;
110 SIGNAL error_wen_f1 : STD_LOGIC;
107 SIGNAL error_wen_f2 : STD_LOGIC;
111 SIGNAL error_wen_f2 : STD_LOGIC;
108
112
109 SIGNAL one_sample_f1_full : STD_LOGIC;
113 SIGNAL one_sample_f1_full : STD_LOGIC;
110 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 SIGNAL one_sample_f1_wen : STD_LOGIC;
111 SIGNAL one_sample_f2_full : STD_LOGIC;
115 SIGNAL one_sample_f2_full : STD_LOGIC;
112 SIGNAL one_sample_f2_wen : STD_LOGIC;
116 SIGNAL one_sample_f2_wen : STD_LOGIC;
113
117
114 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
115 -- FSM / SWITCH SELECT CHANNEL
119 -- FSM / SWITCH SELECT CHANNEL
116 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
117 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
118 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 SIGNAL state_fsm_select_channel : fsm_select_channel;
123 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
119
124
120 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
121 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -125,27 +130,87 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
125 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
126 -- FSM LOAD FFT
131 -- FSM LOAD FFT
127 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
128 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, FIFO_transition);
133 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
129 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
130 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
131
136
132 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 SIGNAL sample_load : STD_LOGIC;
138 SIGNAL sample_load : STD_LOGIC;
134 SIGNAL sample_valid : STD_LOGIC;
139 SIGNAL sample_valid : STD_LOGIC;
135 SIGNAL sample_valid_r : STD_LOGIC;
140 SIGNAL sample_valid_r : STD_LOGIC;
136 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
137
142
138
143
139 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
140 -- FFT
145 -- FFT
141 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
142 SIGNAL fft_read : STD_LOGIC;
147 SIGNAL fft_read : STD_LOGIC;
143 SIGNAL fft_pong : STD_LOGIC;
148 SIGNAL fft_pong : STD_LOGIC;
144 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
145 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
146 SIGNAL fft_data_valid : STD_LOGIC;
151 SIGNAL fft_data_valid : STD_LOGIC;
147 SIGNAL fft_ready : STD_LOGIC;
152 SIGNAL fft_ready : STD_LOGIC;
153 -----------------------------------------------------------------------------
154 SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
155 -----------------------------------------------------------------------------
156 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
157 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
158 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
159 SIGNAL current_fifo_empty : STD_LOGIC;
160 SIGNAL current_fifo_locked : STD_LOGIC;
161 SIGNAL current_fifo_full : STD_LOGIC;
162 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
148
163
164 -----------------------------------------------------------------------------
165 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 -----------------------------------------------------------------------------
174 SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 SIGNAL HEAD_SM_Wen : STD_LOGIC;
177 SIGNAL HEAD_Valid : STD_LOGIC;
178 SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL HEAD_Empty : STD_LOGIC;
180 SIGNAL HEAD_Read : STD_LOGIC;
181 -----------------------------------------------------------------------------
182 SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0);
183 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
185 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
186 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
187 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
188 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
189 -----------------------------------------------------------------------------
190 SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL DMA_Header_Val : STD_LOGIC;
192 SIGNAL DMA_Header_Ack : STD_LOGIC;
193
194 -----------------------------------------------------------------------------
195 -- TIME REG & INFOs
196 -----------------------------------------------------------------------------
197 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
198
199 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
200 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
201 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
202 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
203
204 SIGNAL time_update_f0_A : STD_LOGIC;
205 SIGNAL time_update_f0_B : STD_LOGIC;
206 SIGNAL time_update_f1 : STD_LOGIC;
207 SIGNAL time_update_f2 : STD_LOGIC;
208 --
209 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
210
211 SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 -----------------------------------------------------------------------------
213
149 BEGIN
214 BEGIN
150
215
151 switch_f0_inst : spectral_matrix_switch_f0
216 switch_f0_inst : spectral_matrix_switch_f0
@@ -163,7 +228,7 BEGIN
163 fifo_B_full => sample_f0_B_full,
228 fifo_B_full => sample_f0_B_full,
164 fifo_B_wen => sample_f0_B_wen,
229 fifo_B_wen => sample_f0_B_wen,
165
230
166 error_wen => error_wen_f0); -- TODO
231 error_wen => error_wen_f0); -- TODO
167
232
168 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
169 -- FIFO IN
234 -- FIFO IN
@@ -174,21 +239,22 BEGIN
174 Mem_use => Mem_use,
239 Mem_use => Mem_use,
175 Data_sz => 16,
240 Data_sz => 16,
176 Addr_sz => 8,
241 Addr_sz => 8,
177 FifoCnt => 5,
242 FifoCnt => 5)
178 Enable_ReUse => '0')
179 PORT MAP (
243 PORT MAP (
244 clk => clk,
180 rstn => rstn,
245 rstn => rstn,
181 wclk => clk,
246
182 rclk => clk,
183 ReUse => (OTHERS => '0'),
247 ReUse => (OTHERS => '0'),
184
248
185 wen => sample_f0_A_wen, -- IN in
249 wen => sample_f0_A_wen,
186 ren => sample_f0_A_ren, -- OUT in
250 wdata => sample_f0_wdata,
187 wdata => sample_f0_wdata, -- IN in
251
188 rdata => sample_f0_A_rdata, -- OUT in
252 ren => sample_f0_A_ren,
189 full => sample_f0_A_full, -- IN out
253 rdata => sample_f0_A_rdata,
190 almost_full => OPEN, -- IN out
254
191 empty => sample_f0_A_empty); -- OUT OUT
255 empty => sample_f0_A_empty,
256 full => sample_f0_A_full,
257 almost_full => OPEN);
192
258
193 lppFIFOxN_f0_b : lppFIFOxN
259 lppFIFOxN_f0_b : lppFIFOxN
194 GENERIC MAP (
260 GENERIC MAP (
@@ -196,21 +262,20 BEGIN
196 Mem_use => Mem_use,
262 Mem_use => Mem_use,
197 Data_sz => 16,
263 Data_sz => 16,
198 Addr_sz => 8,
264 Addr_sz => 8,
199 FifoCnt => 5,
265 FifoCnt => 5)
200 Enable_ReUse => '0')
201 PORT MAP (
266 PORT MAP (
267 clk => clk,
202 rstn => rstn,
268 rstn => rstn,
203 wclk => clk,
269
204 rclk => clk,
205 ReUse => (OTHERS => '0'),
270 ReUse => (OTHERS => '0'),
206
271
207 wen => sample_f0_B_wen, -- IN in
272 wen => sample_f0_B_wen,
208 ren => sample_f0_B_ren, -- OUT in
273 wdata => sample_f0_wdata,
209 wdata => sample_f0_wdata, -- IN in
274 ren => sample_f0_B_ren,
210 rdata => sample_f0_B_rdata, -- OUT in
275 rdata => sample_f0_B_rdata,
211 full => sample_f0_B_full, -- IN out
276 empty => sample_f0_B_empty,
212 almost_full => OPEN, -- IN out
277 full => sample_f0_B_full,
213 empty => sample_f0_B_empty); -- OUT OUT
278 almost_full => OPEN);
214
279
215 lppFIFOxN_f1 : lppFIFOxN
280 lppFIFOxN_f1 : lppFIFOxN
216 GENERIC MAP (
281 GENERIC MAP (
@@ -218,31 +283,30 BEGIN
218 Mem_use => Mem_use,
283 Mem_use => Mem_use,
219 Data_sz => 16,
284 Data_sz => 16,
220 Addr_sz => 8,
285 Addr_sz => 8,
221 FifoCnt => 5,
286 FifoCnt => 5)
222 Enable_ReUse => '0')
223 PORT MAP (
287 PORT MAP (
288 clk => clk,
224 rstn => rstn,
289 rstn => rstn,
225 wclk => clk,
290
226 rclk => clk,
227 ReUse => (OTHERS => '0'),
291 ReUse => (OTHERS => '0'),
228
292
229 wen => sample_f1_wen, -- IN in
293 wen => sample_f1_wen,
230 ren => sample_f1_ren, -- OUT in
294 wdata => sample_f1_wdata,
231 wdata => sample_f1_wdata, -- IN in
295 ren => sample_f1_ren,
232 rdata => sample_f1_rdata, -- OUT in
296 rdata => sample_f1_rdata,
233 full => sample_f1_full, -- IN out
297 empty => sample_f1_empty,
234 almost_full => sample_f1_almost_full, -- IN out
298 full => sample_f1_full,
235 empty => sample_f1_empty); -- OUT OUT
299 almost_full => sample_f1_almost_full);
236
300
237
301
238 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
302 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
239
303
240 PROCESS (clk, rstn)
304 PROCESS (clk, rstn)
241 BEGIN -- PROCESS
305 BEGIN -- PROCESS
242 IF rstn = '0' THEN -- asynchronous reset (active low)
306 IF rstn = '0' THEN -- asynchronous reset (active low)
243 one_sample_f1_full <= '0';
307 one_sample_f1_full <= '0';
244 error_wen_f1 <= '0';
308 error_wen_f1 <= '0';
245 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
309 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
246 IF sample_f1_full = "00000" THEN
310 IF sample_f1_full = "00000" THEN
247 one_sample_f1_full <= '0';
311 one_sample_f1_full <= '0';
248 ELSE
312 ELSE
@@ -251,7 +315,7 BEGIN
251 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
315 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
252 END IF;
316 END IF;
253 END PROCESS;
317 END PROCESS;
254
318
255
319
256 lppFIFOxN_f2 : lppFIFOxN
320 lppFIFOxN_f2 : lppFIFOxN
257 GENERIC MAP (
321 GENERIC MAP (
@@ -259,31 +323,30 BEGIN
259 Mem_use => Mem_use,
323 Mem_use => Mem_use,
260 Data_sz => 16,
324 Data_sz => 16,
261 Addr_sz => 8,
325 Addr_sz => 8,
262 FifoCnt => 5,
326 FifoCnt => 5)
263 Enable_ReUse => '0')
264 PORT MAP (
327 PORT MAP (
328 clk => clk,
265 rstn => rstn,
329 rstn => rstn,
266 wclk => clk,
330
267 rclk => clk,
268 ReUse => (OTHERS => '0'),
331 ReUse => (OTHERS => '0'),
269
332
270 wen => sample_f2_wen, -- IN in
333 wen => sample_f2_wen,
271 ren => sample_f2_ren, -- OUT in
334 wdata => sample_f2_wdata,
272 wdata => sample_f2_wdata, -- IN in
335 ren => sample_f2_ren,
273 rdata => sample_f2_rdata, -- OUT in
336 rdata => sample_f2_rdata,
274 full => sample_f2_full, -- IN out
337 empty => sample_f2_empty,
275 almost_full => OPEN, -- IN out
338 full => sample_f2_full,
276 empty => sample_f2_empty); -- OUT OUT
339 almost_full => OPEN);
277
340
278
341
279 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
342 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
280
343
281 PROCESS (clk, rstn)
344 PROCESS (clk, rstn)
282 BEGIN -- PROCESS
345 BEGIN -- PROCESS
283 IF rstn = '0' THEN -- asynchronous reset (active low)
346 IF rstn = '0' THEN -- asynchronous reset (active low)
284 one_sample_f2_full <= '0';
347 one_sample_f2_full <= '0';
285 error_wen_f2 <= '0';
348 error_wen_f2 <= '0';
286 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
349 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
287 IF sample_f2_full = "00000" THEN
350 IF sample_f2_full = "00000" THEN
288 one_sample_f2_full <= '0';
351 one_sample_f2_full <= '0';
289 ELSE
352 ELSE
@@ -337,6 +400,14 BEGIN
337 END IF;
400 END IF;
338 END PROCESS;
401 END PROCESS;
339
402
403 PROCESS (clk, rstn)
404 BEGIN
405 IF rstn = '0' THEN
406 pre_state_fsm_select_channel <= IDLE;
407 ELSIF clk'EVENT AND clk = '1' THEN
408 pre_state_fsm_select_channel <= state_fsm_select_channel;
409 END IF;
410 END PROCESS;
340
411
341
412
342 -----------------------------------------------------------------------------
413 -----------------------------------------------------------------------------
@@ -354,9 +425,9 BEGIN
354 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
425 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
355 (OTHERS => '0');
426 (OTHERS => '0');
356
427
357 sample_rdata <= sample_f0_A_rdata WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
428 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
358 sample_f0_B_rdata WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
429 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
359 sample_f1_rdata WHEN state_fsm_select_channel = SWITCH_F1 ELSE
430 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
360 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
431 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
361
432
362
433
@@ -365,77 +436,67 BEGIN
365 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
436 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
366 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
437 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
367
438
439
440 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
441 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
442 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
443 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
444
368 -----------------------------------------------------------------------------
445 -----------------------------------------------------------------------------
369 -- FSM LOAD FFT
446 -- FSM LOAD FFT
370 -----------------------------------------------------------------------------
447 -----------------------------------------------------------------------------
371
448
372 sample_ren <= sample_ren_s;-- OR sample_empty;
449 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
373
450
374 PROCESS (clk, rstn)
451 PROCESS (clk, rstn)
375 BEGIN
452 BEGIN
376 IF rstn = '0' THEN
453 IF rstn = '0' THEN
377 sample_ren_s <= (OTHERS => '1');
454 sample_ren_s <= (OTHERS => '1');
378 state_fsm_load_FFT <= IDLE;
455 state_fsm_load_FFT <= IDLE;
379 next_state_fsm_load_FFT <= IDLE;
456 --next_state_fsm_load_FFT <= IDLE;
380 sample_valid <= '0';
457 --sample_valid <= '0';
381 ELSIF clk'event AND clk = '1' THEN
458 ELSIF clk'EVENT AND clk = '1' THEN
382 CASE state_fsm_load_FFT IS
459 CASE state_fsm_load_FFT IS
383 WHEN IDLE =>
460 WHEN IDLE =>
384 sample_valid <= '0';
461 --sample_valid <= '0';
385 sample_ren_s <= (OTHERS => '1');
462 sample_ren_s <= (OTHERS => '1');
386 IF sample_full = "11111" AND sample_load = '1' THEN
463 IF sample_full = "11111" AND sample_load = '1' THEN
387 state_fsm_load_FFT <= FIFO_1;
464 state_fsm_load_FFT <= FIFO_1;
388 END IF;
465 END IF;
389 WHEN FIFO_1 =>
466
467 WHEN FIFO_1 =>
390 sample_ren_s <= "1111" & NOT(sample_load);
468 sample_ren_s <= "1111" & NOT(sample_load);
391 sample_valid <= '1';
392 IF sample_empty(0) = '1' THEN
469 IF sample_empty(0) = '1' THEN
393 sample_valid <= '0';
470 sample_ren_s <= (OTHERS => '1');
394 sample_ren_s <= (OTHERS => '1');
471 state_fsm_load_FFT <= FIFO_2;
395 state_fsm_load_FFT <= FIFO_transition;
472 END IF;
396 next_state_fsm_load_FFT <= FIFO_2;
473
474 WHEN FIFO_2 =>
475 sample_ren_s <= "111" & NOT(sample_load) & '1';
476 IF sample_empty(1) = '1' THEN
477 sample_ren_s <= (OTHERS => '1');
478 state_fsm_load_FFT <= FIFO_3;
397 END IF;
479 END IF;
398
480
399 WHEN FIFO_transition =>
481 WHEN FIFO_3 =>
400 sample_valid <= '0';
401 sample_ren_s <= (OTHERS => '1');
402 state_fsm_load_FFT <= next_state_fsm_load_FFT;
403
404 WHEN FIFO_2 =>
405 sample_ren_s <= "111" & NOT(sample_load) & '1';
406 sample_valid <= sample_load;
407 IF sample_empty(1) = '1' THEN
408 sample_valid <= '0';
409 sample_ren_s <= (OTHERS => '1');
410 state_fsm_load_FFT <= FIFO_transition;
411 next_state_fsm_load_FFT <= FIFO_3;
412 END IF;
413 WHEN FIFO_3 =>
414 sample_ren_s <= "11" & NOT(sample_load) & "11";
482 sample_ren_s <= "11" & NOT(sample_load) & "11";
415 sample_valid <= sample_load;--'1';
416 IF sample_empty(2) = '1' THEN
483 IF sample_empty(2) = '1' THEN
417 sample_valid <= '0';
484 sample_ren_s <= (OTHERS => '1');
418 sample_ren_s <= (OTHERS => '1');
485 state_fsm_load_FFT <= FIFO_4;
419 state_fsm_load_FFT <= FIFO_transition;
420 next_state_fsm_load_FFT <= FIFO_4;
421 END IF;
486 END IF;
422 WHEN FIFO_4 =>
487
488 WHEN FIFO_4 =>
423 sample_ren_s <= '1' & NOT(sample_load) & "111";
489 sample_ren_s <= '1' & NOT(sample_load) & "111";
424 sample_valid <= sample_load;--'1';
425 IF sample_empty(3) = '1' THEN
490 IF sample_empty(3) = '1' THEN
426 sample_valid <= '0';
491 sample_ren_s <= (OTHERS => '1');
427 sample_ren_s <= (OTHERS => '1');
492 state_fsm_load_FFT <= FIFO_5;
428 state_fsm_load_FFT <= FIFO_transition;
429 next_state_fsm_load_FFT <= FIFO_5;
430 END IF;
493 END IF;
431 WHEN FIFO_5 =>
494
495 WHEN FIFO_5 =>
432 sample_ren_s <= NOT(sample_load) & "1111";
496 sample_ren_s <= NOT(sample_load) & "1111";
433 sample_valid <= sample_load;--'1';
434 IF sample_empty(4) = '1' THEN
497 IF sample_empty(4) = '1' THEN
435 sample_valid <= '0';
498 sample_ren_s <= (OTHERS => '1');
436 sample_ren_s <= (OTHERS => '1');
499 state_fsm_load_FFT <= IDLE;
437 state_fsm_load_FFT <= FIFO_transition;
438 next_state_fsm_load_FFT <= IDLE;
439 END IF;
500 END IF;
440 WHEN OTHERS => NULL;
501 WHEN OTHERS => NULL;
441 END CASE;
502 END CASE;
@@ -445,22 +506,30 BEGIN
445 PROCESS (clk, rstn)
506 PROCESS (clk, rstn)
446 BEGIN
507 BEGIN
447 IF rstn = '0' THEN
508 IF rstn = '0' THEN
448 sample_valid_r <= '0';
509 sample_valid_r <= '0';
449 ELSIF clk'event AND clk = '1' THEN
510 next_state_fsm_load_FFT <= IDLE;
450 sample_valid_r <= sample_valid AND sample_load;
511 ELSIF clk'EVENT AND clk = '1' THEN
512 next_state_fsm_load_FFT <= state_fsm_load_FFT;
513 IF sample_ren_s = "11111" THEN
514 sample_valid_r <= '0';
515 ELSE
516 sample_valid_r <= '1';
517 END IF;
451 END IF;
518 END IF;
452 END PROCESS;
519 END PROCESS;
453
520
454 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN state_fsm_load_FFT = FIFO_1 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_2) ELSE
521 sample_valid <= sample_valid_r AND sample_load;
455 sample_rdata(16*2-1 DOWNTO 16*1) WHEN state_fsm_load_FFT = FIFO_2 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_3) ELSE
522
456 sample_rdata(16*3-1 DOWNTO 16*2) WHEN state_fsm_load_FFT = FIFO_3 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_4) ELSE
523 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
457 sample_rdata(16*4-1 DOWNTO 16*3) WHEN state_fsm_load_FFT = FIFO_4 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_5) ELSE
524 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
458 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN state_fsm_load_FFT = FIFO_5 ELSE
525 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
526 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
527 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
459
528
460 -----------------------------------------------------------------------------
529 -----------------------------------------------------------------------------
461 -- FFT
530 -- FFT
462 -----------------------------------------------------------------------------
531 -----------------------------------------------------------------------------
463 CoreFFT_1: CoreFFT
532 CoreFFT_1 : CoreFFT
464 GENERIC MAP (
533 GENERIC MAP (
465 LOGPTS => gLOGPTS,
534 LOGPTS => gLOGPTS,
466 LOGLOGPTS => gLOGLOGPTS,
535 LOGLOGPTS => gLOGLOGPTS,
@@ -474,11 +543,11 BEGIN
474 HALFPTS => gHALFPTS,
543 HALFPTS => gHALFPTS,
475 inBuf_RWDLY => gInBuf_RWDLY)
544 inBuf_RWDLY => gInBuf_RWDLY)
476 PORT MAP (
545 PORT MAP (
477 clk => clk,
546 clk => clk,
478 ifiStart => '1',
547 ifiStart => '1',
479 ifiNreset => rstn,
548 ifiNreset => rstn,
480
549
481 ifiD_valid => sample_valid_r, -- IN
550 ifiD_valid => sample_valid, -- IN
482 ifiRead_y => fft_read,
551 ifiRead_y => fft_read,
483 ifiD_im => (OTHERS => '0'), -- IN
552 ifiD_im => (OTHERS => '0'), -- IN
484 ifiD_re => sample_data, -- IN
553 ifiD_re => sample_data, -- IN
@@ -491,37 +560,336 BEGIN
491 ifoY_rdy => fft_ready);
560 ifoY_rdy => fft_ready);
492
561
493 -----------------------------------------------------------------------------
562 -----------------------------------------------------------------------------
494 --
563 -- in fft_data_im & fft_data_re
564 -- in fft_data_valid
565 -- in fft_ready
566 -- out fft_read
567 PROCESS (clk, rstn)
568 BEGIN
569 IF rstn = '0' THEN
570 state_fsm_load_MS_memory <= IDLE;
571 current_fifo_load <= "00001";
572 ELSIF clk'event AND clk = '1' THEN
573 CASE state_fsm_load_MS_memory IS
574 WHEN IDLE =>
575 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
576 state_fsm_load_MS_memory <= LOAD_FIFO;
577 END IF;
578 WHEN LOAD_FIFO =>
579 IF current_fifo_full = '1' THEN
580 state_fsm_load_MS_memory <= TRASH_FFT;
581 END IF;
582 WHEN TRASH_FFT =>
583 IF fft_ready = '0' THEN
584 state_fsm_load_MS_memory <= IDLE;
585 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
586 END IF;
587 WHEN OTHERS => NULL;
588 END CASE;
589
590 END IF;
591 END PROCESS;
592
593 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
594 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
595 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
596 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
597 MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE
598
599 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
600 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
601 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
602 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
603 MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE
604
605 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
606 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
607 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
608 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
609 MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE
610
611 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
612
613 all_fifo: FOR I IN 4 DOWNTO 0 GENERATE
614 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
615 AND state_fsm_load_MS_memory = LOAD_FIFO
616 AND current_fifo_load(I) = '1'
617 ELSE '1';
618 END GENERATE all_fifo;
619
620 PROCESS (clk, rstn)
621 BEGIN
622 IF rstn = '0' THEN
623 MEM_IN_SM_wen <= (OTHERS => '1');
624 ELSIF clk'event AND clk = '1' THEN
625 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
626 END IF;
627 END PROCESS;
628
629 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
630 (fft_data_im & fft_data_re) &
631 (fft_data_im & fft_data_re) &
632 (fft_data_im & fft_data_re) &
633 (fft_data_im & fft_data_re);
634
635
636 -- out SM_MEM_IN_wData
637 -- out SM_MEM_IN_wen
638 -- out SM_MEM_IN_Full
639
640 -- out SM_MEM_IN_locked
641 -----------------------------------------------------------------------------
642 -----------------------------------------------------------------------------
643 -----------------------------------------------------------------------------
644 -----------------------------------------------------------------------------
645 --Linker_FFT_1 : Linker_FFT
646 -- GENERIC MAP (
647 -- Data_sz => 16,
648 -- NbData => 256)
649 -- PORT MAP (
650 -- clk => clk,
651 -- rstn => rstn,
652
653 -- Ready => fft_ready,
654 -- Valid => fft_data_valid,
655
656 -- Full => MEM_IN_SM_Full,
657
658 -- Data_re => fft_data_re,
659 -- Data_im => fft_data_im,
660 -- Read => fft_read,
661
662 -- Write => MEM_IN_SM_wen,
663 -- ReUse => fft_linker_ReUse,
664 -- DATA => MEM_IN_SM_wData);
665
495 -----------------------------------------------------------------------------
666 -----------------------------------------------------------------------------
496 fft_read <= '1';
667 Mem_In_SpectralMatrix : lppFIFOxN
497 -- fft_read OUT
668 GENERIC MAP (
498 -- fft_pong IN
669 tech => 0,
499 -- fft_data_im IN
670 Mem_use => Mem_use,
500 -- fft_data_re IN
671 Data_sz => 32, --16,
501 -- fft_data_valid IN
672 Addr_sz => 7, --8
502 -- fft_ready IN
673 FifoCnt => 5)
674 PORT MAP (
675 clk => clk,
676 rstn => rstn,
677
678 ReUse => MEM_IN_SM_ReUse,
679
680 wen => MEM_IN_SM_wen,
681 wdata => MEM_IN_SM_wData,
682
683 ren => MEM_IN_SM_ren,
684 rdata => MEM_IN_SM_rData,
685 full => MEM_IN_SM_Full,
686 empty => MEM_IN_SM_Empty);
687
688
689 all_lock: FOR I IN 4 DOWNTO 0 GENERATE
690 PROCESS (clk, rstn)
691 BEGIN
692 IF rstn = '0' THEN
693 MEM_IN_SM_locked(I) <= '0';
694 ELSIF clk'event AND clk = '1' THEN
695 MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO
696 END IF;
697 END PROCESS;
698 END GENERATE all_lock;
699
700
701
702 -----------------------------------------------------------------------------
703 SM0 : MatriceSpectrale
704 GENERIC MAP (
705 Input_SZ => 16,
706 Result_SZ => 32)
707 PORT MAP (
708 clkm => clk,
709 rstn => rstn,
710
711 FifoIN_Full => MEM_IN_SM_Full,
712 Data_IN => MEM_IN_SM_rData(79 DOWNTO 0),
713 Read => MEM_IN_SM_ren,
714 ReUse => MEM_IN_SM_ReUse,
715
716 SetReUse => fft_linker_ReUse,
717
718 Valid => HEAD_Valid,
719 ACK => DMA_Header_Ack,
720 SM_Write => HEAD_SM_Wen,
721 FlagError => OPEN,
722 Statu => HEAD_SM_Param,
723 Write => MEM_OUT_SM_Write,
724 Data_OUT => MEM_OUT_SM_Data_in);
725 -----------------------------------------------------------------------------
726 Mem_Out_SpectralMatrix : lppFIFOxN
727 GENERIC MAP (
728 tech => 0,
729 Mem_use => Mem_use,
730 Data_sz => 32,
731 Addr_sz => 8,
732 FifoCnt => 2)
733 PORT MAP (
734 clk => clk,
735 rstn => rstn,
736
737 ReUse => (OTHERS => '0'),
738
739 wen => MEM_OUT_SM_Write,
740 wdata => MEM_OUT_SM_Data_in,
741 ren => MEM_OUT_SM_Read,
742 rdata => MEM_OUT_SM_Data_out,
743
744 full => MEM_OUT_SM_Full,
745 empty => MEM_OUT_SM_Empty);
746 -----------------------------------------------------------------------------
747 Head0 : HeaderBuilder
748 GENERIC MAP (
749 Data_sz => 32)
750 PORT MAP (
751 clkm => clk,
752 rstn => rstn,
753
754 Statu => HEAD_SM_Param,
755 Matrix_Type => HEAD_WorkFreq, -- TODO IN
756 Matrix_Write => HEAD_SM_Wen,
757 Valid => HEAD_Valid,
758
759 dataIN => MEM_OUT_SM_Data_out,
760 emptyIN => MEM_OUT_SM_Empty,
761 RenOUT => MEM_OUT_SM_Read,
762
763 dataOUT => HEAD_Data,
764 emptyOUT => HEAD_Empty,
765 RenIN => HEAD_Read,
766
767 header => DMA_Header,
768 header_val => DMA_Header_Val,
769 header_ack => DMA_Header_Ack);
770 -----------------------------------------------------------------------------
771 -----------------------------------------------------------------------------
772 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
773 PORT MAP (
774 HCLK => clk,
775 HRESETn => rstn,
776
777 data_time => dma_time,
778
779 fifo_data => HEAD_Data,
780 fifo_empty => HEAD_Empty,
781 fifo_ren => HEAD_Read,
782
783 header => DMA_Header,
784 header_val => DMA_Header_Val,
785 header_ack => DMA_Header_Ack,
786
787 dma_addr => dma_addr,
788 dma_data => dma_data,
789 dma_valid => dma_valid,
790 dma_valid_burst => dma_valid_burst,
791 dma_ren => dma_ren,
792 dma_done => dma_done,
793
794 ready_matrix_f0_0 => ready_matrix_f0_0,
795 ready_matrix_f0_1 => ready_matrix_f0_1,
796 ready_matrix_f1 => ready_matrix_f1,
797 ready_matrix_f2 => ready_matrix_f2,
798 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
799 error_bad_component_error => error_bad_component_error,
800 debug_reg => debug_reg,
801 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
802 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
803 status_ready_matrix_f1 => status_ready_matrix_f1,
804 status_ready_matrix_f2 => status_ready_matrix_f2,
805 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
806 status_error_bad_component_error => status_error_bad_component_error,
807 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
808 config_active_interruption_onError => config_active_interruption_onError,
809 addr_matrix_f0_0 => addr_matrix_f0_0,
810 addr_matrix_f0_1 => addr_matrix_f0_1,
811 addr_matrix_f1 => addr_matrix_f1,
812 addr_matrix_f2 => addr_matrix_f2,
813
814 matrix_time_f0_0 => matrix_time_f0_0,
815 matrix_time_f0_1 => matrix_time_f0_1,
816 matrix_time_f1 => matrix_time_f1,
817 matrix_time_f2 => matrix_time_f2
818 );
819 -----------------------------------------------------------------------------
503
820
504 -----------------------------------------------------------------------------
821 -----------------------------------------------------------------------------
505 --
822 -----------------------------------------------------------------------------
823 -----------------------------------------------------------------------------
824 -----------------------------------------------------------------------------
825 -----------------------------------------------------------------------------
506 -----------------------------------------------------------------------------
826 -----------------------------------------------------------------------------
827
828
829
830
831
832
833 -----------------------------------------------------------------------------
834 -- TIME MANAGMENT
835 -----------------------------------------------------------------------------
836 all_time <= coarse_time & fine_time;
837 --
838 time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE
839 '1' WHEN sample_f0_A_empty = "11111" ELSE
840 '0';
507
841
508 dma_addr <= (OTHERS => '0');
842 s_m_t_m_f0_A : spectral_matrix_time_managment
509 dma_data <= (OTHERS => '0');
843 PORT MAP (
510 dma_valid <= '0';
844 clk => clk,
511 dma_valid_burst <= '0';
845 rstn => rstn,
846 time_in => all_time,
847 update_1 => time_update_f0_A,
848 time_out => time_reg_f0_A);
849
850 --
851 time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE
852 '1' WHEN sample_f0_B_empty = "11111" ELSE
853 '0';
512
854
513 ready_matrix_f0_0 <= '0';
855 s_m_t_m_f0_B : spectral_matrix_time_managment
514 ready_matrix_f0_1 <= '0';
856 PORT MAP (
515 ready_matrix_f1 <= '0';
857 clk => clk,
516 ready_matrix_f2 <= '0';
858 rstn => rstn,
517 error_anticipating_empty_fifo <= '0';
859 time_in => all_time,
518 error_bad_component_error <= '0';
860 update_1 => time_update_f0_B,
519 debug_reg <= (OTHERS => '0');
861 time_out => time_reg_f0_B);
862
863 --
864 time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE
865 '1' WHEN sample_f1_empty = "11111" ELSE
866 '0';
867
868 s_m_t_m_f1 : spectral_matrix_time_managment
869 PORT MAP (
870 clk => clk,
871 rstn => rstn,
872 time_in => all_time,
873 update_1 => time_update_f1,
874 time_out => time_reg_f1);
520
875
521 matrix_time_f0_0 <= (OTHERS => '0');
876 --
522 matrix_time_f0_1 <= (OTHERS => '0');
877 time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE
523 matrix_time_f1 <= (OTHERS => '0');
878 '1' WHEN sample_f2_empty = "11111" ELSE
524 matrix_time_f2 <= (OTHERS => '0');
879 '0';
880
881 s_m_t_m_f2 : spectral_matrix_time_managment
882 PORT MAP (
883 clk => clk,
884 rstn => rstn,
885 time_in => all_time,
886 update_1 => time_update_f2,
887 time_out => time_reg_f2);
525
888
526
889 -----------------------------------------------------------------------------
890 dma_time <= (OTHERS => '0'); -- TODO
891 -----------------------------------------------------------------------------
892
893
894
527 END Behavioral;
895 END Behavioral;
Show file before | Show file after | Hide comments
@@ -19,181 +19,223
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 LIBRARY ieee;
23 use ieee.std_logic_1164.all;
23 USE ieee.std_logic_1164.ALL;
24 library grlib;
24 LIBRARY grlib;
25 use grlib.amba.all;
25 USE grlib.amba.ALL;
26 use std.textio.all;
26 USE std.textio.ALL;
27 library lpp;
27 LIBRARY lpp;
28 use lpp.lpp_amba.all;
28 USE lpp.lpp_amba.ALL;
29 use lpp.iir_filter.all;
29 USE lpp.iir_filter.ALL;
30 library gaisler;
30 LIBRARY gaisler;
31 use gaisler.misc.all;
31 USE gaisler.misc.ALL;
32 use gaisler.memctrl.all;
32 USE gaisler.memctrl.ALL;
33 library techmap;
33 LIBRARY techmap;
34 use techmap.gencomp.all;
34 USE techmap.gencomp.ALL;
35
35
36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
37
37
38 package lpp_memory is
38 PACKAGE lpp_memory IS
39
40 component APB_FIFO is
41 generic (
42 tech : integer := apa3;
43 pindex : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
47 abits : integer := 8;
48 FifoCnt : integer := 2;
49 Data_sz : integer := 16;
50 Addr_sz : integer := 9;
51 Enable_ReUse : std_logic := '0';
52 Mem_use : integer := use_RAM;
53 R : integer := 1;
54 W : integer := 1
55 );
56 port (
57 clk : in std_logic; --! Horloge du composant
58 rst : in std_logic; --! Reset general du composant
59 rclk : in std_logic;
60 wclk : in std_logic;
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
70 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
72 );
73 end component;
74
39
75 component FIFO_pipeline is
40 COMPONENT lpp_fifo
76 generic(
41 GENERIC (
77 tech : integer := 0;
42 tech : INTEGER;
78 Mem_use : integer := use_RAM;
43 Mem_use : INTEGER;
79 fifoCount : integer range 2 to 32 := 8;
44 DataSz : INTEGER RANGE 1 TO 32;
80 DataSz : integer range 1 to 32 := 8;
45 AddrSz : INTEGER RANGE 2 TO 12);
81 abits : integer range 2 to 12 := 8
46 PORT (
82 );
47 clk : IN STD_LOGIC;
83 port(
48 rstn : IN STD_LOGIC;
84 rstn : in std_logic;
49 reUse : IN STD_LOGIC;
85 ReUse : in std_logic;
50 ren : IN STD_LOGIC;
86 rclk : in std_logic;
51 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
87 ren : in std_logic;
52 wen : IN STD_LOGIC;
88 rdata : out std_logic_vector(DataSz-1 downto 0);
53 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
89 empty : out std_logic;
54 empty : OUT STD_LOGIC;
90 raddr : out std_logic_vector(abits-1 downto 0);
55 full : OUT STD_LOGIC;
91 wclk : in std_logic;
56 almost_full : OUT STD_LOGIC);
92 wen : in std_logic;
57 END COMPONENT;
93 wdata : in std_logic_vector(DataSz-1 downto 0);
94 full : out std_logic;
95 waddr : out std_logic_vector(abits-1 downto 0)
96 );
97 end component;
98
58
99 component lpp_fifo is
59 COMPONENT lppFIFOxN
100 generic(
60 GENERIC (
101 tech : integer := 0;
61 tech : INTEGER;
102 Mem_use : integer := use_RAM;
62 Mem_use : INTEGER;
103 Enable_ReUse : std_logic := '0';
63 Data_sz : INTEGER RANGE 1 TO 32;
104 DataSz : integer range 1 to 32 := 8;
64 Addr_sz : INTEGER RANGE 2 TO 12;
105 AddrSz : integer range 2 to 12 := 8
65 FifoCnt : INTEGER);
106 );
66 PORT (
107 port(
67 clk : IN STD_LOGIC;
108 rstn : in std_logic;
68 rstn : IN STD_LOGIC;
109 ReUse : in std_logic; --27/01/12
69 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
110 rclk : in std_logic;
70 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
111 ren : in std_logic;
71 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
112 rdata : out std_logic_vector(DataSz-1 downto 0);
72 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
113 empty : out std_logic;
73 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
114 raddr : out std_logic_vector(AddrSz-1 downto 0);
74 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
115 wclk : in std_logic;
75 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
116 wen : in std_logic;
76 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0));
117 wdata : in std_logic_vector(DataSz-1 downto 0);
77 END COMPONENT;
118 full : out std_logic;
119 almost_full : out std_logic;
120 waddr : out std_logic_vector(AddrSz-1 downto 0)
121 );
122 end component;
123
78
124
79
125 component lppFIFOxN is
80
126 generic(
127 tech : integer := 0;
128 Mem_use : integer := use_RAM;
129 Data_sz : integer range 1 to 32 := 8;
130 Addr_sz : integer range 1 to 32 := 8;
131 FifoCnt : integer := 1;
132 Enable_ReUse : std_logic := '0'
133 );
134 port(
135 rstn : in std_logic;
136 wclk : in std_logic;
137 rclk : in std_logic;
138 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
139 wen : in std_logic_vector(FifoCnt-1 downto 0);
140 ren : in std_logic_vector(FifoCnt-1 downto 0);
141 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
142 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
143 full : out std_logic_vector(FifoCnt-1 downto 0);
144 almost_full : out std_logic_vector(FifoCnt-1 downto 0);
145 empty : out std_logic_vector(FifoCnt-1 downto 0)
146 );
147 end component;
148
81
149 component FillFifo is
82 COMPONENT APB_FIFO IS
150 generic(
83 GENERIC (
151 Data_sz : integer range 1 to 32 := 16;
84 tech : INTEGER := apa3;
152 Fifo_cnt : integer range 1 to 8 := 5
85 pindex : INTEGER := 0;
153 );
86 paddr : INTEGER := 0;
154 port(
87 pmask : INTEGER := 16#fff#;
155 clk : in std_logic;
88 pirq : INTEGER := 0;
156 raz : in std_logic;
89 abits : INTEGER := 8;
157 write : out std_logic_vector(Fifo_cnt-1 downto 0);
90 FifoCnt : INTEGER := 2;
158 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
91 Data_sz : INTEGER := 16;
159 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
92 Addr_sz : INTEGER := 9;
160 );
93 Enable_ReUse : STD_LOGIC := '0';
161 end component;
94 Mem_use : INTEGER := use_RAM;
95 R : INTEGER := 1;
96 W : INTEGER := 1
97 );
98 PORT (
99 clk : IN STD_LOGIC; --! Horloge du composant
100 rst : IN STD_LOGIC; --! Reset general du composant
101 rclk : IN STD_LOGIC;
102 wclk : IN STD_LOGIC;
103 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
104 REN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction de lecture en mοΏ½moire
105 WEN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction d'οΏ½criture en mοΏ½moire
106 Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire vide
107 Full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire pleine
108 RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en entrοΏ½e
109 WDATA : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en sortie
110 WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (οΏ½criture)
111 RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (lecture)
112 apbi : IN apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
113 apbo : OUT apb_slv_out_type --! Registre de gestion des sorties du bus
114 );
115 END COMPONENT;
116
117 COMPONENT FIFO_pipeline IS
118 GENERIC(
119 tech : INTEGER := 0;
120 Mem_use : INTEGER := use_RAM;
121 fifoCount : INTEGER RANGE 2 TO 32 := 8;
122 DataSz : INTEGER RANGE 1 TO 32 := 8;
123 abits : INTEGER RANGE 2 TO 12 := 8
124 );
125 PORT(
126 rstn : IN STD_LOGIC;
127 ReUse : IN STD_LOGIC;
128 rclk : IN STD_LOGIC;
129 ren : IN STD_LOGIC;
130 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
131 empty : OUT STD_LOGIC;
132 raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
133 wclk : IN STD_LOGIC;
134 wen : IN STD_LOGIC;
135 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
136 full : OUT STD_LOGIC;
137 waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0)
138 );
139 END COMPONENT;
162
140
163 component Bridge is
141 --COMPONENT lpp_fifo IS
164 port(
142 -- GENERIC(
165 clk : in std_logic;
143 -- tech : INTEGER := 0;
166 raz : in std_logic;
144 -- Mem_use : INTEGER := use_RAM;
167 EmptyUp : in std_logic;
145 -- Enable_ReUse : STD_LOGIC := '0';
168 FullDwn : in std_logic;
146 -- DataSz : INTEGER RANGE 1 TO 32 := 8;
169 WriteDwn : out std_logic;
147 -- AddrSz : INTEGER RANGE 2 TO 12 := 8
170 ReadUp : out std_logic
148 -- );
171 );
149 -- PORT(
172 end component;
150 -- rstn : IN STD_LOGIC;
151 -- ReUse : IN STD_LOGIC; --27/01/12
152 -- rclk : IN STD_LOGIC;
153 -- ren : IN STD_LOGIC;
154 -- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
155 -- empty : OUT STD_LOGIC;
156 -- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
157 -- wclk : IN STD_LOGIC;
158 -- wen : IN STD_LOGIC;
159 -- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
160 -- full : OUT STD_LOGIC;
161 -- almost_full : OUT STD_LOGIC;
162 -- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
163 -- );
164 --END COMPONENT;
165
166
167 --COMPONENT lppFIFOxN IS
168 -- GENERIC(
169 -- tech : INTEGER := 0;
170 -- Mem_use : INTEGER := use_RAM;
171 -- Data_sz : INTEGER RANGE 1 TO 32 := 8;
172 -- Addr_sz : INTEGER RANGE 1 TO 32 := 8;
173 -- FifoCnt : INTEGER := 1;
174 -- Enable_ReUse : STD_LOGIC := '0'
175 -- );
176 -- PORT(
177 -- rstn : IN STD_LOGIC;
178 -- wclk : IN STD_LOGIC;
179 -- rclk : IN STD_LOGIC;
180 -- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
181 -- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
182 -- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
183 -- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
184 -- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
185 -- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
186 -- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
187 -- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
188 -- );
189 --END COMPONENT;
173
190
174 component ssram_plugin is
191 COMPONENT FillFifo IS
175 generic (tech : integer := 0);
192 GENERIC(
176 port
193 Data_sz : INTEGER RANGE 1 TO 32 := 16;
177 (
194 Fifo_cnt : INTEGER RANGE 1 TO 8 := 5
178 clk : in std_logic;
195 );
179 mem_ctrlr_o : in memory_out_type;
196 PORT(
180 SSRAM_CLK : out std_logic;
197 clk : IN STD_LOGIC;
181 nBWa : out std_logic;
198 raz : IN STD_LOGIC;
182 nBWb : out std_logic;
199 write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
183 nBWc : out std_logic;
200 reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
184 nBWd : out std_logic;
201 data : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0)
185 nBWE : out std_logic;
202 );
186 nADSC : out std_logic;
203 END COMPONENT;
187 nADSP : out std_logic;
204
188 nADV : out std_logic;
205 COMPONENT Bridge IS
189 nGW : out std_logic;
206 PORT(
190 nCE1 : out std_logic;
207 clk : IN STD_LOGIC;
191 CE2 : out std_logic;
208 raz : IN STD_LOGIC;
192 nCE3 : out std_logic;
209 EmptyUp : IN STD_LOGIC;
193 nOE : out std_logic;
210 FullDwn : IN STD_LOGIC;
194 MODE : out std_logic;
211 WriteDwn : OUT STD_LOGIC;
195 ZZ : out std_logic
212 ReadUp : OUT STD_LOGIC
196 );
213 );
197 end component;
214 END COMPONENT;
198
215
199 end;
216 COMPONENT ssram_plugin IS
217 GENERIC (tech : INTEGER := 0);
218 PORT
219 (
220 clk : IN STD_LOGIC;
221 mem_ctrlr_o : IN memory_out_type;
222 SSRAM_CLK : OUT STD_LOGIC;
223 nBWa : OUT STD_LOGIC;
224 nBWb : OUT STD_LOGIC;
225 nBWc : OUT STD_LOGIC;
226 nBWd : OUT STD_LOGIC;
227 nBWE : OUT STD_LOGIC;
228 nADSC : OUT STD_LOGIC;
229 nADSP : OUT STD_LOGIC;
230 nADV : OUT STD_LOGIC;
231 nGW : OUT STD_LOGIC;
232 nCE1 : OUT STD_LOGIC;
233 CE2 : OUT STD_LOGIC;
234 nCE3 : OUT STD_LOGIC;
235 nOE : OUT STD_LOGIC;
236 MODE : OUT STD_LOGIC;
237 ZZ : OUT STD_LOGIC
238 );
239 END COMPONENT;
240
241 END;
Show file before | Show file after | Hide comments
@@ -17,4 +17,13 PACKAGE spectral_matrix_package IS
17 error_wen : OUT STD_LOGIC);
17 error_wen : OUT STD_LOGIC);
18 END COMPONENT;
18 END COMPONENT;
19
19
20 COMPONENT spectral_matrix_time_managment
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
25 update_1 : IN STD_LOGIC;
26 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
27 END COMPONENT;
28
20 END spectral_matrix_package;
29 END spectral_matrix_package;
Show file before | Show file after | Hide comments
@@ -41,12 +41,29 add wave -noupdate -expand -group FFT_RE
41 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong
41 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong
42 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy
42 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy
43 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid
43 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid
44 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
44 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
45 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
45 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
46 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray
47 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
48 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
49 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
50 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
51 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
52 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
53 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
54 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
55 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
56 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
57 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
58 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
59 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
60 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
61 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
62 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
46 TreeUpdate [SetDefaultTree]
63 TreeUpdate [SetDefaultTree]
47 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {27617887437 ps} 0} {{Cursor 3} {10382020000 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {95613018769 ps} 0}
64 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {33725957281 ps} 0} {{Cursor 3} {10434056078 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {82561584962 ps} 0}
48 configure wave -namecolwidth 402
65 configure wave -namecolwidth 469
49 configure wave -valuecolwidth 199
66 configure wave -valuecolwidth 112
50 configure wave -justifyvalue left
67 configure wave -justifyvalue left
51 configure wave -signalnamewidth 0
68 configure wave -signalnamewidth 0
52 configure wave -snapdistance 10
69 configure wave -snapdistance 10
@@ -59,6 +76,6 configure wave -griddelta 40
59 configure wave -timeline 0
76 configure wave -timeline 0
60 configure wave -timelineunits ps
77 configure wave -timelineunits ps
61 update
78 update
62 WaveRestoreZoom {10380205948 ps} {10383691010 ps}
79 WaveRestoreZoom {10429891270 ps} {10442522246 ps}
63 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
80 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
64 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
81 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
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