diff --git a/designs/Validation_LFR_SpectralMatrix/Makefile b/designs/Validation_LFR_SpectralMatrix/Makefile
--- a/designs/Validation_LFR_SpectralMatrix/Makefile
+++ b/designs/Validation_LFR_SpectralMatrix/Makefile
@@ -58,6 +58,7 @@ vcom_tb:
 	$(CMD_VCOM) lpp  lpp_FIFO.vhd
 	$(CMD_VCOM) lpp  spectral_matrix_package.vhd
 	$(CMD_VCOM) lpp  spectral_matrix_switch_f0.vhd
+	$(CMD_VCOM) lpp  spectral_matrix_time_managment.vhd
 	$(CMD_VCOM) lpp  lpp_lfr_ms.vhd
 	$(CMD_VCOM) work TB.vhd
 	@echo "vcom done"
@@ -344,7 +345,52 @@ vcom_lpp:
 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
+	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
 	@echo "vcom lpp done"
 
 # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
diff --git a/designs/Validation_LFR_SpectralMatrix/lppFIFOxN.vhd b/designs/Validation_LFR_SpectralMatrix/lppFIFOxN.vhd
--- a/designs/Validation_LFR_SpectralMatrix/lppFIFOxN.vhd
+++ b/designs/Validation_LFR_SpectralMatrix/lppFIFOxN.vhd
@@ -19,52 +19,64 @@
 --                    Author : Martin Morlot
 --                     Mail : martin.morlot@lpp.polytechnique.fr
 ------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-library lpp;
-use lpp.lpp_memory.all;
-use lpp.iir_filter.all;
-library techmap;
-use techmap.gencomp.all;
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+LIBRARY lpp;
+USE lpp.lpp_memory.ALL;
+USE lpp.iir_filter.ALL;
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
 
-entity lppFIFOxN is
-generic(
-    tech          :   integer := 0;
-    Mem_use       :   integer := use_RAM;
-    Data_sz       :   integer range 1 to 32 := 8;
-    Addr_sz       :   integer range 2 to 12 := 8;
-    FifoCnt       :   integer := 1;
-    Enable_ReUse  :   std_logic := '0'
+ENTITY lppFIFOxN IS
+  GENERIC(
+    tech         : INTEGER               := 0;
+    Mem_use      : INTEGER               := use_RAM;
+    Data_sz      : INTEGER RANGE 1 TO 32 := 8;
+    Addr_sz      : INTEGER RANGE 2 TO 12 := 8;
+    FifoCnt      : INTEGER               := 1
     );
-port(
-    rstn     :   in std_logic;
-    wclk    :   in std_logic;    
-    rclk    :   in std_logic;
-    ReUse   :   in std_logic_vector(FifoCnt-1 downto 0);
-    wen     :   in std_logic_vector(FifoCnt-1 downto 0);
-    ren     :   in std_logic_vector(FifoCnt-1 downto 0);
-    wdata   :   in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
-    rdata   :   out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
-    full    :   out std_logic_vector(FifoCnt-1 downto 0);
-    almost_full    :   out std_logic_vector(FifoCnt-1 downto 0);  -- TODO
-    empty   :   out std_logic_vector(FifoCnt-1 downto 0)
-);
-end entity;
+  PORT(
+    clk  : IN STD_LOGIC;
+    rstn : IN STD_LOGIC;
+
+    ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+
+    wen   : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+    wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
+
+    ren   : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+    rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
+
+    empty       : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+    full        : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+    almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
+    );
+END ENTITY;
 
 
-architecture ar_lppFIFOxN of lppFIFOxN is
+ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS
 
-begin
+BEGIN
 
-fifos: for i in 0 to FifoCnt-1 generate
-    FIFO0 : lpp_fifo
-        generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
-        port map(rstn,ReUse(i),
-                 rclk,
-                 ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,
-                 wclk,
-                 wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),almost_full(i),open);
-end generate;
+  fifos : FOR i IN 0 TO FifoCnt-1 GENERATE
+    lpp_fifo_1: lpp_fifo
+      GENERIC MAP (
+        tech         => tech,
+        Mem_use      => Mem_use,
+        DataSz       => Data_sz,
+        AddrSz       => Addr_sz)
+      PORT MAP (
+        clk         => clk,
+        rstn        => rstn,
+        reUse       => reUse(I),
+        ren         => ren(I),
+        rdata       => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
+        wen         => wen(I),
+        wdata       => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
+        empty       => empty(I),
+        full        => full(I),
+        almost_full => almost_full(I));
+  END GENERATE;
 
-end architecture;
+END ARCHITECTURE;
diff --git a/designs/Validation_LFR_SpectralMatrix/lpp_FIFO.vhd b/designs/Validation_LFR_SpectralMatrix/lpp_FIFO.vhd
--- a/designs/Validation_LFR_SpectralMatrix/lpp_FIFO.vhd
+++ b/designs/Validation_LFR_SpectralMatrix/lpp_FIFO.vhd
@@ -32,24 +32,26 @@ ENTITY lpp_fifo IS
   GENERIC(
     tech         : INTEGER               := 0;
     Mem_use      : INTEGER               := use_RAM;
-    Enable_ReUse : STD_LOGIC             := '0';
     DataSz       : INTEGER RANGE 1 TO 32 := 8;
     AddrSz       : INTEGER RANGE 2 TO 12 := 8
     );
   PORT(
+    clk         : IN  STD_LOGIC;
     rstn        : IN  STD_LOGIC;
-    ReUse       : IN  STD_LOGIC;
-    rclk        : IN  STD_LOGIC;
+    --
+    reUse       : IN STD_LOGIC;
+    
+    --IN
     ren         : IN  STD_LOGIC;
     rdata       : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
-    empty       : OUT STD_LOGIC;
-    raddr       : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
-    wclk        : IN  STD_LOGIC;
+    
+    --OUT
     wen         : IN  STD_LOGIC;
     wdata       : IN  STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
+
+    empty       : OUT STD_LOGIC;
     full        : OUT STD_LOGIC;
-    almost_full : OUT STD_LOGIC;        -- TODO
-    waddr       : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
+    almost_full : OUT STD_LOGIC
     );
 END ENTITY;
 
@@ -82,13 +84,13 @@ BEGIN
   memRAM : IF Mem_use = use_RAM GENERATE
     SRAM : syncram_2p
       GENERIC MAP(tech, AddrSz, DataSz)
-      PORT MAP(RCLK, sRE, Raddr_vect, rdata, WCLK, sWE, Waddr_vect, wdata);
+      PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata);
   END GENERATE;
 --================================================================================== 
   memCEL : IF Mem_use = use_CEL GENERATE
     CRAM : RAM_CEL
       GENERIC MAP(DataSz, AddrSz)
-      PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
+      PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
   END GENERATE;
 --================================================================================== 
 
@@ -98,19 +100,19 @@ BEGIN
   sREN <= REN OR sEmpty;
   sRE  <= NOT sREN;
 
-  sEmpty_s <= '0' WHEN ReUse = '1' AND Enable_ReUse = '1' else
+  sEmpty_s <= '0' WHEN ReUse = '1'  else
               '1' WHEN sEmpty = '1' AND Wen = '1'                                               ELSE
               '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
               '0';
 
   Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
 
-  PROCESS (rclk, rstn)
+  PROCESS (clk, rstn)
   BEGIN
     IF(rstn = '0')then
       Raddr_vect <= (OTHERS => '0');
       sempty     <= '1';
-    ELSIF(rclk'EVENT AND rclk = '1')then
+    ELSIF(clk'EVENT AND clk = '1')then
       sEmpty <= sempty_s;
 
       IF(sREN = '0' and sempty = '0')then
@@ -126,7 +128,7 @@ BEGIN
   sWEN <= WEN OR sFull;
   sWE  <= NOT sWEN;
 
-  sFull_s <= '1' WHEN ReUse = '1' AND Enable_ReUse = '1' else
+  sFull_s <= '1' WHEN ReUse = '1' else
              '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
              '1' WHEN sFull = '1' AND REN = '1'                             ELSE
              '0';
@@ -137,13 +139,13 @@ BEGIN
   
   Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
 
-  PROCESS (wclk, rstn)
+  PROCESS (clk, rstn)
   BEGIN
     IF(rstn = '0')then
       Waddr_vect <= (OTHERS => '0');
       sfull      <= '0';
       almost_full_r <= '0';
-    ELSIF(wclk'EVENT AND wclk = '1')then
+    ELSIF(clk'EVENT AND clk = '1')then
       sfull <= sfull_s;
       almost_full_r      <= almost_full_s;
 
@@ -157,8 +159,6 @@ BEGIN
   almost_full <= almost_full_s;
   full        <= sFull_s;
   empty       <= sEmpty_s;
-  waddr       <= Waddr_vect;
-  raddr       <= Raddr_vect;
 
 END ARCHITECTURE;
 
diff --git a/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms.vhd b/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms.vhd
--- a/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms.vhd
+++ b/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms.vhd
@@ -6,9 +6,13 @@ LIBRARY lpp;
 USE lpp.lpp_memory.ALL;
 USE lpp.iir_filter.ALL;
 USE lpp.spectral_matrix_package.ALL;
-
-use lpp.lpp_fft.all;
-use lpp.fft_components.all;
+USE lpp.lpp_dma_pkg.ALL;
+USE lpp.lpp_Header.ALL;
+USE lpp.lpp_matrix.ALL;
+USE lpp.lpp_matrix.ALL;
+USE lpp.lpp_lfr_pkg.ALL;
+USE lpp.lpp_fft.ALL;
+USE lpp.fft_components.ALL;
 
 ENTITY lpp_lfr_ms IS
   GENERIC (
@@ -94,7 +98,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS
   SIGNAL sample_f1_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
   SIGNAL sample_f1_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
   SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  
+
   SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
 
   SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
@@ -105,17 +109,18 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS
   SIGNAL error_wen_f0 : STD_LOGIC;
   SIGNAL error_wen_f1 : STD_LOGIC;
   SIGNAL error_wen_f2 : STD_LOGIC;
-  
+
   SIGNAL one_sample_f1_full : STD_LOGIC;
   SIGNAL one_sample_f1_wen  : STD_LOGIC;
   SIGNAL one_sample_f2_full : STD_LOGIC;
   SIGNAL one_sample_f2_wen  : STD_LOGIC;
-  
+
   -----------------------------------------------------------------------------
   -- FSM / SWITCH SELECT CHANNEL
   -----------------------------------------------------------------------------
   TYPE   fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
-  SIGNAL state_fsm_select_channel : fsm_select_channel;
+  SIGNAL state_fsm_select_channel     : fsm_select_channel;
+  SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
 
   SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
   SIGNAL sample_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -125,27 +130,87 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS
   -----------------------------------------------------------------------------
   -- FSM LOAD FFT
   -----------------------------------------------------------------------------
-  TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, FIFO_transition);
-  SIGNAL state_fsm_load_FFT : fsm_load_FFT;
+  TYPE   fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
+  SIGNAL state_fsm_load_FFT      : fsm_load_FFT;
   SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
 
-  SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL sample_load  : STD_LOGIC;
-  SIGNAL sample_valid : STD_LOGIC;
+  SIGNAL sample_ren_s   : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL sample_load    : STD_LOGIC;
+  SIGNAL sample_valid   : STD_LOGIC;
   SIGNAL sample_valid_r : STD_LOGIC;
-  SIGNAL sample_data  : STD_LOGIC_VECTOR(15 DOWNTO 0);
- 
+  SIGNAL sample_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);
+
 
   -----------------------------------------------------------------------------
   -- FFT
   -----------------------------------------------------------------------------
-  SIGNAL fft_read       : STD_LOGIC;
-  SIGNAL fft_pong       : STD_LOGIC;
-  SIGNAL fft_data_im    : STD_LOGIC_VECTOR(15 DOWNTO 0);
-  SIGNAL fft_data_re    : STD_LOGIC_VECTOR(15 DOWNTO 0);
-  SIGNAL fft_data_valid : STD_LOGIC;
-  SIGNAL fft_ready      : STD_LOGIC;
+  SIGNAL fft_read            : STD_LOGIC;
+  SIGNAL fft_pong            : STD_LOGIC;
+  SIGNAL fft_data_im         : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  SIGNAL fft_data_re         : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  SIGNAL fft_data_valid      : STD_LOGIC;
+  SIGNAL fft_ready           : STD_LOGIC;
+  -----------------------------------------------------------------------------
+  SIGNAL fft_linker_ReUse    : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  -----------------------------------------------------------------------------
+  TYPE   fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
+  SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
+  SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL current_fifo_empty : STD_LOGIC;
+  SIGNAL current_fifo_locked : STD_LOGIC;
+  SIGNAL current_fifo_full : STD_LOGIC;
+  SIGNAL MEM_IN_SM_locked      : STD_LOGIC_VECTOR(4 DOWNTO 0);
   
+  -----------------------------------------------------------------------------
+  SIGNAL MEM_IN_SM_ReUse     : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_wen     : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_wen_s     : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_ren      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_wData      : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
+  SIGNAL MEM_IN_SM_rData  : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
+  SIGNAL MEM_IN_SM_Full      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_Empty      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  -----------------------------------------------------------------------------
+  SIGNAL HEAD_SM_Param       : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL HEAD_WorkFreq       : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL HEAD_SM_Wen         : STD_LOGIC;
+  SIGNAL HEAD_Valid          : STD_LOGIC;
+  SIGNAL HEAD_Data           : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL HEAD_Empty          : STD_LOGIC;
+  SIGNAL HEAD_Read           : STD_LOGIC;
+  -----------------------------------------------------------------------------
+  SIGNAL MEM_OUT_SM_ReUse    : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL MEM_OUT_SM_Data_in  : STD_LOGIC_VECTOR(63 DOWNTO 0);
+  SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
+  SIGNAL MEM_OUT_SM_Full     : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL MEM_OUT_SM_Empty     : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  -----------------------------------------------------------------------------
+  SIGNAL DMA_Header          : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL DMA_Header_Val      : STD_LOGIC;
+  SIGNAL DMA_Header_Ack      : STD_LOGIC;
+
+  -----------------------------------------------------------------------------
+  -- TIME REG & INFOs
+  -----------------------------------------------------------------------------
+  SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
+
+  SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
+  SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
+  SIGNAL time_reg_f1   : STD_LOGIC_VECTOR(47 DOWNTO 0);
+  SIGNAL time_reg_f2   : STD_LOGIC_VECTOR(47 DOWNTO 0);
+
+  SIGNAL time_update_f0_A : STD_LOGIC;
+  SIGNAL time_update_f0_B : STD_LOGIC;
+  SIGNAL time_update_f1   : STD_LOGIC;
+  SIGNAL time_update_f2   : STD_LOGIC;
+  --
+  SIGNAL status_channel   : STD_LOGIC_VECTOR(49 DOWNTO 0);
+  
+  SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
+  -----------------------------------------------------------------------------
+
 BEGIN
 
   switch_f0_inst : spectral_matrix_switch_f0
@@ -163,7 +228,7 @@ BEGIN
       fifo_B_full  => sample_f0_B_full,
       fifo_B_wen   => sample_f0_B_wen,
 
-      error_wen => error_wen_f0);          -- TODO
+      error_wen => error_wen_f0);       -- TODO
 
   -----------------------------------------------------------------------------
   -- FIFO IN
@@ -174,21 +239,22 @@ BEGIN
       Mem_use      => Mem_use,
       Data_sz      => 16,
       Addr_sz      => 8,
-      FifoCnt      => 5,
-      Enable_ReUse => '0')
+      FifoCnt      => 5)
     PORT MAP (
+      clk   => clk,
       rstn  => rstn,
-      wclk  => clk,
-      rclk  => clk,
+      
       ReUse => (OTHERS => '0'),
 
-      wen   => sample_f0_A_wen,         --      IN  in
-      ren   => sample_f0_A_ren,         -- OUT in
-      wdata => sample_f0_wdata,         --      IN  in
-      rdata => sample_f0_A_rdata,       -- OUT in
-      full  => sample_f0_A_full,        --      IN  out
-      almost_full => OPEN,  --      IN  out
-      empty => sample_f0_A_empty);      --      OUT OUT
+      wen         => sample_f0_A_wen,   
+      wdata       => sample_f0_wdata,   
+      
+      ren         => sample_f0_A_ren,   
+      rdata       => sample_f0_A_rdata, 
+      
+      empty       => sample_f0_A_empty, 
+      full        => sample_f0_A_full,  
+      almost_full => OPEN);             
 
   lppFIFOxN_f0_b : lppFIFOxN
     GENERIC MAP (
@@ -196,21 +262,20 @@ BEGIN
       Mem_use      => Mem_use,
       Data_sz      => 16,
       Addr_sz      => 8,
-      FifoCnt      => 5,
-      Enable_ReUse => '0')
+      FifoCnt      => 5)
     PORT MAP (
+      clk   => clk,
       rstn  => rstn,
-      wclk  => clk,
-      rclk  => clk,
+      
       ReUse => (OTHERS => '0'),
 
-      wen   => sample_f0_B_wen,         --      IN  in
-      ren   => sample_f0_B_ren,         -- OUT in
-      wdata => sample_f0_wdata,         --      IN  in
-      rdata => sample_f0_B_rdata,       -- OUT in
-      full  => sample_f0_B_full,        --      IN  out
-      almost_full => OPEN,  --      IN  out
-      empty => sample_f0_B_empty);      --      OUT OUT
+      wen         => sample_f0_B_wen,   
+      wdata       => sample_f0_wdata,   
+      ren         => sample_f0_B_ren,   
+      rdata       => sample_f0_B_rdata, 
+      empty       => sample_f0_B_empty, 
+      full        => sample_f0_B_full,  
+      almost_full => OPEN);             
 
   lppFIFOxN_f1 : lppFIFOxN
     GENERIC MAP (
@@ -218,31 +283,30 @@ BEGIN
       Mem_use      => Mem_use,
       Data_sz      => 16,
       Addr_sz      => 8,
-      FifoCnt      => 5,
-      Enable_ReUse => '0')
+      FifoCnt      => 5)
     PORT MAP (
+      clk   => clk,
       rstn  => rstn,
-      wclk  => clk,
-      rclk  => clk,
+      
       ReUse => (OTHERS => '0'),
 
-      wen         => sample_f1_wen,          --      IN  in
-      ren         => sample_f1_ren,          -- OUT in
-      wdata       => sample_f1_wdata,        --      IN  in
-      rdata       => sample_f1_rdata,        --  OUT in
-      full        => sample_f1_full,         --      IN  out
-      almost_full => sample_f1_almost_full,  --      IN  out
-      empty       => sample_f1_empty);       --      OUT OUT
+      wen         => sample_f1_wen,          
+      wdata       => sample_f1_wdata,        
+      ren         => sample_f1_ren,          
+      rdata       => sample_f1_rdata,        
+      empty       => sample_f1_empty,        
+      full        => sample_f1_full,         
+      almost_full => sample_f1_almost_full); 
 
 
-  one_sample_f1_wen <= '0' WHEN  sample_f1_wen  = "11111" ELSE '1';
+  one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
 
   PROCESS (clk, rstn)
   BEGIN  -- PROCESS
     IF rstn = '0' THEN                  -- asynchronous reset (active low)
-       one_sample_f1_full <= '0';
-       error_wen_f1 <= '0';
-    ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+      one_sample_f1_full <= '0';
+      error_wen_f1       <= '0';
+    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
       IF sample_f1_full = "00000" THEN
         one_sample_f1_full <= '0';
       ELSE
@@ -251,7 +315,7 @@ BEGIN
       error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
     END IF;
   END PROCESS;
-  
+
 
   lppFIFOxN_f2 : lppFIFOxN
     GENERIC MAP (
@@ -259,31 +323,30 @@ BEGIN
       Mem_use      => Mem_use,
       Data_sz      => 16,
       Addr_sz      => 8,
-      FifoCnt      => 5,
-      Enable_ReUse => '0')
+      FifoCnt      => 5)
     PORT MAP (
+      clk   => clk,
       rstn  => rstn,
-      wclk  => clk,
-      rclk  => clk,
+      
       ReUse => (OTHERS => '0'),
 
-      wen   => sample_f2_wen,           --      IN  in
-      ren   => sample_f2_ren,           -- OUT in
-      wdata => sample_f2_wdata,         --      IN  in
-      rdata => sample_f2_rdata,         -- OUT in
-      full  => sample_f2_full,          --      IN  out
-      almost_full => OPEN,  --      IN  out
-      empty => sample_f2_empty);        --      OUT OUT
+      wen         => sample_f2_wen,     
+      wdata       => sample_f2_wdata,   
+      ren         => sample_f2_ren,     
+      rdata       => sample_f2_rdata,   
+      empty       => sample_f2_empty,   
+      full        => sample_f2_full,    
+      almost_full => OPEN);             
 
 
-  one_sample_f2_wen <= '0' WHEN  sample_f2_wen  = "11111" ELSE '1';
-  
+  one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
+
   PROCESS (clk, rstn)
   BEGIN  -- PROCESS
     IF rstn = '0' THEN                  -- asynchronous reset (active low)
-       one_sample_f2_full <= '0';
-       error_wen_f2 <= '0';
-    ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+      one_sample_f2_full <= '0';
+      error_wen_f2       <= '0';
+    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
       IF sample_f2_full = "00000" THEN
         one_sample_f2_full <= '0';
       ELSE
@@ -337,6 +400,14 @@ BEGIN
     END IF;
   END PROCESS;
 
+  PROCESS (clk, rstn)
+  BEGIN
+    IF rstn = '0' THEN
+      pre_state_fsm_select_channel <= IDLE;
+    ELSIF clk'EVENT AND clk = '1' THEN
+      pre_state_fsm_select_channel <= state_fsm_select_channel;
+    END IF;
+  END PROCESS;
 
 
   -----------------------------------------------------------------------------
@@ -354,9 +425,9 @@ BEGIN
                  sample_f2_full   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                  (OTHERS => '0');
   
-  sample_rdata <= sample_f0_A_rdata WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
-                  sample_f0_B_rdata WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
-                  sample_f1_rdata   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
+  sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
+                  sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
+                  sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
                   sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
 
 
@@ -365,77 +436,67 @@ BEGIN
   sample_f1_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1   ELSE (OTHERS => '1');
   sample_f2_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2   ELSE (OTHERS => '1');
 
+
+  status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
+                    time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
+                    time_reg_f1 & "01"   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
+                    time_reg_f2 & "10";  -- WHEN state_fsm_select_channel = SWITCH_F2
+
   -----------------------------------------------------------------------------
   -- FSM LOAD FFT
   -----------------------------------------------------------------------------
 
-  sample_ren <= sample_ren_s;-- OR sample_empty;
-  
+  sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
+
   PROCESS (clk, rstn)
   BEGIN
     IF rstn = '0' THEN
-      sample_ren_s              <= (OTHERS => '1');
-      state_fsm_load_FFT        <= IDLE;
-      next_state_fsm_load_FFT   <= IDLE;
-      sample_valid              <= '0';
-    ELSIF clk'event AND clk = '1' THEN
+      sample_ren_s       <= (OTHERS => '1');
+      state_fsm_load_FFT <= IDLE;
+      --next_state_fsm_load_FFT <= IDLE;
+      --sample_valid              <= '0';
+    ELSIF clk'EVENT AND clk = '1' THEN
       CASE state_fsm_load_FFT IS
-        WHEN IDLE   =>
-          sample_valid <= '0';
+        WHEN IDLE =>
+          --sample_valid <= '0';
           sample_ren_s <= (OTHERS => '1');
           IF sample_full = "11111" AND sample_load = '1' THEN
             state_fsm_load_FFT <= FIFO_1;
           END IF;
-        WHEN FIFO_1 => 
+          
+        WHEN FIFO_1 =>
           sample_ren_s <= "1111" & NOT(sample_load);
-          sample_valid <= '1';
           IF sample_empty(0) = '1' THEN
-            sample_valid <= '0';
-            sample_ren_s   <=  (OTHERS => '1');
-            state_fsm_load_FFT        <= FIFO_transition;
-            next_state_fsm_load_FFT   <= FIFO_2;
+            sample_ren_s       <= (OTHERS => '1');
+            state_fsm_load_FFT <= FIFO_2;
+          END IF;
+          
+        WHEN FIFO_2 =>
+          sample_ren_s <= "111" & NOT(sample_load) & '1';
+          IF sample_empty(1) = '1' THEN
+            sample_ren_s       <= (OTHERS => '1');
+            state_fsm_load_FFT <= FIFO_3;
           END IF;
           
-        WHEN FIFO_transition =>
-          sample_valid       <= '0';
-          sample_ren_s       <= (OTHERS => '1');
-          state_fsm_load_FFT <= next_state_fsm_load_FFT;
-          
-        WHEN FIFO_2 => 
-          sample_ren_s <= "111" & NOT(sample_load) & '1';
-          sample_valid <= sample_load;
-          IF sample_empty(1) = '1' THEN
-            sample_valid       <= '0';
-            sample_ren_s   <=  (OTHERS => '1');
-            state_fsm_load_FFT <= FIFO_transition;
-            next_state_fsm_load_FFT   <= FIFO_3;
-          END IF;
-        WHEN FIFO_3 => 
+        WHEN FIFO_3 =>
           sample_ren_s <= "11" & NOT(sample_load) & "11";
-          sample_valid <= sample_load;--'1';
           IF sample_empty(2) = '1' THEN
-            sample_valid       <= '0';
-            sample_ren_s   <=  (OTHERS => '1');
-            state_fsm_load_FFT <= FIFO_transition;
-            next_state_fsm_load_FFT   <= FIFO_4;
+            sample_ren_s       <= (OTHERS => '1');
+            state_fsm_load_FFT <= FIFO_4;
           END IF;
-        WHEN FIFO_4 => 
+          
+        WHEN FIFO_4 =>
           sample_ren_s <= '1' & NOT(sample_load) & "111";
-          sample_valid <= sample_load;--'1';
           IF sample_empty(3) = '1' THEN
-            sample_valid       <= '0';
-            sample_ren_s   <=  (OTHERS => '1');
-            state_fsm_load_FFT <= FIFO_transition;
-            next_state_fsm_load_FFT   <= FIFO_5;
+            sample_ren_s       <= (OTHERS => '1');
+            state_fsm_load_FFT <= FIFO_5;
           END IF;
-        WHEN FIFO_5 => 
+          
+        WHEN FIFO_5 =>
           sample_ren_s <= NOT(sample_load) & "1111";
-          sample_valid <= sample_load;--'1';
           IF sample_empty(4) = '1' THEN
-            sample_valid       <= '0';
-            sample_ren_s   <=  (OTHERS => '1');
-            state_fsm_load_FFT <= FIFO_transition;
-            next_state_fsm_load_FFT   <= IDLE;
+            sample_ren_s       <= (OTHERS => '1');
+            state_fsm_load_FFT <= IDLE;
           END IF;
         WHEN OTHERS => NULL;
       END CASE;
@@ -445,22 +506,30 @@ BEGIN
   PROCESS (clk, rstn)
   BEGIN
     IF rstn = '0' THEN
-      sample_valid_r <= '0';
-    ELSIF clk'event AND clk = '1' THEN
-      sample_valid_r <= sample_valid AND sample_load;
+      sample_valid_r          <= '0';
+      next_state_fsm_load_FFT <= IDLE;
+    ELSIF clk'EVENT AND clk = '1' THEN
+      next_state_fsm_load_FFT <= state_fsm_load_FFT;
+      IF sample_ren_s = "11111" THEN
+        sample_valid_r <= '0';
+      ELSE
+        sample_valid_r <= '1';
+      END IF;
     END IF;
   END PROCESS;
 
-  sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN state_fsm_load_FFT = FIFO_1 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_2) ELSE
-                 sample_rdata(16*2-1 DOWNTO 16*1) WHEN state_fsm_load_FFT = FIFO_2 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_3) ELSE
-                 sample_rdata(16*3-1 DOWNTO 16*2) WHEN state_fsm_load_FFT = FIFO_3 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_4) ELSE
-                 sample_rdata(16*4-1 DOWNTO 16*3) WHEN state_fsm_load_FFT = FIFO_4 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_5) ELSE
-                 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN state_fsm_load_FFT = FIFO_5 ELSE
+  sample_valid <= sample_valid_r AND sample_load;
+
+  sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
+                 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
+                 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
+                 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
+                 sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
 
   -----------------------------------------------------------------------------
   -- FFT
   -----------------------------------------------------------------------------
-  CoreFFT_1: CoreFFT
+  CoreFFT_1 : CoreFFT
     GENERIC MAP (
       LOGPTS      => gLOGPTS,
       LOGLOGPTS   => gLOGLOGPTS,
@@ -474,11 +543,11 @@ BEGIN
       HALFPTS     => gHALFPTS,
       inBuf_RWDLY => gInBuf_RWDLY)
     PORT MAP (
-      clk        => clk,
-      ifiStart   => '1',
-      ifiNreset  => rstn,
-      
-      ifiD_valid => sample_valid_r,       -- IN
+      clk       => clk,
+      ifiStart  => '1',
+      ifiNreset => rstn,
+
+      ifiD_valid => sample_valid,       -- IN
       ifiRead_y  => fft_read,
       ifiD_im    => (OTHERS => '0'),    -- IN
       ifiD_re    => sample_data,        -- IN
@@ -491,37 +560,336 @@ BEGIN
       ifoY_rdy   => fft_ready);
 
   -----------------------------------------------------------------------------
-  -- 
+  -- in   fft_data_im & fft_data_re
+  -- in   fft_data_valid
+  -- in   fft_ready
+  -- out  fft_read
+  PROCESS (clk, rstn)
+  BEGIN
+    IF rstn = '0' THEN
+      state_fsm_load_MS_memory <= IDLE;
+      current_fifo_load <= "00001";
+    ELSIF clk'event AND clk = '1' THEN
+      CASE state_fsm_load_MS_memory IS
+        WHEN IDLE =>
+          IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
+            state_fsm_load_MS_memory <= LOAD_FIFO;
+          END IF;
+        WHEN LOAD_FIFO =>
+          IF current_fifo_full = '1' THEN
+            state_fsm_load_MS_memory <= TRASH_FFT;
+          END IF;
+        WHEN TRASH_FFT =>
+          IF fft_ready = '0' THEN
+            state_fsm_load_MS_memory <= IDLE;
+            current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
+          END IF;          
+        WHEN OTHERS => NULL;
+      END CASE;
+      
+    END IF;
+  END PROCESS;
+  
+  current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
+                        MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
+                        MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
+                        MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
+                        MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE
+                        
+  current_fifo_full  <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
+                        MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
+                        MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
+                        MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
+                        MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE
+                        
+  current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
+                         MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
+                         MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
+                         MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
+                         MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE
+                        
+  fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
+
+  all_fifo: FOR I IN 4 DOWNTO 0 GENERATE
+      MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
+                                   AND state_fsm_load_MS_memory = LOAD_FIFO
+                                   AND current_fifo_load(I) = '1'
+                          ELSE '1';
+  END GENERATE all_fifo;
+
+  PROCESS (clk, rstn)
+  BEGIN
+    IF rstn = '0' THEN
+      MEM_IN_SM_wen <= (OTHERS => '1');
+    ELSIF clk'event AND clk = '1' THEN
+      MEM_IN_SM_wen <= MEM_IN_SM_wen_s;      
+    END IF;
+  END PROCESS;
+  
+  MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
+                     (fft_data_im & fft_data_re) &
+                     (fft_data_im & fft_data_re) &
+                     (fft_data_im & fft_data_re) &
+                     (fft_data_im & fft_data_re);
+  
+
+  -- out SM_MEM_IN_wData
+  -- out SM_MEM_IN_wen
+  -- out SM_MEM_IN_Full
+  
+  -- out SM_MEM_IN_locked
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  --Linker_FFT_1 : Linker_FFT
+  --  GENERIC MAP (
+  --    Data_sz => 16,
+  --    NbData  => 256)
+  --  PORT MAP (
+  --    clk  => clk,
+  --    rstn => rstn,
+
+  --    Ready => fft_ready,
+  --    Valid => fft_data_valid,
+
+  --    Full => MEM_IN_SM_Full,
+
+  --    Data_re => fft_data_re,
+  --    Data_im => fft_data_im,
+  --    Read    => fft_read,
+
+  --    Write => MEM_IN_SM_wen,
+  --    ReUse => fft_linker_ReUse,
+  --    DATA  => MEM_IN_SM_wData);
+  
   -----------------------------------------------------------------------------
-  fft_read <= '1';
-  -- fft_read       OUT
-  -- fft_pong       IN
-  -- fft_data_im    IN
-  -- fft_data_re    IN
-  -- fft_data_valid IN
-  -- fft_ready      IN
+  Mem_In_SpectralMatrix : lppFIFOxN
+    GENERIC MAP (
+      tech         => 0,
+      Mem_use      => Mem_use,
+      Data_sz      => 32,               --16,
+      Addr_sz      => 7,                --8
+      FifoCnt      => 5)
+    PORT MAP (
+      clk => clk,
+      rstn => rstn,
+
+      ReUse => MEM_IN_SM_ReUse,
+      
+      wen   => MEM_IN_SM_wen,
+      wdata => MEM_IN_SM_wData,
+      
+      ren   => MEM_IN_SM_ren,
+      rdata => MEM_IN_SM_rData,
+      full  => MEM_IN_SM_Full,
+      empty => MEM_IN_SM_Empty);
+
+
+  all_lock: FOR I IN 4 DOWNTO 0 GENERATE
+    PROCESS (clk, rstn)
+    BEGIN
+      IF rstn = '0' THEN
+        MEM_IN_SM_locked(I) <= '0';
+      ELSIF clk'event AND clk = '1' THEN 
+        MEM_IN_SM_locked(I) <=   MEM_IN_SM_Full(I) OR  MEM_IN_SM_locked(I);  -- TODO
+      END IF;
+    END PROCESS;    
+  END GENERATE all_lock;
+  
+
+  
+  -----------------------------------------------------------------------------
+  SM0 : MatriceSpectrale
+    GENERIC MAP (
+      Input_SZ  => 16,
+      Result_SZ => 32)
+    PORT MAP (
+      clkm => clk,
+      rstn => rstn,
+
+      FifoIN_Full => MEM_IN_SM_Full,
+      Data_IN     => MEM_IN_SM_rData(79 DOWNTO 0),
+      Read        => MEM_IN_SM_ren,
+      ReUse       => MEM_IN_SM_ReUse,
+
+      SetReUse => fft_linker_ReUse,
+
+      Valid     => HEAD_Valid,
+      ACK       => DMA_Header_Ack,
+      SM_Write  => HEAD_SM_Wen,
+      FlagError => OPEN,
+      Statu     => HEAD_SM_Param,
+      Write     => MEM_OUT_SM_Write,
+      Data_OUT  => MEM_OUT_SM_Data_in);
+  -----------------------------------------------------------------------------
+  Mem_Out_SpectralMatrix : lppFIFOxN
+    GENERIC MAP (
+      tech         => 0,
+      Mem_use      => Mem_use,
+      Data_sz      => 32,
+      Addr_sz      => 8,
+      FifoCnt      => 2)
+    PORT MAP (
+      clk => clk,
+      rstn => rstn,
+
+      ReUse => (OTHERS => '0'),
+
+      wen   => MEM_OUT_SM_Write,
+      wdata => MEM_OUT_SM_Data_in,
+      ren   => MEM_OUT_SM_Read,
+      rdata => MEM_OUT_SM_Data_out,
+
+      full  => MEM_OUT_SM_Full,
+      empty => MEM_OUT_SM_Empty);       
+  -----------------------------------------------------------------------------
+  Head0 : HeaderBuilder
+    GENERIC MAP (
+      Data_sz => 32)
+    PORT MAP (
+      clkm => clk,
+      rstn => rstn,
+
+      Statu        => HEAD_SM_Param,
+      Matrix_Type  => HEAD_WorkFreq,    -- TODO IN
+      Matrix_Write => HEAD_SM_Wen,
+      Valid        => HEAD_Valid,
+
+      dataIN  => MEM_OUT_SM_Data_out,
+      emptyIN => MEM_OUT_SM_Empty,
+      RenOUT  => MEM_OUT_SM_Read,
+
+      dataOUT  => HEAD_Data,
+      emptyOUT => HEAD_Empty,
+      RenIN    => HEAD_Read,
+
+      header     => DMA_Header,
+      header_val => DMA_Header_Val,
+      header_ack => DMA_Header_Ack);         
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
+    PORT MAP (
+      HCLK    => clk,
+      HRESETn => rstn,
+
+      data_time => dma_time,           
+
+      fifo_data  => HEAD_Data,
+      fifo_empty => HEAD_Empty,
+      fifo_ren   => HEAD_Read,
+
+      header     => DMA_Header,
+      header_val => DMA_Header_Val,
+      header_ack => DMA_Header_Ack,
+
+      dma_addr        => dma_addr,
+      dma_data        => dma_data,
+      dma_valid       => dma_valid,
+      dma_valid_burst => dma_valid_burst,
+      dma_ren         => dma_ren,
+      dma_done        => dma_done,
+
+      ready_matrix_f0_0                      => ready_matrix_f0_0,
+      ready_matrix_f0_1                      => ready_matrix_f0_1,
+      ready_matrix_f1                        => ready_matrix_f1,
+      ready_matrix_f2                        => ready_matrix_f2,
+      error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
+      error_bad_component_error              => error_bad_component_error,
+      debug_reg                              => debug_reg,
+      status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
+      status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
+      status_ready_matrix_f1                 => status_ready_matrix_f1,
+      status_ready_matrix_f2                 => status_ready_matrix_f2,
+      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
+      status_error_bad_component_error       => status_error_bad_component_error,
+      config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
+      config_active_interruption_onError     => config_active_interruption_onError,
+      addr_matrix_f0_0                       => addr_matrix_f0_0,
+      addr_matrix_f0_1                       => addr_matrix_f0_1,
+      addr_matrix_f1                         => addr_matrix_f1,
+      addr_matrix_f2                         => addr_matrix_f2,
+
+      matrix_time_f0_0 => matrix_time_f0_0,
+      matrix_time_f0_1 => matrix_time_f0_1,
+      matrix_time_f1   => matrix_time_f1,
+      matrix_time_f2   => matrix_time_f2
+      );
+  -----------------------------------------------------------------------------
 
   -----------------------------------------------------------------------------
-  -- 
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
   -----------------------------------------------------------------------------
+
+
+
+
+
+
+  -----------------------------------------------------------------------------
+  -- TIME MANAGMENT
+  -----------------------------------------------------------------------------
+  all_time         <= coarse_time & fine_time;
+  --
+  time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE
+                      '1' WHEN sample_f0_A_empty = "11111" ELSE
+                      '0';
   
-  dma_addr        <= (OTHERS => '0');
-  dma_data        <= (OTHERS => '0');
-  dma_valid       <= '0';
-  dma_valid_burst <= '0';
+  s_m_t_m_f0_A : spectral_matrix_time_managment
+    PORT MAP (
+      clk      => clk,
+      rstn     => rstn,
+      time_in  => all_time,
+      update_1 => time_update_f0_A,
+      time_out => time_reg_f0_A);
+
+  --  
+  time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE
+                      '1' WHEN sample_f0_B_empty = "11111" ELSE
+                      '0';
   
-  ready_matrix_f0_0             <= '0';
-  ready_matrix_f0_1             <= '0';
-  ready_matrix_f1               <= '0';
-  ready_matrix_f2               <= '0';
-  error_anticipating_empty_fifo <= '0';
-  error_bad_component_error     <= '0';
-  debug_reg                     <= (OTHERS => '0');
+  s_m_t_m_f0_B : spectral_matrix_time_managment
+    PORT MAP (
+      clk      => clk,
+      rstn     => rstn,
+      time_in  => all_time,
+      update_1 => time_update_f0_B,
+      time_out => time_reg_f0_B);
+
+  --  
+  time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE
+                    '1' WHEN sample_f1_empty = "11111" ELSE
+                    '0';
+  
+  s_m_t_m_f1 : spectral_matrix_time_managment
+    PORT MAP (
+      clk      => clk,
+      rstn     => rstn,
+      time_in  => all_time,
+      update_1 => time_update_f1,
+      time_out => time_reg_f1);
 
-  matrix_time_f0_0 <= (OTHERS => '0');
-  matrix_time_f0_1 <= (OTHERS => '0');
-  matrix_time_f1   <= (OTHERS => '0');
-  matrix_time_f2   <= (OTHERS => '0');
+  --  
+  time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE
+                    '1' WHEN sample_f2_empty = "11111" ELSE
+                    '0';
+  
+  s_m_t_m_f2 : spectral_matrix_time_managment
+    PORT MAP (
+      clk      => clk,
+      rstn     => rstn,
+      time_in  => all_time,
+      update_1 => time_update_f2,
+      time_out => time_reg_f2);
 
-  
+  -----------------------------------------------------------------------------
+  dma_time <= (OTHERS => '0');         -- TODO
+  -----------------------------------------------------------------------------
+
+
+
 END Behavioral;
diff --git a/designs/Validation_LFR_SpectralMatrix/lpp_memory.vhd b/designs/Validation_LFR_SpectralMatrix/lpp_memory.vhd
--- a/designs/Validation_LFR_SpectralMatrix/lpp_memory.vhd
+++ b/designs/Validation_LFR_SpectralMatrix/lpp_memory.vhd
@@ -19,181 +19,223 @@
 --                    Author : Martin Morlot
 --                     Mail : martin.morlot@lpp.polytechnique.fr
 ------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use std.textio.all;
-library lpp;
-use lpp.lpp_amba.all;
-use lpp.iir_filter.all;
-library gaisler;
-use gaisler.misc.all;
-use gaisler.memctrl.all;
-library techmap;
-use techmap.gencomp.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+LIBRARY grlib;
+USE grlib.amba.ALL;
+USE std.textio.ALL;
+LIBRARY lpp;
+USE lpp.lpp_amba.ALL;
+USE lpp.iir_filter.ALL;
+LIBRARY gaisler;
+USE gaisler.misc.ALL;
+USE gaisler.memctrl.ALL;
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
 
 --! Package contenant tous les programmes qui forment le composant intégré dans le léon 
 
-package lpp_memory is
-
-component APB_FIFO is
-generic (
-    tech         : integer := apa3;
-    pindex       : integer := 0;
-    paddr        : integer := 0;
-    pmask        : integer := 16#fff#;
-    pirq         : integer := 0;
-    abits        : integer := 8;
-    FifoCnt      : integer := 2;
-    Data_sz      : integer := 16;
-    Addr_sz        : integer := 9;
-    Enable_ReUse   : std_logic := '0';
-    Mem_use        : integer := use_RAM;
-    R            : integer := 1;
-    W            : integer := 1
-    );
-  port (
-    clk          : in  std_logic;                              --! Horloge du composant
-    rst          : in  std_logic;                              --! Reset general du composant
-    rclk         : in  std_logic; 
-    wclk         : in  std_logic;
-    ReUse        : in  std_logic_vector(FifoCnt-1 downto 0);
-    REN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction de lecture en mémoire
-    WEN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction d'écriture en mémoire
-    Empty        : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire vide
-    Full         : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire pleine
-    RDATA        : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);   --! Registre de données en entrée
-    WDATA        : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);    --! Registre de données en sortie
-    WADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (écriture)
-    RADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (lecture)
-    apbi         : in  apb_slv_in_type;                        --! Registre de gestion des entrées du bus
-    apbo         : out apb_slv_out_type                        --! Registre de gestion des sorties du bus
-    );
-end component;
+PACKAGE lpp_memory IS
 
-component FIFO_pipeline is
-generic(
-    tech          :   integer := 0;
-    Mem_use       :   integer := use_RAM;
-    fifoCount     :   integer range 2 to 32 := 8;
-    DataSz        :   integer range 1 to 32 := 8;
-    abits         :   integer range 2 to 12 := 8
-    );
-port(
-    rstn    :   in std_logic;
-    ReUse   :   in std_logic;
-    rclk    :   in std_logic;
-    ren     :   in std_logic;
-    rdata   :   out std_logic_vector(DataSz-1 downto 0);
-    empty   :   out std_logic;
-    raddr   :   out std_logic_vector(abits-1 downto 0);
-    wclk    :   in std_logic;
-    wen     :   in std_logic;
-    wdata   :   in std_logic_vector(DataSz-1 downto 0);
-    full    :   out std_logic;
-    waddr   :   out std_logic_vector(abits-1 downto 0)
-);
-end component;
+  COMPONENT lpp_fifo
+    GENERIC (
+      tech    : INTEGER;
+      Mem_use : INTEGER;
+      DataSz  : INTEGER RANGE 1 TO 32;
+      AddrSz  : INTEGER RANGE 2 TO 12);
+    PORT (
+      clk         : IN  STD_LOGIC;
+      rstn        : IN  STD_LOGIC;
+      reUse       : IN  STD_LOGIC;
+      ren         : IN  STD_LOGIC;
+      rdata       : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
+      wen         : IN  STD_LOGIC;
+      wdata       : IN  STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
+      empty       : OUT STD_LOGIC;
+      full        : OUT STD_LOGIC;
+      almost_full : OUT STD_LOGIC);
+  END COMPONENT;
 
-component lpp_fifo is
-generic(
-    tech          :   integer := 0;
-    Mem_use       :   integer := use_RAM;
-    Enable_ReUse  :   std_logic := '0';
-    DataSz        :   integer range 1 to 32 := 8;
-    AddrSz        :   integer range 2 to 12 := 8
-    );
-port(
-    rstn    :   in std_logic;
-    ReUse   :   in std_logic;   --27/01/12
-    rclk    :   in std_logic;
-    ren     :   in std_logic;
-    rdata   :   out std_logic_vector(DataSz-1 downto 0);
-    empty   :   out std_logic;
-    raddr   :   out std_logic_vector(AddrSz-1 downto 0);
-    wclk    :   in std_logic;
-    wen     :   in std_logic;
-    wdata   :   in std_logic_vector(DataSz-1 downto 0);
-    full    :   out std_logic;
-    almost_full    :   out std_logic;
-    waddr   :   out std_logic_vector(AddrSz-1 downto 0)
-);
-end component;
+  COMPONENT lppFIFOxN
+    GENERIC (
+      tech    : INTEGER;
+      Mem_use : INTEGER;
+      Data_sz : INTEGER RANGE 1 TO 32;
+      Addr_sz : INTEGER RANGE 2 TO 12;
+      FifoCnt : INTEGER);
+    PORT (
+      clk         : IN  STD_LOGIC;
+      rstn        : IN  STD_LOGIC;
+      ReUse       : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+      wen         : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+      wdata       : IN  STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
+      ren         : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+      rdata       : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
+      empty       : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+      full        : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+      almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0));
+  END COMPONENT;
 
 
-component lppFIFOxN is
-generic(
-    tech          :   integer := 0;
-    Mem_use       :   integer := use_RAM;
-    Data_sz       :   integer range 1 to 32 := 8;
-    Addr_sz       :   integer range 1 to 32 := 8;
-    FifoCnt : integer := 1;
-    Enable_ReUse  :   std_logic := '0'
-    );
-port(
-    rstn     :   in std_logic;
-    wclk    :   in std_logic;    
-    rclk    :   in std_logic;
-    ReUse   :   in std_logic_vector(FifoCnt-1 downto 0);
-    wen     :   in std_logic_vector(FifoCnt-1 downto 0);
-    ren     :   in std_logic_vector(FifoCnt-1 downto 0);
-    wdata   :   in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
-    rdata   :   out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
-    full    :   out std_logic_vector(FifoCnt-1 downto 0);
-    almost_full :   out std_logic_vector(FifoCnt-1 downto 0);
-    empty   :   out std_logic_vector(FifoCnt-1 downto 0)
-);
-end component;
+  
 
-component FillFifo is
-generic(
-    Data_sz  : integer range 1 to 32 := 16;
-    Fifo_cnt : integer range 1 to 8 := 5
-    );
-port(
-    clk         : in std_logic;
-    raz        : in std_logic;
-    write : out std_logic_vector(Fifo_cnt-1 downto 0);
-    reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
-    data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
-);
-end component;
+  COMPONENT APB_FIFO IS
+    GENERIC (
+      tech         : INTEGER   := apa3;
+      pindex       : INTEGER   := 0;
+      paddr        : INTEGER   := 0;
+      pmask        : INTEGER   := 16#fff#;
+      pirq         : INTEGER   := 0;
+      abits        : INTEGER   := 8;
+      FifoCnt      : INTEGER   := 2;
+      Data_sz      : INTEGER   := 16;
+      Addr_sz      : INTEGER   := 9;
+      Enable_ReUse : STD_LOGIC := '0';
+      Mem_use      : INTEGER   := use_RAM;
+      R            : INTEGER   := 1;
+      W            : INTEGER   := 1
+      );
+    PORT (
+      clk   : IN  STD_LOGIC;            --! Horloge du composant
+      rst   : IN  STD_LOGIC;            --! Reset general du composant
+      rclk  : IN  STD_LOGIC;
+      wclk  : IN  STD_LOGIC;
+      ReUse : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+      REN   : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);  --! Instruction de lecture en mémoire
+      WEN   : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);  --! Instruction d'écriture en mémoire
+      Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);  --! Flag, Mémoire vide
+      Full  : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);  --! Flag, Mémoire pleine
+      RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);  --! Registre de données en entrée
+      WDATA : IN  STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);  --! Registre de données en sortie
+      WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0);  --! Registre d'addresse (écriture)
+      RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0);  --! Registre d'addresse (lecture)
+      apbi  : IN  apb_slv_in_type;  --! Registre de gestion des entrées du bus
+      apbo  : OUT apb_slv_out_type  --! Registre de gestion des sorties du bus
+      );
+  END COMPONENT;
+
+  COMPONENT FIFO_pipeline IS
+    GENERIC(
+      tech      : INTEGER               := 0;
+      Mem_use   : INTEGER               := use_RAM;
+      fifoCount : INTEGER RANGE 2 TO 32 := 8;
+      DataSz    : INTEGER RANGE 1 TO 32 := 8;
+      abits     : INTEGER RANGE 2 TO 12 := 8
+      );
+    PORT(
+      rstn  : IN  STD_LOGIC;
+      ReUse : IN  STD_LOGIC;
+      rclk  : IN  STD_LOGIC;
+      ren   : IN  STD_LOGIC;
+      rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
+      empty : OUT STD_LOGIC;
+      raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+      wclk  : IN  STD_LOGIC;
+      wen   : IN  STD_LOGIC;
+      wdata : IN  STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
+      full  : OUT STD_LOGIC;
+      waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
-component Bridge is
-    port(
-        clk         : in std_logic;
-        raz        : in std_logic;
-        EmptyUp : in std_logic;
-        FullDwn : in std_logic;
-        WriteDwn : out std_logic;
-        ReadUp : out std_logic
-        );
-end component;
+  --COMPONENT lpp_fifo IS
+  --  GENERIC(
+  --    tech         : INTEGER               := 0;
+  --    Mem_use      : INTEGER               := use_RAM;
+  --    Enable_ReUse : STD_LOGIC             := '0';
+  --    DataSz       : INTEGER RANGE 1 TO 32 := 8;
+  --    AddrSz       : INTEGER RANGE 2 TO 12 := 8
+  --    );
+  --  PORT(
+  --    rstn        : IN  STD_LOGIC;
+  --    ReUse       : IN  STD_LOGIC;      --27/01/12
+  --    rclk        : IN  STD_LOGIC;
+  --    ren         : IN  STD_LOGIC;
+  --    rdata       : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
+  --    empty       : OUT STD_LOGIC;
+  --    raddr       : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
+  --    wclk        : IN  STD_LOGIC;
+  --    wen         : IN  STD_LOGIC;
+  --    wdata       : IN  STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
+  --    full        : OUT STD_LOGIC;
+  --    almost_full : OUT STD_LOGIC;
+  --    waddr       : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
+  --    );
+  --END COMPONENT;
+
+
+  --COMPONENT lppFIFOxN IS
+  --  GENERIC(
+  --    tech         : INTEGER               := 0;
+  --    Mem_use      : INTEGER               := use_RAM;
+  --    Data_sz      : INTEGER RANGE 1 TO 32 := 8;
+  --    Addr_sz      : INTEGER RANGE 1 TO 32 := 8;
+  --    FifoCnt      : INTEGER               := 1;
+  --    Enable_ReUse : STD_LOGIC             := '0'
+  --    );
+  --  PORT(
+  --    rstn        : IN  STD_LOGIC;
+  --    wclk        : IN  STD_LOGIC;
+  --    rclk        : IN  STD_LOGIC;
+  --    ReUse       : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+  --    wen         : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+  --    ren         : IN  STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+  --    wdata       : IN  STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
+  --    rdata       : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
+  --    full        : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+  --    almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
+  --    empty       : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
+  --    );
+  --END COMPONENT;
 
-component ssram_plugin is
-generic (tech : integer := 0);
-port
-(
-    clk             : in  std_logic;
-    mem_ctrlr_o     : in  memory_out_type;
-    SSRAM_CLK       : out std_logic;
-    nBWa            : out std_logic;
-    nBWb            : out std_logic;
-    nBWc            : out std_logic;
-    nBWd            : out std_logic;
-    nBWE            : out std_logic;
-    nADSC           : out std_logic;
-    nADSP           : out std_logic;
-    nADV            : out std_logic;
-    nGW             : out std_logic;
-    nCE1            : out std_logic;
-    CE2             : out std_logic;
-    nCE3            : out std_logic;
-    nOE             : out std_logic;
-    MODE            : out std_logic;
-    ZZ              : out std_logic
-);
-end component;
+  COMPONENT FillFifo IS
+    GENERIC(
+      Data_sz  : INTEGER RANGE 1 TO 32 := 16;
+      Fifo_cnt : INTEGER RANGE 1 TO 8  := 5
+      );
+    PORT(
+      clk   : IN  STD_LOGIC;
+      raz   : IN  STD_LOGIC;
+      write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
+      reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
+      data  : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0)
+      );
+  END COMPONENT;
+
+  COMPONENT Bridge IS
+    PORT(
+      clk      : IN  STD_LOGIC;
+      raz      : IN  STD_LOGIC;
+      EmptyUp  : IN  STD_LOGIC;
+      FullDwn  : IN  STD_LOGIC;
+      WriteDwn : OUT STD_LOGIC;
+      ReadUp   : OUT STD_LOGIC
+      );
+  END COMPONENT;
 
-end;
+  COMPONENT ssram_plugin IS
+    GENERIC (tech : INTEGER := 0);
+    PORT
+      (
+        clk         : IN  STD_LOGIC;
+        mem_ctrlr_o : IN  memory_out_type;
+        SSRAM_CLK   : OUT STD_LOGIC;
+        nBWa        : OUT STD_LOGIC;
+        nBWb        : OUT STD_LOGIC;
+        nBWc        : OUT STD_LOGIC;
+        nBWd        : OUT STD_LOGIC;
+        nBWE        : OUT STD_LOGIC;
+        nADSC       : OUT STD_LOGIC;
+        nADSP       : OUT STD_LOGIC;
+        nADV        : OUT STD_LOGIC;
+        nGW         : OUT STD_LOGIC;
+        nCE1        : OUT STD_LOGIC;
+        CE2         : OUT STD_LOGIC;
+        nCE3        : OUT STD_LOGIC;
+        nOE         : OUT STD_LOGIC;
+        MODE        : OUT STD_LOGIC;
+        ZZ          : OUT STD_LOGIC
+        );
+  END COMPONENT;
+
+END;
diff --git a/designs/Validation_LFR_SpectralMatrix/spectral_matrix_package.vhd b/designs/Validation_LFR_SpectralMatrix/spectral_matrix_package.vhd
--- a/designs/Validation_LFR_SpectralMatrix/spectral_matrix_package.vhd
+++ b/designs/Validation_LFR_SpectralMatrix/spectral_matrix_package.vhd
@@ -17,4 +17,13 @@ PACKAGE spectral_matrix_package IS
       error_wen    : OUT STD_LOGIC);
   END COMPONENT;
 
+  COMPONENT spectral_matrix_time_managment
+    PORT (
+      clk      : IN  STD_LOGIC;
+      rstn     : IN  STD_LOGIC;
+      time_in  : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
+      update_1 : IN  STD_LOGIC;
+      time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
+  END COMPONENT;
+  
 END spectral_matrix_package;
diff --git a/designs/Validation_LFR_SpectralMatrix/wave.do b/designs/Validation_LFR_SpectralMatrix/wave.do
--- a/designs/Validation_LFR_SpectralMatrix/wave.do
+++ b/designs/Validation_LFR_SpectralMatrix/wave.do
@@ -41,12 +41,29 @@ add wave -noupdate -expand -group FFT_RE
 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong
 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy
 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid
-add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
-add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
+add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
+add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
+add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray
+add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
+add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
+add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix 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/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
+add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
+add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
+add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
+add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
+add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
+add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
+add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
+add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
+add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
+add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
+add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
+add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
+add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {27617887437 ps} 0} {{Cursor 3} {10382020000 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {95613018769 ps} 0}
-configure wave -namecolwidth 402
-configure wave -valuecolwidth 199
+WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {33725957281 ps} 0} {{Cursor 3} {10434056078 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {82561584962 ps} 0}
+configure wave -namecolwidth 469
+configure wave -valuecolwidth 112
 configure wave -justifyvalue left
 configure wave -signalnamewidth 0
 configure wave -snapdistance 10
@@ -59,6 +76,6 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ps
 update
-WaveRestoreZoom {10380205948 ps} {10383691010 ps}
+WaveRestoreZoom {10429891270 ps} {10442522246 ps}
 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0