| @@ -1,188 +1,140 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
| 3 | LIBRARY lpp; |
|
3 | LIBRARY lpp; | |
| 4 | USE lpp.lpp_ad_conv.ALL; |
|
4 | USE lpp.lpp_ad_conv.ALL; | |
| 5 |
|
5 | USE lpp.lpp_top_lfr_pkg.ALL; | ||
| 6 | ------------------------------------------------------------------------------- |
|
6 | ||
| 7 |
|
7 | ------------------------------------------------------------------------------- | ||
| 8 | ENTITY TB_Data_Acquisition IS |
|
8 | ||
| 9 |
|
9 | ENTITY TB_Data_Acquisition IS | ||
| 10 | END TB_Data_Acquisition; |
|
10 | ||
| 11 |
|
11 | END TB_Data_Acquisition; | ||
| 12 | ------------------------------------------------------------------------------- |
|
12 | ||
| 13 |
|
13 | ------------------------------------------------------------------------------- | ||
| 14 | ARCHITECTURE tb OF TB_Data_Acquisition IS |
|
14 | ||
| 15 |
|
15 | ARCHITECTURE tb OF TB_Data_Acquisition IS | ||
| 16 | COMPONENT TestModule_ADS7886 |
|
16 | ||
| 17 | GENERIC ( |
|
17 | COMPONENT TestModule_ADS7886 | |
| 18 | freq : INTEGER; |
|
18 | GENERIC ( | |
| 19 |
|
|
19 | freq : INTEGER; | |
| 20 |
|
|
20 | amplitude : INTEGER; | |
| 21 | PORT ( |
|
21 | impulsion : INTEGER); | |
| 22 | cnv_run : IN STD_LOGIC; |
|
22 | PORT ( | |
| 23 |
cnv : IN |
|
23 | cnv_run : IN STD_LOGIC; | |
| 24 |
|
|
24 | cnv : IN STD_LOGIC; | |
| 25 |
s |
|
25 | sck : IN STD_LOGIC; | |
| 26 | END COMPONENT; |
|
26 | sdo : OUT STD_LOGIC); | |
| 27 |
|
27 | END COMPONENT; | ||
| 28 | COMPONENT Top_Data_Acquisition |
|
28 | ||
| 29 | PORT ( |
|
29 | -- component ports | |
| 30 |
|
|
30 | SIGNAL cnv_rstn : STD_LOGIC; | |
| 31 |
|
|
31 | SIGNAL cnv : STD_LOGIC; | |
| 32 |
|
|
32 | SIGNAL rstn : STD_LOGIC; | |
| 33 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
33 | SIGNAL sck : STD_LOGIC; | |
| 34 | cnv_clk : IN STD_LOGIC; |
|
34 | SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 35 |
|
|
35 | SIGNAL run_cnv : STD_LOGIC; | |
| 36 | clk : IN STD_LOGIC; |
|
36 | ||
| 37 | rstn : IN STD_LOGIC; |
|
37 | ||
| 38 | -- |
|
38 | -- clock | |
| 39 | sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
39 | signal Clk : STD_LOGIC := '1'; | |
| 40 | sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
40 | SIGNAL cnv_clk : STD_LOGIC := '1'; | |
| 41 | sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
41 | ||
| 42 | sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
42 | ----------------------------------------------------------------------------- | |
| 43 | -- |
|
43 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 44 |
|
|
44 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 45 | sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
45 | ----------------------------------------------------------------------------- | |
| 46 |
|
|
46 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 47 |
|
|
47 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 48 | -- |
|
48 | ----------------------------------------------------------------------------- | |
| 49 |
|
|
49 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 50 |
|
|
50 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 51 | sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
51 | ----------------------------------------------------------------------------- | |
| 52 |
|
|
52 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 53 | -- |
|
53 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 54 | sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
54 | ||
| 55 | sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
55 | BEGIN -- tb | |
| 56 | sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
56 | ||
| 57 | sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); |
|
57 | MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE | |
| 58 | END COMPONENT; |
|
58 | TestModule_ADS7886_u: TestModule_ADS7886 | |
| 59 |
|
59 | GENERIC MAP ( | ||
| 60 | -- component ports |
|
60 | freq => 24*(I+1), | |
| 61 | SIGNAL cnv_rstn : STD_LOGIC; |
|
61 | amplitude => 30000/(I+1), | |
| 62 | SIGNAL cnv : STD_LOGIC; |
|
62 | impulsion => 0) | |
| 63 | SIGNAL rstn : STD_LOGIC; |
|
63 | PORT MAP ( | |
| 64 | SIGNAL sck : STD_LOGIC; |
|
64 | cnv_run => run_cnv, | |
| 65 | SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
65 | cnv => cnv, | |
| 66 | SIGNAL run_cnv : STD_LOGIC; |
|
66 | sck => sck, | |
| 67 |
|
67 | sdo => sdo(I)); | ||
| 68 |
|
68 | END GENERATE MODULE_ADS7886; | ||
| 69 | -- clock |
|
69 | ||
| 70 | signal Clk : STD_LOGIC := '1'; |
|
70 | TestModule_ADS7886_u: TestModule_ADS7886 | |
| 71 | SIGNAL cnv_clk : STD_LOGIC := '1'; |
|
71 | GENERIC MAP ( | |
| 72 |
|
72 | freq => 0, | ||
| 73 | ----------------------------------------------------------------------------- |
|
73 | amplitude => 30000, | |
| 74 | SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
74 | impulsion => 1) | |
| 75 | SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
75 | PORT MAP ( | |
| 76 | SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
76 | cnv_run => run_cnv, | |
| 77 | SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
77 | cnv => cnv, | |
| 78 | ----------------------------------------------------------------------------- |
|
78 | sck => sck, | |
| 79 | SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
79 | sdo => sdo(7)); | |
| 80 | SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
80 | ||
| 81 | SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
81 | ||
| 82 | SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
82 | -- clock generation | |
| 83 | ----------------------------------------------------------------------------- |
|
83 | Clk <= not Clk after 20 ns; -- 25 Mhz | |
| 84 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz | |
| 85 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
85 | ||
| 86 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
86 | -- waveform generation | |
| 87 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | WaveGen_Proc: process | |
| 88 | ----------------------------------------------------------------------------- |
|
88 | begin | |
| 89 | SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
89 | -- insert signal assignments here | |
| 90 | SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
90 | wait until Clk = '1'; | |
| 91 | SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
91 | rstn <= '0'; | |
| 92 | SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
92 | cnv_rstn <= '0'; | |
| 93 |
|
93 | run_cnv <= '0'; | ||
| 94 |
|
94 | wait until Clk = '1'; | ||
| 95 | BEGIN -- tb |
|
95 | wait until Clk = '1'; | |
| 96 |
|
96 | wait until Clk = '1'; | ||
| 97 | MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE |
|
97 | rstn <= '1'; | |
| 98 | TestModule_ADS7886_u: TestModule_ADS7886 |
|
98 | cnv_rstn <= '1'; | |
| 99 | GENERIC MAP ( |
|
99 | wait until Clk = '1'; | |
| 100 | freq => 24*(I+1), |
|
100 | wait until Clk = '1'; | |
| 101 | amplitude => 30000/(I+1), |
|
101 | wait until Clk = '1'; | |
| 102 | impulsion => 0) |
|
102 | wait until Clk = '1'; | |
| 103 | PORT MAP ( |
|
103 | wait until Clk = '1'; | |
| 104 | cnv_run => run_cnv, |
|
104 | wait until Clk = '1'; | |
| 105 | cnv => cnv, |
|
105 | run_cnv <= '1'; | |
| 106 | sck => sck, |
|
106 | wait; | |
| 107 | sdo => sdo(I)); |
|
107 | ||
| 108 | END GENERATE MODULE_ADS7886; |
|
108 | end process WaveGen_Proc; | |
| 109 |
|
109 | |||
| 110 | TestModule_ADS7886_u: TestModule_ADS7886 |
|
110 | ----------------------------------------------------------------------------- | |
| 111 | GENERIC MAP ( |
|
111 | ||
| 112 | freq => 0, |
|
112 | Top_Data_Acquisition_1: lpp_top_acq | |
| 113 | amplitude => 30000, |
|
113 | PORT MAP ( | |
| 114 | impulsion => 1) |
|
114 | cnv_run => run_cnv, | |
| 115 | PORT MAP ( |
|
115 | cnv => cnv, | |
| 116 |
|
|
116 | sck => sck, | |
| 117 |
|
|
117 | sdo => sdo, | |
| 118 |
|
|
118 | cnv_clk => cnv_clk, | |
| 119 | sdo => sdo(7)); |
|
119 | cnv_rstn => cnv_rstn, | |
| 120 |
|
120 | clk => clk, | ||
| 121 |
|
121 | rstn => rstn, | ||
| 122 | -- clock generation |
|
122 | -- | |
| 123 | Clk <= not Clk after 20 ns; -- 25 Mhz |
|
123 | sample_f0_wen => sample_f0_wen, | |
| 124 | cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz |
|
124 | sample_f0_wdata => sample_f0_wdata, | |
| 125 |
|
125 | -- | ||
| 126 | -- waveform generation |
|
126 | sample_f1_wen => sample_f1_wen, | |
| 127 | WaveGen_Proc: process |
|
127 | sample_f1_wdata => sample_f1_wdata, | |
| 128 | begin |
|
128 | -- | |
| 129 | -- insert signal assignments here |
|
129 | sample_f2_wen => sample_f2_wen, | |
| 130 | wait until Clk = '1'; |
|
130 | sample_f2_wdata => sample_f2_wdata, | |
| 131 | rstn <= '0'; |
|
131 | -- | |
| 132 | cnv_rstn <= '0'; |
|
132 | sample_f3_wen => sample_f3_wen, | |
| 133 | run_cnv <= '0'; |
|
133 | sample_f3_wdata => sample_f3_wdata | |
| 134 | wait until Clk = '1'; |
|
134 | ); | |
| 135 | wait until Clk = '1'; |
|
135 | ||
| 136 | wait until Clk = '1'; |
|
136 | ||
| 137 | rstn <= '1'; |
|
137 | ||
| 138 | cnv_rstn <= '1'; |
|
138 | ||
| 139 | wait until Clk = '1'; |
|
139 | ||
| 140 | wait until Clk = '1'; |
|
140 | END tb; | |
| 141 | wait until Clk = '1'; |
|
|||
| 142 | wait until Clk = '1'; |
|
|||
| 143 | wait until Clk = '1'; |
|
|||
| 144 | wait until Clk = '1'; |
|
|||
| 145 | run_cnv <= '1'; |
|
|||
| 146 | wait; |
|
|||
| 147 |
|
||||
| 148 | end process WaveGen_Proc; |
|
|||
| 149 |
|
||||
| 150 | ----------------------------------------------------------------------------- |
|
|||
| 151 |
|
||||
| 152 | Top_Data_Acquisition_1: Top_Data_Acquisition |
|
|||
| 153 | PORT MAP ( |
|
|||
| 154 | cnv_run => run_cnv, |
|
|||
| 155 | cnv => cnv, |
|
|||
| 156 | sck => sck, |
|
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| 157 | sdo => sdo, |
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|||
| 158 | cnv_clk => cnv_clk, |
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|||
| 159 | cnv_rstn => cnv_rstn, |
|
|||
| 160 | clk => clk, |
|
|||
| 161 | rstn => rstn, |
|
|||
| 162 | -- |
|
|||
| 163 | sample_f0_0_ren => sample_f0_0_ren, |
|
|||
| 164 | sample_f0_0_rdata => sample_f0_0_rdata, |
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| 165 | sample_f0_0_full => sample_f0_0_full, |
|
|||
| 166 | sample_f0_0_empty => sample_f0_0_empty, |
|
|||
| 167 | -- |
|
|||
| 168 | sample_f0_1_ren => sample_f0_1_ren, |
|
|||
| 169 | sample_f0_1_rdata => sample_f0_1_rdata, |
|
|||
| 170 | sample_f0_1_full => sample_f0_1_full, |
|
|||
| 171 | sample_f0_1_empty => sample_f0_1_empty, |
|
|||
| 172 | -- |
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| 173 | sample_f1_ren => sample_f1_ren, |
|
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| 174 | sample_f1_rdata => sample_f1_rdata, |
|
|||
| 175 | sample_f1_full => sample_f1_full, |
|
|||
| 176 | sample_f1_empty => sample_f1_empty, |
|
|||
| 177 | -- |
|
|||
| 178 | sample_f3_ren => sample_f3_ren, |
|
|||
| 179 | sample_f3_rdata => sample_f3_rdata, |
|
|||
| 180 | sample_f3_full => sample_f3_full, |
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| 181 | sample_f3_empty => sample_f3_empty |
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|||
| 182 | ); |
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|||
| 183 | sample_f0_0_ren <= (OTHERS => '1'); |
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|||
| 184 | sample_f0_1_ren <= (OTHERS => '1'); |
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| 185 | sample_f1_ren <= (OTHERS => '1'); |
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| 186 | sample_f3_ren <= (OTHERS => '1'); |
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| 187 |
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||||
| 188 | END tb; |
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| @@ -1,49 +1,54 | |||||
| 1 |
|
1 | |||
| 2 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd |
|
2 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd | |
| 3 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd |
|
3 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd | |
| 4 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd |
|
4 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd | |
| 5 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd |
|
5 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd | |
| 6 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd |
|
6 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd | |
| 7 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd |
|
7 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd | |
| 8 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
8 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
| 9 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd |
|
9 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd | |
| 10 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd |
|
10 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd | |
| 11 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd |
|
11 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd | |
| 12 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd |
|
12 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd | |
| 13 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd |
|
13 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd | |
| 14 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd |
|
14 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd | |
| 15 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd |
|
15 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd | |
| 16 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd |
|
16 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd | |
| 17 |
|
17 | |||
| 18 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd |
|
18 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd | |
| 19 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd |
|
19 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
| 20 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd |
|
20 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd | |
| 21 |
vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_C |
|
21 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd | |
| 22 |
|
|
22 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd | |
| 23 |
|
23 | #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd | ||
| 24 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd |
|
24 | ||
| 25 |
vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/ |
|
25 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd | |
| 26 |
vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_ |
|
26 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
| 27 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd |
|
27 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |
| 28 |
|
28 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | ||
| 29 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd |
|
29 | ||
| 30 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_ |
|
30 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd | |
| 31 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFO |
|
31 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd | |
| 32 |
|
32 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd | ||
| 33 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd |
|
33 | ||
| 34 |
|
34 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd | ||
| 35 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd |
|
35 | ||
| 36 |
vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_ |
|
36 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |
| 37 |
|
37 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | ||
| 38 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd |
|
38 | ||
| 39 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ |
|
39 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd | |
| 40 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ |
|
40 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd | |
| 41 |
|
41 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd | ||
| 42 | vcom -quiet -93 -work work Top_Data_Acquisition.vhd |
|
42 | ||
| 43 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd |
|
43 | ||
| 44 |
|
44 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | ||
| 45 | #vsim work.TB_Data_Acquisition |
|
45 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | |
| 46 |
|
46 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd | ||
| 47 | #log -r * |
|
47 | ||
| 48 | #do wave_data_acquisition.do |
|
48 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd | |
|
|
49 | ||||
|
|
50 | vsim work.TB_Data_Acquisition | |||
|
|
51 | ||||
|
|
52 | #log -r * | |||
|
|
53 | #do wave_data_acquisition.do | |||
| 49 | #run 5 ms No newline at end of file |
|
54 | #run 5 ms | |
| @@ -1,242 +1,49 | |||||
| 1 | onerror {resume} |
|
1 | onerror {resume} | |
| 2 | quietly WaveActivateNextPane {} 0 |
|
2 | quietly WaveActivateNextPane {} 0 | |
| 3 |
add wave -noupdate -group { |
|
3 | add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample | |
| 4 |
add wave -noupdate -group { |
|
4 | add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val | |
| 5 |
add wave -noupdate -group { |
|
5 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val | |
| 6 |
add wave -noupdate -group { |
|
6 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in | |
| 7 |
add wave -noupdate -group { |
|
7 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val | |
| 8 |
add wave -noupdate -group { |
|
8 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out | |
| 9 |
add wave -noupdate -group { |
|
9 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in_val | |
| 10 |
add wave -noupdate -group { |
|
10 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in | |
| 11 |
add wave -noupdate -group { |
|
11 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out_val | |
| 12 |
add wave -noupdate -group { |
|
12 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out | |
| 13 |
add wave -noupdate -group { |
|
13 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in_val | |
| 14 |
add wave -noupdate -group { |
|
14 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in | |
| 15 |
add wave -noupdate -group { |
|
15 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out_val | |
| 16 |
add wave -noupdate -group { |
|
16 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out | |
| 17 |
add wave -noupdate -group { |
|
17 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in_val | |
| 18 |
add wave -noupdate -group { |
|
18 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in | |
| 19 |
add wave -noupdate -group { |
|
19 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out_val | |
| 20 |
add wave -noupdate -group { |
|
20 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out | |
| 21 |
add wave -noupdate -group { |
|
21 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in_val | |
| 22 |
add wave -noupdate -group { |
|
22 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in | |
| 23 |
add wave -noupdate -group { |
|
23 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out_val | |
| 24 |
add wave -noupdate -group F |
|
24 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out | |
| 25 |
add wave -noupdate -group FI |
|
25 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wen | |
| 26 |
add wave -noupdate -group FI |
|
26 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wdata | |
| 27 |
add wave -noupdate -group FI |
|
27 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wen | |
| 28 |
add wave -noupdate -group FI |
|
28 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wdata | |
| 29 |
add wave -noupdate -group FI |
|
29 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wen | |
| 30 |
add wave -noupdate -group FI |
|
30 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wdata | |
| 31 |
add wave -noupdate -group FI |
|
31 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wen | |
| 32 |
add wave -noupdate -group FI |
|
32 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wdata | |
| 33 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_clk |
|
|||
| 34 | add wave -noupdate -group FILTER -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_in(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in |
|
|||
| 35 | add wave -noupdate -group FILTER -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_out(7) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(6) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(5) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(4) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(3) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(2) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(1) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(0) {-height 15 -radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out |
|
|||
| 36 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/virg_pos |
|
|||
| 37 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/gotest |
|
|||
| 38 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefs |
|
|||
| 39 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/smpl_clk_old |
|
|||
| 40 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/wd_sel |
|
|||
| 41 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/read |
|
|||
| 42 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/svg_addr |
|
|||
| 43 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/count |
|
|||
| 44 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/write |
|
|||
| 45 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/waddr_sel |
|
|||
| 46 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/go_0 |
|
|||
| 47 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in |
|
|||
| 48 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in_bk |
|
|||
| 49 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_out |
|
|||
| 50 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_ctrl |
|
|||
| 51 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_sample_in |
|
|||
| 52 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_coef_in |
|
|||
| 53 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_out |
|
|||
| 54 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentcel |
|
|||
| 55 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentchan |
|
|||
| 56 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_in_buff |
|
|||
| 57 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_out_buff |
|
|||
| 58 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefsreg |
|
|||
| 59 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/iir_cel_state |
|
|||
| 60 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_run |
|
|||
| 61 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv |
|
|||
| 62 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sck |
|
|||
| 63 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sdo |
|
|||
| 64 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_clk |
|
|||
| 65 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_rstn |
|
|||
| 66 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/clk |
|
|||
| 67 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/rstn |
|
|||
| 68 | add wave -noupdate -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/sample(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/sample |
|
|||
| 69 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_val |
|
|||
| 70 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/coefs |
|
|||
| 71 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_in |
|
|||
| 72 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_out |
|
|||
| 73 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state |
|
|||
| 74 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/alu_selected_coeff |
|
|||
| 75 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing |
|
|||
| 76 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing |
|
|||
| 77 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/clk |
|
|||
| 78 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/reset |
|
|||
| 79 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/ctrl |
|
|||
| 80 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op1 |
|
|||
| 81 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op2 |
|
|||
| 82 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/res |
|
|||
| 83 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input |
|
|||
| 84 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
|||
| 85 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
|||
| 86 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/rstn |
|
|||
| 87 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/clk |
|
|||
| 88 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/virg_pos |
|
|||
| 89 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/coefs |
|
|||
| 90 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src |
|
|||
| 91 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata |
|
|||
| 92 | add wave -noupdate -group DATA_FLOW -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input |
|
|||
| 93 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write |
|
|||
| 94 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read |
|
|||
| 95 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst |
|
|||
| 96 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 |
|
|||
| 97 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous |
|
|||
| 98 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input |
|
|||
| 99 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff |
|
|||
| 100 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl |
|
|||
| 101 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in |
|
|||
| 102 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out |
|
|||
| 103 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
|||
| 104 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
|||
| 105 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output |
|
|||
| 106 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample |
|
|||
| 107 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s |
|
|||
| 108 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff |
|
|||
| 109 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s |
|
|||
| 110 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef |
|
|||
| 111 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/rstn |
|
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| 112 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/clk |
|
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| 113 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/virg_pos |
|
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| 114 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/coefs |
|
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| 115 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val |
|
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| 116 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in |
|
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| 117 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val |
|
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| 118 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out |
|
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| 119 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/in_sel_src |
|
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| 120 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_sel_wdata |
|
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| 121 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_write |
|
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| 122 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_read |
|
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| 123 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_rst |
|
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| 124 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_add1 |
|
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| 125 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/waddr_previous |
|
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| 126 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_input |
|
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| 127 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_coeff |
|
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| 128 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_ctrl |
|
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| 129 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_buf |
|
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| 130 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_rotate |
|
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| 131 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_s |
|
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| 132 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s |
|
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| 133 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 |
|
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| 134 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s |
|
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| 135 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(17) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(16) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(15) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(14) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(13) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(12) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(11) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(10) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(9) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(8) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s |
|
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| 136 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 |
|
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| 137 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src |
|
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| 138 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output |
|
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| 139 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
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| 140 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in |
|
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| 141 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
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| 142 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous |
|
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| 143 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write |
|
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| 144 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata |
|
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| 145 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
|||
| 146 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output |
|
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| 147 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
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| 148 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input |
|
|||
| 149 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read |
|
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| 150 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst |
|
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| 151 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 |
|
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| 152 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
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| 153 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff |
|
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| 154 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s |
|
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| 155 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef |
|
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| 156 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff |
|
|||
| 157 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input |
|
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| 158 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
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| 159 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
|||
| 160 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl |
|
|||
| 161 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef |
|
|||
| 162 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample |
|
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| 163 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s |
|
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| 164 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output |
|
|||
| 165 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state |
|
|||
| 166 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing |
|
|||
| 167 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing |
|
|||
| 168 | add wave -noupdate -group DATAFLOW -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out |
|
|||
| 169 | add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rstn |
|
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| 170 | add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/clk |
|
|||
| 171 | add wave -noupdate -group DATAFLOW_RAM -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(0) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(8) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(9) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(10) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(11) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(12) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(13) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(14) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(15) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(16) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(17) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(18) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(19) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(20) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(21) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(22) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(23) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(24) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(25) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(26) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(27) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(28) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(29) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(30) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(31) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(32) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(33) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(34) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(35) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(36) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(37) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(38) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(39) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(40) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(41) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(42) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(43) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(44) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(45) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(46) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(47) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(48) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(49) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(50) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(51) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(52) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(53) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(54) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(55) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(56) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(57) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(58) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(59) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(60) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(61) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(62) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(63) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(64) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(65) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(66) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(67) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(68) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(69) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(70) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(71) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(72) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(73) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(74) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(75) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(76) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(77) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(78) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(79) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(80) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(81) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(82) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(83) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(84) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(85) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(86) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(87) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(88) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(89) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(90) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(91) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(92) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(93) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(94) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(95) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(96) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(97) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(98) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(99) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(100) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(101) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(102) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(103) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(104) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(105) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(106) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(107) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(108) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(109) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(110) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(111) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(112) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(113) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(114) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(115) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(116) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(117) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(118) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(119) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(120) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(121) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(122) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(123) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(124) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(125) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(126) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(127) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(128) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(129) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(130) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(131) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(132) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(133) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(134) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(135) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(136) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(137) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(138) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(139) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(140) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(141) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(142) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(143) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(144) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(145) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(146) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(147) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(148) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(149) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(150) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(151) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(152) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(153) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(154) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(155) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(156) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(157) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(158) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(159) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(160) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(161) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(162) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(163) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(164) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(165) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(166) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(167) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(168) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(169) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(170) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(171) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(172) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(173) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(174) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(175) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(176) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(177) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(178) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(179) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(180) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(181) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(182) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(183) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(184) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(185) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(186) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(187) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(188) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(189) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(190) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(191) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(192) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(193) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(194) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(195) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(196) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(197) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(198) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(199) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(200) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(201) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(202) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(203) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(204) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(205) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(206) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(207) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(208) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(209) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(210) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(211) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(212) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(213) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(214) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(215) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(216) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(217) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(218) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(219) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(220) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(221) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(222) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(223) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(224) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(225) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(226) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(227) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(228) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(229) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(230) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(231) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(232) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(233) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(234) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(235) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(236) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(237) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(238) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(239) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(240) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(241) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(242) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(243) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(244) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(245) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(246) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(247) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(248) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(249) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(250) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(251) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(252) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(253) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(254) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(255) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray |
|
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| 172 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/counter |
|
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| 173 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_rst |
|
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| 174 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_add1 |
|
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| 175 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr_previous |
|
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| 176 | add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_write |
|
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| 177 | add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wen |
|
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| 178 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr |
|
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| 179 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wd |
|
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| 180 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_in |
|
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| 181 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_read |
|
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| 182 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ren |
|
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| 183 | add wave -noupdate -group DATAFLOW_RAM -group READ -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr |
|
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| 184 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rd |
|
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| 185 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_out |
|
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| 186 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val |
|
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| 187 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in |
|
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| 188 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val |
|
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| 189 | add wave -noupdate -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out |
|
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| 190 | add wave -noupdate -height 15 -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) |
|
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| 191 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clk |
|
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| 192 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/reset |
|
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| 193 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac |
|
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| 194 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mac_mul_add |
|
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| 195 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1 |
|
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| 196 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2 |
|
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| 197 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/res |
|
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| 198 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add |
|
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| 199 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mult |
|
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| 200 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout |
|
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| 201 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderina |
|
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| 202 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderinb |
|
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| 203 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderout |
|
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| 204 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel |
|
|||
| 205 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d_resz |
|
|||
| 206 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d_resz |
|
|||
| 207 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel |
|
|||
| 208 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add_d |
|
|||
| 209 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d |
|
|||
| 210 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d |
|
|||
| 211 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout_d |
|
|||
| 212 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel_d |
|
|||
| 213 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d |
|
|||
| 214 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d_d |
|
|||
| 215 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d |
|
|||
| 216 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d_d |
|
|||
| 217 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_val |
|
|||
| 218 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_rot |
|
|||
| 219 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state |
|
|||
| 220 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out |
|
|||
| 221 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s |
|
|||
| 222 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 |
|
|||
| 223 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s |
|
|||
| 224 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s |
|
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| 225 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 |
|
|||
| 226 | TreeUpdate [SetDefaultTree] |
|
33 | TreeUpdate [SetDefaultTree] | |
| 227 |
WaveRestoreCursors {{Cursor 1} { |
|
34 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} | |
| 228 |
configure wave -namecolwidth |
|
35 | configure wave -namecolwidth 430 | |
| 229 | configure wave -valuecolwidth 100 |
|
36 | configure wave -valuecolwidth 100 | |
| 230 | configure wave -justifyvalue left |
|
37 | configure wave -justifyvalue left | |
| 231 | configure wave -signalnamewidth 0 |
|
38 | configure wave -signalnamewidth 0 | |
| 232 | configure wave -snapdistance 10 |
|
39 | configure wave -snapdistance 10 | |
| 233 | configure wave -datasetprefix 0 |
|
40 | configure wave -datasetprefix 0 | |
| 234 | configure wave -rowmargin 4 |
|
41 | configure wave -rowmargin 4 | |
| 235 | configure wave -childrowmargin 2 |
|
42 | configure wave -childrowmargin 2 | |
| 236 | configure wave -gridoffset 0 |
|
43 | configure wave -gridoffset 0 | |
| 237 | configure wave -gridperiod 1 |
|
44 | configure wave -gridperiod 1 | |
| 238 | configure wave -griddelta 40 |
|
45 | configure wave -griddelta 40 | |
| 239 | configure wave -timeline 0 |
|
46 | configure wave -timeline 0 | |
| 240 | configure wave -timelineunits ns |
|
47 | configure wave -timelineunits ns | |
| 241 | update |
|
48 | update | |
| 242 |
WaveRestoreZoom { |
|
49 | WaveRestoreZoom {0 ps} {754717 ps} | |
| @@ -1,250 +1,251 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Jean-christophe PELLION |
|
19 | -- Author : Jean-christophe PELLION | |
| 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
| 21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
| 22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
| 23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
| 24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
| 25 | LIBRARY lpp; |
|
25 | LIBRARY lpp; | |
| 26 | USE lpp.iir_filter.ALL; |
|
26 | USE lpp.iir_filter.ALL; | |
| 27 | USE lpp.general_purpose.ALL; |
|
27 | USE lpp.general_purpose.ALL; | |
| 28 |
|
28 | |||
| 29 |
|
29 | |||
| 30 |
|
30 | |||
| 31 | ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS |
|
31 | ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS | |
| 32 | GENERIC( |
|
32 | GENERIC( | |
| 33 | tech : INTEGER := 0; |
|
33 | tech : INTEGER := 0; | |
| 34 | Mem_use : INTEGER := use_RAM; |
|
34 | Mem_use : INTEGER := use_RAM; | |
| 35 | Sample_SZ : INTEGER := 16; |
|
35 | Sample_SZ : INTEGER := 16; | |
| 36 | Coef_SZ : INTEGER := 9; |
|
36 | Coef_SZ : INTEGER := 9; | |
| 37 | Coef_Nb : INTEGER := 30; |
|
37 | Coef_Nb : INTEGER := 30; | |
| 38 | Coef_sel_SZ : INTEGER := 5 |
|
38 | Coef_sel_SZ : INTEGER := 5 | |
| 39 | ); |
|
39 | ); | |
| 40 | PORT( |
|
40 | PORT( | |
| 41 | rstn : IN STD_LOGIC; |
|
41 | rstn : IN STD_LOGIC; | |
| 42 | clk : IN STD_LOGIC; |
|
42 | clk : IN STD_LOGIC; | |
| 43 | -- PARAMETER |
|
43 | -- PARAMETER | |
| 44 | virg_pos : IN INTEGER; |
|
44 | virg_pos : IN INTEGER; | |
| 45 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); |
|
45 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
| 46 | -- CONTROL |
|
46 | -- CONTROL | |
| 47 | in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
47 | in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 48 | -- |
|
48 | -- | |
| 49 | ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
49 | ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 50 | ram_write : IN STD_LOGIC; |
|
50 | ram_write : IN STD_LOGIC; | |
| 51 | ram_read : IN STD_LOGIC; |
|
51 | ram_read : IN STD_LOGIC; | |
| 52 | raddr_rst : IN STD_LOGIC; |
|
52 | raddr_rst : IN STD_LOGIC; | |
| 53 | raddr_add1 : IN STD_LOGIC; |
|
53 | raddr_add1 : IN STD_LOGIC; | |
| 54 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
54 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 55 | -- |
|
55 | -- | |
| 56 | alu_sel_input : IN STD_LOGIC; |
|
56 | alu_sel_input : IN STD_LOGIC; | |
| 57 | alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); |
|
57 | alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
| 58 | alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) |
|
58 | alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) | |
| 59 | alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
59 | alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 60 | -- DATA |
|
60 | -- DATA | |
| 61 | sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
61 | sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
| 62 | sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0) |
|
62 | sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0) | |
| 63 | ); |
|
63 | ); | |
| 64 | END IIR_CEL_CTRLR_v2_DATAFLOW; |
|
64 | END IIR_CEL_CTRLR_v2_DATAFLOW; | |
| 65 |
|
65 | |||
| 66 | ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS |
|
66 | ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS | |
| 67 |
|
67 | |||
| 68 | COMPONENT RAM_CTRLR_v2 |
|
68 | COMPONENT RAM_CTRLR_v2 | |
| 69 | GENERIC ( |
|
69 | GENERIC ( | |
| 70 | tech : INTEGER; |
|
70 | tech : INTEGER; | |
| 71 | Input_SZ_1 : INTEGER; |
|
71 | Input_SZ_1 : INTEGER; | |
| 72 | Mem_use : INTEGER); |
|
72 | Mem_use : INTEGER); | |
| 73 | PORT ( |
|
73 | PORT ( | |
| 74 | rstn : IN STD_LOGIC; |
|
74 | rstn : IN STD_LOGIC; | |
| 75 | clk : IN STD_LOGIC; |
|
75 | clk : IN STD_LOGIC; | |
| 76 | ram_write : IN STD_LOGIC; |
|
76 | ram_write : IN STD_LOGIC; | |
| 77 | ram_read : IN STD_LOGIC; |
|
77 | ram_read : IN STD_LOGIC; | |
| 78 | raddr_rst : IN STD_LOGIC; |
|
78 | raddr_rst : IN STD_LOGIC; | |
| 79 | raddr_add1 : IN STD_LOGIC; |
|
79 | raddr_add1 : IN STD_LOGIC; | |
| 80 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
80 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 81 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
81 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
| 82 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); |
|
82 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); | |
| 83 | END COMPONENT; |
|
83 | END COMPONENT; | |
| 84 |
|
84 | |||
| 85 | SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
85 | SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
| 86 | SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
86 | SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
| 87 | SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
87 | SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
| 88 | SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
88 | SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
| 89 | SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
89 | SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
| 90 | SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0); |
|
90 | SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0); | |
| 91 |
|
91 | |||
| 92 | SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0); |
|
92 | SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0); | |
| 93 | SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0); |
|
93 | SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0); | |
| 94 |
|
94 | |||
| 95 | SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0); |
|
95 | SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0); | |
| 96 |
|
96 | |||
| 97 | BEGIN |
|
97 | BEGIN | |
| 98 |
|
98 | |||
| 99 | ----------------------------------------------------------------------------- |
|
99 | ----------------------------------------------------------------------------- | |
| 100 | -- INPUT |
|
100 | -- INPUT | |
| 101 | ----------------------------------------------------------------------------- |
|
101 | ----------------------------------------------------------------------------- | |
| 102 | PROCESS (clk, rstn) |
|
102 | PROCESS (clk, rstn) | |
| 103 | BEGIN -- PROCESS |
|
103 | BEGIN -- PROCESS | |
| 104 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
104 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 105 | reg_sample_in <= (OTHERS => '0'); |
|
105 | reg_sample_in <= (OTHERS => '0'); | |
| 106 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
106 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
| 107 | CASE in_sel_src IS |
|
107 | CASE in_sel_src IS | |
| 108 | WHEN "00" => reg_sample_in <= reg_sample_in; |
|
108 | WHEN "00" => reg_sample_in <= reg_sample_in; | |
| 109 | WHEN "01" => reg_sample_in <= sample_in; |
|
109 | WHEN "01" => reg_sample_in <= sample_in; | |
| 110 | WHEN "10" => reg_sample_in <= ram_output; |
|
110 | WHEN "10" => reg_sample_in <= ram_output; | |
| 111 | WHEN "11" => reg_sample_in <= alu_output; |
|
111 | WHEN "11" => reg_sample_in <= alu_output; | |
| 112 | WHEN OTHERS => NULL; |
|
112 | WHEN OTHERS => NULL; | |
| 113 | END CASE; |
|
113 | END CASE; | |
| 114 | END IF; |
|
114 | END IF; | |
| 115 | END PROCESS; |
|
115 | END PROCESS; | |
| 116 |
|
116 | |||
| 117 |
|
117 | |||
| 118 | ----------------------------------------------------------------------------- |
|
118 | ----------------------------------------------------------------------------- | |
| 119 | -- RAM + CTRL |
|
119 | -- RAM + CTRL | |
| 120 | ----------------------------------------------------------------------------- |
|
120 | ----------------------------------------------------------------------------- | |
| 121 |
|
121 | |||
| 122 | ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE |
|
122 | ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE | |
| 123 | alu_output WHEN ram_sel_Wdata = "01" ELSE |
|
123 | alu_output WHEN ram_sel_Wdata = "01" ELSE | |
| 124 | ram_output; |
|
124 | ram_output; | |
| 125 |
|
125 | |||
| 126 | RAM_CTRLR_v2_1: RAM_CTRLR_v2 |
|
126 | RAM_CTRLR_v2_1: RAM_CTRLR_v2 | |
| 127 | GENERIC MAP ( |
|
127 | GENERIC MAP ( | |
| 128 | tech => tech, |
|
128 | tech => tech, | |
| 129 | Input_SZ_1 => Sample_SZ, |
|
129 | Input_SZ_1 => Sample_SZ, | |
| 130 | Mem_use => Mem_use) |
|
130 | Mem_use => Mem_use) | |
| 131 | PORT MAP ( |
|
131 | PORT MAP ( | |
| 132 | clk => clk, |
|
132 | clk => clk, | |
| 133 | rstn => rstn, |
|
133 | rstn => rstn, | |
| 134 | ram_write => ram_write, |
|
134 | ram_write => ram_write, | |
| 135 | ram_read => ram_read, |
|
135 | ram_read => ram_read, | |
| 136 | raddr_rst => raddr_rst, |
|
136 | raddr_rst => raddr_rst, | |
| 137 | raddr_add1 => raddr_add1, |
|
137 | raddr_add1 => raddr_add1, | |
| 138 | waddr_previous => waddr_previous, |
|
138 | waddr_previous => waddr_previous, | |
| 139 | sample_in => ram_input, |
|
139 | sample_in => ram_input, | |
| 140 | sample_out => ram_output); |
|
140 | sample_out => ram_output); | |
| 141 |
|
141 | |||
| 142 | ----------------------------------------------------------------------------- |
|
142 | ----------------------------------------------------------------------------- | |
| 143 | -- MAC_ACC |
|
143 | -- MAC_ACC | |
| 144 | ----------------------------------------------------------------------------- |
|
144 | ----------------------------------------------------------------------------- | |
| 145 | -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE) |
|
145 | -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE) | |
| 146 | -- Data In : mac_sample, mac_coef |
|
146 | -- Data In : mac_sample, mac_coef | |
| 147 | -- Data Out: mac_output |
|
147 | -- Data Out: mac_output | |
| 148 |
|
148 | |||
| 149 | alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output; |
|
149 | alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output; | |
| 150 |
|
150 | |||
| 151 | coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE |
|
151 | coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE | |
| 152 | coeff_in: IF I < Coef_Nb GENERATE |
|
152 | coeff_in: IF I < Coef_Nb GENERATE | |
| 153 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE |
|
153 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |
| 154 | arrayCoeff(I,J) <= coefs(Coef_SZ*I+J); |
|
154 | arrayCoeff(I,J) <= coefs(Coef_SZ*I+J); | |
| 155 | END GENERATE all_bit; |
|
155 | END GENERATE all_bit; | |
| 156 | END GENERATE coeff_in; |
|
156 | END GENERATE coeff_in; | |
| 157 | coeff_null: IF I > (Coef_Nb -1) GENERATE |
|
157 | coeff_null: IF I > (Coef_Nb -1) GENERATE | |
| 158 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE |
|
158 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |
| 159 | arrayCoeff(I,J) <= '0'; |
|
159 | arrayCoeff(I,J) <= '0'; | |
| 160 | END GENERATE all_bit; |
|
160 | END GENERATE all_bit; | |
| 161 | END GENERATE coeff_null; |
|
161 | END GENERATE coeff_null; | |
| 162 | END GENERATE coefftable; |
|
162 | END GENERATE coefftable; | |
| 163 |
|
163 | |||
| 164 | Coeff_Mux : MUXN |
|
164 | Coeff_Mux : MUXN | |
| 165 | GENERIC MAP ( |
|
165 | GENERIC MAP ( | |
| 166 | Input_SZ => Coef_SZ, |
|
166 | Input_SZ => Coef_SZ, | |
| 167 | NbStage => Coef_sel_SZ) |
|
167 | NbStage => Coef_sel_SZ) | |
| 168 | PORT MAP ( |
|
168 | PORT MAP ( | |
| 169 | sel => alu_sel_coeff, |
|
169 | sel => alu_sel_coeff, | |
| 170 | INPUT => arrayCoeff, |
|
170 | INPUT => arrayCoeff, | |
| 171 | RES => alu_coef_s); |
|
171 | RES => alu_coef_s); | |
| 172 |
|
172 | |||
| 173 |
|
173 | |||
| 174 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE |
|
174 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |
| 175 | alu_coef(J) <= alu_coef_s(J); |
|
175 | alu_coef(J) <= alu_coef_s(J); | |
| 176 | END GENERATE all_bit; |
|
176 | END GENERATE all_bit; | |
| 177 |
|
177 | |||
| 178 | ----------------------------------------------------------------------------- |
|
178 | ----------------------------------------------------------------------------- | |
| 179 | -- TODO : just for Synthesis test |
|
179 | -- TODO : just for Synthesis test | |
| 180 |
|
180 | |||
| 181 | --PROCESS (clk, rstn) |
|
181 | --PROCESS (clk, rstn) | |
| 182 | --BEGIN |
|
182 | --BEGIN | |
| 183 | -- IF rstn = '0' THEN |
|
183 | -- IF rstn = '0' THEN | |
| 184 | -- alu_coef <= (OTHERS => '0'); |
|
184 | -- alu_coef <= (OTHERS => '0'); | |
| 185 | -- ELSIF clk'event AND clk = '1' THEN |
|
185 | -- ELSIF clk'event AND clk = '1' THEN | |
| 186 | -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP |
|
186 | -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP | |
| 187 | -- alu_coef(J) <= alu_coef_s(J); |
|
187 | -- alu_coef(J) <= alu_coef_s(J); | |
| 188 | -- END LOOP all_bit; |
|
188 | -- END LOOP all_bit; | |
| 189 | -- END IF; |
|
189 | -- END IF; | |
| 190 | --END PROCESS; |
|
190 | --END PROCESS; | |
| 191 |
|
191 | |||
| 192 | ----------------------------------------------------------------------------- |
|
192 | ----------------------------------------------------------------------------- | |
| 193 |
|
193 | |||
| 194 |
|
194 | |||
| 195 | ALU_1: ALU |
|
195 | ALU_1: ALU | |
| 196 | GENERIC MAP ( |
|
196 | GENERIC MAP ( | |
| 197 | Arith_en => 1, |
|
197 | Arith_en => 1, | |
| 198 | Input_SZ_1 => Sample_SZ, |
|
198 | Input_SZ_1 => Sample_SZ, | |
| 199 |
Input_SZ_2 => Coef_SZ |
|
199 | Input_SZ_2 => Coef_SZ, | |
|
|
200 | COMP_EN => 1) | |||
| 200 | PORT MAP ( |
|
201 | PORT MAP ( | |
| 201 | clk => clk, |
|
202 | clk => clk, | |
| 202 | reset => rstn, |
|
203 | reset => rstn, | |
| 203 | ctrl => alu_ctrl, |
|
204 | ctrl => alu_ctrl, | |
| 204 | comp => alu_comp, |
|
205 | comp => alu_comp, | |
| 205 | OP1 => alu_sample, |
|
206 | OP1 => alu_sample, | |
| 206 | OP2 => alu_coef, |
|
207 | OP2 => alu_coef, | |
| 207 | RES => alu_output_s); |
|
208 | RES => alu_output_s); | |
| 208 |
|
209 | |||
| 209 | alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos); |
|
210 | alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos); | |
| 210 |
|
211 | |||
| 211 | sample_out <= alu_output; |
|
212 | sample_out <= alu_output; | |
| 212 |
|
213 | |||
| 213 | END ar_IIR_CEL_CTRLR_v2_DATAFLOW; |
|
214 | END ar_IIR_CEL_CTRLR_v2_DATAFLOW; | |
| 214 |
|
215 | |||
| 215 |
|
216 | |||
| 216 |
|
217 | |||
| 217 |
|
218 | |||
| 218 |
|
219 | |||
| 219 |
|
220 | |||
| 220 |
|
221 | |||
| 221 |
|
222 | |||
| 222 |
|
223 | |||
| 223 |
|
224 | |||
| 224 |
|
225 | |||
| 225 |
|
226 | |||
| 226 |
|
227 | |||
| 227 |
|
228 | |||
| 228 |
|
229 | |||
| 229 |
|
230 | |||
| 230 |
|
231 | |||
| 231 |
|
232 | |||
| 232 |
|
233 | |||
| 233 |
|
234 | |||
| 234 |
|
235 | |||
| 235 |
|
236 | |||
| 236 |
|
237 | |||
| 237 |
|
238 | |||
| 238 |
|
239 | |||
| 239 |
|
240 | |||
| 240 |
|
241 | |||
| 241 |
|
242 | |||
| 242 |
|
243 | |||
| 243 |
|
244 | |||
| 244 |
|
245 | |||
| 245 |
|
246 | |||
| 246 |
|
247 | |||
| 247 |
|
248 | |||
| 248 |
|
249 | |||
| 249 |
|
250 | |||
| 250 |
|
251 | |||
| @@ -1,120 +1,120 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
| 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
| 21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
| 22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
| 23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
| 24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
| 25 | LIBRARY lpp; |
|
25 | LIBRARY lpp; | |
| 26 | USE lpp.iir_filter.ALL; |
|
26 | USE lpp.iir_filter.ALL; | |
| 27 | USE lpp.FILTERcfg.ALL; |
|
27 | USE lpp.FILTERcfg.ALL; | |
| 28 | USE lpp.general_purpose.ALL; |
|
28 | USE lpp.general_purpose.ALL; | |
| 29 | LIBRARY techmap; |
|
29 | LIBRARY techmap; | |
| 30 | USE techmap.gencomp.ALL; |
|
30 | USE techmap.gencomp.ALL; | |
| 31 |
|
31 | |||
| 32 | ENTITY RAM_CTRLR_v2 IS |
|
32 | ENTITY RAM_CTRLR_v2 IS | |
| 33 | GENERIC( |
|
33 | GENERIC( | |
| 34 | tech : INTEGER := 0; |
|
34 | tech : INTEGER := 0; | |
| 35 | Input_SZ_1 : INTEGER := 16; |
|
35 | Input_SZ_1 : INTEGER := 16; | |
| 36 | Mem_use : INTEGER := use_RAM |
|
36 | Mem_use : INTEGER := use_RAM | |
| 37 | ); |
|
37 | ); | |
| 38 | PORT( |
|
38 | PORT( | |
| 39 | rstn : IN STD_LOGIC; |
|
39 | rstn : IN STD_LOGIC; | |
| 40 | clk : IN STD_LOGIC; |
|
40 | clk : IN STD_LOGIC; | |
| 41 | -- R/W Ctrl |
|
41 | -- R/W Ctrl | |
| 42 | ram_write : IN STD_LOGIC; |
|
42 | ram_write : IN STD_LOGIC; | |
| 43 | ram_read : IN STD_LOGIC; |
|
43 | ram_read : IN STD_LOGIC; | |
| 44 | -- ADDR Ctrl |
|
44 | -- ADDR Ctrl | |
| 45 | raddr_rst : IN STD_LOGIC; |
|
45 | raddr_rst : IN STD_LOGIC; | |
| 46 | raddr_add1 : IN STD_LOGIC; |
|
46 | raddr_add1 : IN STD_LOGIC; | |
| 47 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
47 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 48 | -- Data |
|
48 | -- Data | |
| 49 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
49 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
| 50 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) |
|
50 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) | |
| 51 | ); |
|
51 | ); | |
| 52 | END RAM_CTRLR_v2; |
|
52 | END RAM_CTRLR_v2; | |
| 53 |
|
53 | |||
| 54 |
|
54 | |||
| 55 | ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS |
|
55 | ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS | |
| 56 |
|
56 | |||
| 57 | SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
57 | SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
| 58 | SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
58 | SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
| 59 | SIGNAL WEN, REN : STD_LOGIC; |
|
59 | SIGNAL WEN, REN : STD_LOGIC; | |
| 60 | SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
60 | SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 61 | SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
61 | SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 62 | SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
62 | SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 63 |
|
63 | |||
| 64 | BEGIN |
|
64 | BEGIN | |
| 65 |
|
65 | |||
| 66 | sample_out <= RD(Input_SZ_1-1 DOWNTO 0); |
|
66 | sample_out <= RD(Input_SZ_1-1 DOWNTO 0); | |
| 67 | WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; |
|
67 | WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; | |
| 68 | ----------------------------------------------------------------------------- |
|
68 | ----------------------------------------------------------------------------- | |
| 69 | -- RAM |
|
69 | -- RAM | |
| 70 | ----------------------------------------------------------------------------- |
|
70 | ----------------------------------------------------------------------------- | |
| 71 |
|
71 | |||
| 72 | memCEL : IF Mem_use = use_CEL GENERATE |
|
72 | memCEL : IF Mem_use = use_CEL GENERATE | |
| 73 | WEN <= NOT ram_write; |
|
73 | WEN <= NOT ram_write; | |
| 74 | REN <= NOT ram_read; |
|
74 | REN <= NOT ram_read; | |
| 75 | RAMblk : RAM_CEL |
|
75 | RAMblk : RAM_CEL_N | |
| 76 | GENERIC MAP(Input_SZ_1) |
|
76 | GENERIC MAP(Input_SZ_1) | |
| 77 | PORT MAP( |
|
77 | PORT MAP( | |
| 78 | WD => WD, |
|
78 | WD => WD, | |
| 79 | RD => RD, |
|
79 | RD => RD, | |
| 80 | WEN => WEN, |
|
80 | WEN => WEN, | |
| 81 | REN => REN, |
|
81 | REN => REN, | |
| 82 | WADDR => WADDR, |
|
82 | WADDR => WADDR, | |
| 83 | RADDR => RADDR, |
|
83 | RADDR => RADDR, | |
| 84 | RWCLK => clk, |
|
84 | RWCLK => clk, | |
| 85 | RESET => rstn |
|
85 | RESET => rstn | |
| 86 | ) ; |
|
86 | ) ; | |
| 87 | END GENERATE; |
|
87 | END GENERATE; | |
| 88 |
|
88 | |||
| 89 | memRAM : IF Mem_use = use_RAM GENERATE |
|
89 | memRAM : IF Mem_use = use_RAM GENERATE | |
| 90 | SRAM : syncram_2p |
|
90 | SRAM : syncram_2p | |
| 91 | GENERIC MAP(tech, 8, Input_SZ_1) |
|
91 | GENERIC MAP(tech, 8, Input_SZ_1) | |
| 92 | PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); |
|
92 | PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); | |
| 93 | END GENERATE; |
|
93 | END GENERATE; | |
| 94 |
|
94 | |||
| 95 | ----------------------------------------------------------------------------- |
|
95 | ----------------------------------------------------------------------------- | |
| 96 | -- RADDR |
|
96 | -- RADDR | |
| 97 | ----------------------------------------------------------------------------- |
|
97 | ----------------------------------------------------------------------------- | |
| 98 | PROCESS (clk, rstn) |
|
98 | PROCESS (clk, rstn) | |
| 99 | BEGIN -- PROCESS |
|
99 | BEGIN -- PROCESS | |
| 100 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
100 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 101 | counter <= (OTHERS => '0'); |
|
101 | counter <= (OTHERS => '0'); | |
| 102 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
102 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 103 | IF raddr_rst = '1' THEN |
|
103 | IF raddr_rst = '1' THEN | |
| 104 | counter <= (OTHERS => '0'); |
|
104 | counter <= (OTHERS => '0'); | |
| 105 | ELSIF raddr_add1 = '1' THEN |
|
105 | ELSIF raddr_add1 = '1' THEN | |
| 106 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); |
|
106 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); | |
| 107 | END IF; |
|
107 | END IF; | |
| 108 | END IF; |
|
108 | END IF; | |
| 109 | END PROCESS; |
|
109 | END PROCESS; | |
| 110 | RADDR <= counter; |
|
110 | RADDR <= counter; | |
| 111 |
|
111 | |||
| 112 | ----------------------------------------------------------------------------- |
|
112 | ----------------------------------------------------------------------------- | |
| 113 | -- WADDR |
|
113 | -- WADDR | |
| 114 | ----------------------------------------------------------------------------- |
|
114 | ----------------------------------------------------------------------------- | |
| 115 | WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE |
|
115 | WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE | |
| 116 | STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE |
|
116 | STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE | |
| 117 | STD_LOGIC_VECTOR(UNSIGNED(counter)); |
|
117 | STD_LOGIC_VECTOR(UNSIGNED(counter)); | |
| 118 |
|
118 | |||
| 119 |
|
119 | |||
| 120 | END ar_RAM_CTRLR_v2; |
|
120 | END ar_RAM_CTRLR_v2; | |
| @@ -1,290 +1,302 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
| 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
| 21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
| 22 | LIBRARY ieee; |
|
22 | LIBRARY ieee; | |
| 23 | USE ieee.std_logic_1164.ALL; |
|
23 | USE ieee.std_logic_1164.ALL; | |
| 24 | LIBRARY grlib; |
|
24 | LIBRARY grlib; | |
| 25 | USE grlib.amba.ALL; |
|
25 | USE grlib.amba.ALL; | |
| 26 | USE grlib.stdlib.ALL; |
|
26 | USE grlib.stdlib.ALL; | |
| 27 | USE grlib.devices.ALL; |
|
27 | USE grlib.devices.ALL; | |
| 28 | LIBRARY lpp; |
|
28 | LIBRARY lpp; | |
| 29 |
|
29 | |||
| 30 |
|
30 | |||
| 31 |
|
31 | |||
| 32 |
|
32 | |||
| 33 | PACKAGE iir_filter IS |
|
33 | PACKAGE iir_filter IS | |
| 34 |
|
34 | |||
| 35 |
|
35 | |||
| 36 | --===========================================================| |
|
36 | --===========================================================| | |
| 37 | --================A L U C O N T R O L======================| |
|
37 | --================A L U C O N T R O L======================| | |
| 38 | --===========================================================| |
|
38 | --===========================================================| | |
| 39 | CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; |
|
39 | CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; | |
| 40 | CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; |
|
40 | CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; | |
| 41 | CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; |
|
41 | CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; | |
| 42 | CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; |
|
42 | CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; | |
| 43 | CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; |
|
43 | CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; | |
| 44 | CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; |
|
44 | CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; | |
| 45 |
|
45 | |||
| 46 | --____ |
|
46 | --____ | |
| 47 | --RAM | |
|
47 | --RAM | | |
| 48 | --____| |
|
48 | --____| | |
| 49 | CONSTANT use_RAM : INTEGER := 1; |
|
49 | CONSTANT use_RAM : INTEGER := 1; | |
| 50 | CONSTANT use_CEL : INTEGER := 0; |
|
50 | CONSTANT use_CEL : INTEGER := 0; | |
| 51 |
|
51 | |||
| 52 |
|
52 | |||
| 53 | --===========================================================| |
|
53 | --===========================================================| | |
| 54 | --=============C O E F S ====================================| |
|
54 | --=============C O E F S ====================================| | |
| 55 | --===========================================================| |
|
55 | --===========================================================| | |
| 56 | -- create a specific type of data for coefs to avoid errors | |
|
56 | -- create a specific type of data for coefs to avoid errors | | |
| 57 | --===========================================================| |
|
57 | --===========================================================| | |
| 58 |
|
58 | |||
| 59 | TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER; |
|
59 | TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER; | |
| 60 |
|
60 | |||
| 61 | TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
61 | TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; | |
| 62 |
|
62 | |||
| 63 | TYPE in_IIR_CEL_reg IS RECORD |
|
63 | TYPE in_IIR_CEL_reg IS RECORD | |
| 64 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 65 | virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
65 | virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 66 | END RECORD; |
|
66 | END RECORD; | |
| 67 |
|
67 | |||
| 68 | TYPE out_IIR_CEL_reg IS RECORD |
|
68 | TYPE out_IIR_CEL_reg IS RECORD | |
| 69 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
69 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 70 | status : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
70 | status : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 71 | END RECORD; |
|
71 | END RECORD; | |
| 72 |
|
72 | |||
| 73 |
|
73 | |||
| 74 | COMPONENT APB_IIR_CEL IS |
|
74 | COMPONENT APB_IIR_CEL IS | |
| 75 | GENERIC ( |
|
75 | GENERIC ( | |
| 76 | tech : INTEGER := 0; |
|
76 | tech : INTEGER := 0; | |
| 77 | pindex : INTEGER := 0; |
|
77 | pindex : INTEGER := 0; | |
| 78 | paddr : INTEGER := 0; |
|
78 | paddr : INTEGER := 0; | |
| 79 | pmask : INTEGER := 16#fff#; |
|
79 | pmask : INTEGER := 16#fff#; | |
| 80 | pirq : INTEGER := 0; |
|
80 | pirq : INTEGER := 0; | |
| 81 | abits : INTEGER := 8; |
|
81 | abits : INTEGER := 8; | |
| 82 | Sample_SZ : INTEGER := 16; |
|
82 | Sample_SZ : INTEGER := 16; | |
| 83 | ChanelsCount : INTEGER := 6; |
|
83 | ChanelsCount : INTEGER := 6; | |
| 84 | Coef_SZ : INTEGER := 9; |
|
84 | Coef_SZ : INTEGER := 9; | |
| 85 | CoefCntPerCel : INTEGER := 6; |
|
85 | CoefCntPerCel : INTEGER := 6; | |
| 86 | Cels_count : INTEGER := 5; |
|
86 | Cels_count : INTEGER := 5; | |
| 87 | virgPos : INTEGER := 7; |
|
87 | virgPos : INTEGER := 7; | |
| 88 | Mem_use : INTEGER := use_RAM |
|
88 | Mem_use : INTEGER := use_RAM | |
| 89 | ); |
|
89 | ); | |
| 90 | PORT ( |
|
90 | PORT ( | |
| 91 | rst : IN STD_LOGIC; |
|
91 | rst : IN STD_LOGIC; | |
| 92 | clk : IN STD_LOGIC; |
|
92 | clk : IN STD_LOGIC; | |
| 93 | apbi : IN apb_slv_in_type; |
|
93 | apbi : IN apb_slv_in_type; | |
| 94 | apbo : OUT apb_slv_out_type; |
|
94 | apbo : OUT apb_slv_out_type; | |
| 95 | sample_clk : IN STD_LOGIC; |
|
95 | sample_clk : IN STD_LOGIC; | |
| 96 | sample_clk_out : OUT STD_LOGIC; |
|
96 | sample_clk_out : OUT STD_LOGIC; | |
| 97 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
97 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
| 98 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
98 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
| 99 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') |
|
99 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') | |
| 100 | ); |
|
100 | ); | |
| 101 | END COMPONENT; |
|
101 | END COMPONENT; | |
| 102 |
|
102 | |||
| 103 |
|
103 | |||
| 104 | COMPONENT Top_IIR IS |
|
104 | COMPONENT Top_IIR IS | |
| 105 | GENERIC( |
|
105 | GENERIC( | |
| 106 | Sample_SZ : INTEGER := 18; |
|
106 | Sample_SZ : INTEGER := 18; | |
| 107 | ChanelsCount : INTEGER := 1; |
|
107 | ChanelsCount : INTEGER := 1; | |
| 108 | Coef_SZ : INTEGER := 9; |
|
108 | Coef_SZ : INTEGER := 9; | |
| 109 | CoefCntPerCel : INTEGER := 6; |
|
109 | CoefCntPerCel : INTEGER := 6; | |
| 110 | Cels_count : INTEGER := 5); |
|
110 | Cels_count : INTEGER := 5); | |
| 111 | PORT( |
|
111 | PORT( | |
| 112 | reset : IN STD_LOGIC; |
|
112 | reset : IN STD_LOGIC; | |
| 113 | clk : IN STD_LOGIC; |
|
113 | clk : IN STD_LOGIC; | |
| 114 | sample_clk : IN STD_LOGIC; |
|
114 | sample_clk : IN STD_LOGIC; | |
| 115 | -- BP : in std_logic; |
|
115 | -- BP : in std_logic; | |
| 116 | -- BPinput : in std_logic_vector(3 downto 0); |
|
116 | -- BPinput : in std_logic_vector(3 downto 0); | |
| 117 | LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
117 | LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 118 | INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
118 | INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
| 119 | OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0) |
|
119 | OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0) | |
| 120 | ); |
|
120 | ); | |
| 121 | END COMPONENT; |
|
121 | END COMPONENT; | |
| 122 |
|
122 | |||
| 123 | COMPONENT IIR_CEL_CTRLR_v2 |
|
123 | COMPONENT IIR_CEL_CTRLR_v2 | |
| 124 | GENERIC ( |
|
124 | GENERIC ( | |
| 125 | tech : INTEGER; |
|
125 | tech : INTEGER; | |
| 126 | Mem_use : INTEGER; |
|
126 | Mem_use : INTEGER; | |
| 127 | Sample_SZ : INTEGER; |
|
127 | Sample_SZ : INTEGER; | |
| 128 | Coef_SZ : INTEGER; |
|
128 | Coef_SZ : INTEGER; | |
| 129 | Coef_Nb : INTEGER; |
|
129 | Coef_Nb : INTEGER; | |
| 130 | Coef_sel_SZ : INTEGER; |
|
130 | Coef_sel_SZ : INTEGER; | |
| 131 | Cels_count : INTEGER; |
|
131 | Cels_count : INTEGER; | |
| 132 | ChanelsCount : INTEGER); |
|
132 | ChanelsCount : INTEGER); | |
| 133 | PORT ( |
|
133 | PORT ( | |
| 134 | rstn : IN STD_LOGIC; |
|
134 | rstn : IN STD_LOGIC; | |
| 135 | clk : IN STD_LOGIC; |
|
135 | clk : IN STD_LOGIC; | |
| 136 | virg_pos : IN INTEGER; |
|
136 | virg_pos : IN INTEGER; | |
| 137 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); |
|
137 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
| 138 | sample_in_val : IN STD_LOGIC; |
|
138 | sample_in_val : IN STD_LOGIC; | |
| 139 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
139 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
| 140 | sample_out_val : OUT STD_LOGIC; |
|
140 | sample_out_val : OUT STD_LOGIC; | |
| 141 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); |
|
141 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); | |
| 142 | END COMPONENT; |
|
142 | END COMPONENT; | |
| 143 |
|
143 | |||
| 144 |
|
144 | |||
| 145 | --component FilterCTRLR is |
|
145 | --component FilterCTRLR is | |
| 146 | --port( |
|
146 | --port( | |
| 147 | -- reset : in std_logic; |
|
147 | -- reset : in std_logic; | |
| 148 | -- clk : in std_logic; |
|
148 | -- clk : in std_logic; | |
| 149 | -- sample_clk : in std_logic; |
|
149 | -- sample_clk : in std_logic; | |
| 150 | -- ALU_Ctrl : out std_logic_vector(3 downto 0); |
|
150 | -- ALU_Ctrl : out std_logic_vector(3 downto 0); | |
| 151 | -- sample_in : in samplT; |
|
151 | -- sample_in : in samplT; | |
| 152 | -- coef : out std_logic_vector(Coef_SZ-1 downto 0); |
|
152 | -- coef : out std_logic_vector(Coef_SZ-1 downto 0); | |
| 153 | -- sample : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
153 | -- sample : out std_logic_vector(Smpl_SZ-1 downto 0) | |
| 154 | --); |
|
154 | --); | |
| 155 | --end component; |
|
155 | --end component; | |
| 156 |
|
156 | |||
| 157 |
|
157 | |||
| 158 | --component FILTER_RAM_CTRLR is |
|
158 | --component FILTER_RAM_CTRLR is | |
| 159 | --port( |
|
159 | --port( | |
| 160 | -- reset : in std_logic; |
|
160 | -- reset : in std_logic; | |
| 161 | -- clk : in std_logic; |
|
161 | -- clk : in std_logic; | |
| 162 | -- run : in std_logic; |
|
162 | -- run : in std_logic; | |
| 163 | -- GO_0 : in std_logic; |
|
163 | -- GO_0 : in std_logic; | |
| 164 | -- B_A : in std_logic; |
|
164 | -- B_A : in std_logic; | |
| 165 | -- writeForce : in std_logic; |
|
165 | -- writeForce : in std_logic; | |
| 166 | -- next_blk : in std_logic; |
|
166 | -- next_blk : in std_logic; | |
| 167 | -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); |
|
167 | -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); | |
| 168 | -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
168 | -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) | |
| 169 | --); |
|
169 | --); | |
| 170 | --end component; |
|
170 | --end component; | |
| 171 |
|
171 | |||
| 172 |
|
172 | |||
| 173 | COMPONENT IIR_CEL_CTRLR IS |
|
173 | COMPONENT IIR_CEL_CTRLR IS | |
| 174 | GENERIC( |
|
174 | GENERIC( | |
| 175 | tech : INTEGER := 0; |
|
175 | tech : INTEGER := 0; | |
| 176 | Sample_SZ : INTEGER := 16; |
|
176 | Sample_SZ : INTEGER := 16; | |
| 177 | ChanelsCount : INTEGER := 1; |
|
177 | ChanelsCount : INTEGER := 1; | |
| 178 | Coef_SZ : INTEGER := 9; |
|
178 | Coef_SZ : INTEGER := 9; | |
| 179 | CoefCntPerCel : INTEGER := 3; |
|
179 | CoefCntPerCel : INTEGER := 3; | |
| 180 | Cels_count : INTEGER := 5; |
|
180 | Cels_count : INTEGER := 5; | |
| 181 | Mem_use : INTEGER := use_RAM |
|
181 | Mem_use : INTEGER := use_RAM | |
| 182 | ); |
|
182 | ); | |
| 183 | PORT( |
|
183 | PORT( | |
| 184 | reset : IN STD_LOGIC; |
|
184 | reset : IN STD_LOGIC; | |
| 185 | clk : IN STD_LOGIC; |
|
185 | clk : IN STD_LOGIC; | |
| 186 | sample_clk : IN STD_LOGIC; |
|
186 | sample_clk : IN STD_LOGIC; | |
| 187 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
187 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
| 188 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
188 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
| 189 | virg_pos : IN INTEGER; |
|
189 | virg_pos : IN INTEGER; | |
| 190 | GOtest : OUT STD_LOGIC; |
|
190 | GOtest : OUT STD_LOGIC; | |
| 191 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) |
|
191 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) | |
| 192 | ); |
|
192 | ); | |
| 193 | END COMPONENT; |
|
193 | END COMPONENT; | |
| 194 |
|
194 | |||
| 195 |
|
195 | |||
| 196 | COMPONENT RAM IS |
|
196 | COMPONENT RAM IS | |
| 197 | GENERIC( |
|
197 | GENERIC( | |
| 198 | Input_SZ_1 : INTEGER := 8 |
|
198 | Input_SZ_1 : INTEGER := 8 | |
| 199 | ); |
|
199 | ); | |
| 200 | PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT |
|
200 | PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT | |
| 201 | STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC; |
|
201 | STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC; | |
| 202 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN |
|
202 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN | |
| 203 | STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC |
|
203 | STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC | |
| 204 | ) ; |
|
204 | ) ; | |
| 205 | END COMPONENT; |
|
205 | END COMPONENT; | |
| 206 |
|
206 | |||
| 207 | COMPONENT RAM_CEL |
|
207 | COMPONENT RAM_CEL | |
| 208 | GENERIC ( |
|
208 | GENERIC ( | |
| 209 | Sample_SZ : INTEGER); |
|
209 | Sample_SZ : INTEGER); | |
| 210 | PORT ( |
|
210 | PORT ( | |
| 211 | WD : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
211 | WD : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
| 212 | RD : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
212 | RD : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
| 213 | WEN, REN : IN STD_LOGIC; |
|
213 | WEN, REN : IN STD_LOGIC; | |
| 214 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
214 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 215 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
215 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 216 | RWCLK, RESET : IN STD_LOGIC); |
|
216 | RWCLK, RESET : IN STD_LOGIC); | |
| 217 | END COMPONENT; |
|
217 | END COMPONENT; | |
| 218 |
|
218 | |||
|
|
219 | COMPONENT RAM_CEL_N | |||
|
|
220 | GENERIC ( | |||
|
|
221 | size : INTEGER); | |||
|
|
222 | PORT ( | |||
|
|
223 | WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |||
|
|
224 | RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |||
|
|
225 | WEN, REN : IN STD_LOGIC; | |||
|
|
226 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
227 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
228 | RWCLK, RESET : IN STD_LOGIC); | |||
|
|
229 | END COMPONENT; | |||
|
|
230 | ||||
| 219 | COMPONENT IIR_CEL_FILTER IS |
|
231 | COMPONENT IIR_CEL_FILTER IS | |
| 220 | GENERIC( |
|
232 | GENERIC( | |
| 221 | tech : INTEGER := 0; |
|
233 | tech : INTEGER := 0; | |
| 222 | Sample_SZ : INTEGER := 16; |
|
234 | Sample_SZ : INTEGER := 16; | |
| 223 | ChanelsCount : INTEGER := 1; |
|
235 | ChanelsCount : INTEGER := 1; | |
| 224 | Coef_SZ : INTEGER := 9; |
|
236 | Coef_SZ : INTEGER := 9; | |
| 225 | CoefCntPerCel : INTEGER := 3; |
|
237 | CoefCntPerCel : INTEGER := 3; | |
| 226 | Cels_count : INTEGER := 5; |
|
238 | Cels_count : INTEGER := 5; | |
| 227 | Mem_use : INTEGER := use_RAM); |
|
239 | Mem_use : INTEGER := use_RAM); | |
| 228 | PORT( |
|
240 | PORT( | |
| 229 | reset : IN STD_LOGIC; |
|
241 | reset : IN STD_LOGIC; | |
| 230 | clk : IN STD_LOGIC; |
|
242 | clk : IN STD_LOGIC; | |
| 231 | sample_clk : IN STD_LOGIC; |
|
243 | sample_clk : IN STD_LOGIC; | |
| 232 | regs_in : IN in_IIR_CEL_reg; |
|
244 | regs_in : IN in_IIR_CEL_reg; | |
| 233 | regs_out : IN out_IIR_CEL_reg; |
|
245 | regs_out : IN out_IIR_CEL_reg; | |
| 234 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
246 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
| 235 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
247 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
| 236 | GOtest : OUT STD_LOGIC; |
|
248 | GOtest : OUT STD_LOGIC; | |
| 237 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) |
|
249 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) | |
| 238 |
|
250 | |||
| 239 | ); |
|
251 | ); | |
| 240 | END COMPONENT; |
|
252 | END COMPONENT; | |
| 241 |
|
253 | |||
| 242 |
|
254 | |||
| 243 | COMPONENT RAM_CTRLR2 IS |
|
255 | COMPONENT RAM_CTRLR2 IS | |
| 244 | GENERIC( |
|
256 | GENERIC( | |
| 245 | tech : INTEGER := 0; |
|
257 | tech : INTEGER := 0; | |
| 246 | Input_SZ_1 : INTEGER := 16; |
|
258 | Input_SZ_1 : INTEGER := 16; | |
| 247 | Mem_use : INTEGER := use_RAM |
|
259 | Mem_use : INTEGER := use_RAM | |
| 248 | ); |
|
260 | ); | |
| 249 | PORT( |
|
261 | PORT( | |
| 250 | reset : IN STD_LOGIC; |
|
262 | reset : IN STD_LOGIC; | |
| 251 | clk : IN STD_LOGIC; |
|
263 | clk : IN STD_LOGIC; | |
| 252 | WD_sel : IN STD_LOGIC; |
|
264 | WD_sel : IN STD_LOGIC; | |
| 253 | Read : IN STD_LOGIC; |
|
265 | Read : IN STD_LOGIC; | |
| 254 | WADDR_sel : IN STD_LOGIC; |
|
266 | WADDR_sel : IN STD_LOGIC; | |
| 255 | count : IN STD_LOGIC; |
|
267 | count : IN STD_LOGIC; | |
| 256 | SVG_ADDR : IN STD_LOGIC; |
|
268 | SVG_ADDR : IN STD_LOGIC; | |
| 257 | Write : IN STD_LOGIC; |
|
269 | Write : IN STD_LOGIC; | |
| 258 | GO_0 : IN STD_LOGIC; |
|
270 | GO_0 : IN STD_LOGIC; | |
| 259 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
271 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
| 260 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) |
|
272 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) | |
| 261 | ); |
|
273 | ); | |
| 262 | END COMPONENT; |
|
274 | END COMPONENT; | |
| 263 |
|
275 | |||
| 264 | COMPONENT APB_IIR_Filter IS |
|
276 | COMPONENT APB_IIR_Filter IS | |
| 265 | GENERIC ( |
|
277 | GENERIC ( | |
| 266 | tech : INTEGER := 0; |
|
278 | tech : INTEGER := 0; | |
| 267 | pindex : INTEGER := 0; |
|
279 | pindex : INTEGER := 0; | |
| 268 | paddr : INTEGER := 0; |
|
280 | paddr : INTEGER := 0; | |
| 269 | pmask : INTEGER := 16#fff#; |
|
281 | pmask : INTEGER := 16#fff#; | |
| 270 | pirq : INTEGER := 0; |
|
282 | pirq : INTEGER := 0; | |
| 271 | abits : INTEGER := 8; |
|
283 | abits : INTEGER := 8; | |
| 272 | Sample_SZ : INTEGER := 16; |
|
284 | Sample_SZ : INTEGER := 16; | |
| 273 | ChanelsCount : INTEGER := 1; |
|
285 | ChanelsCount : INTEGER := 1; | |
| 274 | Coef_SZ : INTEGER := 9; |
|
286 | Coef_SZ : INTEGER := 9; | |
| 275 | CoefCntPerCel : INTEGER := 6; |
|
287 | CoefCntPerCel : INTEGER := 6; | |
| 276 | Cels_count : INTEGER := 5; |
|
288 | Cels_count : INTEGER := 5; | |
| 277 | virgPos : INTEGER := 3; |
|
289 | virgPos : INTEGER := 3; | |
| 278 | Mem_use : INTEGER := use_RAM |
|
290 | Mem_use : INTEGER := use_RAM | |
| 279 | ); |
|
291 | ); | |
| 280 | PORT ( |
|
292 | PORT ( | |
| 281 | rst : IN STD_LOGIC; |
|
293 | rst : IN STD_LOGIC; | |
| 282 | clk : IN STD_LOGIC; |
|
294 | clk : IN STD_LOGIC; | |
| 283 | apbi : IN apb_slv_in_type; |
|
295 | apbi : IN apb_slv_in_type; | |
| 284 | apbo : OUT apb_slv_out_type; |
|
296 | apbo : OUT apb_slv_out_type; | |
| 285 | sample_clk_out : OUT STD_LOGIC; |
|
297 | sample_clk_out : OUT STD_LOGIC; | |
| 286 | GOtest : OUT STD_LOGIC; |
|
298 | GOtest : OUT STD_LOGIC; | |
| 287 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') |
|
299 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') | |
| 288 | ); |
|
300 | ); | |
| 289 | END COMPONENT; |
|
301 | END COMPONENT; | |
| 290 | END; |
|
302 | END; | |
| @@ -1,63 +1,65 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
| 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
| 21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
| 22 | library IEEE; |
|
22 | library IEEE; | |
| 23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
| 24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
| 25 | library lpp; |
|
25 | library lpp; | |
| 26 | use lpp.general_purpose.all; |
|
26 | use lpp.general_purpose.all; | |
| 27 |
|
27 | |||
| 28 | --! Une ALU : Arithmetic and logical unit, permettant de rοΏ½aliser une ou plusieurs opοΏ½ration |
|
28 | --! Une ALU : Arithmetic and logical unit, permettant de rοΏ½aliser une ou plusieurs opοΏ½ration | |
| 29 |
|
29 | |||
| 30 | entity ALU is |
|
30 | entity ALU is | |
| 31 | generic( |
|
31 | generic( | |
| 32 | Arith_en : integer := 1; |
|
32 | Arith_en : integer := 1; | |
| 33 | Logic_en : integer := 1; |
|
33 | Logic_en : integer := 1; | |
| 34 | Input_SZ_1 : integer := 16; |
|
34 | Input_SZ_1 : integer := 16; | |
| 35 |
Input_SZ_2 : integer := 16 |
|
35 | Input_SZ_2 : integer := 16; | |
|
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
|
|
37 | ); | |||
| 36 | port( |
|
38 | port( | |
| 37 | clk : in std_logic; --! Horloge du composant |
|
39 | clk : in std_logic; --! Horloge du composant | |
| 38 | reset : in std_logic; --! Reset general du composant |
|
40 | reset : in std_logic; --! Reset general du composant | |
| 39 | ctrl : in std_logic_vector(2 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e |
|
41 | ctrl : in std_logic_vector(2 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e | |
| 40 | comp : in std_logic_vector(1 downto 0); --! (set) Permet de complοΏ½menter les opοΏ½randes |
|
42 | comp : in std_logic_vector(1 downto 0); --! (set) Permet de complοΏ½menter les opοΏ½randes | |
| 41 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande |
|
43 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande | |
| 42 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second OpοΏ½rande |
|
44 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second OpοΏ½rande | |
| 43 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! RοΏ½sultat de l'opοΏ½ration |
|
45 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! RοΏ½sultat de l'opοΏ½ration | |
| 44 | ); |
|
46 | ); | |
| 45 | end ALU; |
|
47 | end ALU; | |
| 46 |
|
48 | |||
| 47 | --! @details SοΏ½lection grace a l'entrοΏ½e "ctrl" : |
|
49 | --! @details SοΏ½lection grace a l'entrοΏ½e "ctrl" : | |
| 48 | --! Pause : IDLE = 000 |
|
50 | --! Pause : IDLE = 000 | |
| 49 | --! Multiplieur/Accumulateur : MAC = 001 |
|
51 | --! Multiplieur/Accumulateur : MAC = 001 | |
| 50 | --! Multiplication : MULT = 010 |
|
52 | --! Multiplication : MULT = 010 | |
| 51 | --! Addition : ADD = 011 |
|
53 | --! Addition : ADD = 011 | |
| 52 | --! Reset du MAC : CLRMAC = 100 |
|
54 | --! Reset du MAC : CLRMAC = 100 | |
| 53 | architecture ar_ALU of ALU is |
|
55 | architecture ar_ALU of ALU is | |
| 54 |
|
56 | |||
| 55 | begin |
|
57 | begin | |
| 56 |
|
58 | |||
| 57 | arith : if Arith_en = 1 generate |
|
59 | arith : if Arith_en = 1 generate | |
| 58 | MACinst : MAC |
|
60 | MACinst : MAC | |
| 59 | generic map(Input_SZ_1,Input_SZ_2) |
|
61 | generic map(Input_SZ_1,Input_SZ_2,COMP_EN) | |
| 60 | port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); |
|
62 | port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); | |
| 61 | end generate; |
|
63 | end generate; | |
| 62 |
|
64 | |||
| 63 | end architecture; No newline at end of file |
|
65 | end architecture; | |
| @@ -1,294 +1,301 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
| 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
| 21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
| 22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
| 23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
| 24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
| 25 | LIBRARY lpp; |
|
25 | LIBRARY lpp; | |
| 26 | USE lpp.general_purpose.ALL; |
|
26 | USE lpp.general_purpose.ALL; | |
| 27 | --TODO |
|
27 | --TODO | |
| 28 | --terminer le testbensh puis changer le resize dans les instanciations |
|
28 | --terminer le testbensh puis changer le resize dans les instanciations | |
| 29 | --par un resize sur un vecteur en combi |
|
29 | --par un resize sur un vecteur en combi | |
| 30 |
|
30 | |||
| 31 |
|
31 | |||
| 32 | ENTITY MAC IS |
|
32 | ENTITY MAC IS | |
| 33 | GENERIC( |
|
33 | GENERIC( | |
| 34 | Input_SZ_A : INTEGER := 8; |
|
34 | Input_SZ_A : INTEGER := 8; | |
| 35 | Input_SZ_B : INTEGER := 8 |
|
35 | Input_SZ_B : INTEGER := 8; | |
|
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
| 36 |
|
37 | |||
| 37 | ); |
|
38 | ); | |
| 38 | PORT( |
|
39 | PORT( | |
| 39 | clk : IN STD_LOGIC; |
|
40 | clk : IN STD_LOGIC; | |
| 40 | reset : IN STD_LOGIC; |
|
41 | reset : IN STD_LOGIC; | |
| 41 | clr_MAC : IN STD_LOGIC; |
|
42 | clr_MAC : IN STD_LOGIC; | |
| 42 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
43 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 43 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
44 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 44 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
45 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 45 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
46 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 46 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
47 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
| 47 | ); |
|
48 | ); | |
| 48 | END MAC; |
|
49 | END MAC; | |
| 49 |
|
50 | |||
| 50 |
|
51 | |||
| 51 |
|
52 | |||
| 52 |
|
53 | |||
| 53 | ARCHITECTURE ar_MAC OF MAC IS |
|
54 | ARCHITECTURE ar_MAC OF MAC IS | |
| 54 |
|
55 | |||
| 55 | signal add,mult : std_logic; |
|
56 | SIGNAL add, mult : STD_LOGIC; | |
| 56 |
|
|
57 | SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 57 |
|
58 | |||
| 58 |
|
|
59 | SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 59 |
|
|
60 | SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 60 |
|
|
61 | SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 61 |
|
62 | |||
| 62 | signal MACMUXsel : std_logic; |
|
63 | SIGNAL MACMUXsel : STD_LOGIC; | |
| 63 |
|
|
64 | SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 64 |
|
|
65 | SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 65 |
|
66 | |||
| 66 | signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0); |
|
67 | SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 67 | signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0); |
|
68 | SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 68 |
|
69 | |||
| 69 | signal MACMUX2sel : std_logic; |
|
70 | SIGNAL MACMUX2sel : STD_LOGIC; | |
| 70 |
|
71 | |||
| 71 | signal add_D : std_logic; |
|
72 | SIGNAL add_D : STD_LOGIC; | |
| 72 | signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0); |
|
73 | SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 73 | signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0); |
|
74 | SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 74 |
|
|
75 | SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 75 | signal MACMUXsel_D : std_logic; |
|
76 | SIGNAL MACMUXsel_D : STD_LOGIC; | |
| 76 | signal MACMUX2sel_D : std_logic; |
|
77 | SIGNAL MACMUX2sel_D : STD_LOGIC; | |
| 77 | signal MACMUX2sel_D_D : std_logic; |
|
78 | SIGNAL MACMUX2sel_D_D : STD_LOGIC; | |
| 78 | signal clr_MAC_D : std_logic; |
|
79 | SIGNAL clr_MAC_D : STD_LOGIC; | |
| 79 | signal clr_MAC_D_D : std_logic; |
|
80 | SIGNAL clr_MAC_D_D : STD_LOGIC; | |
| 80 | signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0); |
|
81 | SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 81 |
|
82 | |||
| 82 | SIGNAL load_mult_result : STD_LOGIC; |
|
83 | SIGNAL load_mult_result : STD_LOGIC; | |
| 83 | SIGNAL load_mult_result_D : STD_LOGIC; |
|
84 | SIGNAL load_mult_result_D : STD_LOGIC; | |
| 84 |
|
85 | |||
| 85 | BEGIN |
|
86 | BEGIN | |
| 86 |
|
87 | |||
| 87 |
|
88 | |||
| 88 |
|
89 | |||
| 89 |
|
90 | |||
| 90 | --============================================================== |
|
91 | --============================================================== | |
| 91 | --=============M A C C O N T R O L E R========================= |
|
92 | --=============M A C C O N T R O L E R========================= | |
| 92 | --============================================================== |
|
93 | --============================================================== | |
| 93 | MAC_CONTROLER1 : MAC_CONTROLER |
|
94 | MAC_CONTROLER1 : MAC_CONTROLER | |
| 94 | PORT MAP( |
|
95 | PORT MAP( | |
| 95 | ctrl => MAC_MUL_ADD, |
|
96 | ctrl => MAC_MUL_ADD, | |
| 96 | MULT => mult, |
|
97 | MULT => mult, | |
| 97 | ADD => add, |
|
98 | ADD => add, | |
| 98 | LOAD_ADDER => load_mult_result, |
|
99 | LOAD_ADDER => load_mult_result, | |
| 99 | MACMUX_sel => MACMUXsel, |
|
100 | MACMUX_sel => MACMUXsel, | |
| 100 | MACMUX2_sel => MACMUX2sel |
|
101 | MACMUX2_sel => MACMUX2sel | |
| 101 |
|
102 | |||
| 102 | ); |
|
103 | ); | |
| 103 | --============================================================== |
|
104 | --============================================================== | |
| 104 |
|
105 | |||
| 105 |
|
106 | |||
| 106 |
|
107 | |||
| 107 |
|
108 | |||
| 108 | --============================================================== |
|
109 | --============================================================== | |
| 109 | --=============M U L T I P L I E R============================== |
|
110 | --=============M U L T I P L I E R============================== | |
| 110 | --============================================================== |
|
111 | --============================================================== | |
| 111 | Multiplieri_nst : Multiplier |
|
112 | Multiplieri_nst : Multiplier | |
| 112 | GENERIC MAP( |
|
113 | GENERIC MAP( | |
| 113 | Input_SZ_A => Input_SZ_A, |
|
114 | Input_SZ_A => Input_SZ_A, | |
| 114 | Input_SZ_B => Input_SZ_B |
|
115 | Input_SZ_B => Input_SZ_B | |
| 115 | ) |
|
116 | ) | |
| 116 | port map( |
|
117 | PORT MAP( | |
| 117 |
clk |
|
118 | clk => clk, | |
| 118 |
reset |
|
119 | reset => reset, | |
| 119 |
mult |
|
120 | mult => mult, | |
| 120 |
OP1 |
|
121 | OP1 => OP1_2C, | |
| 121 |
OP2 |
|
122 | OP2 => OP2_2C, | |
| 122 |
RES |
|
123 | RES => MULTout | |
| 123 | ); |
|
124 | ); | |
| 124 | --============================================================== |
|
125 | --============================================================== | |
| 125 |
|
126 | |||
| 126 | PROCESS (clk, reset) |
|
127 | PROCESS (clk, reset) | |
| 127 | BEGIN -- PROCESS |
|
128 | BEGIN -- PROCESS | |
| 128 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
129 | IF reset = '0' THEN -- asynchronous reset (active low) | |
| 129 | load_mult_result_D <= '0'; |
|
130 | load_mult_result_D <= '0'; | |
| 130 |
ELSIF clk' |
|
131 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 131 | load_mult_result_D <= load_mult_result; |
|
132 | load_mult_result_D <= load_mult_result; | |
| 132 | END IF; |
|
133 | END IF; | |
| 133 | END PROCESS; |
|
134 | END PROCESS; | |
| 134 |
|
135 | |||
| 135 | --============================================================== |
|
136 | --============================================================== | |
| 136 | --======================A D D E R ============================== |
|
137 | --======================A D D E R ============================== | |
| 137 | --============================================================== |
|
138 | --============================================================== | |
| 138 | adder_inst : Adder |
|
139 | adder_inst : Adder | |
| 139 | GENERIC MAP( |
|
140 | GENERIC MAP( | |
| 140 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
141 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
| 141 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
142 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
| 142 | ) |
|
143 | ) | |
| 143 | PORT MAP( |
|
144 | PORT MAP( | |
| 144 | clk => clk, |
|
145 | clk => clk, | |
| 145 | reset => reset, |
|
146 | reset => reset, | |
| 146 | clr => clr_MAC_D, |
|
147 | clr => clr_MAC_D, | |
| 147 | load => load_mult_result_D, |
|
148 | load => load_mult_result_D, | |
| 148 | add => add_D, |
|
149 | add => add_D, | |
| 149 | OP1 => ADDERinA, |
|
150 | OP1 => ADDERinA, | |
| 150 | OP2 => ADDERinB, |
|
151 | OP2 => ADDERinB, | |
| 151 | RES => ADDERout |
|
152 | RES => ADDERout | |
| 152 | ); |
|
153 | ); | |
| 153 |
|
154 | |||
| 154 | --============================================================== |
|
155 | --============================================================== | |
| 155 | --===================TWO COMPLEMENTERS========================== |
|
156 | --===================TWO COMPLEMENTERS========================== | |
| 156 | --============================================================== |
|
157 | --============================================================== | |
| 157 | TWO_COMPLEMENTER1 : TwoComplementer |
|
158 | gen_comp : IF COMP_EN = 0 GENERATE | |
| 158 | generic map( |
|
159 | TWO_COMPLEMENTER1 : TwoComplementer | |
| 159 | Input_SZ => Input_SZ_A |
|
160 | GENERIC MAP( | |
| 160 | ) |
|
161 | Input_SZ => Input_SZ_A | |
| 161 | port map( |
|
162 | ) | |
| 162 | clk => clk, |
|
163 | PORT MAP( | |
| 163 |
|
|
164 | clk => clk, | |
| 164 | clr => clr_MAC, |
|
165 | reset => reset, | |
| 165 | TwoComp => Comp_2C(0), |
|
166 | clr => clr_MAC, | |
| 166 | OP => OP1, |
|
167 | TwoComp => Comp_2C(0), | |
| 167 |
|
|
168 | OP => OP1, | |
| 168 | ); |
|
169 | RES => OP1_2C | |
|
|
170 | ); | |||
| 169 |
|
171 | |||
| 170 |
|
172 | TWO_COMPLEMENTER2 : TwoComplementer | ||
| 171 | TWO_COMPLEMENTER2 : TwoComplementer |
|
173 | GENERIC MAP( | |
| 172 | generic map( |
|
174 | Input_SZ => Input_SZ_B | |
| 173 | Input_SZ => Input_SZ_B |
|
175 | ) | |
| 174 | ) |
|
176 | PORT MAP( | |
| 175 | port map( |
|
177 | clk => clk, | |
| 176 | clk => clk, |
|
178 | reset => reset, | |
| 177 |
|
|
179 | clr => clr_MAC, | |
| 178 | clr => clr_MAC, |
|
180 | TwoComp => Comp_2C(1), | |
| 179 | TwoComp => Comp_2C(1), |
|
181 | OP => OP2, | |
| 180 |
|
|
182 | RES => OP2_2C | |
| 181 | RES => OP2_2C |
|
183 | ); | |
| 182 | ); |
|
184 | END GENERATE gen_comp; | |
|
|
185 | ||||
|
|
186 | no_gen_comp : IF COMP_EN = 1 GENERATE | |||
|
|
187 | OP2_2C <= OP2; | |||
|
|
188 | OP1_2C <= OP1; | |||
|
|
189 | END GENERATE no_gen_comp; | |||
| 183 | --============================================================== |
|
190 | --============================================================== | |
| 184 |
|
191 | |||
| 185 | clr_MACREG1 : MAC_REG |
|
192 | clr_MACREG1 : MAC_REG | |
| 186 | GENERIC MAP(size => 1) |
|
193 | GENERIC MAP(size => 1) | |
| 187 | PORT MAP( |
|
194 | PORT MAP( | |
| 188 | reset => reset, |
|
195 | reset => reset, | |
| 189 | clk => clk, |
|
196 | clk => clk, | |
| 190 | D(0) => clr_MAC, |
|
197 | D(0) => clr_MAC, | |
| 191 | Q(0) => clr_MAC_D |
|
198 | Q(0) => clr_MAC_D | |
| 192 | ); |
|
199 | ); | |
| 193 |
|
200 | |||
| 194 | addREG : MAC_REG |
|
201 | addREG : MAC_REG | |
| 195 | GENERIC MAP(size => 1) |
|
202 | GENERIC MAP(size => 1) | |
| 196 | PORT MAP( |
|
203 | PORT MAP( | |
| 197 | reset => reset, |
|
204 | reset => reset, | |
| 198 | clk => clk, |
|
205 | clk => clk, | |
| 199 | D(0) => add, |
|
206 | D(0) => add, | |
| 200 | Q(0) => add_D |
|
207 | Q(0) => add_D | |
| 201 | ); |
|
208 | ); | |
| 202 |
|
209 | |||
| 203 | OP1REG : MAC_REG |
|
210 | OP1REG : MAC_REG | |
| 204 |
|
|
211 | GENERIC MAP(size => Input_SZ_A) | |
| 205 | port map( |
|
212 | PORT MAP( | |
| 206 |
reset |
|
213 | reset => reset, | |
| 207 |
clk |
|
214 | clk => clk, | |
| 208 |
D |
|
215 | D => OP1_2C, | |
| 209 |
Q |
|
216 | Q => OP1_2C_D | |
| 210 | ); |
|
217 | ); | |
| 211 |
|
218 | |||
| 212 |
|
219 | |||
| 213 | OP2REG : MAC_REG |
|
220 | OP2REG : MAC_REG | |
| 214 |
|
|
221 | GENERIC MAP(size => Input_SZ_B) | |
| 215 | port map( |
|
222 | PORT MAP( | |
| 216 |
reset |
|
223 | reset => reset, | |
| 217 |
clk |
|
224 | clk => clk, | |
| 218 |
D |
|
225 | D => OP2_2C, | |
| 219 |
Q |
|
226 | Q => OP2_2C_D | |
| 220 | ); |
|
227 | ); | |
| 221 |
|
228 | |||
| 222 | MULToutREG : MAC_REG |
|
229 | MULToutREG : MAC_REG | |
| 223 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) |
|
230 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) | |
| 224 | PORT MAP( |
|
231 | PORT MAP( | |
| 225 | reset => reset, |
|
232 | reset => reset, | |
| 226 | clk => clk, |
|
233 | clk => clk, | |
| 227 | D => MULTout, |
|
234 | D => MULTout, | |
| 228 | Q => MULTout_D |
|
235 | Q => MULTout_D | |
| 229 | ); |
|
236 | ); | |
| 230 |
|
237 | |||
| 231 | MACMUXselREG : MAC_REG |
|
238 | MACMUXselREG : MAC_REG | |
| 232 | GENERIC MAP(size => 1) |
|
239 | GENERIC MAP(size => 1) | |
| 233 | PORT MAP( |
|
240 | PORT MAP( | |
| 234 | reset => reset, |
|
241 | reset => reset, | |
| 235 | clk => clk, |
|
242 | clk => clk, | |
| 236 | D(0) => MACMUXsel, |
|
243 | D(0) => MACMUXsel, | |
| 237 | Q(0) => MACMUXsel_D |
|
244 | Q(0) => MACMUXsel_D | |
| 238 | ); |
|
245 | ); | |
| 239 |
|
246 | |||
| 240 | MACMUX2selREG : MAC_REG |
|
247 | MACMUX2selREG : MAC_REG | |
| 241 | GENERIC MAP(size => 1) |
|
248 | GENERIC MAP(size => 1) | |
| 242 | PORT MAP( |
|
249 | PORT MAP( | |
| 243 | reset => reset, |
|
250 | reset => reset, | |
| 244 | clk => clk, |
|
251 | clk => clk, | |
| 245 | D(0) => MACMUX2sel, |
|
252 | D(0) => MACMUX2sel, | |
| 246 | Q(0) => MACMUX2sel_D |
|
253 | Q(0) => MACMUX2sel_D | |
| 247 | ); |
|
254 | ); | |
| 248 |
|
255 | |||
| 249 | MACMUX2selREG2 : MAC_REG |
|
256 | MACMUX2selREG2 : MAC_REG | |
| 250 | GENERIC MAP(size => 1) |
|
257 | GENERIC MAP(size => 1) | |
| 251 | PORT MAP( |
|
258 | PORT MAP( | |
| 252 | reset => reset, |
|
259 | reset => reset, | |
| 253 | clk => clk, |
|
260 | clk => clk, | |
| 254 | D(0) => MACMUX2sel_D, |
|
261 | D(0) => MACMUX2sel_D, | |
| 255 | Q(0) => MACMUX2sel_D_D |
|
262 | Q(0) => MACMUX2sel_D_D | |
| 256 | ); |
|
263 | ); | |
| 257 |
|
264 | |||
| 258 | --============================================================== |
|
265 | --============================================================== | |
| 259 | --======================M A C M U X =========================== |
|
266 | --======================M A C M U X =========================== | |
| 260 | --============================================================== |
|
267 | --============================================================== | |
| 261 | MACMUX_inst : MAC_MUX |
|
268 | MACMUX_inst : MAC_MUX | |
| 262 | GENERIC MAP( |
|
269 | GENERIC MAP( | |
| 263 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
270 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
| 264 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
271 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
| 265 |
|
272 | |||
| 266 | ) |
|
273 | ) | |
| 267 | PORT MAP( |
|
274 | PORT MAP( | |
| 268 | sel => MACMUXsel_D, |
|
275 | sel => MACMUXsel_D, | |
| 269 | INA1 => ADDERout, |
|
276 | INA1 => ADDERout, | |
| 270 | INA2 => OP2_2C_D_Resz, |
|
277 | INA2 => OP2_2C_D_Resz, | |
| 271 | INB1 => MULTout, |
|
278 | INB1 => MULTout, | |
| 272 | INB2 => OP1_2C_D_Resz, |
|
279 | INB2 => OP1_2C_D_Resz, | |
| 273 | OUTA => ADDERinA, |
|
280 | OUTA => ADDERinA, | |
| 274 | OUTB => ADDERinB |
|
281 | OUTB => ADDERinB | |
| 275 | ); |
|
282 | ); | |
| 276 | OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); |
|
283 | OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); | |
| 277 | OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); |
|
284 | OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); | |
| 278 | --============================================================== |
|
285 | --============================================================== | |
| 279 |
|
286 | |||
| 280 |
|
287 | |||
| 281 | --============================================================== |
|
288 | --============================================================== | |
| 282 | --======================M A C M U X2 ========================== |
|
289 | --======================M A C M U X2 ========================== | |
| 283 | --============================================================== |
|
290 | --============================================================== | |
| 284 | MAC_MUX2_inst : MAC_MUX2 |
|
291 | MAC_MUX2_inst : MAC_MUX2 | |
| 285 | GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) |
|
292 | GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) | |
| 286 | PORT MAP( |
|
293 | PORT MAP( | |
| 287 | sel => MACMUX2sel_D_D, |
|
294 | sel => MACMUX2sel_D_D, | |
| 288 | RES2 => MULTout_D, |
|
295 | RES2 => MULTout_D, | |
| 289 | RES1 => ADDERout, |
|
296 | RES1 => ADDERout, | |
| 290 | RES => RES |
|
297 | RES => RES | |
| 291 | ); |
|
298 | ); | |
| 292 | --============================================================== |
|
299 | --============================================================== | |
| 293 |
|
300 | |||
| 294 | END ar_MAC; |
|
301 | END ar_MAC; | |
| @@ -1,270 +1,272 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
| 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
| 21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
| 22 | --UPDATE |
|
22 | --UPDATE | |
| 23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
| 24 | -- 14-03-2013 - Jean-christophe Pellion |
|
24 | -- 14-03-2013 - Jean-christophe Pellion | |
| 25 | -- ADD MUXN (a parametric multiplexor (N stage of MUX2)) |
|
25 | -- ADD MUXN (a parametric multiplexor (N stage of MUX2)) | |
| 26 | ------------------------------------------------------------------------------- |
|
26 | ------------------------------------------------------------------------------- | |
| 27 |
|
27 | |||
| 28 | LIBRARY ieee; |
|
28 | LIBRARY ieee; | |
| 29 | USE ieee.std_logic_1164.ALL; |
|
29 | USE ieee.std_logic_1164.ALL; | |
| 30 |
|
30 | |||
| 31 |
|
31 | |||
| 32 |
|
32 | |||
| 33 | PACKAGE general_purpose IS |
|
33 | PACKAGE general_purpose IS | |
| 34 |
|
34 | |||
| 35 |
|
35 | |||
| 36 |
|
36 | |||
| 37 | COMPONENT Clk_divider IS |
|
37 | COMPONENT Clk_divider IS | |
| 38 | GENERIC(OSC_freqHz : INTEGER := 50000000; |
|
38 | GENERIC(OSC_freqHz : INTEGER := 50000000; | |
| 39 | TargetFreq_Hz : INTEGER := 50000); |
|
39 | TargetFreq_Hz : INTEGER := 50000); | |
| 40 | PORT (clk : IN STD_LOGIC; |
|
40 | PORT (clk : IN STD_LOGIC; | |
| 41 | reset : IN STD_LOGIC; |
|
41 | reset : IN STD_LOGIC; | |
| 42 | clk_divided : OUT STD_LOGIC); |
|
42 | clk_divided : OUT STD_LOGIC); | |
| 43 | END COMPONENT; |
|
43 | END COMPONENT; | |
| 44 |
|
44 | |||
| 45 |
|
45 | |||
| 46 | COMPONENT Clk_divider2 IS |
|
46 | COMPONENT Clk_divider2 IS | |
| 47 | generic(N : integer := 16); |
|
47 | generic(N : integer := 16); | |
| 48 | port( |
|
48 | port( | |
| 49 | clk_in : in std_logic; |
|
49 | clk_in : in std_logic; | |
| 50 | clk_out : out std_logic); |
|
50 | clk_out : out std_logic); | |
| 51 | END COMPONENT; |
|
51 | END COMPONENT; | |
| 52 |
|
52 | |||
| 53 | COMPONENT Adder IS |
|
53 | COMPONENT Adder IS | |
| 54 | GENERIC( |
|
54 | GENERIC( | |
| 55 | Input_SZ_A : INTEGER := 16; |
|
55 | Input_SZ_A : INTEGER := 16; | |
| 56 | Input_SZ_B : INTEGER := 16 |
|
56 | Input_SZ_B : INTEGER := 16 | |
| 57 |
|
57 | |||
| 58 | ); |
|
58 | ); | |
| 59 | PORT( |
|
59 | PORT( | |
| 60 | clk : IN STD_LOGIC; |
|
60 | clk : IN STD_LOGIC; | |
| 61 | reset : IN STD_LOGIC; |
|
61 | reset : IN STD_LOGIC; | |
| 62 | clr : IN STD_LOGIC; |
|
62 | clr : IN STD_LOGIC; | |
| 63 | load : IN STD_LOGIC; |
|
63 | load : IN STD_LOGIC; | |
| 64 | add : IN STD_LOGIC; |
|
64 | add : IN STD_LOGIC; | |
| 65 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
65 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 66 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
66 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 67 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) |
|
67 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) | |
| 68 | ); |
|
68 | ); | |
| 69 | END COMPONENT; |
|
69 | END COMPONENT; | |
| 70 |
|
70 | |||
| 71 | COMPONENT ADDRcntr IS |
|
71 | COMPONENT ADDRcntr IS | |
| 72 | PORT( |
|
72 | PORT( | |
| 73 | clk : IN STD_LOGIC; |
|
73 | clk : IN STD_LOGIC; | |
| 74 | reset : IN STD_LOGIC; |
|
74 | reset : IN STD_LOGIC; | |
| 75 | count : IN STD_LOGIC; |
|
75 | count : IN STD_LOGIC; | |
| 76 | clr : IN STD_LOGIC; |
|
76 | clr : IN STD_LOGIC; | |
| 77 | Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
|
77 | Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) | |
| 78 | ); |
|
78 | ); | |
| 79 | END COMPONENT; |
|
79 | END COMPONENT; | |
| 80 |
|
80 | |||
| 81 | COMPONENT ALU IS |
|
81 | COMPONENT ALU IS | |
| 82 | GENERIC( |
|
82 | GENERIC( | |
| 83 | Arith_en : INTEGER := 1; |
|
83 | Arith_en : INTEGER := 1; | |
| 84 | Logic_en : INTEGER := 1; |
|
84 | Logic_en : INTEGER := 1; | |
| 85 | Input_SZ_1 : INTEGER := 16; |
|
85 | Input_SZ_1 : INTEGER := 16; | |
| 86 | Input_SZ_2 : INTEGER := 9 |
|
86 | Input_SZ_2 : INTEGER := 9; | |
|
|
87 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
| 87 |
|
88 | |||
| 88 | ); |
|
89 | ); | |
| 89 | PORT( |
|
90 | PORT( | |
| 90 | clk : IN STD_LOGIC; |
|
91 | clk : IN STD_LOGIC; | |
| 91 | reset : IN STD_LOGIC; |
|
92 | reset : IN STD_LOGIC; | |
| 92 | ctrl : IN STD_LOGIC_VECTOR(2 downto 0); |
|
93 | ctrl : IN STD_LOGIC_VECTOR(2 downto 0); | |
| 93 | comp : IN STD_LOGIC_VECTOR(1 downto 0); |
|
94 | comp : IN STD_LOGIC_VECTOR(1 downto 0); | |
| 94 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
95 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
| 95 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); |
|
96 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); | |
| 96 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) |
|
97 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) | |
| 97 | ); |
|
98 | ); | |
| 98 | END COMPONENT; |
|
99 | END COMPONENT; | |
| 99 |
|
100 | |||
| 100 | --------------------------------------------------------- |
|
101 | --------------------------------------------------------- | |
| 101 | -------- // SοΏ½lection grace a l'entrοΏ½e "ctrl" \\ -------- |
|
102 | -------- // SοΏ½lection grace a l'entrοΏ½e "ctrl" \\ -------- | |
| 102 | --------------------------------------------------------- |
|
103 | --------------------------------------------------------- | |
| 103 | Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; |
|
104 | Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; | |
| 104 | Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; |
|
105 | Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; | |
| 105 | Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; |
|
106 | Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; | |
| 106 | Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; |
|
107 | Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; | |
| 107 | Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; |
|
108 | Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; | |
| 108 | --------------------------------------------------------- |
|
109 | --------------------------------------------------------- | |
| 109 |
|
110 | |||
| 110 | COMPONENT MAC IS |
|
111 | COMPONENT MAC IS | |
| 111 | GENERIC( |
|
112 | GENERIC( | |
| 112 | Input_SZ_A : INTEGER := 8; |
|
113 | Input_SZ_A : INTEGER := 8; | |
| 113 | Input_SZ_B : INTEGER := 8 |
|
114 | Input_SZ_B : INTEGER := 8; | |
|
|
115 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
| 114 | ); |
|
116 | ); | |
| 115 | PORT( |
|
117 | PORT( | |
| 116 | clk : IN STD_LOGIC; |
|
118 | clk : IN STD_LOGIC; | |
| 117 | reset : IN STD_LOGIC; |
|
119 | reset : IN STD_LOGIC; | |
| 118 | clr_MAC : IN STD_LOGIC; |
|
120 | clr_MAC : IN STD_LOGIC; | |
| 119 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
121 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 120 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
122 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 121 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
123 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 122 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
124 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 123 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
125 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
| 124 | ); |
|
126 | ); | |
| 125 | END COMPONENT; |
|
127 | END COMPONENT; | |
| 126 |
|
128 | |||
| 127 | COMPONENT TwoComplementer is |
|
129 | COMPONENT TwoComplementer is | |
| 128 | generic( |
|
130 | generic( | |
| 129 | Input_SZ : integer := 16); |
|
131 | Input_SZ : integer := 16); | |
| 130 | port( |
|
132 | port( | |
| 131 | clk : in std_logic; --! Horloge du composant |
|
133 | clk : in std_logic; --! Horloge du composant | |
| 132 | reset : in std_logic; --! Reset general du composant |
|
134 | reset : in std_logic; --! Reset general du composant | |
| 133 | clr : in std_logic; --! Un reset spοΏ½cifique au programme |
|
135 | clr : in std_logic; --! Un reset spοΏ½cifique au programme | |
| 134 | TwoComp : in std_logic; --! Autorise l'utilisation du complοΏ½ment |
|
136 | TwoComp : in std_logic; --! Autorise l'utilisation du complοΏ½ment | |
| 135 | OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpοΏ½rande d'entrοΏ½e |
|
137 | OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpοΏ½rande d'entrοΏ½e | |
| 136 | RES : out std_logic_vector(Input_SZ-1 downto 0) --! RοΏ½sultat, opοΏ½rande complοΏ½mentοΏ½ ou non |
|
138 | RES : out std_logic_vector(Input_SZ-1 downto 0) --! RοΏ½sultat, opοΏ½rande complοΏ½mentοΏ½ ou non | |
| 137 | ); |
|
139 | ); | |
| 138 | end COMPONENT; |
|
140 | end COMPONENT; | |
| 139 |
|
141 | |||
| 140 | COMPONENT MAC_CONTROLER IS |
|
142 | COMPONENT MAC_CONTROLER IS | |
| 141 | PORT( |
|
143 | PORT( | |
| 142 | ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
144 | ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 143 | MULT : OUT STD_LOGIC; |
|
145 | MULT : OUT STD_LOGIC; | |
| 144 | ADD : OUT STD_LOGIC; |
|
146 | ADD : OUT STD_LOGIC; | |
| 145 | LOAD_ADDER : out std_logic; |
|
147 | LOAD_ADDER : out std_logic; | |
| 146 | MACMUX_sel : OUT STD_LOGIC; |
|
148 | MACMUX_sel : OUT STD_LOGIC; | |
| 147 | MACMUX2_sel : OUT STD_LOGIC |
|
149 | MACMUX2_sel : OUT STD_LOGIC | |
| 148 | ); |
|
150 | ); | |
| 149 | END COMPONENT; |
|
151 | END COMPONENT; | |
| 150 |
|
152 | |||
| 151 | COMPONENT MAC_MUX IS |
|
153 | COMPONENT MAC_MUX IS | |
| 152 | GENERIC( |
|
154 | GENERIC( | |
| 153 | Input_SZ_A : INTEGER := 16; |
|
155 | Input_SZ_A : INTEGER := 16; | |
| 154 | Input_SZ_B : INTEGER := 16 |
|
156 | Input_SZ_B : INTEGER := 16 | |
| 155 |
|
157 | |||
| 156 | ); |
|
158 | ); | |
| 157 | PORT( |
|
159 | PORT( | |
| 158 | sel : IN STD_LOGIC; |
|
160 | sel : IN STD_LOGIC; | |
| 159 | INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
161 | INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 160 | INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
162 | INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 161 | INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
163 | INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 162 | INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
164 | INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 163 | OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
165 | OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 164 | OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0) |
|
166 | OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0) | |
| 165 | ); |
|
167 | ); | |
| 166 | END COMPONENT; |
|
168 | END COMPONENT; | |
| 167 |
|
169 | |||
| 168 |
|
170 | |||
| 169 | COMPONENT MAC_MUX2 IS |
|
171 | COMPONENT MAC_MUX2 IS | |
| 170 | GENERIC(Input_SZ : INTEGER := 16); |
|
172 | GENERIC(Input_SZ : INTEGER := 16); | |
| 171 | PORT( |
|
173 | PORT( | |
| 172 | sel : IN STD_LOGIC; |
|
174 | sel : IN STD_LOGIC; | |
| 173 | RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
175 | RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
| 174 | RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
176 | RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
| 175 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
|
177 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) | |
| 176 | ); |
|
178 | ); | |
| 177 | END COMPONENT; |
|
179 | END COMPONENT; | |
| 178 |
|
180 | |||
| 179 |
|
181 | |||
| 180 | COMPONENT MAC_REG IS |
|
182 | COMPONENT MAC_REG IS | |
| 181 | GENERIC(size : INTEGER := 16); |
|
183 | GENERIC(size : INTEGER := 16); | |
| 182 | PORT( |
|
184 | PORT( | |
| 183 | reset : IN STD_LOGIC; |
|
185 | reset : IN STD_LOGIC; | |
| 184 | clk : IN STD_LOGIC; |
|
186 | clk : IN STD_LOGIC; | |
| 185 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
|
187 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |
| 186 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) |
|
188 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) | |
| 187 | ); |
|
189 | ); | |
| 188 | END COMPONENT; |
|
190 | END COMPONENT; | |
| 189 |
|
191 | |||
| 190 |
|
192 | |||
| 191 | COMPONENT MUX2 IS |
|
193 | COMPONENT MUX2 IS | |
| 192 | GENERIC(Input_SZ : INTEGER := 16); |
|
194 | GENERIC(Input_SZ : INTEGER := 16); | |
| 193 | PORT( |
|
195 | PORT( | |
| 194 | sel : IN STD_LOGIC; |
|
196 | sel : IN STD_LOGIC; | |
| 195 | IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
197 | IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
| 196 | IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
198 | IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
| 197 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
|
199 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) | |
| 198 | ); |
|
200 | ); | |
| 199 | END COMPONENT; |
|
201 | END COMPONENT; | |
| 200 |
|
202 | |||
| 201 | TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
203 | TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; | |
| 202 | TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; |
|
204 | TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; | |
| 203 |
|
205 | |||
| 204 | COMPONENT MUXN |
|
206 | COMPONENT MUXN | |
| 205 | GENERIC ( |
|
207 | GENERIC ( | |
| 206 | Input_SZ : INTEGER; |
|
208 | Input_SZ : INTEGER; | |
| 207 | NbStage : INTEGER); |
|
209 | NbStage : INTEGER); | |
| 208 | PORT ( |
|
210 | PORT ( | |
| 209 | sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); |
|
211 | sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); | |
| 210 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); |
|
212 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); | |
| 211 | --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
213 | --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
| 212 | RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); |
|
214 | RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); | |
| 213 | END COMPONENT; |
|
215 | END COMPONENT; | |
| 214 |
|
216 | |||
| 215 |
|
217 | |||
| 216 |
|
218 | |||
| 217 | COMPONENT Multiplier IS |
|
219 | COMPONENT Multiplier IS | |
| 218 | GENERIC( |
|
220 | GENERIC( | |
| 219 | Input_SZ_A : INTEGER := 16; |
|
221 | Input_SZ_A : INTEGER := 16; | |
| 220 | Input_SZ_B : INTEGER := 16 |
|
222 | Input_SZ_B : INTEGER := 16 | |
| 221 |
|
223 | |||
| 222 | ); |
|
224 | ); | |
| 223 | PORT( |
|
225 | PORT( | |
| 224 | clk : IN STD_LOGIC; |
|
226 | clk : IN STD_LOGIC; | |
| 225 | reset : IN STD_LOGIC; |
|
227 | reset : IN STD_LOGIC; | |
| 226 | mult : IN STD_LOGIC; |
|
228 | mult : IN STD_LOGIC; | |
| 227 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
229 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 228 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
230 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 229 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
231 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
| 230 | ); |
|
232 | ); | |
| 231 | END COMPONENT; |
|
233 | END COMPONENT; | |
| 232 |
|
234 | |||
| 233 | COMPONENT REG IS |
|
235 | COMPONENT REG IS | |
| 234 | GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0); |
|
236 | GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0); | |
| 235 | PORT( |
|
237 | PORT( | |
| 236 | reset : IN STD_LOGIC; |
|
238 | reset : IN STD_LOGIC; | |
| 237 | clk : IN STD_LOGIC; |
|
239 | clk : IN STD_LOGIC; | |
| 238 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
|
240 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |
| 239 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) |
|
241 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) | |
| 240 | ); |
|
242 | ); | |
| 241 | END COMPONENT; |
|
243 | END COMPONENT; | |
| 242 |
|
244 | |||
| 243 |
|
245 | |||
| 244 |
|
246 | |||
| 245 | COMPONENT RShifter IS |
|
247 | COMPONENT RShifter IS | |
| 246 | GENERIC( |
|
248 | GENERIC( | |
| 247 | Input_SZ : INTEGER := 16; |
|
249 | Input_SZ : INTEGER := 16; | |
| 248 | shift_SZ : INTEGER := 4 |
|
250 | shift_SZ : INTEGER := 4 | |
| 249 | ); |
|
251 | ); | |
| 250 | PORT( |
|
252 | PORT( | |
| 251 | clk : IN STD_LOGIC; |
|
253 | clk : IN STD_LOGIC; | |
| 252 | reset : IN STD_LOGIC; |
|
254 | reset : IN STD_LOGIC; | |
| 253 | shift : IN STD_LOGIC; |
|
255 | shift : IN STD_LOGIC; | |
| 254 | OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
256 | OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
| 255 | cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0); |
|
257 | cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0); | |
| 256 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
|
258 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) | |
| 257 | ); |
|
259 | ); | |
| 258 | END COMPONENT; |
|
260 | END COMPONENT; | |
| 259 |
|
261 | |||
| 260 | COMPONENT SYNC_FF |
|
262 | COMPONENT SYNC_FF | |
| 261 | GENERIC ( |
|
263 | GENERIC ( | |
| 262 | NB_FF_OF_SYNC : INTEGER); |
|
264 | NB_FF_OF_SYNC : INTEGER); | |
| 263 | PORT ( |
|
265 | PORT ( | |
| 264 | clk : IN STD_LOGIC; |
|
266 | clk : IN STD_LOGIC; | |
| 265 | rstn : IN STD_LOGIC; |
|
267 | rstn : IN STD_LOGIC; | |
| 266 | A : IN STD_LOGIC; |
|
268 | A : IN STD_LOGIC; | |
| 267 | A_sync : OUT STD_LOGIC); |
|
269 | A_sync : OUT STD_LOGIC); | |
| 268 | END COMPONENT; |
|
270 | END COMPONENT; | |
| 269 |
|
271 | |||
| 270 | END; |
|
272 | END; | |
| This diff has been collapsed as it changes many lines, (606 lines changed) Show them Hide them | |||||
| @@ -1,303 +1,303 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
| 3 | LIBRARY lpp; |
|
3 | LIBRARY lpp; | |
| 4 | USE lpp.lpp_ad_conv.ALL; |
|
4 | USE lpp.lpp_ad_conv.ALL; | |
| 5 | USE lpp.iir_filter.ALL; |
|
5 | USE lpp.iir_filter.ALL; | |
| 6 | USE lpp.FILTERcfg.ALL; |
|
6 | USE lpp.FILTERcfg.ALL; | |
| 7 | USE lpp.lpp_memory.ALL; |
|
7 | USE lpp.lpp_memory.ALL; | |
| 8 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
8 | USE lpp.lpp_top_lfr_pkg.ALL; | |
| 9 | LIBRARY techmap; |
|
9 | LIBRARY techmap; | |
| 10 | USE techmap.gencomp.ALL; |
|
10 | USE techmap.gencomp.ALL; | |
| 11 |
|
11 | |||
| 12 | ENTITY lpp_top_acq IS |
|
12 | ENTITY lpp_top_acq IS | |
| 13 | GENERIC( |
|
13 | GENERIC( | |
| 14 | tech : INTEGER := 0 |
|
14 | tech : INTEGER := 0 | |
| 15 | ); |
|
15 | ); | |
| 16 | PORT ( |
|
16 | PORT ( | |
| 17 | -- ADS7886 |
|
17 | -- ADS7886 | |
| 18 | cnv_run : IN STD_LOGIC; |
|
18 | cnv_run : IN STD_LOGIC; | |
| 19 | cnv : OUT STD_LOGIC; |
|
19 | cnv : OUT STD_LOGIC; | |
| 20 | sck : OUT STD_LOGIC; |
|
20 | sck : OUT STD_LOGIC; | |
| 21 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
21 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 22 | -- |
|
22 | -- | |
| 23 | cnv_clk : IN STD_LOGIC; -- 49 MHz |
|
23 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
| 24 | cnv_rstn : IN STD_LOGIC; |
|
24 | cnv_rstn : IN STD_LOGIC; | |
| 25 | -- |
|
25 | -- | |
| 26 | clk : IN STD_LOGIC; -- 25 MHz |
|
26 | clk : IN STD_LOGIC; -- 25 MHz | |
| 27 | rstn : IN STD_LOGIC; |
|
27 | rstn : IN STD_LOGIC; | |
| 28 | -- |
|
28 | -- | |
| 29 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
29 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 30 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
30 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 31 | -- |
|
31 | -- | |
| 32 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
32 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 33 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
33 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 34 | -- |
|
34 | -- | |
| 35 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
35 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 36 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
36 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 37 | -- |
|
37 | -- | |
| 38 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
38 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 39 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) |
|
39 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |
| 40 | ); |
|
40 | ); | |
| 41 | END lpp_top_acq; |
|
41 | END lpp_top_acq; | |
| 42 |
|
42 | |||
| 43 | ARCHITECTURE tb OF lpp_top_acq IS |
|
43 | ARCHITECTURE tb OF lpp_top_acq IS | |
| 44 |
|
44 | |||
| 45 | COMPONENT Downsampling |
|
45 | COMPONENT Downsampling | |
| 46 | GENERIC ( |
|
46 | GENERIC ( | |
| 47 | ChanelCount : INTEGER; |
|
47 | ChanelCount : INTEGER; | |
| 48 | SampleSize : INTEGER; |
|
48 | SampleSize : INTEGER; | |
| 49 | DivideParam : INTEGER); |
|
49 | DivideParam : INTEGER); | |
| 50 | PORT ( |
|
50 | PORT ( | |
| 51 | clk : IN STD_LOGIC; |
|
51 | clk : IN STD_LOGIC; | |
| 52 | rstn : IN STD_LOGIC; |
|
52 | rstn : IN STD_LOGIC; | |
| 53 | sample_in_val : IN STD_LOGIC; |
|
53 | sample_in_val : IN STD_LOGIC; | |
| 54 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); |
|
54 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
| 55 | sample_out_val : OUT STD_LOGIC; |
|
55 | sample_out_val : OUT STD_LOGIC; | |
| 56 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); |
|
56 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
| 57 | END COMPONENT; |
|
57 | END COMPONENT; | |
| 58 |
|
58 | |||
| 59 | ----------------------------------------------------------------------------- |
|
59 | ----------------------------------------------------------------------------- | |
| 60 | CONSTANT ChanelCount : INTEGER := 8; |
|
60 | CONSTANT ChanelCount : INTEGER := 8; | |
| 61 | CONSTANT ncycle_cnv_high : INTEGER := 79; |
|
61 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
| 62 | CONSTANT ncycle_cnv : INTEGER := 500; |
|
62 | CONSTANT ncycle_cnv : INTEGER := 500; | |
| 63 |
|
63 | |||
| 64 | ----------------------------------------------------------------------------- |
|
64 | ----------------------------------------------------------------------------- | |
| 65 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); |
|
65 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
| 66 | SIGNAL sample_val : STD_LOGIC; |
|
66 | SIGNAL sample_val : STD_LOGIC; | |
| 67 | SIGNAL sample_val_delay : STD_LOGIC; |
|
67 | SIGNAL sample_val_delay : STD_LOGIC; | |
| 68 | ----------------------------------------------------------------------------- |
|
68 | ----------------------------------------------------------------------------- | |
| 69 | CONSTANT Coef_SZ : INTEGER := 9; |
|
69 | CONSTANT Coef_SZ : INTEGER := 9; | |
| 70 | CONSTANT CoefCntPerCel : INTEGER := 6; |
|
70 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
| 71 | CONSTANT CoefPerCel : INTEGER := 5; |
|
71 | CONSTANT CoefPerCel : INTEGER := 5; | |
| 72 | CONSTANT Cels_count : INTEGER := 5; |
|
72 | CONSTANT Cels_count : INTEGER := 5; | |
| 73 |
|
73 | |||
| 74 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); |
|
74 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
| 75 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
75 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 76 | -- |
|
76 | -- | |
| 77 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; |
|
77 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
| 78 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
78 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 79 | -- |
|
79 | -- | |
| 80 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; |
|
80 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; | |
| 81 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
81 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 82 | ----------------------------------------------------------------------------- |
|
82 | ----------------------------------------------------------------------------- | |
| 83 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
83 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 84 | SIGNAL sample_downsampling_out_val : STD_LOGIC; |
|
84 | SIGNAL sample_downsampling_out_val : STD_LOGIC; | |
| 85 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
85 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 86 | -- |
|
86 | -- | |
| 87 | SIGNAL sample_f0_val : STD_LOGIC; |
|
87 | SIGNAL sample_f0_val : STD_LOGIC; | |
| 88 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
88 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 89 | ----------------------------------------------------------------------------- |
|
89 | ----------------------------------------------------------------------------- | |
| 90 | SIGNAL sample_f1_val : STD_LOGIC; |
|
90 | SIGNAL sample_f1_val : STD_LOGIC; | |
| 91 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
91 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 92 | -- |
|
92 | -- | |
| 93 | SIGNAL sample_f2_val : STD_LOGIC; |
|
93 | SIGNAL sample_f2_val : STD_LOGIC; | |
| 94 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
94 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 95 | -- |
|
95 | -- | |
| 96 | SIGNAL sample_f3_val : STD_LOGIC; |
|
96 | SIGNAL sample_f3_val : STD_LOGIC; | |
| 97 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
97 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 98 |
|
98 | |||
| 99 | BEGIN |
|
99 | BEGIN | |
| 100 |
|
100 | |||
| 101 | -- component instantiation |
|
101 | -- component instantiation | |
| 102 | ----------------------------------------------------------------------------- |
|
102 | ----------------------------------------------------------------------------- | |
| 103 |
DIGITAL_acquisition : AD |
|
103 | DIGITAL_acquisition : AD7688_drvr | |
| 104 | GENERIC MAP ( |
|
104 | GENERIC MAP ( | |
| 105 | ChanelCount => ChanelCount, |
|
105 | ChanelCount => ChanelCount, | |
| 106 | ncycle_cnv_high => ncycle_cnv_high, |
|
106 | ncycle_cnv_high => ncycle_cnv_high, | |
| 107 | ncycle_cnv => ncycle_cnv) |
|
107 | ncycle_cnv => ncycle_cnv) | |
| 108 | PORT MAP ( |
|
108 | PORT MAP ( | |
| 109 | cnv_clk => cnv_clk, -- |
|
109 | cnv_clk => cnv_clk, -- | |
| 110 | cnv_rstn => cnv_rstn, -- |
|
110 | cnv_rstn => cnv_rstn, -- | |
| 111 | cnv_run => cnv_run, -- |
|
111 | cnv_run => cnv_run, -- | |
| 112 | cnv => cnv, -- |
|
112 | cnv => cnv, -- | |
| 113 | clk => clk, -- |
|
113 | clk => clk, -- | |
| 114 | rstn => rstn, -- |
|
114 | rstn => rstn, -- | |
| 115 | sck => sck, -- |
|
115 | sck => sck, -- | |
| 116 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- |
|
116 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
| 117 | sample => sample, |
|
117 | sample => sample, | |
| 118 | sample_val => sample_val); |
|
118 | sample_val => sample_val); | |
| 119 |
|
119 | |||
| 120 | ----------------------------------------------------------------------------- |
|
120 | ----------------------------------------------------------------------------- | |
| 121 |
|
121 | |||
| 122 | PROCESS (clk, rstn) |
|
122 | PROCESS (clk, rstn) | |
| 123 | BEGIN -- PROCESS |
|
123 | BEGIN -- PROCESS | |
| 124 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
124 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 125 | sample_val_delay <= '0'; |
|
125 | sample_val_delay <= '0'; | |
| 126 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
126 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 127 | sample_val_delay <= sample_val; |
|
127 | sample_val_delay <= sample_val; | |
| 128 | END IF; |
|
128 | END IF; | |
| 129 | END PROCESS; |
|
129 | END PROCESS; | |
| 130 |
|
130 | |||
| 131 | ----------------------------------------------------------------------------- |
|
131 | ----------------------------------------------------------------------------- | |
| 132 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE |
|
132 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
| 133 | SampleLoop : FOR j IN 0 TO 15 GENERATE |
|
133 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
| 134 | sample_filter_in(i, j) <= sample(i)(j); |
|
134 | sample_filter_in(i, j) <= sample(i)(j); | |
| 135 | END GENERATE; |
|
135 | END GENERATE; | |
| 136 |
|
136 | |||
| 137 | sample_filter_in(i, 16) <= sample(i)(15); |
|
137 | sample_filter_in(i, 16) <= sample(i)(15); | |
| 138 | sample_filter_in(i, 17) <= sample(i)(15); |
|
138 | sample_filter_in(i, 17) <= sample(i)(15); | |
| 139 | END GENERATE; |
|
139 | END GENERATE; | |
| 140 |
|
140 | |||
| 141 | coefs_v2 <= CoefsInitValCst_v2; |
|
141 | coefs_v2 <= CoefsInitValCst_v2; | |
| 142 |
|
142 | |||
| 143 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
|
143 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
| 144 | GENERIC MAP ( |
|
144 | GENERIC MAP ( | |
| 145 | tech => 0, |
|
145 | tech => 0, | |
| 146 |
Mem_use => use_ |
|
146 | Mem_use => use_CEL, | |
| 147 | Sample_SZ => 18, |
|
147 | Sample_SZ => 18, | |
| 148 | Coef_SZ => Coef_SZ, |
|
148 | Coef_SZ => Coef_SZ, | |
| 149 | Coef_Nb => 25, -- TODO |
|
149 | Coef_Nb => 25, -- TODO | |
| 150 | Coef_sel_SZ => 5, -- TODO |
|
150 | Coef_sel_SZ => 5, -- TODO | |
| 151 | Cels_count => Cels_count, |
|
151 | Cels_count => Cels_count, | |
| 152 | ChanelsCount => ChanelCount) |
|
152 | ChanelsCount => ChanelCount) | |
| 153 | PORT MAP ( |
|
153 | PORT MAP ( | |
| 154 | rstn => rstn, |
|
154 | rstn => rstn, | |
| 155 | clk => clk, |
|
155 | clk => clk, | |
| 156 | virg_pos => 7, |
|
156 | virg_pos => 7, | |
| 157 | coefs => coefs_v2, |
|
157 | coefs => coefs_v2, | |
| 158 | sample_in_val => sample_val_delay, |
|
158 | sample_in_val => sample_val_delay, | |
| 159 | sample_in => sample_filter_in, |
|
159 | sample_in => sample_filter_in, | |
| 160 | sample_out_val => sample_filter_v2_out_val, |
|
160 | sample_out_val => sample_filter_v2_out_val, | |
| 161 | sample_out => sample_filter_v2_out); |
|
161 | sample_out => sample_filter_v2_out); | |
| 162 |
|
162 | |||
| 163 | ----------------------------------------------------------------------------- |
|
163 | ----------------------------------------------------------------------------- | |
| 164 | PROCESS (clk, rstn) |
|
164 | PROCESS (clk, rstn) | |
| 165 | BEGIN -- PROCESS |
|
165 | BEGIN -- PROCESS | |
| 166 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
166 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 167 | sample_filter_v2_out_r_val <= '0'; |
|
167 | sample_filter_v2_out_r_val <= '0'; | |
| 168 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP |
|
168 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP | |
| 169 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP |
|
169 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP | |
| 170 | sample_filter_v2_out_r(I, J) <= '0'; |
|
170 | sample_filter_v2_out_r(I, J) <= '0'; | |
| 171 | END LOOP rst_all_bits; |
|
171 | END LOOP rst_all_bits; | |
| 172 | END LOOP rst_all_chanel; |
|
172 | END LOOP rst_all_chanel; | |
| 173 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
173 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 174 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; |
|
174 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; | |
| 175 | IF sample_filter_v2_out_val = '1' THEN |
|
175 | IF sample_filter_v2_out_val = '1' THEN | |
| 176 | sample_filter_v2_out_r <= sample_filter_v2_out; |
|
176 | sample_filter_v2_out_r <= sample_filter_v2_out; | |
| 177 | END IF; |
|
177 | END IF; | |
| 178 | END IF; |
|
178 | END IF; | |
| 179 | END PROCESS; |
|
179 | END PROCESS; | |
| 180 |
|
180 | |||
| 181 | ----------------------------------------------------------------------------- |
|
181 | ----------------------------------------------------------------------------- | |
| 182 | -- F0 -- @24.576 kHz |
|
182 | -- F0 -- @24.576 kHz | |
| 183 | ----------------------------------------------------------------------------- |
|
183 | ----------------------------------------------------------------------------- | |
| 184 | Downsampling_f0 : Downsampling |
|
184 | Downsampling_f0 : Downsampling | |
| 185 | GENERIC MAP ( |
|
185 | GENERIC MAP ( | |
| 186 | ChanelCount => ChanelCount, |
|
186 | ChanelCount => ChanelCount, | |
| 187 | SampleSize => 18, |
|
187 | SampleSize => 18, | |
| 188 | DivideParam => 4) |
|
188 | DivideParam => 4) | |
| 189 | PORT MAP ( |
|
189 | PORT MAP ( | |
| 190 | clk => clk, |
|
190 | clk => clk, | |
| 191 | rstn => rstn, |
|
191 | rstn => rstn, | |
| 192 | sample_in_val => sample_filter_v2_out_val , |
|
192 | sample_in_val => sample_filter_v2_out_val , | |
| 193 | sample_in => sample_filter_v2_out, |
|
193 | sample_in => sample_filter_v2_out, | |
| 194 | sample_out_val => sample_f0_val, |
|
194 | sample_out_val => sample_f0_val, | |
| 195 | sample_out => sample_f0); |
|
195 | sample_out => sample_f0); | |
| 196 |
|
196 | |||
| 197 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE |
|
197 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 198 | sample_f0_wdata(I) <= sample_f0(0, I); |
|
198 | sample_f0_wdata(I) <= sample_f0(0, I); | |
| 199 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); |
|
199 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); | |
| 200 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); |
|
200 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); | |
| 201 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); |
|
201 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); | |
| 202 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); |
|
202 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); | |
| 203 | END GENERATE all_bit_sample_f0; |
|
203 | END GENERATE all_bit_sample_f0; | |
| 204 |
|
204 | |||
| 205 | sample_f0_wen <= NOT(sample_f0_val) & |
|
205 | sample_f0_wen <= NOT(sample_f0_val) & | |
| 206 | NOT(sample_f0_val) & |
|
206 | NOT(sample_f0_val) & | |
| 207 | NOT(sample_f0_val) & |
|
207 | NOT(sample_f0_val) & | |
| 208 | NOT(sample_f0_val) & |
|
208 | NOT(sample_f0_val) & | |
| 209 | NOT(sample_f0_val); |
|
209 | NOT(sample_f0_val); | |
| 210 |
|
210 | |||
| 211 | ----------------------------------------------------------------------------- |
|
211 | ----------------------------------------------------------------------------- | |
| 212 | -- F1 -- @4096 Hz |
|
212 | -- F1 -- @4096 Hz | |
| 213 | ----------------------------------------------------------------------------- |
|
213 | ----------------------------------------------------------------------------- | |
| 214 | Downsampling_f1 : Downsampling |
|
214 | Downsampling_f1 : Downsampling | |
| 215 | GENERIC MAP ( |
|
215 | GENERIC MAP ( | |
| 216 | ChanelCount => ChanelCount, |
|
216 | ChanelCount => ChanelCount, | |
| 217 | SampleSize => 18, |
|
217 | SampleSize => 18, | |
| 218 | DivideParam => 6) |
|
218 | DivideParam => 6) | |
| 219 | PORT MAP ( |
|
219 | PORT MAP ( | |
| 220 | clk => clk, |
|
220 | clk => clk, | |
| 221 | rstn => rstn, |
|
221 | rstn => rstn, | |
| 222 | sample_in_val => sample_f0_val , |
|
222 | sample_in_val => sample_f0_val , | |
| 223 | sample_in => sample_f0, |
|
223 | sample_in => sample_f0, | |
| 224 | sample_out_val => sample_f1_val, |
|
224 | sample_out_val => sample_f1_val, | |
| 225 | sample_out => sample_f1); |
|
225 | sample_out => sample_f1); | |
| 226 |
|
226 | |||
| 227 | sample_f1_wen <= NOT(sample_f1_val) & |
|
227 | sample_f1_wen <= NOT(sample_f1_val) & | |
| 228 | NOT(sample_f1_val) & |
|
228 | NOT(sample_f1_val) & | |
| 229 | NOT(sample_f1_val) & |
|
229 | NOT(sample_f1_val) & | |
| 230 | NOT(sample_f1_val) & |
|
230 | NOT(sample_f1_val) & | |
| 231 | NOT(sample_f1_val); |
|
231 | NOT(sample_f1_val); | |
| 232 |
|
232 | |||
| 233 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
233 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 234 | sample_f1_wdata(I) <= sample_f1(0, I); |
|
234 | sample_f1_wdata(I) <= sample_f1(0, I); | |
| 235 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); |
|
235 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); | |
| 236 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); |
|
236 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); | |
| 237 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); |
|
237 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); | |
| 238 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); |
|
238 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); | |
| 239 | END GENERATE all_bit_sample_f1; |
|
239 | END GENERATE all_bit_sample_f1; | |
| 240 |
|
240 | |||
| 241 | ----------------------------------------------------------------------------- |
|
241 | ----------------------------------------------------------------------------- | |
| 242 | -- F2 -- @16 Hz |
|
242 | -- F2 -- @16 Hz | |
| 243 | ----------------------------------------------------------------------------- |
|
243 | ----------------------------------------------------------------------------- | |
| 244 | Downsampling_f2 : Downsampling |
|
244 | Downsampling_f2 : Downsampling | |
| 245 | GENERIC MAP ( |
|
245 | GENERIC MAP ( | |
| 246 | ChanelCount => ChanelCount, |
|
246 | ChanelCount => ChanelCount, | |
| 247 | SampleSize => 18, |
|
247 | SampleSize => 18, | |
| 248 | DivideParam => 256) |
|
248 | DivideParam => 256) | |
| 249 | PORT MAP ( |
|
249 | PORT MAP ( | |
| 250 | clk => clk, |
|
250 | clk => clk, | |
| 251 | rstn => rstn, |
|
251 | rstn => rstn, | |
| 252 | sample_in_val => sample_f1_val , |
|
252 | sample_in_val => sample_f1_val , | |
| 253 | sample_in => sample_f1, |
|
253 | sample_in => sample_f1, | |
| 254 | sample_out_val => sample_f2_val, |
|
254 | sample_out_val => sample_f2_val, | |
| 255 | sample_out => sample_f2); |
|
255 | sample_out => sample_f2); | |
| 256 |
|
256 | |||
| 257 | sample_f2_wen <= NOT(sample_f2_val) & |
|
257 | sample_f2_wen <= NOT(sample_f2_val) & | |
| 258 | NOT(sample_f2_val) & |
|
258 | NOT(sample_f2_val) & | |
| 259 | NOT(sample_f2_val) & |
|
259 | NOT(sample_f2_val) & | |
| 260 | NOT(sample_f2_val) & |
|
260 | NOT(sample_f2_val) & | |
| 261 | NOT(sample_f2_val); |
|
261 | NOT(sample_f2_val); | |
| 262 |
|
262 | |||
| 263 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE |
|
263 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 264 | sample_f2_wdata(I) <= sample_f2(0, I); |
|
264 | sample_f2_wdata(I) <= sample_f2(0, I); | |
| 265 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); |
|
265 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); | |
| 266 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); |
|
266 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); | |
| 267 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); |
|
267 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); | |
| 268 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); |
|
268 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); | |
| 269 | END GENERATE all_bit_sample_f2; |
|
269 | END GENERATE all_bit_sample_f2; | |
| 270 |
|
270 | |||
| 271 | ----------------------------------------------------------------------------- |
|
271 | ----------------------------------------------------------------------------- | |
| 272 | -- F3 -- @256 Hz |
|
272 | -- F3 -- @256 Hz | |
| 273 | ----------------------------------------------------------------------------- |
|
273 | ----------------------------------------------------------------------------- | |
| 274 | Downsampling_f3 : Downsampling |
|
274 | Downsampling_f3 : Downsampling | |
| 275 | GENERIC MAP ( |
|
275 | GENERIC MAP ( | |
| 276 | ChanelCount => ChanelCount, |
|
276 | ChanelCount => ChanelCount, | |
| 277 | SampleSize => 18, |
|
277 | SampleSize => 18, | |
| 278 | DivideParam => 96) |
|
278 | DivideParam => 96) | |
| 279 | PORT MAP ( |
|
279 | PORT MAP ( | |
| 280 | clk => clk, |
|
280 | clk => clk, | |
| 281 | rstn => rstn, |
|
281 | rstn => rstn, | |
| 282 | sample_in_val => sample_f0_val , |
|
282 | sample_in_val => sample_f0_val , | |
| 283 | sample_in => sample_f0, |
|
283 | sample_in => sample_f0, | |
| 284 | sample_out_val => sample_f3_val, |
|
284 | sample_out_val => sample_f3_val, | |
| 285 | sample_out => sample_f3); |
|
285 | sample_out => sample_f3); | |
| 286 |
|
286 | |||
| 287 | sample_f3_wen <= (NOT sample_f3_val) & |
|
287 | sample_f3_wen <= (NOT sample_f3_val) & | |
| 288 | (NOT sample_f3_val) & |
|
288 | (NOT sample_f3_val) & | |
| 289 | (NOT sample_f3_val) & |
|
289 | (NOT sample_f3_val) & | |
| 290 | (NOT sample_f3_val) & |
|
290 | (NOT sample_f3_val) & | |
| 291 | (NOT sample_f3_val); |
|
291 | (NOT sample_f3_val); | |
| 292 |
|
292 | |||
| 293 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE |
|
293 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 294 | sample_f3_wdata(I) <= sample_f3(0, I); |
|
294 | sample_f3_wdata(I) <= sample_f3(0, I); | |
| 295 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); |
|
295 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); | |
| 296 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); |
|
296 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); | |
| 297 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); |
|
297 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); | |
| 298 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); |
|
298 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); | |
| 299 | END GENERATE all_bit_sample_f3; |
|
299 | END GENERATE all_bit_sample_f3; | |
| 300 |
|
300 | |||
| 301 |
|
301 | |||
| 302 |
|
302 | |||
| 303 | END tb; |
|
303 | END tb; | |
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