diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd @@ -1,188 +1,140 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; - -------------------------------------------------------------------------------- - -ENTITY TB_Data_Acquisition IS - -END TB_Data_Acquisition; - -------------------------------------------------------------------------------- - -ARCHITECTURE tb OF TB_Data_Acquisition IS - - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - COMPONENT Top_Data_Acquisition - PORT ( - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - -- - sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); - END COMPONENT; - - -- component ports - SIGNAL cnv_rstn : STD_LOGIC; - SIGNAL cnv : STD_LOGIC; - SIGNAL rstn : STD_LOGIC; - SIGNAL sck : STD_LOGIC; - SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL run_cnv : STD_LOGIC; - - - -- clock - signal Clk : STD_LOGIC := '1'; - SIGNAL cnv_clk : STD_LOGIC := '1'; - - ----------------------------------------------------------------------------- - SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - -BEGIN -- tb - - MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(7)); - - - -- clock generation - Clk <= not Clk after 20 ns; -- 25 Mhz - cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz - - -- waveform generation - WaveGen_Proc: process - begin - -- insert signal assignments here - wait until Clk = '1'; - rstn <= '0'; - cnv_rstn <= '0'; - run_cnv <= '0'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - rstn <= '1'; - cnv_rstn <= '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - run_cnv <= '1'; - wait; - - end process WaveGen_Proc; - - ----------------------------------------------------------------------------- - - Top_Data_Acquisition_1: Top_Data_Acquisition - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo, - cnv_clk => cnv_clk, - cnv_rstn => cnv_rstn, - clk => clk, - rstn => rstn, - -- - sample_f0_0_ren => sample_f0_0_ren, - sample_f0_0_rdata => sample_f0_0_rdata, - sample_f0_0_full => sample_f0_0_full, - sample_f0_0_empty => sample_f0_0_empty, - -- - sample_f0_1_ren => sample_f0_1_ren, - sample_f0_1_rdata => sample_f0_1_rdata, - sample_f0_1_full => sample_f0_1_full, - sample_f0_1_empty => sample_f0_1_empty, - -- - sample_f1_ren => sample_f1_ren, - sample_f1_rdata => sample_f1_rdata, - sample_f1_full => sample_f1_full, - sample_f1_empty => sample_f1_empty, - -- - sample_f3_ren => sample_f3_ren, - sample_f3_rdata => sample_f3_rdata, - sample_f3_full => sample_f3_full, - sample_f3_empty => sample_f3_empty - ); - sample_f0_0_ren <= (OTHERS => '1'); - sample_f0_1_ren <= (OTHERS => '1'); - sample_f1_ren <= (OTHERS => '1'); - sample_f3_ren <= (OTHERS => '1'); - -END tb; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; + +------------------------------------------------------------------------------- + +ENTITY TB_Data_Acquisition IS + +END TB_Data_Acquisition; + +------------------------------------------------------------------------------- + +ARCHITECTURE tb OF TB_Data_Acquisition IS + + COMPONENT TestModule_ADS7886 + GENERIC ( + freq : INTEGER; + amplitude : INTEGER; + impulsion : INTEGER); + PORT ( + cnv_run : IN STD_LOGIC; + cnv : IN STD_LOGIC; + sck : IN STD_LOGIC; + sdo : OUT STD_LOGIC); + END COMPONENT; + + -- component ports + SIGNAL cnv_rstn : STD_LOGIC; + SIGNAL cnv : STD_LOGIC; + SIGNAL rstn : STD_LOGIC; + SIGNAL sck : STD_LOGIC; + SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL run_cnv : STD_LOGIC; + + + -- clock + signal Clk : STD_LOGIC := '1'; + SIGNAL cnv_clk : STD_LOGIC := '1'; + + ----------------------------------------------------------------------------- + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + +BEGIN -- tb + + MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE + TestModule_ADS7886_u: TestModule_ADS7886 + GENERIC MAP ( + freq => 24*(I+1), + amplitude => 30000/(I+1), + impulsion => 0) + PORT MAP ( + cnv_run => run_cnv, + cnv => cnv, + sck => sck, + sdo => sdo(I)); + END GENERATE MODULE_ADS7886; + + TestModule_ADS7886_u: TestModule_ADS7886 + GENERIC MAP ( + freq => 0, + amplitude => 30000, + impulsion => 1) + PORT MAP ( + cnv_run => run_cnv, + cnv => cnv, + sck => sck, + sdo => sdo(7)); + + + -- clock generation + Clk <= not Clk after 20 ns; -- 25 Mhz + cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz + + -- waveform generation + WaveGen_Proc: process + begin + -- insert signal assignments here + wait until Clk = '1'; + rstn <= '0'; + cnv_rstn <= '0'; + run_cnv <= '0'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + rstn <= '1'; + cnv_rstn <= '1'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + run_cnv <= '1'; + wait; + + end process WaveGen_Proc; + + ----------------------------------------------------------------------------- + + Top_Data_Acquisition_1: lpp_top_acq + PORT MAP ( + cnv_run => run_cnv, + cnv => cnv, + sck => sck, + sdo => sdo, + cnv_clk => cnv_clk, + cnv_rstn => cnv_rstn, + clk => clk, + rstn => rstn, + -- + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + -- + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + -- + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + -- + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata + ); + + + + + +END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do @@ -1,49 +1,54 @@ - -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd -#vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd - -vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd -vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd - -vcom -quiet -93 -work work Top_Data_Acquisition.vhd -vcom -quiet -93 -work work TB_Data_Acquisition.vhd - -#vsim work.TB_Data_Acquisition - -#log -r * -#do wave_data_acquisition.do + +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd + +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd + + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd + +vcom -quiet -93 -work work TB_Data_Acquisition.vhd + +vsim work.TB_Data_Acquisition + +#log -r * +#do wave_data_acquisition.do #run 5 ms \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do @@ -1,231 +1,38 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/chanelcount -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv_high -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_clk -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_rstn -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/clk -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/rstn -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sck -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sdo -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_cycle_counter -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_s -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync_r -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_done -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_bit_counter -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/shift_reg -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run_sync -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/tech -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_sz -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/chanelscount -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coef_sz -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefcntpercel -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/cels_count -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/mem_use -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/reset -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/clk -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_clk -add wave -noupdate -group FILTER -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_in(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in -add wave -noupdate -group FILTER -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_out(7) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(6) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(5) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(4) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(3) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(2) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(1) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(0) {-height 15 -radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/virg_pos -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/gotest -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefs -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/smpl_clk_old -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/wd_sel -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/read -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/svg_addr -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/count -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/write -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/waddr_sel -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/go_0 -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in_bk -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_out -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_ctrl -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_sample_in -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_coef_in -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_out -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentcel -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentchan -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_in_buff -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_out_buff -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefsreg -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/iir_cel_state -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_run -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sck -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sdo -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_clk -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_rstn -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/clk -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/rstn -add wave -noupdate -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/sample(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/sample -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_val -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/coefs -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_in -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_out -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/alu_selected_coeff -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing -add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/clk -add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/reset -add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/ctrl -add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op1 -add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op2 -add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/res -add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input -add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/rstn -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/clk -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/virg_pos -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/coefs -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src -add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata -add wave -noupdate -group DATA_FLOW -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input -add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write -add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/rstn -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/clk -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/virg_pos -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/coefs -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/in_sel_src -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_sel_wdata -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_write -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_read -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_rst -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_add1 -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/waddr_previous -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_input -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_coeff -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_ctrl -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_buf -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_rotate -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_s -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(17) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(16) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(15) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(14) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(13) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(12) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(11) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(10) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(9) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(8) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input -add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read -add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst -add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 -add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff -add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s -add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef -add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output -add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state -add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing -add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing -add wave -noupdate -group DATAFLOW -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out -add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rstn -add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/clk -add wave -noupdate -group DATAFLOW_RAM -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(0) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(8) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(9) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(10) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(11) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(12) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(13) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(14) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(15) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(16) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(17) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(18) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(19) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(20) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(21) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(22) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(23) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(24) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(25) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(26) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(27) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(28) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(29) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(30) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(31) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(32) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(33) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(34) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(35) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(36) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(37) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(38) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(39) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(40) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(41) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(42) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(43) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(44) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(45) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(46) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(47) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(48) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(49) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(50) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(51) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(52) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(53) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(54) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(55) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(56) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(57) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(58) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(59) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(60) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(61) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(62) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(63) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(64) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(65) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(66) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(67) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(68) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(69) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(70) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(71) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(72) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(73) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(74) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(75) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(76) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(77) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(78) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(79) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(80) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(81) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(82) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(83) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(84) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(85) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(86) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(87) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(88) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(89) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(90) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(91) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(92) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(93) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(94) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(95) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(96) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(97) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(98) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(99) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(100) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(101) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(102) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(103) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(104) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(105) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(106) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(107) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(108) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(109) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(110) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(111) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(112) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(113) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(114) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(115) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(116) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(117) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(118) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(119) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(120) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(121) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(122) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(123) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(124) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(125) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(126) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(127) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(128) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(129) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(130) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(131) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(132) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(133) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(134) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(135) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(136) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(137) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(138) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(139) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(140) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(141) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(142) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(143) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(144) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(145) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(146) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(147) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(148) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(149) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(150) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(151) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(152) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(153) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(154) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(155) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(156) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(157) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(158) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(159) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(160) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(161) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(162) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(163) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(164) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(165) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(166) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(167) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(168) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(169) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(170) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(171) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(172) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(173) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(174) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(175) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(176) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(177) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(178) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(179) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(180) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(181) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(182) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(183) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(184) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(185) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(186) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(187) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(188) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(189) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(190) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(191) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(192) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(193) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(194) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(195) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(196) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(197) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(198) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(199) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(200) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(201) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(202) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(203) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(204) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(205) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(206) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(207) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(208) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(209) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(210) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(211) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(212) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(213) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(214) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(215) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(216) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(217) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(218) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(219) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(220) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(221) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(222) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(223) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(224) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(225) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(226) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(227) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(228) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(229) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(230) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(231) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(232) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(233) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(234) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(235) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(236) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(237) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(238) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(239) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(240) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(241) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(242) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(243) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(244) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(245) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(246) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(247) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(248) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(249) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(250) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(251) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(252) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(253) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(254) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(255) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray -add wave -noupdate -group DATAFLOW_RAM -group COUNTER -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/counter -add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_rst -add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_add1 -add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr_previous -add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_write -add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wen -add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr -add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wd -add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_in -add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_read -add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ren -add wave -noupdate -group DATAFLOW_RAM -group READ -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr -add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rd -add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_out -add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val -add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in -add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val -add wave -noupdate -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out -add wave -noupdate -height 15 -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clk -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/reset -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mac_mul_add -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1 -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2 -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/res -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mult -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderina -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderinb -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderout -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d_resz -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d_resz -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d_d -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_val -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_rot -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 +add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample +add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val +add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wen +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wdata +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wen +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wdata +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wen +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wdata +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wen +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wdata TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {4520000 ps} 0} -configure wave -namecolwidth 677 +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 430 configure wave -valuecolwidth 100 configure wave -justifyvalue left configure wave -signalnamewidth 0 @@ -239,4 +46,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2722930 ps} {6210191 ps} +WaveRestoreZoom {0 ps} {754717 ps} diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd @@ -196,7 +196,8 @@ BEGIN GENERIC MAP ( Arith_en => 1, Input_SZ_1 => Sample_SZ, - Input_SZ_2 => Coef_SZ) + Input_SZ_2 => Coef_SZ, + COMP_EN => 1) PORT MAP ( clk => clk, reset => rstn, diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd @@ -72,7 +72,7 @@ BEGIN memCEL : IF Mem_use = use_CEL GENERATE WEN <= NOT ram_write; REN <= NOT ram_read; - RAMblk : RAM_CEL + RAMblk : RAM_CEL_N GENERIC MAP(Input_SZ_1) PORT MAP( WD => WD, diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd --- a/lib/lpp/dsp/iir_filter/iir_filter.vhd +++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd @@ -216,6 +216,18 @@ PACKAGE iir_filter IS RWCLK, RESET : IN STD_LOGIC); END COMPONENT; + COMPONENT RAM_CEL_N + GENERIC ( + size : INTEGER); + PORT ( + WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); + RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0); + WEN, REN : IN STD_LOGIC; + WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + RWCLK, RESET : IN STD_LOGIC); + END COMPONENT; + COMPONENT IIR_CEL_FILTER IS GENERIC( tech : INTEGER := 0; diff --git a/lib/lpp/general_purpose/ALU.vhd b/lib/lpp/general_purpose/ALU.vhd --- a/lib/lpp/general_purpose/ALU.vhd +++ b/lib/lpp/general_purpose/ALU.vhd @@ -32,7 +32,9 @@ generic( Arith_en : integer := 1; Logic_en : integer := 1; Input_SZ_1 : integer := 16; - Input_SZ_2 : integer := 16); + Input_SZ_2 : integer := 16; + COMP_EN : INTEGER := 0 -- 1 => No Comp + ); port( clk : in std_logic; --! Horloge du composant reset : in std_logic; --! Reset general du composant @@ -56,8 +58,8 @@ begin arith : if Arith_en = 1 generate MACinst : MAC -generic map(Input_SZ_1,Input_SZ_2) +generic map(Input_SZ_1,Input_SZ_2,COMP_EN) port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); end generate; -end architecture; \ No newline at end of file +end architecture; diff --git a/lib/lpp/general_purpose/MAC.vhd b/lib/lpp/general_purpose/MAC.vhd --- a/lib/lpp/general_purpose/MAC.vhd +++ b/lib/lpp/general_purpose/MAC.vhd @@ -32,7 +32,8 @@ USE lpp.general_purpose.ALL; ENTITY MAC IS GENERIC( Input_SZ_A : INTEGER := 8; - Input_SZ_B : INTEGER := 8 + Input_SZ_B : INTEGER := 8; + COMP_EN : INTEGER := 0 -- 1 => No Comp ); PORT( @@ -52,35 +53,35 @@ END MAC; ARCHITECTURE ar_MAC OF MAC IS -signal add,mult : std_logic; -signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + SIGNAL add, mult : STD_LOGIC; + SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); -signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); -signal MACMUXsel : std_logic; -signal OP1_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal OP2_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + SIGNAL MACMUXsel : STD_LOGIC; + SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); -signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0); -signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0); + SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); -signal MACMUX2sel : std_logic; + SIGNAL MACMUX2sel : STD_LOGIC; -signal add_D : std_logic; -signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0); -signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0); -signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal MACMUXsel_D : std_logic; -signal MACMUX2sel_D : std_logic; -signal MACMUX2sel_D_D : std_logic; -signal clr_MAC_D : std_logic; -signal clr_MAC_D_D : std_logic; -signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0); + SIGNAL add_D : STD_LOGIC; + SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL MACMUXsel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D_D : STD_LOGIC; + SIGNAL clr_MAC_D : STD_LOGIC; + SIGNAL clr_MAC_D_D : STD_LOGIC; + SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); -SIGNAL load_mult_result : STD_LOGIC; -SIGNAL load_mult_result_D : STD_LOGIC; + SIGNAL load_mult_result : STD_LOGIC; + SIGNAL load_mult_result_D : STD_LOGIC; BEGIN @@ -113,25 +114,25 @@ BEGIN Input_SZ_A => Input_SZ_A, Input_SZ_B => Input_SZ_B ) -port map( - clk => clk, - reset => reset, - mult => mult, - OP1 => OP1_2C, - OP2 => OP2_2C, - RES => MULTout -); + PORT MAP( + clk => clk, + reset => reset, + mult => mult, + OP1 => OP1_2C, + OP2 => OP2_2C, + RES => MULTout + ); --============================================================== PROCESS (clk, reset) BEGIN -- PROCESS IF reset = '0' THEN -- asynchronous reset (active low) load_mult_result_D <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge load_mult_result_D <= load_mult_result; END IF; END PROCESS; - + --============================================================== --======================A D D E R ============================== --============================================================== @@ -154,32 +155,38 @@ port map( --============================================================== --===================TWO COMPLEMENTERS========================== --============================================================== -TWO_COMPLEMENTER1 : TwoComplementer -generic map( - Input_SZ => Input_SZ_A -) -port map( - clk => clk, - reset => reset, - clr => clr_MAC, - TwoComp => Comp_2C(0), - OP => OP1, - RES => OP1_2C -); + gen_comp : IF COMP_EN = 0 GENERATE + TWO_COMPLEMENTER1 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_A + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(0), + OP => OP1, + RES => OP1_2C + ); - -TWO_COMPLEMENTER2 : TwoComplementer -generic map( - Input_SZ => Input_SZ_B -) -port map( - clk => clk, - reset => reset, - clr => clr_MAC, - TwoComp => Comp_2C(1), - OP => OP2, - RES => OP2_2C -); + TWO_COMPLEMENTER2 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(1), + OP => OP2, + RES => OP2_2C + ); + END GENERATE gen_comp; + + no_gen_comp : IF COMP_EN = 1 GENERATE + OP2_2C <= OP2; + OP1_2C <= OP1; + END GENERATE no_gen_comp; --============================================================== clr_MACREG1 : MAC_REG @@ -200,24 +207,24 @@ port map( Q(0) => add_D ); -OP1REG : MAC_REG -generic map(size => Input_SZ_A) -port map( - reset => reset, - clk => clk, - D => OP1_2C, - Q => OP1_2C_D -); + OP1REG : MAC_REG + GENERIC MAP(size => Input_SZ_A) + PORT MAP( + reset => reset, + clk => clk, + D => OP1_2C, + Q => OP1_2C_D + ); -OP2REG : MAC_REG -generic map(size => Input_SZ_B) -port map( - reset => reset, - clk => clk, - D => OP2_2C, - Q => OP2_2C_D -); + OP2REG : MAC_REG + GENERIC MAP(size => Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => OP2_2C, + Q => OP2_2C_D + ); MULToutREG : MAC_REG GENERIC MAP(size => Input_SZ_A+Input_SZ_B) diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -83,7 +83,8 @@ PACKAGE general_purpose IS Arith_en : INTEGER := 1; Logic_en : INTEGER := 1; Input_SZ_1 : INTEGER := 16; - Input_SZ_2 : INTEGER := 9 + Input_SZ_2 : INTEGER := 9; + COMP_EN : INTEGER := 0 -- 1 => No Comp ); PORT( @@ -110,7 +111,8 @@ Constant ctrl_CLRMAC : std_logic_vector( COMPONENT MAC IS GENERIC( Input_SZ_A : INTEGER := 8; - Input_SZ_B : INTEGER := 8 + Input_SZ_B : INTEGER := 8; + COMP_EN : INTEGER := 0 -- 1 => No Comp ); PORT( clk : IN STD_LOGIC; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd @@ -1,303 +1,303 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_top_acq IS - GENERIC( - tech : INTEGER := 0 - ); - PORT ( - -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- - cnv_clk : IN STD_LOGIC; -- 49 MHz - cnv_rstn : IN STD_LOGIC; - -- - clk : IN STD_LOGIC; -- 25 MHz - rstn : IN STD_LOGIC; - -- - sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) - ); -END lpp_top_acq; - -ARCHITECTURE tb OF lpp_top_acq IS - - COMPONENT Downsampling - GENERIC ( - ChanelCount : INTEGER; - SampleSize : INTEGER; - DivideParam : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_in_val : IN STD_LOGIC; - sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); - sample_out_val : OUT STD_LOGIC; - sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); - END COMPONENT; - - ----------------------------------------------------------------------------- - CONSTANT ChanelCount : INTEGER := 8; - CONSTANT ncycle_cnv_high : INTEGER := 79; - CONSTANT ncycle_cnv : INTEGER := 500; - - ----------------------------------------------------------------------------- - SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL sample_val_delay : STD_LOGIC; - ----------------------------------------------------------------------------- - CONSTANT Coef_SZ : INTEGER := 9; - CONSTANT CoefCntPerCel : INTEGER := 6; - CONSTANT CoefPerCel : INTEGER := 5; - CONSTANT Cels_count : INTEGER := 5; - - SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_val : STD_LOGIC; - SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; - SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL sample_downsampling_out_val : STD_LOGIC; - SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f2_val : STD_LOGIC; - SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -BEGIN - - -- component instantiation - ----------------------------------------------------------------------------- - DIGITAL_acquisition : ADS7886_drvr - GENERIC MAP ( - ChanelCount => ChanelCount, - ncycle_cnv_high => ncycle_cnv_high, - ncycle_cnv => ncycle_cnv) - PORT MAP ( - cnv_clk => cnv_clk, -- - cnv_rstn => cnv_rstn, -- - cnv_run => cnv_run, -- - cnv => cnv, -- - clk => clk, -- - rstn => rstn, -- - sck => sck, -- - sdo => sdo(ChanelCount-1 DOWNTO 0), -- - sample => sample, - sample_val => sample_val); - - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_val_delay <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_val_delay <= sample_val; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE - SampleLoop : FOR j IN 0 TO 15 GENERATE - sample_filter_in(i, j) <= sample(i)(j); - END GENERATE; - - sample_filter_in(i, 16) <= sample(i)(15); - sample_filter_in(i, 17) <= sample(i)(15); - END GENERATE; - - coefs_v2 <= CoefsInitValCst_v2; - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - GENERIC MAP ( - tech => 0, - Mem_use => use_RAM, - Sample_SZ => 18, - Coef_SZ => Coef_SZ, - Coef_Nb => 25, -- TODO - Coef_sel_SZ => 5, -- TODO - Cels_count => Cels_count, - ChanelsCount => ChanelCount) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => 7, - coefs => coefs_v2, - sample_in_val => sample_val_delay, - sample_in => sample_filter_in, - sample_out_val => sample_filter_v2_out_val, - sample_out => sample_filter_v2_out); - - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_filter_v2_out_r_val <= '0'; - rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP - rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP - sample_filter_v2_out_r(I, J) <= '0'; - END LOOP rst_all_bits; - END LOOP rst_all_chanel; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_filter_v2_out_r_val <= sample_filter_v2_out_val; - IF sample_filter_v2_out_val = '1' THEN - sample_filter_v2_out_r <= sample_filter_v2_out; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- F0 -- @24.576 kHz - ----------------------------------------------------------------------------- - Downsampling_f0 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 4) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_filter_v2_out_val , - sample_in => sample_filter_v2_out, - sample_out_val => sample_f0_val, - sample_out => sample_f0); - - all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_wdata(I) <= sample_f0(0, I); - sample_f0_wdata(16*1+I) <= sample_f0(1, I); - sample_f0_wdata(16*2+I) <= sample_f0(2, I); - sample_f0_wdata(16*3+I) <= sample_f0(6, I); - sample_f0_wdata(16*4+I) <= sample_f0(7, I); - END GENERATE all_bit_sample_f0; - - sample_f0_wen <= NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val); - - ----------------------------------------------------------------------------- - -- F1 -- @4096 Hz - ----------------------------------------------------------------------------- - Downsampling_f1 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 6) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f1_val, - sample_out => sample_f1); - - sample_f1_wen <= NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val); - - all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_wdata(I) <= sample_f1(0, I); - sample_f1_wdata(16*1+I) <= sample_f1(1, I); - sample_f1_wdata(16*2+I) <= sample_f1(2, I); - sample_f1_wdata(16*3+I) <= sample_f1(6, I); - sample_f1_wdata(16*4+I) <= sample_f1(7, I); - END GENERATE all_bit_sample_f1; - - ----------------------------------------------------------------------------- - -- F2 -- @16 Hz - ----------------------------------------------------------------------------- - Downsampling_f2 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 256) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f1_val , - sample_in => sample_f1, - sample_out_val => sample_f2_val, - sample_out => sample_f2); - - sample_f2_wen <= NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val); - - all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f2_wdata(I) <= sample_f2(0, I); - sample_f2_wdata(16*1+I) <= sample_f2(1, I); - sample_f2_wdata(16*2+I) <= sample_f2(2, I); - sample_f2_wdata(16*3+I) <= sample_f2(6, I); - sample_f2_wdata(16*4+I) <= sample_f2(7, I); - END GENERATE all_bit_sample_f2; - - ----------------------------------------------------------------------------- - -- F3 -- @256 Hz - ----------------------------------------------------------------------------- - Downsampling_f3 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 96) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f3_val, - sample_out => sample_f3); - - sample_f3_wen <= (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val); - - all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f3_wdata(I) <= sample_f3(0, I); - sample_f3_wdata(16*1+I) <= sample_f3(1, I); - sample_f3_wdata(16*2+I) <= sample_f3(2, I); - sample_f3_wdata(16*3+I) <= sample_f3(6, I); - sample_f3_wdata(16*4+I) <= sample_f3(7, I); - END GENERATE all_bit_sample_f3; - - - -END tb; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_top_acq IS + GENERIC( + tech : INTEGER := 0 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; -- 49 MHz + cnv_rstn : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; -- 25 MHz + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) + ); +END lpp_top_acq; + +ARCHITECTURE tb OF lpp_top_acq IS + + COMPONENT Downsampling + GENERIC ( + ChanelCount : INTEGER; + SampleSize : INTEGER; + DivideParam : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + CONSTANT ChanelCount : INTEGER := 8; + CONSTANT ncycle_cnv_high : INTEGER := 79; + CONSTANT ncycle_cnv : INTEGER := 500; + + ----------------------------------------------------------------------------- + SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL sample_val_delay : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; + SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL sample_downsampling_out_val : STD_LOGIC; + SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_f3_val : STD_LOGIC; + SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + +BEGIN + + -- component instantiation + ----------------------------------------------------------------------------- + DIGITAL_acquisition : AD7688_drvr + GENERIC MAP ( + ChanelCount => ChanelCount, + ncycle_cnv_high => ncycle_cnv_high, + ncycle_cnv => ncycle_cnv) + PORT MAP ( + cnv_clk => cnv_clk, -- + cnv_rstn => cnv_rstn, -- + cnv_run => cnv_run, -- + cnv => cnv, -- + clk => clk, -- + rstn => rstn, -- + sck => sck, -- + sdo => sdo(ChanelCount-1 DOWNTO 0), -- + sample => sample, + sample_val => sample_val); + + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val_delay <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_val_delay <= sample_val; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE + SampleLoop : FOR j IN 0 TO 15 GENERATE + sample_filter_in(i, j) <= sample(i)(j); + END GENERATE; + + sample_filter_in(i, 16) <= sample(i)(15); + sample_filter_in(i, 17) <= sample(i)(15); + END GENERATE; + + coefs_v2 <= CoefsInitValCst_v2; + + IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + GENERIC MAP ( + tech => 0, + Mem_use => use_CEL, + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, -- TODO + Coef_sel_SZ => 5, -- TODO + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => coefs_v2, + sample_in_val => sample_val_delay, + sample_in => sample_filter_in, + sample_out_val => sample_filter_v2_out_val, + sample_out => sample_filter_v2_out); + + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_filter_v2_out_r_val <= '0'; + rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP + rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP + sample_filter_v2_out_r(I, J) <= '0'; + END LOOP rst_all_bits; + END LOOP rst_all_chanel; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_filter_v2_out_r_val <= sample_filter_v2_out_val; + IF sample_filter_v2_out_val = '1' THEN + sample_filter_v2_out_r <= sample_filter_v2_out; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- F0 -- @24.576 kHz + ----------------------------------------------------------------------------- + Downsampling_f0 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_filter_v2_out_val , + sample_in => sample_filter_v2_out, + sample_out_val => sample_f0_val, + sample_out => sample_f0); + + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_wdata(I) <= sample_f0(0, I); + sample_f0_wdata(16*1+I) <= sample_f0(1, I); + sample_f0_wdata(16*2+I) <= sample_f0(2, I); + sample_f0_wdata(16*3+I) <= sample_f0(6, I); + sample_f0_wdata(16*4+I) <= sample_f0(7, I); + END GENERATE all_bit_sample_f0; + + sample_f0_wen <= NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val); + + ----------------------------------------------------------------------------- + -- F1 -- @4096 Hz + ----------------------------------------------------------------------------- + Downsampling_f1 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 6) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f1_val, + sample_out => sample_f1); + + sample_f1_wen <= NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val); + + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata(I) <= sample_f1(0, I); + sample_f1_wdata(16*1+I) <= sample_f1(1, I); + sample_f1_wdata(16*2+I) <= sample_f1(2, I); + sample_f1_wdata(16*3+I) <= sample_f1(6, I); + sample_f1_wdata(16*4+I) <= sample_f1(7, I); + END GENERATE all_bit_sample_f1; + + ----------------------------------------------------------------------------- + -- F2 -- @16 Hz + ----------------------------------------------------------------------------- + Downsampling_f2 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 256) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f1_val , + sample_in => sample_f1, + sample_out_val => sample_f2_val, + sample_out => sample_f2); + + sample_f2_wen <= NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val); + + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f2_wdata(I) <= sample_f2(0, I); + sample_f2_wdata(16*1+I) <= sample_f2(1, I); + sample_f2_wdata(16*2+I) <= sample_f2(2, I); + sample_f2_wdata(16*3+I) <= sample_f2(6, I); + sample_f2_wdata(16*4+I) <= sample_f2(7, I); + END GENERATE all_bit_sample_f2; + + ----------------------------------------------------------------------------- + -- F3 -- @256 Hz + ----------------------------------------------------------------------------- + Downsampling_f3 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 96) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f3_val, + sample_out => sample_f3); + + sample_f3_wen <= (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val); + + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f3_wdata(I) <= sample_f3(0, I); + sample_f3_wdata(16*1+I) <= sample_f3(1, I); + sample_f3_wdata(16*2+I) <= sample_f3(2, I); + sample_f3_wdata(16*3+I) <= sample_f3(6, I); + sample_f3_wdata(16*4+I) <= sample_f3(7, I); + END GENERATE all_bit_sample_f3; + + + +END tb;