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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.stdlib.ALL;
28 LIBRARY gaisler;
29 USE gaisler.libdcom.ALL;
30 USE gaisler.sim.ALL;
31 USE gaisler.jtagtst.ALL;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
34 LIBRARY lpp;
35 USE lpp.lpp_sim_pkg.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
38
39 PACKAGE lpp_lfr_sim_pkg IS
40
41 PROCEDURE UNRESET_LFR (
42 SIGNAL TX : OUT STD_LOGIC;
43 CONSTANT tx_period : IN TIME;
44 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
45 );
46
47 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
48 SIGNAL TX : OUT STD_LOGIC;
49 SIGNAL RX : IN STD_LOGIC;
50 CONSTANT tx_period : IN TIME;
51 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
52 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
55 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
56 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
58 );
59
60 -----------------------------------------------------------------------------
61 -- SM function
62 -----------------------------------------------------------------------------
63
64 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
65 SIGNAL TX : OUT STD_LOGIC;
66 SIGNAL RX : IN STD_LOGIC;
67 CONSTANT tx_period : IN TIME;
68 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
69 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
75 );
76
77 PROCEDURE SET_SM_IRQ_onNewMatrix(
78 SIGNAL TX : OUT STD_LOGIC;
79 SIGNAL RX : IN STD_LOGIC;
80 CONSTANT tx_period : IN TIME;
81 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
82 CONSTANT PARAM_value : IN STD_LOGIC
83 );
84
85 PROCEDURE SET_SM_IRQ_ERROR(
86 SIGNAL TX : OUT STD_LOGIC;
87 SIGNAL RX : IN STD_LOGIC;
88 CONSTANT tx_period : IN TIME;
89 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
90 CONSTANT PARAM_value : IN STD_LOGIC
91 );
92
93 PROCEDURE RESET_SM_STATUS(
94 SIGNAL TX : OUT STD_LOGIC;
95 SIGNAL RX : IN STD_LOGIC;
96 CONSTANT tx_period : IN TIME;
97 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
98 );
99
100 END lpp_lfr_sim_pkg;
101
102
103
104 PACKAGE BODY lpp_lfr_sim_pkg IS
105
106 PROCEDURE UNRESET_LFR (
107 SIGNAL TX : OUT STD_LOGIC;
108 CONSTANT tx_period : IN TIME;
109 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
110 IS
111 BEGIN
112 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
113 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
114 END;
115
116 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
117 SIGNAL TX : OUT STD_LOGIC;
118 SIGNAL RX : IN STD_LOGIC;
119 CONSTANT tx_period : IN TIME;
120 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
121 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
122 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
123 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
124 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
125 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
126 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
127 )
128 IS
129 BEGIN
130 RESET_SPECTRAL_MATRIX_REGS(TX,RX,tx_period,ADDR_BASE_LFR,
131 PARAM_SM_f0_0_addr, PARAM_SM_f0_1_addr, PARAM_SM_f1_0_addr,
132 PARAM_SM_f1_1_addr, PARAM_SM_f2_0_addr, PARAM_SM_f2_1_addr);
133 SET_SM_IRQ_onNewMatrix (TX,RX,tx_period,ADDR_BASE_LFR,
134 '1');
135 END;
136
137 -----------------------------------------------------------------------------
138 -- SM function
139 -----------------------------------------------------------------------------
140 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
141 SIGNAL TX : OUT STD_LOGIC;
142 SIGNAL RX : IN STD_LOGIC;
143 CONSTANT tx_period : IN TIME;
144 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
145 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
149 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
150 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
151 )
152 IS
153 BEGIN
154 SET_SM_IRQ_ERROR (TX,RX,tx_period,ADDR_BASE_LFR,'0');
155 SET_SM_IRQ_onNewMatrix(TX,RX,tx_period,ADDR_BASE_LFR,'0');
156 RESET_SM_STATUS (TX,RX,tx_period,ADDR_BASE_LFR);
157 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR,PARAM_SM_f0_0_addr);
158 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_1_ADDR,PARAM_SM_f0_1_addr);
159 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_0_ADDR,PARAM_SM_f1_0_addr);
160 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_1_ADDR,PARAM_SM_f1_1_addr);
161 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_0_ADDR,PARAM_SM_f2_0_addr);
162 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_1_ADDR,PARAM_SM_f2_1_addr);
163 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_LENGTH ,X"000000C8");
164 END;
165
166 PROCEDURE SET_SM_IRQ_onNewMatrix(
167 SIGNAL TX : OUT STD_LOGIC;
168 SIGNAL RX : IN STD_LOGIC;
169 CONSTANT tx_period : IN TIME;
170 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
171 CONSTANT PARAM_value : IN STD_LOGIC
172 )
173 IS
174 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 BEGIN
176 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
177 IF PARAM_value = '1' THEN
178 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '1' );
179 ELSE
180 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '0' );
181 END IF;
182 END;
183
184 PROCEDURE SET_SM_IRQ_ERROR(
185 SIGNAL TX : OUT STD_LOGIC;
186 SIGNAL RX : IN STD_LOGIC;
187 CONSTANT tx_period : IN TIME;
188 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
189 CONSTANT PARAM_value : IN STD_LOGIC
190 )
191 IS
192 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 BEGIN
194 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
195 IF PARAM_value = '1' THEN
196 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '1' & data_read(0) );
197 ELSE
198 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '0' & data_read(0) );
199 END IF;
200 END;
201
202 PROCEDURE RESET_SM_STATUS(
203 SIGNAL TX : OUT STD_LOGIC;
204 SIGNAL RX : IN STD_LOGIC;
205 CONSTANT tx_period : IN TIME;
206 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
207 )
208 IS
209 BEGIN
210 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, X"000007FF");
211 END;
212
213 END lpp_lfr_sim_pkg;
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@@ -1,280 +1,297
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
5 LIBRARY STD;
6 use std.textio.all;
6 use std.textio.all;
7
7
8 LIBRARY grlib;
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 LIBRARY lpp;
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
22
22
23
23
24 ENTITY testbench IS
24 ENTITY testbench IS
25 END;
25 END;
26
26
27 ARCHITECTURE behav OF testbench IS
27 ARCHITECTURE behav OF testbench IS
28
28
29 COMPONENT MINI_LFR_top
29 COMPONENT MINI_LFR_top
30 PORT (
30 PORT (
31 clk_50 : IN STD_LOGIC;
31 clk_50 : IN STD_LOGIC;
32 clk_49 : IN STD_LOGIC;
32 clk_49 : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
73 SRAM_nWE : OUT STD_LOGIC;
73 SRAM_nWE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
79 END COMPONENT;
79 END COMPONENT;
80
80
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 SIGNAL clk_50 : STD_LOGIC := '0';
82 SIGNAL clk_50 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
84 SIGNAL reset : STD_LOGIC;
84 SIGNAL reset : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
90 SIGNAL TXD1 : STD_LOGIC;
90 SIGNAL TXD1 : STD_LOGIC;
91 SIGNAL RXD1 : STD_LOGIC;
91 SIGNAL RXD1 : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
124 SIGNAL SRAM_nWE : STD_LOGIC;
124 SIGNAL SRAM_nWE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
131
131
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
135
135
136
136
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
138
138
139 SIGNAL data_message : STRING(1 TO 15) := "---------------";
139 SIGNAL data_message : STRING(1 TO 15) := "---------------";
140 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
140 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
141
141
142 BEGIN
142 BEGIN
143
143
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145 -- TB
145 -- TB
146 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
147 PROCESS
147 PROCESS
148 CONSTANT txp : TIME := 320 ns;
148 CONSTANT txp : TIME := 320 ns;
149 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 BEGIN -- PROCESS
150 BEGIN -- PROCESS
151 TXD1 <= '1';
151 TXD1 <= '1';
152 reset <= '0';
152 reset <= '0';
153 WAIT FOR 500 ns;
153 WAIT FOR 500 ns;
154 reset <= '1';
154 reset <= '1';
155 WAIT FOR 10000 ns;
155 WAIT FOR 10000 ns;
156 message_simu <= "0 - UART init ";
156 message_simu <= "0 - UART init ";
157 UART_INIT(TXD1,txp);
157 UART_INIT(TXD1,txp);
158
158
159 message_simu <= "1 - UART test ";
159 message_simu <= "1 - UART test ";
160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
162 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
162 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
163 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
163 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
164 data_read <= data_read_v;
164 data_read <= data_read_v;
165 data_message <= "GPIO_data_write";
165 data_message <= "GPIO_data_write";
166
166
167 -- UNSET the LFR reset
167 -- UNSET the LFR reset
168 message_simu <= "2 - LFR UNRESET";
168 message_simu <= "2 - LFR UNRESET";
169 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
169 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
171 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
171 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
172 --
172 --
173 message_simu <= "3 - LFR CONFIG ";
173 message_simu <= "3 - LFR CONFIG ";
174 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
174 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
175 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
176 X"40000000",
177 X"40001000",
178 X"40002000",
179 X"40003000",
180 X"40004000",
181 X"40005000");
182 message_simu <= "4 - GO GO GO !!";
183 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
184
185 READ_STATUS: LOOP
186 WAIT FOR 2 ms;
187 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
188 data_read <= data_read_v;
189 data_message <= "READ_NEW_STATUS";
190 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
191 END LOOP READ_STATUS;
175
192
176 WAIT;
193 WAIT;
177 END PROCESS;
194 END PROCESS;
178
195
179 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
180 -- CLOCK
197 -- CLOCK
181 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
182 clk_50 <= NOT clk_50 AFTER 5 ns;
199 clk_50 <= NOT clk_50 AFTER 5 ns;
183 clk_49 <= NOT clk_49 AFTER 10172 ps;
200 clk_49 <= NOT clk_49 AFTER 10172 ps;
184
201
185 -----------------------------------------------------------------------------
202 -----------------------------------------------------------------------------
186 -- DON'T CARE
203 -- DON'T CARE
187 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
188 BP0 <= '0';
205 BP0 <= '0';
189 BP1 <= '0';
206 BP1 <= '0';
190 nRTS1 <= '0' ;
207 nRTS1 <= '0' ;
191
208
192 TXD2 <= '1';
209 TXD2 <= '1';
193 nRTS2 <= '1';
210 nRTS2 <= '1';
194 nDTR2 <= '1';
211 nDTR2 <= '1';
195
212
196 SPW_NOM_DIN <= '1';
213 SPW_NOM_DIN <= '1';
197 SPW_NOM_SIN <= '1';
214 SPW_NOM_SIN <= '1';
198 SPW_RED_DIN <= '1';
215 SPW_RED_DIN <= '1';
199 SPW_RED_SIN <= '1';
216 SPW_RED_SIN <= '1';
200
217
201 ADC_SDO <= x"AA";
218 ADC_SDO <= x"AA";
202
219
203 SRAM_DQ <= (OTHERS => 'Z');
220 SRAM_DQ <= (OTHERS => 'Z');
204 --IO0 <= 'Z';
221 --IO0 <= 'Z';
205 --IO1 <= 'Z';
222 --IO1 <= 'Z';
206 --IO2 <= 'Z';
223 --IO2 <= 'Z';
207 --IO3 <= 'Z';
224 --IO3 <= 'Z';
208 --IO4 <= 'Z';
225 --IO4 <= 'Z';
209 --IO5 <= 'Z';
226 --IO5 <= 'Z';
210 --IO6 <= 'Z';
227 --IO6 <= 'Z';
211 --IO7 <= 'Z';
228 --IO7 <= 'Z';
212 --IO8 <= 'Z';
229 --IO8 <= 'Z';
213 --IO9 <= 'Z';
230 --IO9 <= 'Z';
214 --IO10 <= 'Z';
231 --IO10 <= 'Z';
215 --IO11 <= 'Z';
232 --IO11 <= 'Z';
216
233
217 -----------------------------------------------------------------------------
234 -----------------------------------------------------------------------------
218 -- DUT
235 -- DUT
219 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
220 MINI_LFR_top_1: MINI_LFR_top
237 MINI_LFR_top_1: MINI_LFR_top
221 PORT MAP (
238 PORT MAP (
222 clk_50 => clk_50,
239 clk_50 => clk_50,
223 clk_49 => clk_49,
240 clk_49 => clk_49,
224 reset => reset,
241 reset => reset,
225
242
226 BP0 => BP0,
243 BP0 => BP0,
227 BP1 => BP1,
244 BP1 => BP1,
228
245
229 LED0 => LED0,
246 LED0 => LED0,
230 LED1 => LED1,
247 LED1 => LED1,
231 LED2 => LED2,
248 LED2 => LED2,
232
249
233 TXD1 => TXD1,
250 TXD1 => TXD1,
234 RXD1 => RXD1,
251 RXD1 => RXD1,
235 nCTS1 => nCTS1,
252 nCTS1 => nCTS1,
236 nRTS1 => nRTS1,
253 nRTS1 => nRTS1,
237
254
238 TXD2 => TXD2,
255 TXD2 => TXD2,
239 RXD2 => RXD2,
256 RXD2 => RXD2,
240 nCTS2 => nCTS2,
257 nCTS2 => nCTS2,
241 nDTR2 => nDTR2,
258 nDTR2 => nDTR2,
242 nRTS2 => nRTS2,
259 nRTS2 => nRTS2,
243 nDCD2 => nDCD2,
260 nDCD2 => nDCD2,
244
261
245 IO0 => IO0,
262 IO0 => IO0,
246 IO1 => IO1,
263 IO1 => IO1,
247 IO2 => IO2,
264 IO2 => IO2,
248 IO3 => IO3,
265 IO3 => IO3,
249 IO4 => IO4,
266 IO4 => IO4,
250 IO5 => IO5,
267 IO5 => IO5,
251 IO6 => IO6,
268 IO6 => IO6,
252 IO7 => IO7,
269 IO7 => IO7,
253 IO8 => IO8,
270 IO8 => IO8,
254 IO9 => IO9,
271 IO9 => IO9,
255 IO10 => IO10,
272 IO10 => IO10,
256 IO11 => IO11,
273 IO11 => IO11,
257
274
258 SPW_EN => SPW_EN,
275 SPW_EN => SPW_EN,
259 SPW_NOM_DIN => SPW_NOM_DIN,
276 SPW_NOM_DIN => SPW_NOM_DIN,
260 SPW_NOM_SIN => SPW_NOM_SIN,
277 SPW_NOM_SIN => SPW_NOM_SIN,
261 SPW_NOM_DOUT => SPW_NOM_DOUT,
278 SPW_NOM_DOUT => SPW_NOM_DOUT,
262 SPW_NOM_SOUT => SPW_NOM_SOUT,
279 SPW_NOM_SOUT => SPW_NOM_SOUT,
263 SPW_RED_DIN => SPW_RED_DIN,
280 SPW_RED_DIN => SPW_RED_DIN,
264 SPW_RED_SIN => SPW_RED_SIN,
281 SPW_RED_SIN => SPW_RED_SIN,
265 SPW_RED_DOUT => SPW_RED_DOUT,
282 SPW_RED_DOUT => SPW_RED_DOUT,
266 SPW_RED_SOUT => SPW_RED_SOUT,
283 SPW_RED_SOUT => SPW_RED_SOUT,
267
284
268 ADC_nCS => ADC_nCS,
285 ADC_nCS => ADC_nCS,
269 ADC_CLK => ADC_CLK,
286 ADC_CLK => ADC_CLK,
270 ADC_SDO => ADC_SDO,
287 ADC_SDO => ADC_SDO,
271
288
272 SRAM_nWE => SRAM_nWE,
289 SRAM_nWE => SRAM_nWE,
273 SRAM_CE => SRAM_CE,
290 SRAM_CE => SRAM_CE,
274 SRAM_nOE => SRAM_nOE,
291 SRAM_nOE => SRAM_nOE,
275 SRAM_nBE => SRAM_nBE,
292 SRAM_nBE => SRAM_nBE,
276 SRAM_A => SRAM_A,
293 SRAM_A => SRAM_A,
277 SRAM_DQ => SRAM_DQ);
294 SRAM_DQ => SRAM_DQ);
278
295
279
296
280 END;
297 END;
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