##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

sauvegarde
pellion -
r469:28e2bc810da9 JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,213
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.stdlib.ALL;
28 LIBRARY gaisler;
29 USE gaisler.libdcom.ALL;
30 USE gaisler.sim.ALL;
31 USE gaisler.jtagtst.ALL;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
34 LIBRARY lpp;
35 USE lpp.lpp_sim_pkg.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
38
39 PACKAGE lpp_lfr_sim_pkg IS
40
41 PROCEDURE UNRESET_LFR (
42 SIGNAL TX : OUT STD_LOGIC;
43 CONSTANT tx_period : IN TIME;
44 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
45 );
46
47 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
48 SIGNAL TX : OUT STD_LOGIC;
49 SIGNAL RX : IN STD_LOGIC;
50 CONSTANT tx_period : IN TIME;
51 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
52 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
55 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
56 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
58 );
59
60 -----------------------------------------------------------------------------
61 -- SM function
62 -----------------------------------------------------------------------------
63
64 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
65 SIGNAL TX : OUT STD_LOGIC;
66 SIGNAL RX : IN STD_LOGIC;
67 CONSTANT tx_period : IN TIME;
68 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
69 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
75 );
76
77 PROCEDURE SET_SM_IRQ_onNewMatrix(
78 SIGNAL TX : OUT STD_LOGIC;
79 SIGNAL RX : IN STD_LOGIC;
80 CONSTANT tx_period : IN TIME;
81 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
82 CONSTANT PARAM_value : IN STD_LOGIC
83 );
84
85 PROCEDURE SET_SM_IRQ_ERROR(
86 SIGNAL TX : OUT STD_LOGIC;
87 SIGNAL RX : IN STD_LOGIC;
88 CONSTANT tx_period : IN TIME;
89 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
90 CONSTANT PARAM_value : IN STD_LOGIC
91 );
92
93 PROCEDURE RESET_SM_STATUS(
94 SIGNAL TX : OUT STD_LOGIC;
95 SIGNAL RX : IN STD_LOGIC;
96 CONSTANT tx_period : IN TIME;
97 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
98 );
99
100 END lpp_lfr_sim_pkg;
101
102
103
104 PACKAGE BODY lpp_lfr_sim_pkg IS
105
106 PROCEDURE UNRESET_LFR (
107 SIGNAL TX : OUT STD_LOGIC;
108 CONSTANT tx_period : IN TIME;
109 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
110 IS
111 BEGIN
112 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
113 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
114 END;
115
116 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
117 SIGNAL TX : OUT STD_LOGIC;
118 SIGNAL RX : IN STD_LOGIC;
119 CONSTANT tx_period : IN TIME;
120 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
121 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
122 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
123 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
124 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
125 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
126 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
127 )
128 IS
129 BEGIN
130 RESET_SPECTRAL_MATRIX_REGS(TX,RX,tx_period,ADDR_BASE_LFR,
131 PARAM_SM_f0_0_addr, PARAM_SM_f0_1_addr, PARAM_SM_f1_0_addr,
132 PARAM_SM_f1_1_addr, PARAM_SM_f2_0_addr, PARAM_SM_f2_1_addr);
133 SET_SM_IRQ_onNewMatrix (TX,RX,tx_period,ADDR_BASE_LFR,
134 '1');
135 END;
136
137 -----------------------------------------------------------------------------
138 -- SM function
139 -----------------------------------------------------------------------------
140 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
141 SIGNAL TX : OUT STD_LOGIC;
142 SIGNAL RX : IN STD_LOGIC;
143 CONSTANT tx_period : IN TIME;
144 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
145 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
149 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
150 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
151 )
152 IS
153 BEGIN
154 SET_SM_IRQ_ERROR (TX,RX,tx_period,ADDR_BASE_LFR,'0');
155 SET_SM_IRQ_onNewMatrix(TX,RX,tx_period,ADDR_BASE_LFR,'0');
156 RESET_SM_STATUS (TX,RX,tx_period,ADDR_BASE_LFR);
157 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR,PARAM_SM_f0_0_addr);
158 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_1_ADDR,PARAM_SM_f0_1_addr);
159 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_0_ADDR,PARAM_SM_f1_0_addr);
160 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_1_ADDR,PARAM_SM_f1_1_addr);
161 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_0_ADDR,PARAM_SM_f2_0_addr);
162 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_1_ADDR,PARAM_SM_f2_1_addr);
163 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_LENGTH ,X"000000C8");
164 END;
165
166 PROCEDURE SET_SM_IRQ_onNewMatrix(
167 SIGNAL TX : OUT STD_LOGIC;
168 SIGNAL RX : IN STD_LOGIC;
169 CONSTANT tx_period : IN TIME;
170 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
171 CONSTANT PARAM_value : IN STD_LOGIC
172 )
173 IS
174 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 BEGIN
176 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
177 IF PARAM_value = '1' THEN
178 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '1' );
179 ELSE
180 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '0' );
181 END IF;
182 END;
183
184 PROCEDURE SET_SM_IRQ_ERROR(
185 SIGNAL TX : OUT STD_LOGIC;
186 SIGNAL RX : IN STD_LOGIC;
187 CONSTANT tx_period : IN TIME;
188 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
189 CONSTANT PARAM_value : IN STD_LOGIC
190 )
191 IS
192 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 BEGIN
194 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
195 IF PARAM_value = '1' THEN
196 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '1' & data_read(0) );
197 ELSE
198 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '0' & data_read(0) );
199 END IF;
200 END;
201
202 PROCEDURE RESET_SM_STATUS(
203 SIGNAL TX : OUT STD_LOGIC;
204 SIGNAL RX : IN STD_LOGIC;
205 CONSTANT tx_period : IN TIME;
206 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
207 )
208 IS
209 BEGIN
210 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, X"000007FF");
211 END;
212
213 END lpp_lfr_sim_pkg;
Show file before | Show file after | Hide comments
@@ -171,7 +171,24 BEGIN
171 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
171 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
172 --
172 --
173 message_simu <= "3 - LFR CONFIG ";
173 message_simu <= "3 - LFR CONFIG ";
174 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
174 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
175 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
176 X"40000000",
177 X"40001000",
178 X"40002000",
179 X"40003000",
180 X"40004000",
181 X"40005000");
182 message_simu <= "4 - GO GO GO !!";
183 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
184
185 READ_STATUS: LOOP
186 WAIT FOR 2 ms;
187 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
188 data_read <= data_read_v;
189 data_message <= "READ_NEW_STATUS";
190 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
191 END LOOP READ_STATUS;
175
192
176 WAIT;
193 WAIT;
177 END PROCESS;
194 END PROCESS;
General Comments 0
You need to be logged in to leave comments. Login now