##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Update Matrix Spectral function with 2 fifo inputs (APB and C-driver)
martin -
r95:236e70a254cc martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,128
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity Starter is
27 port(
28 clk : in std_logic;
29 raz : in std_logic;
30 Full : in std_logic_vector(1 downto 0);
31 Empty : in std_logic_vector(1 downto 0);
32 Statu : in std_logic_vector(3 downto 0);
33 Write : in std_logic;
34 Start : out std_logic
35 );
36 end Starter;
37
38
39 architecture ar_Starter of Starter is
40
41 type etat is (eX,e0,e1,e2);
42 signal ect : etat;
43
44 signal Write_reg : std_logic;
45 signal Conjugate : std_logic;
46
47 begin
48 process(clk,raz)
49 begin
50
51 if(raz='0')then
52 Start <= '0';
53 Write_reg <= '0';
54 ect <= eX;
55
56 elsif(clk'event and clk='1')then
57 Write_reg <= Write;
58
59 case ect is
60 when eX =>
61 if(Conjugate='0')then
62 if(full="11")then
63 Start <= '1';
64 ect <= e0;
65 end if;
66 else
67 if(full(0)='1')then
68 Start <= '1';
69 ect <= e0;
70 end if;
71 end if;
72
73 when e0 =>
74 if(Conjugate='0')then
75 if(empty="11")then
76 ect <= e1;
77 end if;
78 else
79 if(empty(0)='1')then
80 ect <= e2;
81 end if;
82 end if;
83
84 when e1 =>
85 if(Write_reg='1' and Write='0')then
86 ect <= e2;
87 end if;
88
89 when e2 =>
90 if(Write_reg='1' and Write='0')then
91 Start <= '0';
92 ect <= eX;
93 end if;
94
95 end case;
96
97 end if;
98 end process;
99
100
101 With Statu select
102 Conjugate <= '1' when "0001",
103 '1' when "0011",
104 '1' when "0110",
105 '1' when "1010",
106 '1' when "1111",
107 '0' when others;
108
109 end ar_Starter;
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Show file before | Show file after | Hide comments
@@ -0,0 +1,62
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26
27 entity Top_MatrixSpec is
28 generic(
29 Input_SZ : integer := 16;
30 Result_SZ : integer := 32);
31 port(
32 clk : in std_logic;
33 reset : in std_logic;
34 Statu : in std_logic_vector(3 downto 0);
35 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
36 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
37 Full : in std_logic_vector(1 downto 0);
38 Empty : in std_logic_vector(1 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 FullFIFO : in std_logic;
41 WriteFIFO : out std_logic;
42 Result : out std_logic_vector(Result_SZ-1 downto 0)
43 );
44 end entity;
45
46
47 architecture ar_Top_MatrixSpec of Top_MatrixSpec is
48
49 signal Start : std_logic;
50 signal Write : std_logic;
51
52 begin
53 WriteFIFO <= Write;
54
55 ST0 : Starter
56 port map(clk,reset,Full,Empty,Statu,Write,Start);
57
58 Mspec : SpectralMatrix
59 generic map(Input_SZ,Result_SZ)
60 port map(clk,reset,Start,FIFO1,FIFO2,Statu,FullFIFO,ReadFIFO,Write,Result);
61
62 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -3,10 +3,9
3 #include "apb_fifo_Driver.h"
3 #include "apb_fifo_Driver.h"
4 #include "apb_Matrix_Driver.h"
4 #include "apb_Matrix_Driver.h"
5 #include "apb_uart_Driver.h"
5 #include "apb_uart_Driver.h"
6 #include "apb_delay_Driver.h"
7 #include "apb_gpio_Driver.h"
6 #include "apb_gpio_Driver.h"
8
7
9 // Matrix With 2 FIFO Input
8 ///////////// Matrix With 2 FIFO Input /////////////////////////////////////////////
10 int main()
9 int main()
11 {
10 {
12 int i=0,save;
11 int i=0,save;
@@ -20,7 +19,6 int main()
20
19
21
20
22 FIFO_Device* fifoX = openFIFO(0);
21 FIFO_Device* fifoX = openFIFO(0);
23 DELAY_Device* delay0 = openDELAY(0);
24 UART_Device* uart0 = openUART(0);
22 UART_Device* uart0 = openUART(0);
25 FIFO_Device* fifoIn = openFIFO(1);
23 FIFO_Device* fifoIn = openFIFO(1);
26 MATRIX_Device* mspec = openMatrix(0);
24 MATRIX_Device* mspec = openMatrix(0);
@@ -29,7 +27,6 int main()
29
27
30 printf("\nDebut Main\n\n");
28 printf("\nDebut Main\n\n");
31
29
32 Setup(delay0,30000000);
33 gpio0->oen = 0x3;
30 gpio0->oen = 0x3;
34 gpio0->Dout = 0x0;
31 gpio0->Dout = 0x0;
35
32
@@ -61,7 +58,6 int main()
61 mspec->Statu = 1;
58 mspec->Statu = 1;
62 FillFifo(fifoIn,0,TblB1);
59 FillFifo(fifoIn,0,TblB1);
63 gpio0->Dout = 0x1;
60 gpio0->Dout = 0x1;
64 Delay_us(delay0,20);
65 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
61 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
66 {
62 {
67 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
63 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
@@ -109,7 +105,7 int main()
109 }
105 }
110
106
111
107
112 // Matrix With 5 FIFO Input
108 ///////////// Matrix With 5 FIFO Input /////////////////////////////////////////////
113 int main2()
109 int main2()
114 {
110 {
115 int save1,save2;
111 int save1,save2;
Show file before | Show file after | Hide comments
@@ -42,11 +42,14 entity APB_Matrix is
42 Input_SZ : integer := 16;
42 Input_SZ : integer := 16;
43 Result_SZ : integer := 32);
43 Result_SZ : integer := 32);
44 port (
44 port (
45 clk : in std_logic; --! Horloge du composant
45 clk : in std_logic;
46 rst : in std_logic; --! Reset general du composant
46 rst : in std_logic;
47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
49 Full : in std_logic_vector(1 downto 0);
50 Empty : in std_logic_vector(1 downto 0);
49 ReadFIFO : out std_logic_vector(1 downto 0);
51 ReadFIFO : out std_logic_vector(1 downto 0);
52 FullFIFO : in std_logic;
50 WriteFIFO : out std_logic;
53 WriteFIFO : out std_logic;
51 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 Result : out std_logic_vector(Result_SZ-1 downto 0);
52 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
@@ -64,27 +67,23 constant pconfig : apb_config_type := (
64 1 => apb_iobar(paddr, pmask));
67 1 => apb_iobar(paddr, pmask));
65
68
66 type MATRIX_ctrlr_Reg is record
69 type MATRIX_ctrlr_Reg is record
67 MATRIX_Ctrl : std_logic_vector(4 downto 0);
70 MATRIX_Statu : std_logic_vector(3 downto 0);
68 end record;
71 end record;
69
72
70 signal Rec : MATRIX_ctrlr_Reg;
73 signal Rec : MATRIX_ctrlr_Reg;
71 signal Rdata : std_logic_vector(31 downto 0);
74 signal Rdata : std_logic_vector(31 downto 0);
72 signal Start : std_logic;
73 signal statu : std_logic_vector(3 downto 0);
74
75
75 begin
76 begin
76
77
77 Mspec0 : SpectralMatrix
78 Mspec0 : Top_MatrixSpec
78 generic map (Input_SZ,Result_SZ)
79 generic map (Input_SZ,Result_SZ)
79 port map(clk,rst,Start,FIFO1,FIFO2,Statu,ReadFIFO,WriteFIFO,Result);
80 port map(clk,rst,Rec.MATRIX_Statu,FIFO1,FIFO2,Full,Empty,ReadFIFO,FullFIFO,WriteFIFO,Result);
80
81
81 Statu <= Rec.MATRIX_Ctrl(3 downto 0);
82 Start <= Rec.MATRIX_Ctrl(4);
83
82
84 process(rst,clk)
83 process(rst,clk)
85 begin
84 begin
86 if(rst='0')then
85 if(rst='0')then
87 Rec.MATRIX_Ctrl <= (others => '0');
86 Rec.MATRIX_Statu <= (others => '0');
88
87
89 elsif(clk'event and clk='1')then
88 elsif(clk'event and clk='1')then
90
89
@@ -92,7 +91,7 Start <= Rec.MATRIX_Ctrl(4);
92 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
91 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
93 case apbi.paddr(abits-1 downto 2) is
92 case apbi.paddr(abits-1 downto 2) is
94 when "000000" =>
93 when "000000" =>
95 Rec.MATRIX_Ctrl <= apbi.pwdata(4 downto 0);
94 Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
96 when others =>
95 when others =>
97 null;
96 null;
98 end case;
97 end case;
@@ -102,8 +101,8 Start <= Rec.MATRIX_Ctrl(4);
102 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
101 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
103 case apbi.paddr(abits-1 downto 2) is
102 case apbi.paddr(abits-1 downto 2) is
104 when "000000" =>
103 when "000000" =>
105 Rdata(31 downto 5) <= (others => '0');
104 Rdata(31 downto 4) <= (others => '0');
106 Rdata(4 downto 0) <= Rec.MATRIX_Ctrl;
105 Rdata(3 downto 0) <= Rec.MATRIX_Statu;
107 when others =>
106 when others =>
108 Rdata <= (others => '0');
107 Rdata <= (others => '0');
109 end case;
108 end case;
Show file before | Show file after | Hide comments
@@ -41,11 +41,14 component APB_Matrix is
41 Input_SZ : integer := 16;
41 Input_SZ : integer := 16;
42 Result_SZ : integer := 32);
42 Result_SZ : integer := 32);
43 port (
43 port (
44 clk : in std_logic; --! Horloge du composant
44 clk : in std_logic;
45 rst : in std_logic; --! Reset general du composant
45 rst : in std_logic;
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
48 ReadFIFO : out std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
51 FullFIFO : in std_logic;
49 WriteFIFO : out std_logic;
52 WriteFIFO : out std_logic;
50 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
51 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
@@ -53,6 +56,24 component APB_Matrix is
53 );
56 );
54 end component;
57 end component;
55
58
59 component Top_MatrixSpec is
60 generic(
61 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
63 port(
64 clk : in std_logic;
65 reset : in std_logic;
66 Statu : in std_logic_vector(3 downto 0);
67 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
68 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
69 Full : in std_logic_vector(1 downto 0);
70 Empty : in std_logic_vector(1 downto 0);
71 ReadFIFO : out std_logic_vector(1 downto 0);
72 FullFIFO : in std_logic;
73 WriteFIFO : out std_logic;
74 Result : out std_logic_vector(Result_SZ-1 downto 0)
75 );
76 end component;
56
77
57 component SpectralMatrix is
78 component SpectralMatrix is
58 generic(
79 generic(
@@ -138,6 +159,17 port(
138 );
159 );
139 end component;
160 end component;
140
161
162 component Starter is
163 port(
164 clk : in std_logic;
165 raz : in std_logic;
166 Full : in std_logic_vector(1 downto 0);
167 Empty : in std_logic_vector(1 downto 0);
168 Statu : in std_logic_vector(3 downto 0);
169 Write : in std_logic;
170 Start : out std_logic
171 );
172 end component;
141
173
142 component ALU_Driver is
174 component ALU_Driver is
143 generic(
175 generic(
Show file before | Show file after | Hide comments
@@ -46,6 +46,7 generic (
46 FifoCnt : integer := 2;
46 FifoCnt : integer := 2;
47 Data_sz : integer := 16;
47 Data_sz : integer := 16;
48 Addr_sz : integer := 9;
48 Addr_sz : integer := 9;
49 Enable_ReUse : std_logic := '0';
49 R : integer := 1;
50 R : integer := 1;
50 W : integer := 1
51 W : integer := 1
51 );
52 );
@@ -168,7 +169,7 Full <= sFull;
168
169
169 fifos: for i in 0 to FifoCnt-1 generate
170 fifos: for i in 0 to FifoCnt-1 generate
170 FIFO0 : lpp_fifo
171 FIFO0 : lpp_fifo
171 generic map (tech,Data_sz,Addr_sz)
172 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
172 port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
173 port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
173 end generate;
174 end generate;
174
175
Show file before | Show file after | Hide comments
@@ -30,6 +30,7 use techmap.gencomp.all;
30 entity lpp_fifo is
30 entity lpp_fifo is
31 generic(
31 generic(
32 tech : integer := 0;
32 tech : integer := 0;
33 Enable_ReUse : std_logic := '0';
33 DataSz : integer range 1 to 32 := 8;
34 DataSz : integer range 1 to 32 := 8;
34 abits : integer range 2 to 12 := 8
35 abits : integer range 2 to 12 := 8
35 );
36 );
@@ -85,7 +86,7 begin
85 Raddr_vect_d <= (others =>'1');
86 Raddr_vect_d <= (others =>'1');
86 sempty <= '1';
87 sempty <= '1';
87 elsif(rclk'event and rclk='1')then
88 elsif(rclk'event and rclk='1')then
88 if(ReUse = '1')then --27/01/12
89 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
89 sempty <= '0'; --27/01/12
90 sempty <= '0'; --27/01/12
90 elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
91 elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
91 sempty <= '1';
92 sempty <= '1';
@@ -112,7 +113,7 begin
112 Waddr_vect_d <= (others =>'1');
113 Waddr_vect_d <= (others =>'1');
113 sfull <= '0';
114 sfull <= '0';
114 elsif(wclk'event and wclk='1')then
115 elsif(wclk'event and wclk='1')then
115 if(ReUse = '1')then --27/01/12
116 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
116 sfull <= '1'; --27/01/12
117 sfull <= '1'; --27/01/12
117 elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
118 elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
118 sfull <= '1';
119 sfull <= '1';
Show file before | Show file after | Hide comments
@@ -47,6 +47,7 generic (
47 FifoCnt : integer := 2;
47 FifoCnt : integer := 2;
48 Data_sz : integer := 16;
48 Data_sz : integer := 16;
49 Addr_sz : integer := 9;
49 Addr_sz : integer := 9;
50 Enable_ReUse : std_logic := '0';
50 R : integer := 1;
51 R : integer := 1;
51 W : integer := 1
52 W : integer := 1
52 );
53 );
@@ -72,6 +73,7 end component;
72 component lpp_fifo is
73 component lpp_fifo is
73 generic(
74 generic(
74 tech : integer := 0;
75 tech : integer := 0;
76 Enable_ReUse : std_logic := '0';
75 DataSz : integer range 1 to 32 := 8;
77 DataSz : integer range 1 to 32 := 8;
76 abits : integer range 2 to 12 := 8
78 abits : integer range 2 to 12 := 8
77 );
79 );
General Comments 0
You need to be logged in to leave comments. Login now