# HG changeset patch # User martin # Date 2012-02-01 14:21:15 # Node ID 236e70a254cc8364ca55a81f1cec1d4acbfd344f # Parent 87d4a9c4bb62f34c544e60d79ed7440c94638fd6 Update Matrix Spectral function with 2 fifo inputs (APB and C-driver) diff --git a/LPP_drivers/exemples/BenchMatrix/main.c b/LPP_drivers/exemples/BenchMatrix/main.c --- a/LPP_drivers/exemples/BenchMatrix/main.c +++ b/LPP_drivers/exemples/BenchMatrix/main.c @@ -3,10 +3,9 @@ #include "apb_fifo_Driver.h" #include "apb_Matrix_Driver.h" #include "apb_uart_Driver.h" -#include "apb_delay_Driver.h" #include "apb_gpio_Driver.h" -// Matrix With 2 FIFO Input +///////////// Matrix With 2 FIFO Input ///////////////////////////////////////////// int main() { int i=0,save; @@ -20,7 +19,6 @@ int main() FIFO_Device* fifoX = openFIFO(0); - DELAY_Device* delay0 = openDELAY(0); UART_Device* uart0 = openUART(0); FIFO_Device* fifoIn = openFIFO(1); MATRIX_Device* mspec = openMatrix(0); @@ -29,7 +27,6 @@ int main() printf("\nDebut Main\n\n"); - Setup(delay0,30000000); gpio0->oen = 0x3; gpio0->Dout = 0x0; @@ -61,7 +58,6 @@ int main() mspec->Statu = 1; FillFifo(fifoIn,0,TblB1); gpio0->Dout = 0x1; - Delay_us(delay0,20); while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS { Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; @@ -109,7 +105,7 @@ int main() } -// Matrix With 5 FIFO Input +///////////// Matrix With 5 FIFO Input ///////////////////////////////////////////// int main2() { int save1,save2; diff --git a/lib/lpp/lpp_matrix/APB_Matrix.vhd b/lib/lpp/lpp_matrix/APB_Matrix.vhd --- a/lib/lpp/lpp_matrix/APB_Matrix.vhd +++ b/lib/lpp/lpp_matrix/APB_Matrix.vhd @@ -42,15 +42,18 @@ entity APB_Matrix is Input_SZ : integer := 16; Result_SZ : integer := 32); port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant + clk : in std_logic; + rst : in std_logic; FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + Full : in std_logic_vector(1 downto 0); + Empty : in std_logic_vector(1 downto 0); ReadFIFO : out std_logic_vector(1 downto 0); + FullFIFO : in std_logic; WriteFIFO : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0); - apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end APB_Matrix; @@ -64,27 +67,23 @@ constant pconfig : apb_config_type := ( 1 => apb_iobar(paddr, pmask)); type MATRIX_ctrlr_Reg is record - MATRIX_Ctrl : std_logic_vector(4 downto 0); + MATRIX_Statu : std_logic_vector(3 downto 0); end record; signal Rec : MATRIX_ctrlr_Reg; signal Rdata : std_logic_vector(31 downto 0); -signal Start : std_logic; -signal statu : std_logic_vector(3 downto 0); begin -Mspec0 : SpectralMatrix +Mspec0 : Top_MatrixSpec generic map (Input_SZ,Result_SZ) - port map(clk,rst,Start,FIFO1,FIFO2,Statu,ReadFIFO,WriteFIFO,Result); + port map(clk,rst,Rec.MATRIX_Statu,FIFO1,FIFO2,Full,Empty,ReadFIFO,FullFIFO,WriteFIFO,Result); -Statu <= Rec.MATRIX_Ctrl(3 downto 0); -Start <= Rec.MATRIX_Ctrl(4); process(rst,clk) begin if(rst='0')then - Rec.MATRIX_Ctrl <= (others => '0'); + Rec.MATRIX_Statu <= (others => '0'); elsif(clk'event and clk='1')then @@ -92,7 +91,7 @@ Start <= Rec.MATRIX_Ctrl(4); if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - Rec.MATRIX_Ctrl <= apbi.pwdata(4 downto 0); + Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0); when others => null; end case; @@ -102,8 +101,8 @@ Start <= Rec.MATRIX_Ctrl(4); if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - Rdata(31 downto 5) <= (others => '0'); - Rdata(4 downto 0) <= Rec.MATRIX_Ctrl; + Rdata(31 downto 4) <= (others => '0'); + Rdata(3 downto 0) <= Rec.MATRIX_Statu; when others => Rdata <= (others => '0'); end case; diff --git a/lib/lpp/lpp_matrix/Starter.vhd b/lib/lpp/lpp_matrix/Starter.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/Starter.vhd @@ -0,0 +1,128 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity Starter is +port( + clk : in std_logic; + raz : in std_logic; + Full : in std_logic_vector(1 downto 0); + Empty : in std_logic_vector(1 downto 0); + Statu : in std_logic_vector(3 downto 0); + Write : in std_logic; + Start : out std_logic +); +end Starter; + + +architecture ar_Starter of Starter is + +type etat is (eX,e0,e1,e2); +signal ect : etat; + +signal Write_reg : std_logic; +signal Conjugate : std_logic; + +begin + process(clk,raz) + begin + + if(raz='0')then + Start <= '0'; + Write_reg <= '0'; + ect <= eX; + + elsif(clk'event and clk='1')then + Write_reg <= Write; + + case ect is + when eX => + if(Conjugate='0')then + if(full="11")then + Start <= '1'; + ect <= e0; + end if; + else + if(full(0)='1')then + Start <= '1'; + ect <= e0; + end if; + end if; + + when e0 => + if(Conjugate='0')then + if(empty="11")then + ect <= e1; + end if; + else + if(empty(0)='1')then + ect <= e2; + end if; + end if; + + when e1 => + if(Write_reg='1' and Write='0')then + ect <= e2; + end if; + + when e2 => + if(Write_reg='1' and Write='0')then + Start <= '0'; + ect <= eX; + end if; + + end case; + + end if; + end process; + + +With Statu select + Conjugate <= '1' when "0001", + '1' when "0011", + '1' when "0110", + '1' when "1010", + '1' when "1111", + '0' when others; + +end ar_Starter; + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_matrix/Top_MatrixSpec.vhd b/lib/lpp/lpp_matrix/Top_MatrixSpec.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/Top_MatrixSpec.vhd @@ -0,0 +1,62 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +use lpp.lpp_matrix.all; + +entity Top_MatrixSpec is +generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); +port( + clk : in std_logic; + reset : in std_logic; + Statu : in std_logic_vector(3 downto 0); + FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + Full : in std_logic_vector(1 downto 0); + Empty : in std_logic_vector(1 downto 0); + ReadFIFO : out std_logic_vector(1 downto 0); + FullFIFO : in std_logic; + WriteFIFO : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) +); +end entity; + + +architecture ar_Top_MatrixSpec of Top_MatrixSpec is + +signal Start : std_logic; +signal Write : std_logic; + +begin +WriteFIFO <= Write; + +ST0 : Starter + port map(clk,reset,Full,Empty,Statu,Write,Start); + +Mspec : SpectralMatrix + generic map(Input_SZ,Result_SZ) + port map(clk,reset,Start,FIFO1,FIFO2,Statu,FullFIFO,ReadFIFO,Write,Result); + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -41,18 +41,39 @@ component APB_Matrix is Input_SZ : integer := 16; Result_SZ : integer := 32); port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant + clk : in std_logic; + rst : in std_logic; FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + Full : in std_logic_vector(1 downto 0); + Empty : in std_logic_vector(1 downto 0); ReadFIFO : out std_logic_vector(1 downto 0); + FullFIFO : in std_logic; WriteFIFO : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0); - apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end component; +component Top_MatrixSpec is +generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); +port( + clk : in std_logic; + reset : in std_logic; + Statu : in std_logic_vector(3 downto 0); + FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + Full : in std_logic_vector(1 downto 0); + Empty : in std_logic_vector(1 downto 0); + ReadFIFO : out std_logic_vector(1 downto 0); + FullFIFO : in std_logic; + WriteFIFO : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) +); +end component; component SpectralMatrix is generic( @@ -138,6 +159,17 @@ port( ); end component; +component Starter is +port( + clk : in std_logic; + raz : in std_logic; + Full : in std_logic_vector(1 downto 0); + Empty : in std_logic_vector(1 downto 0); + Statu : in std_logic_vector(3 downto 0); + Write : in std_logic; + Start : out std_logic +); +end component; component ALU_Driver is generic( diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd --- a/lib/lpp/lpp_memory/APB_FIFO.vhd +++ b/lib/lpp/lpp_memory/APB_FIFO.vhd @@ -37,29 +37,30 @@ use lpp.lpp_memory.all; entity APB_FIFO is generic ( - tech : integer := apa3; - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - FifoCnt : integer := 2; - Data_sz : integer := 16; - Addr_sz : integer := 9; - R : integer := 1; - W : integer := 1 + tech : integer := apa3; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + FifoCnt : integer := 2; + Data_sz : integer := 16; + Addr_sz : integer := 9; + Enable_ReUse : std_logic := '0'; + R : integer := 1; + W : integer := 1 ); port ( clk : in std_logic; --! Horloge du composant rst : in std_logic; --! Reset general du composant rclk : in std_logic; wclk : in std_logic; - REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire - WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire + REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire + WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e - WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie + WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture) RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus @@ -168,7 +169,7 @@ Full <= sFull; fifos: for i in 0 to FifoCnt-1 generate FIFO0 : lpp_fifo - generic map (tech,Data_sz,Addr_sz) + generic map (tech,Enable_ReUse,Data_sz,Addr_sz) port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); end generate; diff --git a/lib/lpp/lpp_memory/lpp_FIFO.vhd b/lib/lpp/lpp_memory/lpp_FIFO.vhd --- a/lib/lpp/lpp_memory/lpp_FIFO.vhd +++ b/lib/lpp/lpp_memory/lpp_FIFO.vhd @@ -29,9 +29,10 @@ use techmap.gencomp.all; entity lpp_fifo is generic( - tech : integer := 0; - DataSz : integer range 1 to 32 := 8; - abits : integer range 2 to 12 := 8 + tech : integer := 0; + Enable_ReUse : std_logic := '0'; + DataSz : integer range 1 to 32 := 8; + abits : integer range 2 to 12 := 8 ); port( rstn : in std_logic; @@ -85,7 +86,7 @@ begin Raddr_vect_d <= (others =>'1'); sempty <= '1'; elsif(rclk'event and rclk='1')then - if(ReUse = '1')then --27/01/12 + if(ReUse = '1' and Enable_ReUse='1')then --27/01/12 sempty <= '0'; --27/01/12 elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then sempty <= '1'; @@ -112,7 +113,7 @@ begin Waddr_vect_d <= (others =>'1'); sfull <= '0'; elsif(wclk'event and wclk='1')then - if(ReUse = '1')then --27/01/12 + if(ReUse = '1' and Enable_ReUse='1')then --27/01/12 sfull <= '1'; --27/01/12 elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then sfull <= '1'; diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -46,7 +46,8 @@ generic ( abits : integer := 8; FifoCnt : integer := 2; Data_sz : integer := 16; - Addr_sz : integer := 9; + Addr_sz : integer := 9; + Enable_ReUse : std_logic := '0'; R : integer := 1; W : integer := 1 ); @@ -71,9 +72,10 @@ end component; component lpp_fifo is generic( - tech : integer := 0; - DataSz : integer range 1 to 32 := 8; - abits : integer range 2 to 12 := 8 + tech : integer := 0; + Enable_ReUse : std_logic := '0'; + DataSz : integer range 1 to 32 := 8; + abits : integer range 2 to 12 := 8 ); port( rstn : in std_logic;