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(MINI-LFR) WFP_MS_0-1-10
pellion -
r345:21fc600461fa (MINI-LFR) WFP_MS-0-1-10 JC
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@@ -353,7 +353,7 BEGIN -- beh
353 353 pirq_ms => 6,
354 354 pirq_wfp => 14,
355 355 hindex => 2,
356 top_lfr_version => X"000109") -- aa.bb.cc version
356 top_lfr_version => X"00010A") -- aa.bb.cc version
357 357 -- AA : BOARD NUMBER
358 358 -- 0 => MINI_LFR
359 359 -- 1 => EM
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@@ -425,7 +425,7 BEGIN -- beh
425 425 pirq_ms => 6,
426 426 pirq_wfp => 14,
427 427 hindex => 2,
428 top_lfr_version => X"000109") -- aa.bb.cc version
428 top_lfr_version => X"00010A") -- aa.bb.cc version
429 429 PORT MAP (
430 430 clk => clk_25,
431 431 rstn => reset,
@@ -577,4 +577,4 BEGIN -- beh
577 577 END IF;
578 578 END PROCESS;
579 579
580 END beh; No newline at end of file
580 END beh;
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@@ -19,103 +19,104
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 25
26 entity Driver_FFT is
27 generic(
28 Data_sz : integer range 1 to 32 := 16;
29 NbData : integer range 1 to 512 := 256
26 ENTITY Driver_FFT IS
27 GENERIC(
28 Data_sz : INTEGER RANGE 1 TO 32 := 16;
29 NbData : INTEGER RANGE 1 TO 512 := 256
30 30 );
31 port(
32 clk : in std_logic;
33 rstn : in std_logic;
34 Load : in std_logic;
35 Empty : in std_logic_vector(4 downto 0);
36 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
37 Valid : out std_logic;
38 Read : out std_logic_vector(4 downto 0);
39 Data_re : out std_logic_vector(Data_sz-1 downto 0);
40 Data_im : out std_logic_vector(Data_sz-1 downto 0)
41 );
42 end entity;
31 PORT(
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 Load : IN STD_LOGIC; -- (CoreFFT) FFT_Load
35 -- Load
36 Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- FifoIN_Empty
37 DATA : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); -- FifoIN_Data
38 Valid : OUT STD_LOGIC; --(CoreFFT) Drive_write
39 Read : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- Read
40 Data_re : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --(CoreFFT) Drive_DataRE
41 Data_im : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0) --(CoreFFT) Drive_DataIM
42 );
43 END ENTITY;
43 44
44 45
45 architecture ar_Driver of Driver_FFT is
46 ARCHITECTURE ar_Driver OF Driver_FFT IS
46 47
47 type etat is (eX,e0,e1,e2);
48 signal ect : etat;
48 TYPE etat IS (eX, e0, e1, e2);
49 SIGNAL ect : etat;
49 50
50 signal DataCount : integer range 0 to 255 := 0;
51 signal FifoCpt : integer range 0 to 4 := 0;
51 SIGNAL DataCount : INTEGER RANGE 0 TO 255 := 0;
52 SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0;
52 53
53 signal sLoad : std_logic;
54 SIGNAL sLoad : STD_LOGIC;
54 55
55 begin
56 BEGIN
56 57
57 process(clk,rstn)
58 begin
59 if(rstn='0')then
60 ect <= e0;
61 Read <= (others => '1');
62 Valid <= '0';
63 Data_re <= (others => '0');
64 Data_im <= (others => '0');
65 DataCount <= 0;
66 FifoCpt <= 0;
67 sLoad <= '0';
68
69 elsif(clk'event and clk='1')then
70 sLoad <= Load;
58 PROCESS(clk, rstn)
59 BEGIN
60 IF(rstn = '0')then
61 ect <= e0;
62 Read <= (OTHERS => '1');
63 Valid <= '0';
64 Data_re <= (OTHERS => '0');
65 Data_im <= (OTHERS => '0');
66 DataCount <= 0;
67 FifoCpt <= 0;
68 sLoad <= '0';
69
70 ELSIF(clk'EVENT AND clk = '1')then
71 sLoad <= Load;
71 72
72 if(sLoad='1' and Load='0')then
73 if(FifoCpt=4)then
74 FifoCpt <= 0;
75 else
76 FifoCpt <= FifoCpt + 1;
77 end if;
78 end if;
79
80 case ect is
73 IF(sLoad = '1' and Load = '0')THEN
74 IF(FifoCpt = 4)THEN
75 FifoCpt <= 0;
76 ELSE
77 FifoCpt <= FifoCpt + 1;
78 END IF;
79 END IF;
80
81 CASE ect IS
81 82
82 when e0 =>
83 if(Load='1' and Empty(FifoCpt)='0')then
84 Read(FifoCpt) <= '0';
85 ect <= e1;
86 end if;
83 WHEN e0 =>
84 IF(Load = '1' and Empty(FifoCpt) = '0')THEN
85 Read(FifoCpt) <= '0';
86 ect <= e1;
87 END IF;
87 88
88 when e1 =>
89 Valid <= '0';
90 Read(FifoCpt) <= '1';
91 ect <= e2;
92
93 when e2 =>
94 Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz));
95 Data_im <= (others => '0');
96 Valid <= '1';
97 if(DataCount=NbData-1)then
98 DataCount <= 0;
99 ect <= eX;
100 else
101 DataCount <= DataCount + 1;
102 if(Load='1' and Empty(FifoCpt)='0')then
103 Read(FifoCpt) <= '0';
104 ect <= e1;
105 else
106 ect <= eX;
107 end if;
108 end if;
89 WHEN e1 =>
90 Valid <= '0';
91 Read(FifoCpt) <= '1';
92 ect <= e2;
93
94 WHEN e2 =>
95 Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz));
96 Data_im <= (OTHERS => '0');
97 Valid <= '1';
98 IF(DataCount = NbData-1)THEN
99 DataCount <= 0;
100 ect <= eX;
101 ELSE
102 DataCount <= DataCount + 1;
103 IF(Load = '1' and Empty(FifoCpt) = '0')THEN
104 Read(FifoCpt) <= '0';
105 ect <= e1;
106 ELSE
107 ect <= eX;
108 END IF;
109 END IF;
109 110
110 when eX =>
111 Valid <= '0';
112 ect <= e0;
111 WHEN eX =>
112 Valid <= '0';
113 ect <= e0;
113 114
114 when others =>
115 null;
115 WHEN OTHERS =>
116 NULL;
116 117
117 end case;
118 end if;
119 end process;
118 END CASE;
119 END IF;
120 END PROCESS;
120 121
121 end architecture; No newline at end of file
122 END ARCHITECTURE;
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@@ -85,11 +85,16 Load <= FFT_Load;
85 85 HALFPTS => gHALFPTS,
86 86 inBuf_RWDLY => gInBuf_RWDLY)
87 87 port map(clkm,start,rstn,
88 Drive_Write,Link_Read,
89 Drive_DataIM,Drive_DataRE,
90 FFT_Load,open,
91 FFT_DataIM,FFT_DataRE,
92 FFT_Valid,FFT_Ready);
88 Drive_Write, -- ifiD_valid
89 Link_Read, -- ifiRead_y
90 Drive_DataIM, -- ifiD_im
91 Drive_DataRE, -- ifiD_re
92 FFT_Load, -- ifoLoad
93 open, -- ifoPong
94 FFT_DataIM, -- ifoY_im
95 FFT_DataRE, -- ifoY_re
96 FFT_Valid, -- ifiY_valid
97 FFT_Ready); -- ifiY_rdy
93 98
94 99
95 100 LINK : Linker_FFT
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@@ -19,94 +19,95
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 25
26 entity Linker_FFT is
27 generic(
28 Data_sz : integer range 1 to 32 := 16;
29 NbData : integer range 1 to 512 := 256
26 ENTITY Linker_FFT IS
27 GENERIC(
28 Data_sz : INTEGER RANGE 1 TO 32 := 16;
29 NbData : INTEGER RANGE 1 TO 512 := 256
30 30 );
31 port(
32 clk : in std_logic;
33 rstn : in std_logic;
34 Ready : in std_logic;
35 Valid : in std_logic;
36 Full : in std_logic_vector(4 downto 0);
37 Data_re : in std_logic_vector(Data_sz-1 downto 0);
38 Data_im : in std_logic_vector(Data_sz-1 downto 0);
39 Read : out std_logic;
40 Write : out std_logic_vector(4 downto 0);
41 ReUse : out std_logic_vector(4 downto 0);
42 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
43 );
44 end entity;
31 PORT(
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 Ready : IN STD_LOGIC; --
35 Valid : IN STD_LOGIC; --
36 Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --
37 Data_re : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
38 Data_im : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
39
40 Read : OUT STD_LOGIC; -- Link_Read
41 Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --
42 ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
43 DATA : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0)
44 );
45 END ENTITY;
45 46
46 47
47 architecture ar_Linker of Linker_FFT is
48 ARCHITECTURE ar_Linker OF Linker_FFT IS
48 49
49 type etat is (eX,e0,e1,e2);
50 signal ect : etat;
50 TYPE etat IS (eX, e0, e1, e2);
51 SIGNAL ect : etat;
51 52
52 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
53 SIGNAL DataTmp : STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0);
53 54
54 signal sRead : std_logic;
55 signal sReady : std_logic;
55 SIGNAL sRead : STD_LOGIC;
56 SIGNAL sReady : STD_LOGIC;
56 57
57 signal FifoCpt : integer range 0 to 4 := 0;
58 SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0;
58 59
59 begin
60 BEGIN
60 61
61 process(clk,rstn)
62 begin
63 if(rstn='0')then
64 ect <= e0;
65 sRead <= '0';
66 sReady <= '0';
67 Write <= (others => '1');
68 Reuse <= (others => '0');
69 FifoCpt <= 0;
70
71 elsif(clk'event and clk='1')then
72 sReady <= Ready;
62 PROCESS(clk, rstn)
63 BEGIN
64 IF(rstn = '0')then
65 ect <= e0;
66 sRead <= '0';
67 sReady <= '0';
68 Write <= (OTHERS => '1');
69 Reuse <= (OTHERS => '0');
70 FifoCpt <= 0;
71
72 ELSIF(clk'EVENT AND clk = '1')then
73 sReady <= Ready;
73 74
74 if(sReady='1' and Ready='0')then
75 if(FifoCpt=4)then
76 FifoCpt <= 0;
77 else
78 FifoCpt <= FifoCpt + 1;
79 end if;
80 elsif(Ready='1')then
81 sRead <= not sRead;
82 else
83 sRead <= '0';
84 end if;
75 IF(sReady = '1' and Ready = '0')THEN
76 IF(FifoCpt = 4)THEN
77 FifoCpt <= 0;
78 ELSE
79 FifoCpt <= FifoCpt + 1;
80 END IF;
81 ELSIF(Ready = '1')then
82 sRead <= NOT sRead;
83 ELSE
84 sRead <= '0';
85 END IF;
85 86
86 case ect is
87 CASE ect IS
87 88
88 when e0 =>
89 Write(FifoCpt) <= '1';
90 if(Valid='1' and Full(FifoCpt)='0')then
91 DataTmp <= Data_im;
92 DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= Data_re;
93 Write(FifoCpt) <= '0';
94 ect <= e1;
95 elsif(Full(FifoCpt)='1')then
96 ReUse(FifoCpt) <= '1';
97 end if;
89 WHEN e0 =>
90 Write(FifoCpt) <= '1';
91 IF(Valid = '1' and Full(FifoCpt) = '0')THEN
92 DataTmp <= Data_im;
93 DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= Data_re;
94 Write(FifoCpt) <= '0';
95 ect <= e1;
96 ELSIF(Full(FifoCpt) = '1')then
97 ReUse(FifoCpt) <= '1';
98 END IF;
98 99
99 when e1 =>
100 DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= DataTmp;
101 ect <= e0;
102
103 when others =>
104 null;
100 WHEN e1 =>
101 DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= DataTmp;
102 ect <= e0;
103
104 WHEN OTHERS =>
105 NULL;
105 106
106 end case;
107 end if;
108 end process;
107 END CASE;
108 END IF;
109 END PROCESS;
109 110
110 Read <= sRead;
111 Read <= sRead;
111 112
112 end architecture; No newline at end of file
113 END ARCHITECTURE;
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@@ -16,138 +16,141
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 -- Update : Jean-christophe Pellion
23 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 24 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 LIBRARY IEEE;
26 USE IEEE.std_logic_1164.ALL;
27 USE IEEE.numeric_std.ALL;
25 28
26 entity DEMUX is
27 generic(
28 Data_sz : integer range 1 to 32 := 16);
29 port(
30 clk : in std_logic;
31 rstn : in std_logic;
29 ENTITY DEMUX IS
30 GENERIC(
31 Data_sz : INTEGER RANGE 1 TO 32 := 16);
32 PORT(
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
32 35
33 Read : in std_logic_vector(4 downto 0);
34 Load : in std_logic;
36 Read : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 Load : IN STD_LOGIC;
35 38
36 EmptyF0 : in std_logic_vector(4 downto 0);
37 EmptyF1 : in std_logic_vector(4 downto 0);
38 EmptyF2 : in std_logic_vector(4 downto 0);
39 EmptyF0 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 EmptyF1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
41 EmptyF2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 42
40 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
41 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
42 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
43 DataF0 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0);
44 DataF1 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0);
45 DataF2 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0);
43 46
44 WorkFreq : out std_logic_vector(1 downto 0);
45 Read_DEMUX : out std_logic_vector(14 downto 0);
46 Empty : out std_logic_vector(4 downto 0);
47 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
48 );
49 end entity;
47 WorkFreq : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
48 Read_DEMUX : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
49 Empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
50 Data : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0)
51 );
52 END ENTITY;
50 53
51 54
52 architecture ar_DEMUX of DEMUX is
55 ARCHITECTURE ar_DEMUX OF DEMUX IS
53 56
54 type etat is (eX,e0,e1,e2,e3);
55 signal ect : etat;
57 TYPE etat IS (eX, e0, e1, e2, e3);
58 SIGNAL ect : etat;
56 59
57 60
58 signal load_reg : std_logic;
59 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
61 SIGNAL load_reg : STD_LOGIC;
62 CONSTANT Dummy_Read : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
60 63
61 signal Countf0 : integer;
62 signal Countf1 : integer;
63 signal i : integer;
64 SIGNAL Countf0 : INTEGER;
65 SIGNAL Countf1 : INTEGER;
66 SIGNAL i : INTEGER;
64 67
65 begin
66 process(clk,rstn)
67 begin
68 if(rstn='0')then
69 ect <= e0;
70 load_reg <= '0';
71 Countf0 <= 0;
72 Countf1 <= 0;
73 i <= 0;
68 BEGIN
69 PROCESS(clk, rstn)
70 BEGIN
71 IF(rstn = '0')then
72 ect <= e0;
73 load_reg <= '0';
74 Countf0 <= 0;
75 Countf1 <= 0;
76 i <= 0;
74 77
75 elsif(clk'event and clk='1')then
76 load_reg <= Load;
78 ELSIF(clk'EVENT AND clk = '1')then
79 load_reg <= Load;
77 80
78 case ect is
81 CASE ect IS
79 82
80 when e0 =>
81 if(load_reg = '1' and Load = '0')then
82 if(Countf0 = 24)then
83 Countf0 <= 0;
84 ect <= e1;
85 else
86 Countf0 <= Countf0 + 1;
87 ect <= e0;
88 end if;
89 end if;
83 WHEN e0 =>
84 IF(load_reg = '1' AND Load = '0')THEN
85 IF(Countf0 = 24)THEN
86 Countf0 <= 0;
87 ect <= e1;
88 ELSE
89 Countf0 <= Countf0 + 1;
90 ect <= e0;
91 END IF;
92 END IF;
90 93
91 when e1 =>
92 if(load_reg = '1' and Load = '0')then
93 if(Countf1 = 74)then
94 Countf1 <= 0;
95 ect <= e2;
96 else
97 Countf1 <= Countf1 + 1;
98 if(i=4)then
99 i <= 0;
100 ect <= e0;
101 else
102 i <= i+1;
103 ect <= e1;
104 end if;
105 end if;
106 end if;
94 WHEN e1 =>
95 IF(load_reg = '1' AND Load = '0')THEN
96 IF(Countf1 = 74)THEN
97 Countf1 <= 0;
98 ect <= e2;
99 ELSE
100 Countf1 <= Countf1 + 1;
101 IF(i = 4)THEN
102 i <= 0;
103 ect <= e0;
104 ELSE
105 i <= i+1;
106 ect <= e1;
107 END IF;
108 END IF;
109 END IF;
107 110
108 when e2 =>
109 if(load_reg = '1' and Load = '0')then
110 if(i=4)then
111 i <= 0;
112 ect <= e0;
113 else
114 i <= i+1;
115 ect <= e2;
116 end if;
117 end if;
118
119 when others =>
120 null;
111 WHEN e2 =>
112 IF(load_reg = '1' AND Load = '0')THEN
113 IF(i = 4)THEN
114 i <= 0;
115 ect <= e0;
116 ELSE
117 i <= i+1;
118 ect <= e2;
119 END IF;
120 END IF;
121
122 WHEN OTHERS =>
123 NULL;
121 124
122 end case;
123 end if;
124 end process;
125 END CASE;
126 END IF;
127 END PROCESS;
125 128
126 with ect select
127 Empty <= EmptyF0 when e0,
128 EmptyF1 when e1,
129 EmptyF2 when e2,
130 (others => '1') when others;
129 WITH ect SELECT
130 Empty <= EmptyF0 WHEN e0,
131 EmptyF1 WHEN e1,
132 EmptyF2 WHEN e2,
133 (OTHERS => '1') WHEN OTHERS;
131 134
132 with ect select
133 Data <= DataF0 when e0,
134 DataF1 when e1,
135 DataF2 when e2,
136 (others => '0') when others;
135 WITH ect SELECT
136 Data <= DataF0 WHEN e0,
137 DataF1 WHEN e1,
138 DataF2 WHEN e2,
139 (OTHERS => '0') WHEN OTHERS;
137 140
138 with ect select
139 Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0,
140 Dummy_Read & Read & Dummy_Read when e1,
141 Read & Dummy_Read & Dummy_Read when e2,
142 (others => '1') when others;
141 WITH ect SELECT
142 Read_DEMUX <= Dummy_Read & Dummy_Read & Read WHEN e0,
143 Dummy_Read & Read & Dummy_Read WHEN e1,
144 Read & Dummy_Read & Dummy_Read WHEN e2,
145 (OTHERS => '1') WHEN OTHERS;
143 146
144 with ect select
145 WorkFreq <= "01" when e0,
146 "10" when e1,
147 "11" when e2,
148 "00" when others;
147 WITH ect SELECT
148 WorkFreq <= "01" WHEN e0,
149 "10" WHEN e1,
150 "11" WHEN e2,
151 "00" WHEN OTHERS;
149 152
150 end architecture;
153 END ARCHITECTURE;
151 154
152 155
153 156
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@@ -33,17 +33,17 entity MatriceSpectrale is
33 33 clkm : in std_logic;
34 34 rstn : in std_logic;
35 35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
36 FifoIN_Full : in std_logic_vector(4 downto 0); --
37 SetReUse : in std_logic_vector(4 downto 0); --
38 38 Valid : in std_logic;
39 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
39 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); --
40 40 ACK : in std_logic;
41 41 SM_Write : out std_logic;
42 42 FlagError : out std_logic;
43 43 Statu : out std_logic_vector(3 downto 0);
44 44 Write : out std_logic_vector(1 downto 0);
45 Read : out std_logic_vector(4 downto 0);
46 ReUse : out std_logic_vector(4 downto 0);
45 Read : out std_logic_vector(4 downto 0); --
46 ReUse : out std_logic_vector(4 downto 0); --
47 47 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
48 48 );
49 49 end entity;
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@@ -262,19 +262,19 BEGIN
262 262 PORT MAP (
263 263 clkm => clk,
264 264 rstn => rstn,
265 FifoIN_Full => FifoINT_Full,
266 SetReUse => FFT_ReUse,
267 Valid => Head_Valid,
268 Data_IN => FifoINT_Data,
269 ACK => DMA_ack,
270 SM_Write => SM_Wen,
271 FlagError => SM_FlagError,
265 FifoIN_Full => FifoINT_Full, --
266 SetReUse => FFT_ReUse, --
267 Valid => Head_Valid, -- HeaderBuilder
268 Data_IN => FifoINT_Data, --
269 ACK => DMA_ack, -- HeaderBuilder
270 SM_Write => SM_Wen, -- HeaderBuilder
271 FlagError => SM_FlagError, -- UNUSED
272 272 -- Pong => SM_Pong,
273 Statu => SM_Param,
274 Write => SM_Write,
275 Read => SM_Read,
276 ReUse => SM_ReUse,
277 Data_OUT => SM_Data);
273 Statu => SM_Param, -- HeaderBuilder
274 Write => SM_Write, -- FIFO MemOut
275 Read => SM_Read, --
276 ReUse => SM_ReUse, --
277 Data_OUT => SM_Data); -- FIFO MemOut
278 278 -----------------------------------------------------------------------------
279 279
280 280 -----------------------------------------------------------------------------
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@@ -91,10 +91,10 ENTITY lpp_lfr_ms_fsmdma IS
91 91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 93
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
98 98
99 99 );
100 100 END;
@@ -169,7 +169,7 BEGIN
169 169 '0';
170 170
171 171 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
172 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
172 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
173 173 '1' WHEN component_type = component_type_pre + "0001" ELSE
174 174 '0';
175 175
@@ -204,7 +204,7 BEGIN
204 204 header_data <= (OTHERS => '0');
205 205 fine_time_reg <= (OTHERS => '0');
206 206
207 debug_reg_s( 2 DOWNTO 0) <= (OTHERS => '0');
207 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
208 208 debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0');
209 209
210 210 log_empty_fifo <= '0';
@@ -212,12 +212,12 BEGIN
212 212 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
213 213 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
214 214 header_reg_ack <= '0';
215
215
216 216 CASE state IS
217 217 WHEN IDLE =>
218 218 debug_reg_s(2 DOWNTO 0) <= "000";
219
220 matrix_type <= header(1 DOWNTO 0);
219
220 --matrix_type <= header(1 DOWNTO 0);
221 221 --component_type <= header(5 DOWNTO 2);
222 222
223 223 ready_matrix_f0_0 <= '0';
@@ -225,13 +225,13 BEGIN
225 225 ready_matrix_f1 <= '0';
226 226 ready_matrix_f2 <= '0';
227 227 error_bad_component_error <= '0';
228 header_select <= '1';
229
228 --header_select <= '1';
229
230 230 IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
231 header_reg_ack <= '1';
231 header_reg_ack <= '1';
232 232 debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0);
233 233 debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2);
234
234
235 235 matrix_type <= header_reg(1 DOWNTO 0);
236 236 component_type <= header_reg(5 DOWNTO 2);
237 237 component_type_pre <= component_type;
@@ -242,22 +242,22 BEGIN
242 242 WHEN CHECK_COMPONENT_TYPE =>
243 243 debug_reg_s(2 DOWNTO 0) <= "001";
244 244 --header_ack <= '0';
245
245
246 246 IF header_check_ok = '1' THEN
247 247 header_send <= '0';
248 248 --
249 249 IF component_type = "0000" THEN
250 address <= address_matrix;
250 address <= address_matrix;
251 251 CASE matrix_type IS
252 WHEN "00" => matrix_time_f0_0 <= data_time;
253 WHEN "01" => matrix_time_f0_1 <= data_time;
254 WHEN "10" => matrix_time_f1 <= data_time;
255 WHEN "11" => matrix_time_f2 <= data_time ;
252 WHEN "00" => matrix_time_f0_0 <= data_time;
253 WHEN "01" => matrix_time_f0_1 <= data_time;
254 WHEN "10" => matrix_time_f1 <= data_time;
255 WHEN "11" => matrix_time_f2 <= data_time;
256 256 WHEN OTHERS => NULL;
257 257 END CASE;
258
259 header_data <= data_time(31 DOWNTO 0);
260 fine_time_reg <= data_time(47 DOWNTO 32);
258
259 header_data <= data_time(31 DOWNTO 0);
260 fine_time_reg <= data_time(47 DOWNTO 32);
261 261 --state <= WRITE_COARSE_TIME;
262 262 --header_send <= '1';
263 263 state <= SEND_DATA;
@@ -274,59 +274,59 BEGIN
274 274 state <= TRASH_FIFO;
275 275 END IF;
276 276
277 --WHEN WRITE_COARSE_TIME =>
278 -- debug_reg_s(2 DOWNTO 0) <= "010";
279
280 -- header_ack <= '0';
277 --WHEN WRITE_COARSE_TIME =>
278 -- debug_reg_s(2 DOWNTO 0) <= "010";
279
280 -- header_ack <= '0';
281 281
282 -- IF dma_ren = '0' THEN
283 -- header_send <= '0';
284 -- ELSE
285 -- header_send <= header_send;
286 -- END IF;
282 -- IF dma_ren = '0' THEN
283 -- header_send <= '0';
284 -- ELSE
285 -- header_send <= header_send;
286 -- END IF;
287 287
288 288
289 -- IF header_send_ko = '1' THEN
290 -- header_send <= '0';
291 -- state <= TRASH_FIFO;
292 -- error_anticipating_empty_fifo <= '1';
293 -- -- TODO : error sending header
294 -- ELSIF header_send_ok = '1' THEN
295 -- header_send <= '1';
296 -- header_select <= '1';
297 -- header_data(15 DOWNTO 0) <= fine_time_reg;
298 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
299 -- state <= WRITE_FINE_TIME;
300 -- address <= address + 4;
301 -- END IF;
302
303
304 --WHEN WRITE_FINE_TIME =>
305 -- debug_reg_s(2 DOWNTO 0) <= "011";
306
307 -- header_ack <= '0';
289 -- IF header_send_ko = '1' THEN
290 -- header_send <= '0';
291 -- state <= TRASH_FIFO;
292 -- error_anticipating_empty_fifo <= '1';
293 -- -- TODO : error sending header
294 -- ELSIF header_send_ok = '1' THEN
295 -- header_send <= '1';
296 -- header_select <= '1';
297 -- header_data(15 DOWNTO 0) <= fine_time_reg;
298 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
299 -- state <= WRITE_FINE_TIME;
300 -- address <= address + 4;
301 -- END IF;
302
303
304 --WHEN WRITE_FINE_TIME =>
305 -- debug_reg_s(2 DOWNTO 0) <= "011";
308 306
309 -- IF dma_ren = '0' THEN
310 -- header_send <= '0';
311 -- ELSE
312 -- header_send <= header_send;
313 -- END IF;
307 -- header_ack <= '0';
308
309 -- IF dma_ren = '0' THEN
310 -- header_send <= '0';
311 -- ELSE
312 -- header_send <= header_send;
313 -- END IF;
314 314
315 -- IF header_send_ko = '1' THEN
316 -- header_send <= '0';
317 -- state <= TRASH_FIFO;
318 -- error_anticipating_empty_fifo <= '1';
319 -- -- TODO : error sending header
320 -- ELSIF header_send_ok = '1' THEN
321 -- header_send <= '0';
322 -- header_select <= '0';
323 -- state <= SEND_DATA;
324 -- address <= address + 4;
325 -- END IF;
315 -- IF header_send_ko = '1' THEN
316 -- header_send <= '0';
317 -- state <= TRASH_FIFO;
318 -- error_anticipating_empty_fifo <= '1';
319 -- -- TODO : error sending header
320 -- ELSIF header_send_ok = '1' THEN
321 -- header_send <= '0';
322 -- header_select <= '0';
323 -- state <= SEND_DATA;
324 -- address <= address + 4;
325 -- END IF;
326 326
327 327 WHEN TRASH_FIFO =>
328 328 debug_reg_s(2 DOWNTO 0) <= "100";
329
329
330 330 -- header_ack <= '0';
331 331 error_bad_component_error <= '0';
332 332 error_anticipating_empty_fifo <= '0';
@@ -340,7 +340,7 BEGIN
340 340 WHEN SEND_DATA =>
341 341 -- header_ack <= '0';
342 342 debug_reg_s(2 DOWNTO 0) <= "101";
343
343
344 344 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
345 345 state <= IDLE;
346 346 IF component_type = "1110" THEN --"1110" -- JC
@@ -361,30 +361,30 BEGIN
361 361
362 362 WHEN WAIT_DATA_ACK =>
363 363 log_empty_fifo <= fifo_empty OR log_empty_fifo;
364
364
365 365 debug_reg_s(2 DOWNTO 0) <= "110";
366
366
367 367 component_send <= '0';
368 368 IF component_send_ok = '1' THEN
369 369 address <= address + 64;
370 370 state <= SEND_DATA;
371 371 ELSIF component_send_ko = '1' THEN
372 372 error_anticipating_empty_fifo <= '0';
373 state <= TRASH_FIFO;
373 state <= TRASH_FIFO;
374 374 END IF;
375
376
377 --WHEN CHECK_LENGTH =>
378 -- component_send <= '0';
379 -- debug_reg_s(2 DOWNTO 0) <= "111";
380 -- state <= IDLE;
375
376
377 --WHEN CHECK_LENGTH =>
378 -- component_send <= '0';
379 -- debug_reg_s(2 DOWNTO 0) <= "111";
380 -- state <= IDLE;
381 381
382 382 WHEN OTHERS => NULL;
383 383 END CASE;
384 384
385 385 END IF;
386 386 END PROCESS DMAWriteFSM_p;
387
387
388 388 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
389 389 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
390 390 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
@@ -403,13 +403,13 BEGIN
403 403 -----------------------------------------------------------------------------
404 404 PROCESS (HCLK, HRESETn)
405 405 BEGIN -- PROCESS
406 IF HRESETn = '0' THEN -- asynchronous reset (active low)
406 IF HRESETn = '0' THEN -- asynchronous reset (active low)
407 407 header_ack <= '0';
408 408 header_reg <= (OTHERS => '0');
409 409 header_reg_val <= '0';
410 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
410 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
411 411 header_ack <= '0';
412
412
413 413 IF header_val = '1' THEN
414 414 header_ack <= '1';
415 415 header_reg <= header;
@@ -428,4 +428,4 BEGIN
428 428
429 429 debug_reg_s(3) <= header_error;
430 430
431 END Behavioral; No newline at end of file
431 END Behavioral;
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