# HG changeset patch # User pellion # Date 2014-04-14 09:15:27 # Node ID 21fc600461fa3d46d898f0f2be2e6fbc40719aa0 # Parent b5e18177453d6ecd13c0925a2a39aaff9245bf5d (MINI-LFR) WFP_MS_0-1-10 diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd --- a/designs/LFR-em-WFP_MS/LFR-em.vhd +++ b/designs/LFR-em-WFP_MS/LFR-em.vhd @@ -353,7 +353,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000109") -- aa.bb.cc version + top_lfr_version => X"00010A") -- aa.bb.cc version -- AA : BOARD NUMBER -- 0 => MINI_LFR -- 1 => EM diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -425,7 +425,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000109") -- aa.bb.cc version + top_lfr_version => X"00010A") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, @@ -577,4 +577,4 @@ BEGIN -- beh END IF; END PROCESS; -END beh; \ No newline at end of file +END beh; diff --git a/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd b/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd --- a/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd @@ -19,103 +19,104 @@ -- Author : Martin Morlot -- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; -entity Driver_FFT is -generic( - Data_sz : integer range 1 to 32 := 16; - NbData : integer range 1 to 512 := 256 +ENTITY Driver_FFT IS + GENERIC( + Data_sz : INTEGER RANGE 1 TO 32 := 16; + NbData : INTEGER RANGE 1 TO 512 := 256 ); -port( - clk : in std_logic; - rstn : in std_logic; - Load : in std_logic; - Empty : in std_logic_vector(4 downto 0); - DATA : in std_logic_vector((5*Data_sz)-1 downto 0); - Valid : out std_logic; - Read : out std_logic_vector(4 downto 0); - Data_re : out std_logic_vector(Data_sz-1 downto 0); - Data_im : out std_logic_vector(Data_sz-1 downto 0) -); -end entity; + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + Load : IN STD_LOGIC; -- (CoreFFT) FFT_Load + -- Load + Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- FifoIN_Empty + DATA : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); -- FifoIN_Data + Valid : OUT STD_LOGIC; --(CoreFFT) Drive_write + Read : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- Read + Data_re : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --(CoreFFT) Drive_DataRE + Data_im : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0) --(CoreFFT) Drive_DataIM + ); +END ENTITY; -architecture ar_Driver of Driver_FFT is +ARCHITECTURE ar_Driver OF Driver_FFT IS -type etat is (eX,e0,e1,e2); -signal ect : etat; + TYPE etat IS (eX, e0, e1, e2); + SIGNAL ect : etat; -signal DataCount : integer range 0 to 255 := 0; -signal FifoCpt : integer range 0 to 4 := 0; + SIGNAL DataCount : INTEGER RANGE 0 TO 255 := 0; + SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0; -signal sLoad : std_logic; + SIGNAL sLoad : STD_LOGIC; -begin +BEGIN - process(clk,rstn) - begin - if(rstn='0')then - ect <= e0; - Read <= (others => '1'); - Valid <= '0'; - Data_re <= (others => '0'); - Data_im <= (others => '0'); - DataCount <= 0; - FifoCpt <= 0; - sLoad <= '0'; - - elsif(clk'event and clk='1')then - sLoad <= Load; + PROCESS(clk, rstn) + BEGIN + IF(rstn = '0')then + ect <= e0; + Read <= (OTHERS => '1'); + Valid <= '0'; + Data_re <= (OTHERS => '0'); + Data_im <= (OTHERS => '0'); + DataCount <= 0; + FifoCpt <= 0; + sLoad <= '0'; + + ELSIF(clk'EVENT AND clk = '1')then + sLoad <= Load; - if(sLoad='1' and Load='0')then - if(FifoCpt=4)then - FifoCpt <= 0; - else - FifoCpt <= FifoCpt + 1; - end if; - end if; - - case ect is + IF(sLoad = '1' and Load = '0')THEN + IF(FifoCpt = 4)THEN + FifoCpt <= 0; + ELSE + FifoCpt <= FifoCpt + 1; + END IF; + END IF; + + CASE ect IS - when e0 => - if(Load='1' and Empty(FifoCpt)='0')then - Read(FifoCpt) <= '0'; - ect <= e1; - end if; + WHEN e0 => + IF(Load = '1' and Empty(FifoCpt) = '0')THEN + Read(FifoCpt) <= '0'; + ect <= e1; + END IF; - when e1 => - Valid <= '0'; - Read(FifoCpt) <= '1'; - ect <= e2; - - when e2 => - Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)); - Data_im <= (others => '0'); - Valid <= '1'; - if(DataCount=NbData-1)then - DataCount <= 0; - ect <= eX; - else - DataCount <= DataCount + 1; - if(Load='1' and Empty(FifoCpt)='0')then - Read(FifoCpt) <= '0'; - ect <= e1; - else - ect <= eX; - end if; - end if; + WHEN e1 => + Valid <= '0'; + Read(FifoCpt) <= '1'; + ect <= e2; + + WHEN e2 => + Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)); + Data_im <= (OTHERS => '0'); + Valid <= '1'; + IF(DataCount = NbData-1)THEN + DataCount <= 0; + ect <= eX; + ELSE + DataCount <= DataCount + 1; + IF(Load = '1' and Empty(FifoCpt) = '0')THEN + Read(FifoCpt) <= '0'; + ect <= e1; + ELSE + ect <= eX; + END IF; + END IF; - when eX => - Valid <= '0'; - ect <= e0; + WHEN eX => + Valid <= '0'; + ect <= e0; - when others => - null; + WHEN OTHERS => + NULL; - end case; - end if; - end process; + END CASE; + END IF; + END PROCESS; -end architecture; \ No newline at end of file +END ARCHITECTURE; diff --git a/lib/lpp/dsp/lpp_fft/FFT.vhd b/lib/lpp/dsp/lpp_fft/FFT.vhd --- a/lib/lpp/dsp/lpp_fft/FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/FFT.vhd @@ -85,11 +85,16 @@ Load <= FFT_Load; HALFPTS => gHALFPTS, inBuf_RWDLY => gInBuf_RWDLY) port map(clkm,start,rstn, - Drive_Write,Link_Read, - Drive_DataIM,Drive_DataRE, - FFT_Load,open, - FFT_DataIM,FFT_DataRE, - FFT_Valid,FFT_Ready); + Drive_Write, -- ifiD_valid + Link_Read, -- ifiRead_y + Drive_DataIM, -- ifiD_im + Drive_DataRE, -- ifiD_re + FFT_Load, -- ifoLoad + open, -- ifoPong + FFT_DataIM, -- ifoY_im + FFT_DataRE, -- ifoY_re + FFT_Valid, -- ifiY_valid + FFT_Ready); -- ifiY_rdy LINK : Linker_FFT diff --git a/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd b/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd --- a/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd @@ -19,94 +19,95 @@ -- Author : Martin Morlot -- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; -entity Linker_FFT is -generic( - Data_sz : integer range 1 to 32 := 16; - NbData : integer range 1 to 512 := 256 +ENTITY Linker_FFT IS + GENERIC( + Data_sz : INTEGER RANGE 1 TO 32 := 16; + NbData : INTEGER RANGE 1 TO 512 := 256 ); -port( - clk : in std_logic; - rstn : in std_logic; - Ready : in std_logic; - Valid : in std_logic; - Full : in std_logic_vector(4 downto 0); - Data_re : in std_logic_vector(Data_sz-1 downto 0); - Data_im : in std_logic_vector(Data_sz-1 downto 0); - Read : out std_logic; - Write : out std_logic_vector(4 downto 0); - ReUse : out std_logic_vector(4 downto 0); - DATA : out std_logic_vector((5*Data_sz)-1 downto 0) -); -end entity; + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + Ready : IN STD_LOGIC; -- + Valid : IN STD_LOGIC; -- + Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- + Data_re : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); -- + Data_im : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); -- + + Read : OUT STD_LOGIC; -- Link_Read + Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- + ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + DATA : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0) + ); +END ENTITY; -architecture ar_Linker of Linker_FFT is +ARCHITECTURE ar_Linker OF Linker_FFT IS -type etat is (eX,e0,e1,e2); -signal ect : etat; + TYPE etat IS (eX, e0, e1, e2); + SIGNAL ect : etat; -signal DataTmp : std_logic_vector(Data_sz-1 downto 0); + SIGNAL DataTmp : STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); -signal sRead : std_logic; -signal sReady : std_logic; + SIGNAL sRead : STD_LOGIC; + SIGNAL sReady : STD_LOGIC; -signal FifoCpt : integer range 0 to 4 := 0; + SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0; -begin +BEGIN - process(clk,rstn) - begin - if(rstn='0')then - ect <= e0; - sRead <= '0'; - sReady <= '0'; - Write <= (others => '1'); - Reuse <= (others => '0'); - FifoCpt <= 0; - - elsif(clk'event and clk='1')then - sReady <= Ready; + PROCESS(clk, rstn) + BEGIN + IF(rstn = '0')then + ect <= e0; + sRead <= '0'; + sReady <= '0'; + Write <= (OTHERS => '1'); + Reuse <= (OTHERS => '0'); + FifoCpt <= 0; + + ELSIF(clk'EVENT AND clk = '1')then + sReady <= Ready; - if(sReady='1' and Ready='0')then - if(FifoCpt=4)then - FifoCpt <= 0; - else - FifoCpt <= FifoCpt + 1; - end if; - elsif(Ready='1')then - sRead <= not sRead; - else - sRead <= '0'; - end if; + IF(sReady = '1' and Ready = '0')THEN + IF(FifoCpt = 4)THEN + FifoCpt <= 0; + ELSE + FifoCpt <= FifoCpt + 1; + END IF; + ELSIF(Ready = '1')then + sRead <= NOT sRead; + ELSE + sRead <= '0'; + END IF; - case ect is + CASE ect IS - when e0 => - Write(FifoCpt) <= '1'; - if(Valid='1' and Full(FifoCpt)='0')then - DataTmp <= Data_im; - DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= Data_re; - Write(FifoCpt) <= '0'; - ect <= e1; - elsif(Full(FifoCpt)='1')then - ReUse(FifoCpt) <= '1'; - end if; + WHEN e0 => + Write(FifoCpt) <= '1'; + IF(Valid = '1' and Full(FifoCpt) = '0')THEN + DataTmp <= Data_im; + DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= Data_re; + Write(FifoCpt) <= '0'; + ect <= e1; + ELSIF(Full(FifoCpt) = '1')then + ReUse(FifoCpt) <= '1'; + END IF; - when e1 => - DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= DataTmp; - ect <= e0; - - when others => - null; + WHEN e1 => + DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= DataTmp; + ect <= e0; + + WHEN OTHERS => + NULL; - end case; - end if; - end process; + END CASE; + END IF; + END PROCESS; -Read <= sRead; + Read <= sRead; -end architecture; \ No newline at end of file +END ARCHITECTURE; diff --git a/lib/lpp/lpp_demux/DEMUX.vhd b/lib/lpp/lpp_demux/DEMUX.vhd --- a/lib/lpp/lpp_demux/DEMUX.vhd +++ b/lib/lpp/lpp_demux/DEMUX.vhd @@ -16,138 +16,141 @@ -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +-- Update : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr ------------------------------------------------------------------------------ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; -entity DEMUX is -generic( - Data_sz : integer range 1 to 32 := 16); -port( - clk : in std_logic; - rstn : in std_logic; +ENTITY DEMUX IS + GENERIC( + Data_sz : INTEGER RANGE 1 TO 32 := 16); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; - Read : in std_logic_vector(4 downto 0); - Load : in std_logic; + Read : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + Load : IN STD_LOGIC; - EmptyF0 : in std_logic_vector(4 downto 0); - EmptyF1 : in std_logic_vector(4 downto 0); - EmptyF2 : in std_logic_vector(4 downto 0); + EmptyF0 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + EmptyF1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + EmptyF2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF0 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); + DataF1 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); + DataF2 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); - WorkFreq : out std_logic_vector(1 downto 0); - Read_DEMUX : out std_logic_vector(14 downto 0); - Empty : out std_logic_vector(4 downto 0); - Data : out std_logic_vector((5*Data_sz)-1 downto 0) -); -end entity; + WorkFreq : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + Read_DEMUX : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); + Empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + Data : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0) + ); +END ENTITY; -architecture ar_DEMUX of DEMUX is +ARCHITECTURE ar_DEMUX OF DEMUX IS -type etat is (eX,e0,e1,e2,e3); -signal ect : etat; + TYPE etat IS (eX, e0, e1, e2, e3); + SIGNAL ect : etat; -signal load_reg : std_logic; -constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1'); + SIGNAL load_reg : STD_LOGIC; + CONSTANT Dummy_Read : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); -signal Countf0 : integer; -signal Countf1 : integer; -signal i : integer; + SIGNAL Countf0 : INTEGER; + SIGNAL Countf1 : INTEGER; + SIGNAL i : INTEGER; -begin - process(clk,rstn) - begin - if(rstn='0')then - ect <= e0; - load_reg <= '0'; - Countf0 <= 0; - Countf1 <= 0; - i <= 0; +BEGIN + PROCESS(clk, rstn) + BEGIN + IF(rstn = '0')then + ect <= e0; + load_reg <= '0'; + Countf0 <= 0; + Countf1 <= 0; + i <= 0; - elsif(clk'event and clk='1')then - load_reg <= Load; + ELSIF(clk'EVENT AND clk = '1')then + load_reg <= Load; - case ect is + CASE ect IS - when e0 => - if(load_reg = '1' and Load = '0')then - if(Countf0 = 24)then - Countf0 <= 0; - ect <= e1; - else - Countf0 <= Countf0 + 1; - ect <= e0; - end if; - end if; + WHEN e0 => + IF(load_reg = '1' AND Load = '0')THEN + IF(Countf0 = 24)THEN + Countf0 <= 0; + ect <= e1; + ELSE + Countf0 <= Countf0 + 1; + ect <= e0; + END IF; + END IF; - when e1 => - if(load_reg = '1' and Load = '0')then - if(Countf1 = 74)then - Countf1 <= 0; - ect <= e2; - else - Countf1 <= Countf1 + 1; - if(i=4)then - i <= 0; - ect <= e0; - else - i <= i+1; - ect <= e1; - end if; - end if; - end if; + WHEN e1 => + IF(load_reg = '1' AND Load = '0')THEN + IF(Countf1 = 74)THEN + Countf1 <= 0; + ect <= e2; + ELSE + Countf1 <= Countf1 + 1; + IF(i = 4)THEN + i <= 0; + ect <= e0; + ELSE + i <= i+1; + ect <= e1; + END IF; + END IF; + END IF; - when e2 => - if(load_reg = '1' and Load = '0')then - if(i=4)then - i <= 0; - ect <= e0; - else - i <= i+1; - ect <= e2; - end if; - end if; - - when others => - null; + WHEN e2 => + IF(load_reg = '1' AND Load = '0')THEN + IF(i = 4)THEN + i <= 0; + ect <= e0; + ELSE + i <= i+1; + ect <= e2; + END IF; + END IF; + + WHEN OTHERS => + NULL; - end case; - end if; - end process; + END CASE; + END IF; + END PROCESS; -with ect select - Empty <= EmptyF0 when e0, - EmptyF1 when e1, - EmptyF2 when e2, - (others => '1') when others; + WITH ect SELECT + Empty <= EmptyF0 WHEN e0, + EmptyF1 WHEN e1, + EmptyF2 WHEN e2, + (OTHERS => '1') WHEN OTHERS; -with ect select - Data <= DataF0 when e0, - DataF1 when e1, - DataF2 when e2, - (others => '0') when others; + WITH ect SELECT + Data <= DataF0 WHEN e0, + DataF1 WHEN e1, + DataF2 WHEN e2, + (OTHERS => '0') WHEN OTHERS; -with ect select - Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0, - Dummy_Read & Read & Dummy_Read when e1, - Read & Dummy_Read & Dummy_Read when e2, - (others => '1') when others; + WITH ect SELECT + Read_DEMUX <= Dummy_Read & Dummy_Read & Read WHEN e0, + Dummy_Read & Read & Dummy_Read WHEN e1, + Read & Dummy_Read & Dummy_Read WHEN e2, + (OTHERS => '1') WHEN OTHERS; -with ect select - WorkFreq <= "01" when e0, - "10" when e1, - "11" when e2, - "00" when others; + WITH ect SELECT + WorkFreq <= "01" WHEN e0, + "10" WHEN e1, + "11" WHEN e2, + "00" WHEN OTHERS; -end architecture; +END ARCHITECTURE; diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd --- a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd +++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd @@ -33,17 +33,17 @@ entity MatriceSpectrale is clkm : in std_logic; rstn : in std_logic; - FifoIN_Full : in std_logic_vector(4 downto 0); - SetReUse : in std_logic_vector(4 downto 0); + FifoIN_Full : in std_logic_vector(4 downto 0); -- + SetReUse : in std_logic_vector(4 downto 0); -- Valid : in std_logic; - Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); + Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); -- ACK : in std_logic; SM_Write : out std_logic; FlagError : out std_logic; Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); - Read : out std_logic_vector(4 downto 0); - ReUse : out std_logic_vector(4 downto 0); + Read : out std_logic_vector(4 downto 0); -- + ReUse : out std_logic_vector(4 downto 0); -- Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) ); end entity; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -262,19 +262,19 @@ BEGIN PORT MAP ( clkm => clk, rstn => rstn, - FifoIN_Full => FifoINT_Full, - SetReUse => FFT_ReUse, - Valid => Head_Valid, - Data_IN => FifoINT_Data, - ACK => DMA_ack, - SM_Write => SM_Wen, - FlagError => SM_FlagError, + FifoIN_Full => FifoINT_Full, -- + SetReUse => FFT_ReUse, -- + Valid => Head_Valid, -- HeaderBuilder + Data_IN => FifoINT_Data, -- + ACK => DMA_ack, -- HeaderBuilder + SM_Write => SM_Wen, -- HeaderBuilder + FlagError => SM_FlagError, -- UNUSED -- Pong => SM_Pong, - Statu => SM_Param, - Write => SM_Write, - Read => SM_Read, - ReUse => SM_ReUse, - Data_OUT => SM_Data); + Statu => SM_Param, -- HeaderBuilder + Write => SM_Write, -- FIFO MemOut + Read => SM_Read, -- + ReUse => SM_ReUse, -- + Data_OUT => SM_Data); -- FIFO MemOut ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd @@ -91,10 +91,10 @@ ENTITY lpp_lfr_ms_fsmdma IS addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) ); END; @@ -169,7 +169,7 @@ BEGIN '0'; header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" - '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE + '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE '1' WHEN component_type = component_type_pre + "0001" ELSE '0'; @@ -204,7 +204,7 @@ BEGIN header_data <= (OTHERS => '0'); fine_time_reg <= (OTHERS => '0'); - debug_reg_s( 2 DOWNTO 0) <= (OTHERS => '0'); + debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0'); log_empty_fifo <= '0'; @@ -212,12 +212,12 @@ BEGIN ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); header_reg_ack <= '0'; - + CASE state IS WHEN IDLE => debug_reg_s(2 DOWNTO 0) <= "000"; - - matrix_type <= header(1 DOWNTO 0); + + --matrix_type <= header(1 DOWNTO 0); --component_type <= header(5 DOWNTO 2); ready_matrix_f0_0 <= '0'; @@ -225,13 +225,13 @@ BEGIN ready_matrix_f1 <= '0'; ready_matrix_f2 <= '0'; error_bad_component_error <= '0'; - header_select <= '1'; - + --header_select <= '1'; + IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN - header_reg_ack <= '1'; + header_reg_ack <= '1'; debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0); debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2); - + matrix_type <= header_reg(1 DOWNTO 0); component_type <= header_reg(5 DOWNTO 2); component_type_pre <= component_type; @@ -242,22 +242,22 @@ BEGIN WHEN CHECK_COMPONENT_TYPE => debug_reg_s(2 DOWNTO 0) <= "001"; --header_ack <= '0'; - + IF header_check_ok = '1' THEN header_send <= '0'; -- IF component_type = "0000" THEN - address <= address_matrix; + address <= address_matrix; CASE matrix_type IS - WHEN "00" => matrix_time_f0_0 <= data_time; - WHEN "01" => matrix_time_f0_1 <= data_time; - WHEN "10" => matrix_time_f1 <= data_time; - WHEN "11" => matrix_time_f2 <= data_time ; + WHEN "00" => matrix_time_f0_0 <= data_time; + WHEN "01" => matrix_time_f0_1 <= data_time; + WHEN "10" => matrix_time_f1 <= data_time; + WHEN "11" => matrix_time_f2 <= data_time; WHEN OTHERS => NULL; END CASE; - - header_data <= data_time(31 DOWNTO 0); - fine_time_reg <= data_time(47 DOWNTO 32); + + header_data <= data_time(31 DOWNTO 0); + fine_time_reg <= data_time(47 DOWNTO 32); --state <= WRITE_COARSE_TIME; --header_send <= '1'; state <= SEND_DATA; @@ -274,59 +274,59 @@ BEGIN state <= TRASH_FIFO; END IF; - --WHEN WRITE_COARSE_TIME => - -- debug_reg_s(2 DOWNTO 0) <= "010"; - - -- header_ack <= '0'; + --WHEN WRITE_COARSE_TIME => + -- debug_reg_s(2 DOWNTO 0) <= "010"; + + -- header_ack <= '0'; - -- IF dma_ren = '0' THEN - -- header_send <= '0'; - -- ELSE - -- header_send <= header_send; - -- END IF; + -- IF dma_ren = '0' THEN + -- header_send <= '0'; + -- ELSE + -- header_send <= header_send; + -- END IF; - -- IF header_send_ko = '1' THEN - -- header_send <= '0'; - -- state <= TRASH_FIFO; - -- error_anticipating_empty_fifo <= '1'; - -- -- TODO : error sending header - -- ELSIF header_send_ok = '1' THEN - -- header_send <= '1'; - -- header_select <= '1'; - -- header_data(15 DOWNTO 0) <= fine_time_reg; - -- header_data(31 DOWNTO 16) <= (OTHERS => '0'); - -- state <= WRITE_FINE_TIME; - -- address <= address + 4; - -- END IF; - - - --WHEN WRITE_FINE_TIME => - -- debug_reg_s(2 DOWNTO 0) <= "011"; - - -- header_ack <= '0'; + -- IF header_send_ko = '1' THEN + -- header_send <= '0'; + -- state <= TRASH_FIFO; + -- error_anticipating_empty_fifo <= '1'; + -- -- TODO : error sending header + -- ELSIF header_send_ok = '1' THEN + -- header_send <= '1'; + -- header_select <= '1'; + -- header_data(15 DOWNTO 0) <= fine_time_reg; + -- header_data(31 DOWNTO 16) <= (OTHERS => '0'); + -- state <= WRITE_FINE_TIME; + -- address <= address + 4; + -- END IF; + + + --WHEN WRITE_FINE_TIME => + -- debug_reg_s(2 DOWNTO 0) <= "011"; - -- IF dma_ren = '0' THEN - -- header_send <= '0'; - -- ELSE - -- header_send <= header_send; - -- END IF; + -- header_ack <= '0'; + + -- IF dma_ren = '0' THEN + -- header_send <= '0'; + -- ELSE + -- header_send <= header_send; + -- END IF; - -- IF header_send_ko = '1' THEN - -- header_send <= '0'; - -- state <= TRASH_FIFO; - -- error_anticipating_empty_fifo <= '1'; - -- -- TODO : error sending header - -- ELSIF header_send_ok = '1' THEN - -- header_send <= '0'; - -- header_select <= '0'; - -- state <= SEND_DATA; - -- address <= address + 4; - -- END IF; + -- IF header_send_ko = '1' THEN + -- header_send <= '0'; + -- state <= TRASH_FIFO; + -- error_anticipating_empty_fifo <= '1'; + -- -- TODO : error sending header + -- ELSIF header_send_ok = '1' THEN + -- header_send <= '0'; + -- header_select <= '0'; + -- state <= SEND_DATA; + -- address <= address + 4; + -- END IF; WHEN TRASH_FIFO => debug_reg_s(2 DOWNTO 0) <= "100"; - + -- header_ack <= '0'; error_bad_component_error <= '0'; error_anticipating_empty_fifo <= '0'; @@ -340,7 +340,7 @@ BEGIN WHEN SEND_DATA => -- header_ack <= '0'; debug_reg_s(2 DOWNTO 0) <= "101"; - + IF fifo_empty = '1' OR log_empty_fifo = '1' THEN state <= IDLE; IF component_type = "1110" THEN --"1110" -- JC @@ -361,30 +361,30 @@ BEGIN WHEN WAIT_DATA_ACK => log_empty_fifo <= fifo_empty OR log_empty_fifo; - + debug_reg_s(2 DOWNTO 0) <= "110"; - + component_send <= '0'; IF component_send_ok = '1' THEN address <= address + 64; state <= SEND_DATA; ELSIF component_send_ko = '1' THEN error_anticipating_empty_fifo <= '0'; - state <= TRASH_FIFO; + state <= TRASH_FIFO; END IF; - - - --WHEN CHECK_LENGTH => - -- component_send <= '0'; - -- debug_reg_s(2 DOWNTO 0) <= "111"; - -- state <= IDLE; + + + --WHEN CHECK_LENGTH => + -- component_send <= '0'; + -- debug_reg_s(2 DOWNTO 0) <= "111"; + -- state <= IDLE; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS DMAWriteFSM_p; - + dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; dma_valid <= header_send WHEN header_select = '1' ELSE '0'; dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; @@ -403,13 +403,13 @@ BEGIN ----------------------------------------------------------------------------- PROCESS (HCLK, HRESETn) BEGIN -- PROCESS - IF HRESETn = '0' THEN -- asynchronous reset (active low) + IF HRESETn = '0' THEN -- asynchronous reset (active low) header_ack <= '0'; header_reg <= (OTHERS => '0'); header_reg_val <= '0'; - ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge header_ack <= '0'; - + IF header_val = '1' THEN header_ack <= '1'; header_reg <= header; @@ -428,4 +428,4 @@ BEGIN debug_reg_s(3) <= header_error; -END Behavioral; \ No newline at end of file +END Behavioral;