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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | |
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23 | 23 | LIBRARY IEEE; |
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24 | 24 | USE IEEE.STD_LOGIC_1164.ALL; |
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25 | 25 | USE IEEE.NUMERIC_STD.ALL; |
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26 | 26 | |
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27 | 27 | LIBRARY techmap; |
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28 | 28 | USE techmap.gencomp.ALL; |
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29 | 29 | |
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30 | 30 | LIBRARY lpp; |
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31 | 31 | USE lpp.lpp_sim_pkg.ALL; |
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32 | 32 | USE lpp.lpp_lfr_sim_pkg.ALL; |
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33 | 33 | USE lpp.lpp_lfr_apbreg_pkg.ALL; |
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34 | 34 | USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
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35 | 35 | USE lpp.iir_filter.ALL; |
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36 | 36 | USE lpp.FILTERcfg.ALL; |
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37 | 37 | USE lpp.lpp_memory.ALL; |
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38 | 38 | USE lpp.lpp_waveform_pkg.ALL; |
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39 | 39 | USE lpp.lpp_dma_pkg.ALL; |
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40 | 40 | USE lpp.lpp_top_lfr_pkg.ALL; |
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41 | 41 | USE lpp.lpp_lfr_pkg.ALL; |
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42 | 42 | USE lpp.general_purpose.ALL; |
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43 | 43 | --LIBRARY lpp; |
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44 | 44 | USE lpp.lpp_ad_conv.ALL; |
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45 | 45 | --USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
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46 | 46 | --USE lpp.lpp_lfr_apbreg_pkg.ALL; |
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47 | 47 | |
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48 | 48 | --USE work.debug.ALL; |
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49 | 49 | |
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50 | 50 | LIBRARY gaisler; |
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51 | 51 | USE gaisler.libdcom.ALL; |
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52 | 52 | USE gaisler.sim.ALL; |
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53 | 53 | USE gaisler.memctrl.ALL; |
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54 | 54 | USE gaisler.leon3.ALL; |
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55 | 55 | USE gaisler.uart.ALL; |
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56 | 56 | USE gaisler.misc.ALL; |
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57 | 57 | USE gaisler.spacewire.ALL; |
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58 | 58 | |
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59 | 59 | ENTITY TB IS |
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60 | 60 | |
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61 | 61 | END TB; |
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62 | 62 | |
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63 | 63 | ARCHITECTURE beh OF TB IS |
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64 | 64 | CONSTANT sramfile : STRING := "prom.srec"; |
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65 | 65 | -- CONSTANT sramfile : STRING; |
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66 | 66 | |
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67 | 67 | CONSTANT USE_ESA_MEMCTRL : INTEGER := 0; |
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68 | 68 | |
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69 | 69 | COMPONENT LFR_EQM |
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70 | 70 | GENERIC ( |
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71 | 71 | Mem_use : INTEGER; |
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72 | 72 | USE_BOOTLOADER : INTEGER; |
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73 | 73 | USE_ADCDRIVER : INTEGER; |
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74 | 74 | tech : INTEGER; |
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75 | 75 | tech_leon : INTEGER; |
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76 | 76 | DEBUG_FORCE_DATA_DMA : INTEGER; |
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77 | 77 | USE_DEBUG_VECTOR : INTEGER ); |
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78 | 78 | PORT ( |
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79 | 79 | clk50MHz : IN STD_ULOGIC; |
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80 | 80 | clk49_152MHz : IN STD_ULOGIC; |
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81 | 81 | reset : IN STD_ULOGIC; |
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82 | 82 | --TAG1 : IN STD_ULOGIC; |
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83 | 83 | --TAG3 : OUT STD_ULOGIC; |
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84 | 84 | --TAG2 : IN STD_ULOGIC; |
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85 | 85 | --TAG4 : OUT STD_ULOGIC; |
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86 | 86 | TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); |
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87 | 87 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); |
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88 | 88 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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89 | 89 | nSRAM_MBE : INOUT STD_LOGIC; |
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90 | 90 | nSRAM_E1 : OUT STD_LOGIC; |
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91 | 91 | nSRAM_E2 : OUT STD_LOGIC; |
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92 | 92 | nSRAM_W : OUT STD_LOGIC; |
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93 | 93 | nSRAM_G : OUT STD_LOGIC; |
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94 | 94 | nSRAM_BUSY : IN STD_LOGIC; |
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95 | 95 | spw1_en : OUT STD_LOGIC; |
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96 | 96 | spw1_din : IN STD_LOGIC; |
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97 | 97 | spw1_sin : IN STD_LOGIC; |
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98 | 98 | spw1_dout : OUT STD_LOGIC; |
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99 | 99 | spw1_sout : OUT STD_LOGIC; |
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100 | 100 | spw2_en : OUT STD_LOGIC; |
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101 | 101 | spw2_din : IN STD_LOGIC; |
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102 | 102 | spw2_sin : IN STD_LOGIC; |
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103 | 103 | spw2_dout : OUT STD_LOGIC; |
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104 | 104 | spw2_sout : OUT STD_LOGIC; |
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105 | 105 | bias_fail_sw : OUT STD_LOGIC; |
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106 | 106 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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107 | 107 | ADC_smpclk : OUT STD_LOGIC; |
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108 | 108 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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109 | 109 | DAC_SDO : OUT STD_LOGIC; |
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110 | 110 | DAC_SCK : OUT STD_LOGIC; |
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111 | 111 | DAC_SYNC : OUT STD_LOGIC; |
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112 | 112 | DAC_CAL_EN : OUT STD_LOGIC; |
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113 | 113 | HK_smpclk : OUT STD_LOGIC; |
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114 | 114 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
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115 | 115 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); |
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116 | 116 | END COMPONENT; |
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117 | 117 | |
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118 | 118 | SIGNAL clk50MHz : STD_ULOGIC := '0'; |
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119 | 119 | SIGNAL clk49_152MHz : STD_ULOGIC := '0'; |
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120 | 120 | SIGNAL reset : STD_ULOGIC; |
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121 | 121 | SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1); |
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122 | 122 | --SIGNAL TAG3 : STD_ULOGIC; |
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123 | 123 | --SIGNAL TAG2 : STD_ULOGIC := '1'; |
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124 | 124 | --SIGNAL TAG4 : STD_ULOGIC; |
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125 | 125 | SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0); |
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126 | 126 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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127 | 127 | SIGNAL nSRAM_MBE : STD_LOGIC; |
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128 | 128 | SIGNAL nSRAM_E1 : STD_LOGIC; |
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129 | 129 | SIGNAL nSRAM_E2 : STD_LOGIC; |
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130 | 130 | SIGNAL nSRAM_W : STD_LOGIC; |
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131 | 131 | SIGNAL nSRAM_G : STD_LOGIC; |
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132 | 132 | SIGNAL nSRAM_BUSY : STD_LOGIC; |
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133 | 133 | SIGNAL spw1_en : STD_LOGIC; |
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134 | 134 | SIGNAL spw1_din : STD_LOGIC := '1'; |
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135 | 135 | SIGNAL spw1_sin : STD_LOGIC := '1'; |
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136 | 136 | SIGNAL spw1_dout : STD_LOGIC; |
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137 | 137 | SIGNAL spw1_sout : STD_LOGIC; |
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138 | 138 | SIGNAL spw2_en : STD_LOGIC; |
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139 | 139 | SIGNAL spw2_din : STD_LOGIC := '1'; |
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140 | 140 | SIGNAL spw2_sin : STD_LOGIC := '1'; |
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141 | 141 | SIGNAL spw2_dout : STD_LOGIC; |
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142 | 142 | SIGNAL spw2_sout : STD_LOGIC; |
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143 | 143 | SIGNAL bias_fail_sw : STD_LOGIC; |
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144 | 144 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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145 | 145 | SIGNAL ADC_OEB_bar_CH_r : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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146 | 146 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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147 | 147 | SIGNAL ADC_smpclk : STD_LOGIC; |
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148 | 148 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); |
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149 | 149 | SIGNAL ADC_data_s : STD_LOGIC_VECTOR(13 DOWNTO 0); |
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150 | 150 | SIGNAL DAC_SDO : STD_LOGIC; |
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151 | 151 | SIGNAL DAC_SCK : STD_LOGIC; |
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152 | 152 | SIGNAL DAC_SYNC : STD_LOGIC; |
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153 | 153 | SIGNAL DAC_CAL_EN : STD_LOGIC; |
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154 | 154 | SIGNAL HK_smpclk : STD_LOGIC; |
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155 | 155 | SIGNAL ADC_OEB_bar_HK : STD_LOGIC; |
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156 | 156 | SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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157 | 157 | -- SIGNAL TAG8 : STD_LOGIC; |
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158 | 158 | |
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159 | 159 | CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20; |
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160 | 160 | CONSTANT SCRUB_PERIOD : INTEGER := 200/20; |
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161 | 161 | CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20; |
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162 | 162 | CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20; |
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163 | 163 | SIGNAL counter_scrub_period : INTEGER; |
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164 | 164 | |
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165 | 165 | |
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166 | 166 | --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800"; |
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167 | 167 | --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006"; |
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168 | 168 | --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F"; |
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169 | 169 | |
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170 | 170 | CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90"; |
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171 | 171 | CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; |
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172 | 172 | CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E"; |
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173 | 173 | CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; |
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174 | 174 | CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; |
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175 | 175 | CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000"; |
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176 | 176 | |
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177 | 177 | SIGNAL message_simu : STRING(1 TO 15) := "---------------"; |
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178 | 178 | SIGNAL data_message : STRING(1 TO 15) := "---------------"; |
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179 | 179 | SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); |
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180 | 180 | SIGNAL TXD1 : STD_LOGIC; |
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181 | 181 | SIGNAL RXD1 : STD_LOGIC; |
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182 | 182 | |
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183 | 183 | ----------------------------------------------------------------------------- |
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184 | 184 | CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000"; |
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185 | 185 | CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000"; |
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186 | 186 | CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000"; |
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187 | 187 | CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000"; |
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188 | 188 | CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000"; |
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189 | 189 | CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000"; |
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190 | 190 | CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000"; |
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191 | 191 | CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000"; |
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192 | 192 | CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000"; |
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193 | 193 | CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000"; |
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194 | 194 | CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000"; |
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195 | 195 | CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000"; |
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196 | 196 | CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000"; |
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197 | 197 | CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000"; |
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198 | 198 | |
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199 | 199 | |
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200 | 200 | TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
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201 | 201 | SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0); |
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202 | 202 | |
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203 | 203 | TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; |
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204 | 204 | SIGNAL sample_counter : counter_vector( 2 DOWNTO 0); |
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205 | 205 | |
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206 | 206 | SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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207 | 207 | SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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208 | 208 | SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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209 | 209 | SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0); |
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210 | 210 | |
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211 | 211 | SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
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212 | 212 | SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
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213 | 213 | SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
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214 | 214 | |
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215 | 215 | |
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216 | 216 | SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0); |
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217 | 217 | ----------------------------------------------------------------------------- |
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218 | 218 | CONSTANT srambanks : INTEGER := 2; |
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219 | 219 | CONSTANT sramwidth : INTEGER := 32; |
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220 | 220 | CONSTANT sramdepth : INTEGER := 19; |
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221 | 221 | SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0); |
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222 | 222 | ----------------------------------------------------------------------------- |
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223 | 223 | |
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224 | 224 | BEGIN -- beh |
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225 | 225 | |
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226 | 226 | LFR_EQM_1 : LFR_EQM |
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227 | 227 | GENERIC MAP ( |
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228 | 228 | Mem_use => use_RAM, |
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229 | 229 | USE_BOOTLOADER => 0, |
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230 | 230 | USE_ADCDRIVER => 1, |
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231 | 231 | tech => apa3e, |
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232 | 232 | tech_leon => apa3e, |
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233 | 233 | DEBUG_FORCE_DATA_DMA => 0, |
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234 | 234 | USE_DEBUG_VECTOR => 0) |
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235 | 235 | PORT MAP ( |
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236 | 236 | clk50MHz => clk50MHz, --IN --ok |
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237 | 237 | clk49_152MHz => clk49_152MHz, --in --ok |
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238 | 238 | reset => reset, --IN --ok |
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239 | 239 | |
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240 | 240 | TAG => TAG, |
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241 | 241 | --TAG1 => TAG1, --in |
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242 | 242 | --TAG3 => TAG3, --out |
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243 | 243 | --TAG2 => TAG2, --IN --ok |
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244 | 244 | --TAG4 => TAG4, --out --ok |
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245 | 245 | |
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246 | 246 | address => address, --out |
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247 | 247 | data => data, --inout |
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248 | 248 | nSRAM_MBE => nSRAM_MBE, --inout |
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249 | 249 | nSRAM_E1 => nSRAM_E1, --out |
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250 | 250 | nSRAM_E2 => nSRAM_E2, --out |
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251 | 251 | nSRAM_W => nSRAM_W, --out |
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252 | 252 | nSRAM_G => nSRAM_G, --out |
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253 | 253 | nSRAM_BUSY => nSRAM_BUSY, --in |
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254 | 254 | |
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255 | 255 | spw1_en => spw1_en, --out --ok |
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256 | 256 | spw1_din => spw1_din, --in --ok |
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257 | 257 | spw1_sin => spw1_sin, --in --ok |
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258 | 258 | spw1_dout => spw1_dout, --out --ok |
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259 | 259 | spw1_sout => spw1_sout, --out --ok |
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260 | 260 | |
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261 | 261 | spw2_en => spw2_en, --out --ok |
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262 | 262 | spw2_din => spw2_din, --in --ok |
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263 | 263 | spw2_sin => spw2_sin, --in --ok |
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264 | 264 | spw2_dout => spw2_dout, --out --ok |
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265 | 265 | spw2_sout => spw2_sout, --out --ok |
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266 | 266 | |
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267 | 267 | bias_fail_sw => bias_fail_sw, --OUT --ok |
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268 | 268 | |
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269 | 269 | ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok |
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270 | 270 | ADC_smpclk => ADC_smpclk, --out --ok |
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271 | 271 | ADC_data => ADC_data, --IN --ok |
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272 | 272 | |
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273 | 273 | DAC_SDO => DAC_SDO, --out --ok |
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274 | 274 | DAC_SCK => DAC_SCK, --out --ok |
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275 | 275 | DAC_SYNC => DAC_SYNC, --out --ok |
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276 | 276 | DAC_CAL_EN => DAC_CAL_EN, --out --ok |
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277 | 277 | |
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278 | 278 | HK_smpclk => HK_smpclk, --out --ok |
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279 | 279 | ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok |
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280 | 280 | HK_SEL => HK_SEL); --out --ok |
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281 | 281 | |
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282 | 282 | |
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283 | 283 | ----------------------------------------------------------------------------- |
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284 | 284 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
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285 | 285 | clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz |
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286 | 286 | ----------------------------------------------------------------------------- |
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287 | 287 | |
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288 | 288 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
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289 | 289 | TestModule_RHF1401_1 : TestModule_RHF1401 |
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290 | 290 | GENERIC MAP ( |
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291 | 291 | freq => 2400,--24*(I*5+1), |
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292 | 292 | amplitude => 4000,--8000/(I*5+1), |
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293 | 293 | impulsion => 0) |
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294 | 294 | PORT MAP ( |
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295 | 295 | ADC_smpclk => ADC_smpclk, |
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296 | 296 | ADC_OEB_bar => ADC_OEB_bar_CH_s(I), |
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297 | 297 | ADC_data => ADC_data_s); |
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298 | 298 | --ADC_data_s <= "00" & X"190"; |
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299 | 299 | END GENERATE MODULE_RHF1401; |
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300 | 300 | |
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301 | 301 | ADC_OEB_bar_CH_s <= TRANSPORT ADC_OEB_bar_CH AFTER 10 ns; |
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302 |
ADC_data <= TRANSPORT ADC_data_s AFTER |
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302 | ADC_data <= TRANSPORT ADC_data_s AFTER 35 ns; | |
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303 | 303 | ----------------------------------------------------------------------------- |
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304 | 304 | PROCESS (clk50MHz, reset) |
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305 | 305 | BEGIN -- PROCESS |
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306 | 306 | IF reset = '0' THEN -- asynchronous reset (active low) |
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307 | 307 | nSRAM_BUSY <= '1'; |
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308 | 308 | counter_scrub_period <= 0; |
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309 | 309 | ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge |
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310 | 310 | IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN |
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311 | 311 | counter_scrub_period <= 0; |
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312 | 312 | ELSE |
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313 | 313 | counter_scrub_period <= counter_scrub_period + 1; |
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314 | 314 | END IF; |
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315 | 315 | |
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316 | 316 | IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN |
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317 | 317 | nSRAM_BUSY <= '1'; |
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318 | 318 | ELSE |
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319 | 319 | nSRAM_BUSY <= '0'; |
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320 | 320 | END IF; |
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321 | 321 | END IF; |
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322 | 322 | END PROCESS; |
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323 | 323 | |
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324 | 324 | ----------------------------------------------------------------------------- |
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325 | 325 | -- TB |
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326 | 326 | ----------------------------------------------------------------------------- |
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327 | 327 | TAG(1) <= TXD1; |
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328 | 328 | TAG(2) <= '1'; |
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329 | 329 | RXD1 <= TAG(3); |
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330 | 330 | |
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331 | 331 | PROCESS |
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332 | 332 | CONSTANT txp : TIME := 320 ns; |
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333 | 333 | VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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334 | 334 | BEGIN -- PROCESS |
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335 | 335 | TXD1 <= '1'; |
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336 | 336 | reset <= '0'; |
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337 | 337 | WAIT FOR 500 ns; |
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338 | 338 | reset <= '1'; |
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339 | 339 | WAIT FOR 100 us; |
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340 | 340 | message_simu <= "0 - UART init "; |
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341 | 341 | UART_INIT(TXD1, txp); |
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342 | 342 | |
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343 | 343 | --------------------------------------------------------------------------- |
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344 | 344 | -- LAUNCH leon 3 software |
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345 | 345 | --------------------------------------------------------------------------- |
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346 | 346 | message_simu <= "2- GO Leon3...."; |
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347 | 347 | |
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348 | 348 | -- bool dsu3plugin::configureTarget() --------------------------------------------------------------------------------------------------------------------------- |
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349 | 349 | --Force a debug break |
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350 | 350 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS); |
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351 | 351 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20); |
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352 | 352 | --Clear time tag counter |
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353 | 353 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8); |
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354 | 354 | --Clear ASR registers |
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355 | 355 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040); |
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356 | 356 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000"); |
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357 | 357 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000"); |
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358 | 358 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024); |
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359 | 359 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); |
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360 | 360 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); |
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361 | 361 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); |
|
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362 | 362 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); |
|
|
363 | 363 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000"); |
|
|
364 | 364 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000"); |
|
|
365 | 365 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000"); |
|
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366 | 366 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000"); |
|
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367 | 367 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48); |
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368 | 368 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C); |
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369 | 369 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040); |
|
|
370 | 370 | |
|
|
371 | 371 | IF USE_ESA_MEMCTRL = 1 THEN |
|
|
372 | 372 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS); |
|
|
373 | 373 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60"); |
|
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374 | 374 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000"); |
|
|
375 | 375 | END IF; |
|
|
376 | 376 | |
|
|
377 | 377 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); |
|
|
378 | 378 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); |
|
|
379 | 379 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); |
|
|
380 | 380 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); |
|
|
381 | 381 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24); |
|
|
382 | 382 | |
|
|
383 | 383 | --memSet(DSUBASEADDRESS+0x300000,0,1567); |
|
|
384 | 384 | |
|
|
385 | 385 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000); |
|
|
386 | 386 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0"); |
|
|
387 | 387 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002"); |
|
|
388 | 388 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000"); |
|
|
389 | 389 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000"); |
|
|
390 | 390 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004"); |
|
|
391 | 391 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000"); |
|
|
392 | 392 | |
|
|
393 | 393 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020); |
|
|
394 | 394 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000"); |
|
|
395 | 395 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000"); |
|
|
396 | 396 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000"); |
|
|
397 | 397 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000"); |
|
|
398 | 398 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000"); |
|
|
399 | 399 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0"); |
|
|
400 | 400 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000"); |
|
|
401 | 401 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000"); |
|
|
402 | 402 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000"); |
|
|
403 | 403 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000"); |
|
|
404 | 404 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000"); |
|
|
405 | 405 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000"); |
|
|
406 | 406 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000"); |
|
|
407 | 407 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000"); |
|
|
408 | 408 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000"); |
|
|
409 | 409 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000"); |
|
|
410 | 410 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000"); |
|
|
411 | 411 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000"); |
|
|
412 | 412 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000"); |
|
|
413 | 413 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000"); |
|
|
414 | 414 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000"); |
|
|
415 | 415 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000"); |
|
|
416 | 416 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000"); |
|
|
417 | 417 | |
|
|
418 | 418 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS); |
|
|
419 | 419 | |
|
|
420 | 420 | --//Disable interrupts |
|
|
421 | 421 | --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0); |
|
|
422 | 422 | --if(APBIRQCTRLRBASEADD == (unsigned int)-1) |
|
|
423 | 423 | -- return false; |
|
|
424 | 424 | --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040); |
|
|
425 | 425 | --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080); |
|
|
426 | 426 | --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD); |
|
|
427 | 427 | |
|
|
428 | 428 | -- //Set up timer |
|
|
429 | 429 | --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0); |
|
|
430 | 430 | --if(APBTIMERBASEADD == (unsigned int)-1) |
|
|
431 | 431 | -- return false; |
|
|
432 | 432 | --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014); |
|
|
433 | 433 | --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04); |
|
|
434 | 434 | --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018); |
|
|
435 | 435 | |
|
|
436 | 436 | |
|
|
437 | 437 | --------------------------------------------------------------------------- |
|
|
438 | 438 | --bool dsu3plugin::setCacheEnable(bool enabled) |
|
|
439 | 439 | --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0); |
|
|
440 | 440 | --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000; |
|
|
441 | 441 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024); |
|
|
442 | 442 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000); |
|
|
443 | 443 | data_read <= data_read_v; |
|
|
444 | 444 | --if(enabled){ |
|
|
445 | 445 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000); |
|
|
446 | 446 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000); |
|
|
447 | 447 | --}else{ |
|
|
448 | 448 | --WriteRegs(uIntlist()<<((!0x0001000F)®),DSUBASEADDRESS+0x700000); |
|
|
449 | 449 | --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000); |
|
|
450 | 450 | --} |
|
|
451 | 451 | |
|
|
452 | 452 | |
|
|
453 | 453 | -- void dsu3plugin::run() --------------------------------------------------------------------------------------------------------------------------------------- |
|
|
454 | 454 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020); |
|
|
455 | 455 | |
|
|
456 | 456 | --------------------------------------------------------------------------- |
|
|
457 | 457 | --message_simu <= "1 - UART test "; |
|
|
458 | 458 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF"); |
|
|
459 | 459 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A"); |
|
|
460 | 460 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B"); |
|
|
461 | 461 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v); |
|
|
462 | 462 | --data_read <= data_read_v; |
|
|
463 | 463 | --data_message <= "GPIO_data_write"; |
|
|
464 | 464 | |
|
|
465 | 465 | -- UNSET the LFR reset |
|
|
466 | 466 | message_simu <= "2 - LFR UNRESET"; |
|
|
467 | 467 | UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT); |
|
|
468 | 468 | -- |
|
|
469 | 469 | message_simu <= "3 - LFR CONFIG "; |
|
|
470 | 470 | LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR, |
|
|
471 | 471 | ADDR_BUFFER_MS_F0_0, |
|
|
472 | 472 | ADDR_BUFFER_MS_F0_1, |
|
|
473 | 473 | ADDR_BUFFER_MS_F1_0, |
|
|
474 | 474 | ADDR_BUFFER_MS_F1_1, |
|
|
475 | 475 | ADDR_BUFFER_MS_F2_0, |
|
|
476 | 476 | ADDR_BUFFER_MS_F2_1); |
|
|
477 | 477 | |
|
|
478 | 478 | |
|
|
479 | 479 | LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp, |
|
|
480 | 480 | LFR_MODE_SBM1, |
|
|
481 | 481 | X"7FFFFFFF", -- START DATE |
|
|
482 | 482 | |
|
|
483 | 483 | "00000", --DATA_SHAPING ( 4 DOWNTO 0) |
|
|
484 | 484 | X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0) |
|
|
485 | 485 | X"0001280A", --DELTA_F0 (31 DOWNTO 0) |
|
|
486 | 486 | X"00000007", --DELTA_F0_2 (31 DOWNTO 0) |
|
|
487 | 487 | X"0001283F", --DELTA_F1 (31 DOWNTO 0) |
|
|
488 | 488 | X"000127FF", --DELTA_F2 (31 DOWNTO 0) |
|
|
489 | 489 | |
|
|
490 | 490 | ADDR_BASE_LFR, |
|
|
491 | 491 | ADDR_BUFFER_WFP_F0_0, |
|
|
492 | 492 | ADDR_BUFFER_WFP_F0_1, |
|
|
493 | 493 | ADDR_BUFFER_WFP_F1_0, |
|
|
494 | 494 | ADDR_BUFFER_WFP_F1_1, |
|
|
495 | 495 | ADDR_BUFFER_WFP_F2_0, |
|
|
496 | 496 | ADDR_BUFFER_WFP_F2_1, |
|
|
497 | 497 | ADDR_BUFFER_WFP_F3_0, |
|
|
498 | 498 | ADDR_BUFFER_WFP_F3_1); |
|
|
499 | 499 | |
|
|
500 | 500 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); |
|
|
501 | 501 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); |
|
|
502 | 502 | |
|
|
503 | 503 | |
|
|
504 | 504 | --------------------------------------------------------------------------- |
|
|
505 | 505 | -- CONFIG LFR 2 |
|
|
506 | 506 | --------------------------------------------------------------------------- |
|
|
507 | 507 | --message_simu <= "3 - LFR2 CONFIG"; |
|
|
508 | 508 | --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2, |
|
|
509 | 509 | -- X"40000000", |
|
|
510 | 510 | -- X"40001000", |
|
|
511 | 511 | -- X"40002000", |
|
|
512 | 512 | -- X"40003000", |
|
|
513 | 513 | -- X"40004000", |
|
|
514 | 514 | -- X"40005000"); |
|
|
515 | 515 | |
|
|
516 | 516 | |
|
|
517 | 517 | --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, |
|
|
518 | 518 | -- LFR_MODE_SBM1, |
|
|
519 | 519 | -- X"7FFFFFFF", -- START DATE |
|
|
520 | 520 | |
|
|
521 | 521 | -- "00000",--DATA_SHAPING ( 4 DOWNTO 0) |
|
|
522 | 522 | -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) |
|
|
523 | 523 | -- X"0001280A",--DELTA_F0 (31 DOWNTO 0) |
|
|
524 | 524 | -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0) |
|
|
525 | 525 | -- X"0001283F",--DELTA_F1 (31 DOWNTO 0) |
|
|
526 | 526 | -- X"000127FF",--DELTA_F2 (31 DOWNTO 0) |
|
|
527 | 527 | |
|
|
528 | 528 | -- ADDR_BASE_LFR_2, |
|
|
529 | 529 | -- X"40006000", |
|
|
530 | 530 | -- X"40007000", |
|
|
531 | 531 | -- X"40008000", |
|
|
532 | 532 | -- X"40009000", |
|
|
533 | 533 | -- X"4000A000", |
|
|
534 | 534 | -- X"4000B000", |
|
|
535 | 535 | -- X"4000C000", |
|
|
536 | 536 | -- X"4000D000"); |
|
|
537 | 537 | |
|
|
538 | 538 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F"); |
|
|
539 | 539 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); |
|
|
540 | 540 | |
|
|
541 | 541 | --------------------------------------------------------------------------- |
|
|
542 | 542 | --------------------------------------------------------------------------- |
|
|
543 | 543 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"5" & "10", X"FFFFFFFF"); |
|
|
544 | 544 | |
|
|
545 | 545 | |
|
|
546 | 546 | message_simu <= "4 - GO GO GO !!"; |
|
|
547 | 547 | data_message <= "---------------"; |
|
|
548 | 548 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000"); |
|
|
549 | 549 | -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000"); |
|
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550 | 550 | |
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551 | 551 | |
|
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552 | 552 | data_read_v := (OTHERS => '1'); |
|
|
553 | 553 | READ_STATUS : LOOP |
|
|
554 | 554 | data_message <= "---------------"; |
|
|
555 | 555 | WAIT FOR 2 ms; |
|
|
556 | 556 | data_message <= "READ_STATUS_SM_"; |
|
|
557 | 557 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); |
|
|
558 | 558 | --data_message <= "--------------r"; |
|
|
559 | 559 | --data_read <= data_read_v; |
|
|
560 | 560 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); |
|
|
561 | 561 | |
|
|
562 | 562 | data_message <= "READ_STATUS_WF_"; |
|
|
563 | 563 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); |
|
|
564 | 564 | --data_message <= "--------------r"; |
|
|
565 | 565 | --data_read <= data_read_v; |
|
|
566 | 566 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); |
|
|
567 | 567 | END LOOP READ_STATUS; |
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568 | 568 | |
|
|
569 | 569 | WAIT; |
|
|
570 | 570 | END PROCESS; |
|
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571 | 571 | |
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572 | 572 | |
|
|
573 | 573 | ----------------------------------------------------------------------------- |
|
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574 | 574 | PROCESS (nSRAM_W, reset) |
|
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575 | 575 | BEGIN -- PROCESS |
|
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576 | 576 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
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577 | 577 | data_pre_f0 <= X"00020001"; |
|
|
578 | 578 | data_pre_f1 <= X"00020001"; |
|
|
579 | 579 | data_pre_f2 <= X"00020001"; |
|
|
580 | 580 | |
|
|
581 | 581 | addr_pre_f0 <= (OTHERS => '0'); |
|
|
582 | 582 | addr_pre_f1 <= (OTHERS => '0'); |
|
|
583 | 583 | addr_pre_f2 <= (OTHERS => '0'); |
|
|
584 | 584 | |
|
|
585 | 585 | error_wfp <= "000"; |
|
|
586 | 586 | error_wfp_addr <= "000"; |
|
|
587 | 587 | |
|
|
588 | 588 | sample_counter <= (0,0,0); |
|
|
589 | 589 | |
|
|
590 | 590 | ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge |
|
|
591 | 591 | error_wfp <= "000"; |
|
|
592 | 592 | error_wfp_addr <= "000"; |
|
|
593 | 593 | ------------------------------------------------------------------------- |
|
|
594 | 594 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR |
|
|
595 | 595 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN |
|
|
596 | 596 | |
|
|
597 | 597 | addr_pre_f0 <= address(13 DOWNTO 0); |
|
|
598 | 598 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN |
|
|
599 | 599 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
|
600 | 600 | error_wfp_addr(0) <= '1'; |
|
|
601 | 601 | END IF; |
|
|
602 | 602 | END IF; |
|
|
603 | 603 | |
|
|
604 | 604 | data_pre_f0 <= data; |
|
|
605 | 605 | CASE data_pre_f0 IS |
|
|
606 | 606 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF; |
|
|
607 | 607 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF; |
|
|
608 | 608 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF; |
|
|
609 | 609 | WHEN OTHERS => error_wfp(0) <= '1'; |
|
|
610 | 610 | END CASE; |
|
|
611 | 611 | |
|
|
612 | 612 | |
|
|
613 | 613 | END IF; |
|
|
614 | 614 | ------------------------------------------------------------------------- |
|
|
615 | 615 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR |
|
|
616 | 616 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN |
|
|
617 | 617 | |
|
|
618 | 618 | addr_pre_f1 <= address(13 DOWNTO 0); |
|
|
619 | 619 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN |
|
|
620 | 620 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
|
621 | 621 | error_wfp_addr(1) <= '1'; |
|
|
622 | 622 | END IF; |
|
|
623 | 623 | END IF; |
|
|
624 | 624 | |
|
|
625 | 625 | data_pre_f1 <= data; |
|
|
626 | 626 | CASE data_pre_f1 IS |
|
|
627 | 627 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF; |
|
|
628 | 628 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF; |
|
|
629 | 629 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF; |
|
|
630 | 630 | WHEN OTHERS => error_wfp(1) <= '1'; |
|
|
631 | 631 | END CASE; |
|
|
632 | 632 | |
|
|
633 | 633 | sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16); |
|
|
634 | 634 | sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0); |
|
|
635 | 635 | sample_counter(1) <= (sample_counter(1) + 1) MOD 3; |
|
|
636 | 636 | |
|
|
637 | 637 | END IF; |
|
|
638 | 638 | ------------------------------------------------------------------------- |
|
|
639 | 639 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR |
|
|
640 | 640 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN |
|
|
641 | 641 | |
|
|
642 | 642 | addr_pre_f2 <= address(13 DOWNTO 0); |
|
|
643 | 643 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN |
|
|
644 | 644 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
|
645 | 645 | error_wfp_addr(2) <= '1'; |
|
|
646 | 646 | END IF; |
|
|
647 | 647 | END IF; |
|
|
648 | 648 | |
|
|
649 | 649 | data_pre_f2 <= data; |
|
|
650 | 650 | CASE data_pre_f2 IS |
|
|
651 | 651 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF; |
|
|
652 | 652 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF; |
|
|
653 | 653 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF; |
|
|
654 | 654 | WHEN OTHERS => error_wfp(2) <= '1'; |
|
|
655 | 655 | END CASE; |
|
|
656 | 656 | |
|
|
657 | 657 | sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16); |
|
|
658 | 658 | sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0); |
|
|
659 | 659 | sample_counter(2) <= (sample_counter(2) + 1) MOD 3; |
|
|
660 | 660 | |
|
|
661 | 661 | END IF; |
|
|
662 | 662 | END IF; |
|
|
663 | 663 | END PROCESS; |
|
|
664 | 664 | ----------------------------------------------------------------------------- |
|
|
665 | 665 | ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1; |
|
|
666 | 666 | |
|
|
667 | 667 | sbanks : FOR k IN 0 TO srambanks-1 GENERATE |
|
|
668 | 668 | sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE |
|
|
669 | 669 | sr0 : sram |
|
|
670 | 670 | GENERIC MAP ( |
|
|
671 | 671 | index => i, |
|
|
672 | 672 | abits => sramdepth, |
|
|
673 | 673 | fname => sramfile) |
|
|
674 | 674 | PORT MAP ( |
|
|
675 | 675 | address, |
|
|
676 | 676 | data(31-i*8 DOWNTO 24-i*8), |
|
|
677 | 677 | ramsn(k), |
|
|
678 | 678 | nSRAM_W, |
|
|
679 | 679 | nSRAM_G |
|
|
680 | 680 | ); |
|
|
681 | 681 | END GENERATE; |
|
|
682 | 682 | END GENERATE; |
|
|
683 | 683 | |
|
|
684 | 684 | END beh; |
|
|
685 | 685 | |
| @@ -1,213 +1,216 | |||
|
|
1 | 1 | onerror {resume} |
|
|
2 | 2 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc |
|
|
3 | 3 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(4 downto 3)} HWDATA |
|
|
4 | 4 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(7 downto 6)} DMA_DATA |
|
|
5 | 5 | quietly WaveActivateNextPane {} 0 |
|
|
6 | 6 | add wave -noupdate -expand -group ALL /tb/data_message |
|
|
7 | 7 | add wave -noupdate -expand -group ALL /tb/message_simu |
|
|
8 | 8 | add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1 |
|
|
9 | 9 | add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2 |
|
|
10 | 10 | add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G |
|
|
11 | 11 | add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W |
|
|
12 | 12 | add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/data |
|
|
13 | 13 | add wave -noupdate -expand -group ALL -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc |
|
|
14 | 14 | add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address |
|
|
15 | 15 | add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY |
|
|
16 | 16 | add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE |
|
|
17 | 17 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val |
|
|
18 | 18 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid |
|
|
19 | 19 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current |
|
|
20 | 20 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data |
|
|
21 | 21 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg |
|
|
22 | 22 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/state_GEN_OEn |
|
|
23 | 23 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_falling |
|
|
24 | 24 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s |
|
|
25 | 25 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s_reg |
|
|
26 | 26 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync |
|
|
27 | 27 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_reg |
|
|
28 | 28 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled |
|
|
29 | 29 | add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data |
|
|
30 | 30 | add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk |
|
|
31 | 31 | add wave -noupdate -expand -group ALL -expand -group ADC -format Analog-Step -height 74 -max 24.0 /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_cycle_counter |
|
|
32 | 32 | add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/ADC_OEB_bar_HK |
|
|
33 | 33 | add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_OEB_bar_CH |
|
|
34 | 34 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample |
|
|
35 | 35 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val |
|
|
36 | 36 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val |
|
|
37 | 37 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata |
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38 | 38 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val |
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39 | 39 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata |
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40 | 40 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val |
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41 | 41 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata |
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42 | 42 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val |
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43 | 43 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata |
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44 | 44 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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45 | 45 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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46 | 46 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
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47 | 47 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data |
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48 | 48 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send |
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49 | 49 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter |
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50 | 50 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg |
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51 | 51 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig |
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52 | 52 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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53 | 53 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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54 | 54 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out |
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55 | 55 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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56 | 56 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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57 | 57 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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58 | 58 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk |
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59 | 59 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data |
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60 | 60 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid |
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61 | 61 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex |
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62 | 62 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn |
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63 | 63 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send |
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64 | 64 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
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65 | 65 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid |
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66 | 66 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version |
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67 | 67 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out |
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68 | 68 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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69 | 69 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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70 | 70 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig |
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71 | 71 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter |
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72 | 72 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg |
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73 | 73 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window |
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74 | 74 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window |
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75 | 75 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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76 | 76 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp |
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77 | 77 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp |
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78 | 78 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 |
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79 | 79 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/data_pre_f1 |
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80 | 80 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/data_pre_f2 |
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81 | 81 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f0 |
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82 | 82 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f1 |
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83 | 83 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f2 |
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84 | 84 | add wave -noupdate -expand -group ALL /tb/error_wfp |
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85 | 85 | add wave -noupdate -expand -group ALL /tb/error_wfp_addr |
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86 | 86 | add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a |
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87 | 87 | add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1 |
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88 | 88 | add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe |
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89 | 89 | add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we |
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90 | 90 | add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a |
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91 | 91 | add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1 |
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92 | 92 | add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe |
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93 | 93 | add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we |
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94 | 94 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi |
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95 | 95 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo |
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96 | 96 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi |
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97 | 97 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso |
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98 | 98 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}} -expand} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmi |
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99 | 99 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo |
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100 | 100 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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101 | 101 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out |
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102 | 102 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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103 | 103 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
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104 | 104 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data |
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105 | 105 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send |
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106 | 106 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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107 | 107 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg |
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108 | 108 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig |
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109 | 109 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window |
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110 | 110 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window |
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111 | 111 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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112 | 112 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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113 | 113 | add wave -noupdate -expand -group ALL -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1) |
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114 | 114 | add wave -noupdate -expand -group ALL -height 74 -max 326.0 -min 256.0 /tb/sample_counter |
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115 | 115 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/debug_vector |
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116 | 116 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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117 | 117 | add wave -noupdate -expand -group ALL -radix unsigned /tb/LFR_EQM_1/HWDATA |
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118 | 118 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY |
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119 | 119 | add wave -noupdate -expand -group ALL -radix unsigned /tb/LFR_EQM_1/DMA_DATA |
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120 | 120 | add wave -noupdate -expand -group ALL -label DMA_REN /tb/LFR_EQM_1/debug_vector(8) |
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121 | 121 | add wave -noupdate -expand -group ALL -label HREADY /tb/LFR_EQM_1/debug_vector(5) |
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122 | 122 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_clk |
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123 | 123 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_rstn |
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124 | 124 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn |
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125 | 125 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk |
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126 | 126 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data |
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127 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg | |
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128 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid_s | |
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129 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid | |
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130 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val_s2 | |
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127 | 131 | add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE |
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128 | 132 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) |
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129 | 133 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) |
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130 | 134 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) |
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131 | 135 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) |
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132 | 136 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) |
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133 | 137 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) |
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134 | 138 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) |
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135 | 139 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) |
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136 | 140 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) |
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137 | 141 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv |
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138 | 142 | add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample |
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139 | 143 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val |
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140 | 144 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high |
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141 | 145 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv |
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142 | 146 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current |
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143 | 147 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled |
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144 | 148 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result |
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145 | 149 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled |
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146 | 150 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid |
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147 | 151 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data |
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148 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg | |
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149 | 152 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected |
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150 | 153 | add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg |
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151 | 154 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample |
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152 | 155 | add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val |
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153 | 156 | add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-format Analog-Step -height 15 -max 7517.0 -min -7504.0 -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) {-height 15 -radix decimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample |
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154 | 157 | add wave -noupdate -radix decimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in_val |
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155 | 158 | add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in |
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156 | 159 | add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val |
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157 | 160 | add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out |
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158 | 161 | add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(7)/TestModule_RHF1401_1/reg |
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159 | 162 | add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(6)/TestModule_RHF1401_1/reg |
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160 | 163 | add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(5)/TestModule_RHF1401_1/reg |
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161 | 164 | add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(4)/TestModule_RHF1401_1/reg |
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162 | 165 | add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(3)/TestModule_RHF1401_1/reg |
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163 | 166 | add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(2)/TestModule_RHF1401_1/reg |
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164 | 167 | add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(1)/TestModule_RHF1401_1/reg |
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165 | 168 | add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(0)/TestModule_RHF1401_1/reg |
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166 | 169 | add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) {-format Analog-Step -height 74 -max 14061.999999999998 -min -14378.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim |
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167 | 170 | add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim |
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168 | 171 | add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim |
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169 | 172 | add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim |
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170 | 173 | add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/sample(8) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(7) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(6) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(5) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(4) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(3) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(2) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(1) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(0) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal}} /tb/LFR_EQM_1/sample |
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171 | 174 | add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample_s(8) -radix decimal} {/tb/LFR_EQM_1/sample_s(7) -radix decimal} {/tb/LFR_EQM_1/sample_s(6) -radix decimal} {/tb/LFR_EQM_1/sample_s(5) -radix decimal} {/tb/LFR_EQM_1/sample_s(4) -radix decimal} {/tb/LFR_EQM_1/sample_s(3) -radix decimal} {/tb/LFR_EQM_1/sample_s(2) -radix decimal} {/tb/LFR_EQM_1/sample_s(1) -radix decimal} {/tb/LFR_EQM_1/sample_s(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/sample_s(8) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/sample_s |
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172 | 175 | add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in |
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173 | 176 | add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim |
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174 | 177 | add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out |
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175 | 178 | add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0 |
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176 | 179 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH |
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177 | 180 | add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data |
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178 | 181 | add wave -noupdate /tb/LFR_EQM_1/sample_val |
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179 | 182 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/state_GEN_OEn |
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180 | 183 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg |
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181 | 184 | add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg |
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182 | 185 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current |
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183 | 186 | add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out |
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184 | 187 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_wen |
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185 | 188 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/wdata |
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186 | 189 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_data |
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187 | 190 | add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_ren |
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188 | 191 | add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_buffer_full |
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189 | 192 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/data |
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190 | 193 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W |
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191 | 194 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/address |
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192 | 195 | add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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193 | 196 | add wave -noupdate -expand /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/fifo_ren |
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194 | 197 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample |
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195 | 198 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val |
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196 | 199 | TreeUpdate [SetDefaultTree] |
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197 |
WaveRestoreCursors {{Cursor 1} { |
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198 |
quietly wave cursor active |
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200 | WaveRestoreCursors {{Cursor 1} {42970000 ps} 0} {{Cursor 2} {33108681 ps} 0} {{Cursor 3} {515290000 ps} 0} {{Cursor 4} {8300650000 ps} 0} | |
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201 | quietly wave cursor active 1 | |
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199 | 202 | configure wave -namecolwidth 619 |
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200 | 203 | configure wave -valuecolwidth 311 |
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201 | 204 | configure wave -justifyvalue left |
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|
202 | 205 | configure wave -signalnamewidth 0 |
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|
203 | 206 | configure wave -snapdistance 10 |
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|
204 | 207 | configure wave -datasetprefix 0 |
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205 | 208 | configure wave -rowmargin 4 |
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|
206 | 209 | configure wave -childrowmargin 2 |
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207 | 210 | configure wave -gridoffset 0 |
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208 | 211 | configure wave -gridperiod 1 |
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209 | 212 | configure wave -griddelta 40 |
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210 | 213 | configure wave -timeline 0 |
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211 | 214 | configure wave -timelineunits ns |
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212 | 215 | update |
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|
213 |
WaveRestoreZoom { |
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|
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216 | WaveRestoreZoom {31103383 ps} {50275736 ps} | |
| @@ -1,31 +1,32 | |||
|
|
1 | 1 | ./amba_lcd_16x2_ctrlr |
|
|
2 | 2 | ./general_purpose |
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|
3 | 3 | ./general_purpose/lpp_AMR |
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|
4 | 4 | ./general_purpose/lpp_balise |
|
|
5 | 5 | ./general_purpose/lpp_delay |
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|
6 | 6 | ./lpp_amba |
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|
7 | 7 | ./dsp/chirp |
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|
8 | 8 | ./dsp/iir_filter |
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|
9 | 9 | ./dsp/cic |
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|
10 | 10 | ./dsp/lpp_downsampling |
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|
11 | 11 | ./dsp/lpp_fft_rtax |
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12 | ./dsp/window_function | |
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|
12 | 13 | ./lpp_memory |
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|
13 | 14 | ./dsp/lpp_fft |
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|
14 | 15 | ./lpp_cna |
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|
15 | 16 | ./lfr_management |
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16 | 17 | ./lpp_ad_Conv |
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|
17 | 18 | ./lpp_bootloader |
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|
18 | 19 | ./lpp_spectral_matrix |
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|
19 | 20 | ./lpp_demux |
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|
20 | 21 | ./lpp_Header |
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|
21 | 22 | ./lpp_matrix |
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|
22 | 23 | ./lpp_uart |
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|
23 | 24 | ./lpp_usb |
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|
24 | 25 | ./lpp_dma |
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|
25 | 26 | ./lpp_waveform |
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26 | 27 | ./lpp_top_lfr |
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|
27 | 28 | ./lpp_Header |
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|
28 | 29 | ./lpp_leon3_soc |
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|
29 | 30 | ./lpp_debug_lfr |
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|
30 | 31 | ./lpp_sim/CY7C1061DV33 |
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|
31 | 32 | ./lpp_sim |
| @@ -1,523 +1,524 | |||
|
|
1 | 1 | ---------------------------------------------------------------------------------- |
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|
2 | 2 | -- Company: |
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3 | 3 | -- Engineer: |
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|
4 | 4 | -- |
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5 | 5 | -- Create Date: 11:17:05 07/02/2012 |
|
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6 | 6 | -- Design Name: |
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7 | 7 | -- Module Name: apb_lfr_time_management - Behavioral |
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8 | 8 | -- Project Name: |
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9 | 9 | -- Target Devices: |
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10 | 10 | -- Tool versions: |
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11 | 11 | -- Description: |
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12 | 12 | -- |
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|
13 | 13 | -- Dependencies: |
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|
14 | 14 | -- |
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|
15 | 15 | -- Revision: |
|
|
16 | 16 | -- Revision 0.01 - File Created |
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|
17 | 17 | -- Additional Comments: |
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|
18 | 18 | -- |
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|
19 | 19 | ---------------------------------------------------------------------------------- |
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|
20 | 20 | LIBRARY IEEE; |
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|
21 | 21 | USE IEEE.STD_LOGIC_1164.ALL; |
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22 | 22 | USE IEEE.NUMERIC_STD.ALL; |
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23 | 23 | LIBRARY grlib; |
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24 | 24 | USE grlib.amba.ALL; |
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25 | 25 | USE grlib.stdlib.ALL; |
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26 | 26 | USE grlib.devices.ALL; |
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27 | 27 | LIBRARY lpp; |
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28 | 28 | USE lpp.apb_devices_list.ALL; |
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29 | 29 | USE lpp.general_purpose.ALL; |
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30 | 30 | USE lpp.lpp_lfr_management.ALL; |
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31 | 31 | USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
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32 | 32 | USE lpp.lpp_cna.ALL; |
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33 | 33 | LIBRARY techmap; |
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34 | 34 | USE techmap.gencomp.ALL; |
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35 | 35 | |
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36 | 36 | |
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37 | 37 | ENTITY apb_lfr_management IS |
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38 | 38 | |
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39 | 39 | GENERIC( |
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40 | 40 | tech : INTEGER := 0; |
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41 | 41 | pindex : INTEGER := 0; --! APB slave index |
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42 | 42 | paddr : INTEGER := 0; --! ADDR field of the APB BAR |
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43 | 43 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR |
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44 | 44 | -- FIRST_DIVISION : INTEGER := 374; |
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45 | 45 | NB_SECOND_DESYNC : INTEGER := 60 |
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46 | 46 | ); |
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47 | 47 | |
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48 | 48 | PORT ( |
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49 | 49 | clk25MHz : IN STD_LOGIC; --! Clock |
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50 | 50 | resetn_25MHz : IN STD_LOGIC; --! Reset |
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51 | 51 | -- clk24_576MHz : IN STD_LOGIC; --! secondary clock |
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52 | 52 | -- resetn_24_576MHz : IN STD_LOGIC; --! Reset |
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53 | 53 | |
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54 | 54 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received |
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55 | 55 | |
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56 | 56 | apbi : IN apb_slv_in_type; --! APB slave input signals |
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57 | 57 | apbo : OUT apb_slv_out_type; --! APB slave output signals |
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58 | 58 | --------------------------------------------------------------------------- |
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59 | 59 | HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
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60 | 60 | HK_val : IN STD_LOGIC; |
|
|
61 | 61 | HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
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62 | 62 | --------------------------------------------------------------------------- |
|
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63 | 63 | DAC_SDO : OUT STD_LOGIC; |
|
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64 | 64 | DAC_SCK : OUT STD_LOGIC; |
|
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65 | 65 | DAC_SYNC : OUT STD_LOGIC; |
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66 | 66 | DAC_CAL_EN : OUT STD_LOGIC; |
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67 | 67 | --------------------------------------------------------------------------- |
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68 | 68 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time |
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69 | 69 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME |
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|
70 | 70 | --------------------------------------------------------------------------- |
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71 | 71 | LFR_soft_rstn : OUT STD_LOGIC |
|
|
72 | 72 | ); |
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73 | 73 | |
|
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74 | 74 | END apb_lfr_management; |
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|
75 | 75 | |
|
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76 | 76 | ARCHITECTURE Behavioral OF apb_lfr_management IS |
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77 | 77 | |
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78 | 78 | CONSTANT REVISION : INTEGER := 1; |
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79 | 79 | CONSTANT pconfig : apb_config_type := ( |
|
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80 | 80 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0), |
|
|
81 | 81 | 1 => apb_iobar(paddr, pmask) |
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|
82 | 82 | ); |
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|
83 | 83 | |
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84 | 84 | TYPE apb_lfr_time_management_Reg IS RECORD |
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85 | 85 | ctrl : STD_LOGIC; |
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86 | 86 | soft_reset : STD_LOGIC; |
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87 | 87 | coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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88 | 88 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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89 | 89 | fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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90 | 90 | LFR_soft_reset : STD_LOGIC; |
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91 | 91 | HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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92 | 92 | HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|
93 | 93 | HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|
94 | 94 | END RECORD; |
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95 | 95 | SIGNAL r : apb_lfr_time_management_Reg; |
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96 | 96 | |
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97 | 97 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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98 | 98 | SIGNAL force_tick : STD_LOGIC; |
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99 | 99 | SIGNAL previous_force_tick : STD_LOGIC; |
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100 | 100 | SIGNAL soft_tick : STD_LOGIC; |
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101 | 101 | |
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102 | 102 | SIGNAL coarsetime_reg_updated : STD_LOGIC; |
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103 | 103 | SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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104 | 104 | |
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105 | 105 | --SIGNAL coarse_time_new : STD_LOGIC; |
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106 | 106 | SIGNAL coarse_time_new_49 : STD_LOGIC; |
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107 | 107 | SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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108 | 108 | SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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109 | 109 | |
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110 | 110 | --SIGNAL fine_time_new : STD_LOGIC; |
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111 | 111 | --SIGNAL fine_time_new_temp : STD_LOGIC; |
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112 | 112 | SIGNAL fine_time_new_49 : STD_LOGIC; |
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113 | 113 | SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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114 | 114 | SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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115 | 115 | SIGNAL tick : STD_LOGIC; |
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116 | 116 | SIGNAL new_timecode : STD_LOGIC; |
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117 | 117 | SIGNAL new_coarsetime : STD_LOGIC; |
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118 | 118 | |
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119 | 119 | SIGNAL time_new_49 : STD_LOGIC; |
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120 | 120 | SIGNAL time_new : STD_LOGIC; |
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121 | 121 | |
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122 | 122 | ----------------------------------------------------------------------------- |
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123 | 123 | SIGNAL force_reset : STD_LOGIC; |
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124 | 124 | SIGNAL previous_force_reset : STD_LOGIC; |
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125 | 125 | SIGNAL soft_reset : STD_LOGIC; |
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126 | 126 | SIGNAL soft_reset_sync : STD_LOGIC; |
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127 | 127 | ----------------------------------------------------------------------------- |
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128 | 128 | SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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129 | 129 | |
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130 | 130 | SIGNAL previous_fine_time_bit : STD_LOGIC; |
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131 | 131 | |
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132 | 132 | SIGNAL rstn_LFR_TM : STD_LOGIC; |
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133 | 133 | |
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134 | 134 | ----------------------------------------------------------------------------- |
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135 | 135 | -- DAC |
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136 | 136 | ----------------------------------------------------------------------------- |
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137 | 137 | CONSTANT PRESZ : INTEGER := 8; |
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138 | 138 | CONSTANT CPTSZ : INTEGER := 16; |
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139 | 139 | CONSTANT datawidth : INTEGER := 18; |
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140 | 140 | CONSTANT dacresolution : INTEGER := 12; |
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141 | 141 | CONSTANT abits : INTEGER := 8; |
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142 | 142 | |
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143 | 143 | SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0); |
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144 | 144 | SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0); |
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145 | 145 | SIGNAL Reload : STD_LOGIC; |
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146 | 146 | SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0); |
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147 | 147 | SIGNAL WEN : STD_LOGIC; |
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148 | 148 | SIGNAL LOAD_ADDRESSN : STD_LOGIC; |
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149 | 149 | SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0); |
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150 | 150 | SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0); |
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151 | 151 | SIGNAL INTERLEAVED : STD_LOGIC; |
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152 | 152 | SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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153 | 153 | SIGNAL DAC_CAL_EN_s : STD_LOGIC; |
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154 | 154 | |
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155 | 155 | BEGIN |
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156 | 156 | |
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157 | 157 | LFR_soft_rstn <= NOT r.LFR_soft_reset; |
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158 | 158 | |
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159 | 159 | PROCESS(resetn_25MHz, clk25MHz) |
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160 | 160 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
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161 | 161 | BEGIN |
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162 | 162 | |
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163 | 163 | IF resetn_25MHz = '0' THEN |
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164 | 164 | Rdata <= (OTHERS => '0'); |
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165 | 165 | r.coarse_time_load <= (OTHERS => '0'); |
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166 | 166 | r.soft_reset <= '0'; |
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167 | 167 | r.ctrl <= '0'; |
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168 | 168 | r.LFR_soft_reset <= '1'; |
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169 | 169 | |
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170 | 170 | force_tick <= '0'; |
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171 | 171 | previous_force_tick <= '0'; |
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172 | 172 | soft_tick <= '0'; |
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173 | 173 | |
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174 | 174 | coarsetime_reg_updated <= '0'; |
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175 | 175 | --DAC |
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176 | 176 | pre <= (OTHERS => '1'); |
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177 | 177 | N <= (OTHERS => '1'); |
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178 | 178 | Reload <= '1'; |
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179 | 179 | DATA_IN <= (OTHERS => '0'); |
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180 | 180 | WEN <= '1'; |
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181 | 181 | LOAD_ADDRESSN <= '1'; |
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182 | 182 | ADDRESS_IN <= (OTHERS => '1'); |
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183 | 183 | INTERLEAVED <= '0'; |
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184 | 184 | DAC_CFG <= (OTHERS => '0'); |
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185 | 185 | -- |
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186 | 186 | DAC_CAL_EN_s <= '0'; |
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187 | force_reset <= '0'; | |
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187 | 188 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN |
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188 | 189 | coarsetime_reg_updated <= '0'; |
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189 | 190 | |
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190 | 191 | force_tick <= r.ctrl; |
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191 | 192 | previous_force_tick <= force_tick; |
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192 | 193 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN |
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193 | 194 | soft_tick <= '1'; |
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194 | 195 | ELSE |
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195 | 196 | soft_tick <= '0'; |
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196 | 197 | END IF; |
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197 | 198 | |
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198 | 199 | force_reset <= r.soft_reset; |
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199 | 200 | previous_force_reset <= force_reset; |
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200 | 201 | IF (previous_force_reset = '0') AND (force_reset = '1') THEN |
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201 | 202 | soft_reset <= '1'; |
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202 | 203 | ELSE |
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203 | 204 | soft_reset <= '0'; |
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|
204 | 205 | END IF; |
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205 | 206 | |
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206 | 207 | paddr := "000000"; |
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207 | 208 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
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208 | 209 | Rdata <= (OTHERS => '0'); |
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209 | 210 | |
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210 | 211 | LOAD_ADDRESSN <= '1'; |
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211 | 212 | WEN <= '1'; |
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212 | 213 | |
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|
213 | 214 | IF apbi.psel(pindex) = '1' THEN |
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214 | 215 | --APB READ OP |
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215 | 216 | CASE paddr(7 DOWNTO 2) IS |
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216 | 217 | WHEN ADDR_LFR_MANAGMENT_CONTROL => |
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217 | 218 | Rdata(0) <= r.ctrl; |
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218 | 219 | Rdata(1) <= r.soft_reset; |
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219 | 220 | Rdata(2) <= r.LFR_soft_reset; |
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220 | 221 | Rdata(31 DOWNTO 3) <= (OTHERS => '0'); |
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221 | 222 | WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => |
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222 | 223 | Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); |
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223 | 224 | WHEN ADDR_LFR_MANAGMENT_TIME_COARSE => |
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224 | 225 | Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); |
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|
225 | 226 | WHEN ADDR_LFR_MANAGMENT_TIME_FINE => |
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226 | 227 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
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227 | 228 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); |
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228 | 229 | WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 => |
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229 | 230 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
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230 | 231 | Rdata(15 DOWNTO 0) <= r.HK_temp_0; |
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231 | 232 | WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 => |
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232 | 233 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
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233 | 234 | Rdata(15 DOWNTO 0) <= r.HK_temp_1; |
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234 | 235 | WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 => |
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235 | 236 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
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|
236 | 237 | Rdata(15 DOWNTO 0) <= r.HK_temp_2; |
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|
237 | 238 | WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL => |
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238 | 239 | Rdata(3 DOWNTO 0) <= DAC_CFG; |
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|
239 | 240 | Rdata(4) <= Reload; |
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|
240 | 241 | Rdata(5) <= INTERLEAVED; |
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|
241 | 242 | Rdata(6) <= DAC_CAL_EN_s; |
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|
242 | 243 | Rdata(31 DOWNTO 7) <= (OTHERS => '0'); |
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|
243 | 244 | WHEN ADDR_LFR_MANAGMENT_DAC_PRE => |
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244 | 245 | Rdata(PRESZ-1 DOWNTO 0) <= pre; |
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|
245 | 246 | Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0'); |
|
|
246 | 247 | WHEN ADDR_LFR_MANAGMENT_DAC_N => |
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|
247 | 248 | Rdata(CPTSZ-1 DOWNTO 0) <= N; |
|
|
248 | 249 | Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0'); |
|
|
249 | 250 | WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT => |
|
|
250 | 251 | Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT; |
|
|
251 | 252 | Rdata(31 DOWNTO abits) <= (OTHERS => '0'); |
|
|
252 | 253 | WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN => |
|
|
253 | 254 | Rdata(datawidth-1 DOWNTO 0) <= DATA_IN; |
|
|
254 | 255 | Rdata(31 DOWNTO datawidth) <= (OTHERS => '0'); |
|
|
255 | 256 | WHEN OTHERS => |
|
|
256 | 257 | Rdata(31 DOWNTO 0) <= (OTHERS => '0'); |
|
|
257 | 258 | END CASE; |
|
|
258 | 259 | |
|
|
259 | 260 | --APB Write OP |
|
|
260 | 261 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
|
261 | 262 | CASE paddr(7 DOWNTO 2) IS |
|
|
262 | 263 | WHEN ADDR_LFR_MANAGMENT_CONTROL => |
|
|
263 | 264 | r.ctrl <= apbi.pwdata(0); |
|
|
264 | 265 | r.soft_reset <= apbi.pwdata(1); |
|
|
265 | 266 | r.LFR_soft_reset <= apbi.pwdata(2); |
|
|
266 | 267 | WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => |
|
|
267 | 268 | r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); |
|
|
268 | 269 | coarsetime_reg_updated <= '1'; |
|
|
269 | 270 | WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL => |
|
|
270 | 271 | DAC_CFG <= apbi.pwdata(3 DOWNTO 0); |
|
|
271 | 272 | Reload <= apbi.pwdata(4); |
|
|
272 | 273 | INTERLEAVED <= apbi.pwdata(5); |
|
|
273 | 274 | DAC_CAL_EN_s <= apbi.pwdata(6); |
|
|
274 | 275 | WHEN ADDR_LFR_MANAGMENT_DAC_PRE => |
|
|
275 | 276 | pre <= apbi.pwdata(PRESZ-1 DOWNTO 0); |
|
|
276 | 277 | WHEN ADDR_LFR_MANAGMENT_DAC_N => |
|
|
277 | 278 | N <= apbi.pwdata(CPTSZ-1 DOWNTO 0); |
|
|
278 | 279 | WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT => |
|
|
279 | 280 | ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0); |
|
|
280 | 281 | LOAD_ADDRESSN <= '0'; |
|
|
281 | 282 | WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN => |
|
|
282 | 283 | DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0); |
|
|
283 | 284 | WEN <= '0'; |
|
|
284 | 285 | |
|
|
285 | 286 | WHEN OTHERS => |
|
|
286 | 287 | NULL; |
|
|
287 | 288 | END CASE; |
|
|
288 | 289 | ELSE |
|
|
289 | 290 | IF r.ctrl = '1' THEN |
|
|
290 | 291 | r.ctrl <= '0'; |
|
|
291 | 292 | END IF; |
|
|
292 | 293 | IF r.soft_reset = '1' THEN |
|
|
293 | 294 | r.soft_reset <= '0'; |
|
|
294 | 295 | END IF; |
|
|
295 | 296 | END IF; |
|
|
296 | 297 | |
|
|
297 | 298 | END IF; |
|
|
298 | 299 | |
|
|
299 | 300 | END IF; |
|
|
300 | 301 | END PROCESS; |
|
|
301 | 302 | |
|
|
302 | 303 | apbo.pirq <= (OTHERS => '0'); |
|
|
303 | 304 | apbo.prdata <= Rdata; |
|
|
304 | 305 | apbo.pconfig <= pconfig; |
|
|
305 | 306 | apbo.pindex <= pindex; |
|
|
306 | 307 | |
|
|
307 | 308 | |
|
|
308 | 309 | |
|
|
309 | 310 | |
|
|
310 | 311 | |
|
|
311 | 312 | |
|
|
312 | 313 | |
|
|
313 | 314 | |
|
|
314 | 315 | |
|
|
315 | 316 | |
|
|
316 | 317 | |
|
|
317 | 318 | |
|
|
318 | 319 | |
|
|
319 | 320 | |
|
|
320 | 321 | ----------------------------------------------------------------------------- |
|
|
321 | 322 | -- IN |
|
|
322 | 323 | coarse_time <= r.coarse_time; |
|
|
323 | 324 | fine_time <= r.fine_time; |
|
|
324 | 325 | coarsetime_reg <= r.coarse_time_load; |
|
|
325 | 326 | ----------------------------------------------------------------------------- |
|
|
326 | 327 | |
|
|
327 | 328 | ----------------------------------------------------------------------------- |
|
|
328 | 329 | -- OUT |
|
|
329 | 330 | r.coarse_time <= coarse_time_s; |
|
|
330 | 331 | r.fine_time <= fine_time_s; |
|
|
331 | 332 | ----------------------------------------------------------------------------- |
|
|
332 | 333 | |
|
|
333 | 334 | ----------------------------------------------------------------------------- |
|
|
334 | 335 | tick <= grspw_tick OR soft_tick; |
|
|
335 | 336 | |
|
|
336 | 337 | --SYNC_VALID_BIT_1 : SYNC_VALID_BIT |
|
|
337 | 338 | -- GENERIC MAP ( |
|
|
338 | 339 | -- NB_FF_OF_SYNC => 2) |
|
|
339 | 340 | -- PORT MAP ( |
|
|
340 | 341 | -- clk_in => clk25MHz, |
|
|
341 | 342 | -- rstn_in => resetn_25MHz, |
|
|
342 | 343 | -- clk_out => clk24_576MHz, |
|
|
343 | 344 | -- rstn_out => resetn_24_576MHz, |
|
|
344 | 345 | -- sin => tick, |
|
|
345 | 346 | -- sout => new_timecode); |
|
|
346 | 347 | new_timecode <= tick; |
|
|
347 | 348 | |
|
|
348 | 349 | --SYNC_VALID_BIT_2 : SYNC_VALID_BIT |
|
|
349 | 350 | -- GENERIC MAP ( |
|
|
350 | 351 | -- NB_FF_OF_SYNC => 2) |
|
|
351 | 352 | -- PORT MAP ( |
|
|
352 | 353 | -- clk_in => clk25MHz, |
|
|
353 | 354 | -- rstn_in => resetn_25MHz, |
|
|
354 | 355 | -- clk_out => clk24_576MHz, |
|
|
355 | 356 | -- rstn_out => resetn_24_576MHz, |
|
|
356 | 357 | -- sin => coarsetime_reg_updated, |
|
|
357 | 358 | -- sout => new_coarsetime); |
|
|
358 | 359 | |
|
|
359 | 360 | new_coarsetime <= coarsetime_reg_updated; |
|
|
360 | 361 | |
|
|
361 | 362 | --SYNC_VALID_BIT_3 : SYNC_VALID_BIT |
|
|
362 | 363 | -- GENERIC MAP ( |
|
|
363 | 364 | -- NB_FF_OF_SYNC => 2) |
|
|
364 | 365 | -- PORT MAP ( |
|
|
365 | 366 | -- clk_in => clk25MHz, |
|
|
366 | 367 | -- rstn_in => resetn_25MHz, |
|
|
367 | 368 | -- clk_out => clk24_576MHz, |
|
|
368 | 369 | -- rstn_out => resetn_24_576MHz, |
|
|
369 | 370 | -- sin => soft_reset, |
|
|
370 | 371 | -- sout => soft_reset_sync); |
|
|
371 | 372 | |
|
|
372 | 373 | |
|
|
373 | 374 | ----------------------------------------------------------------------------- |
|
|
374 | 375 | time_new_49 <= coarse_time_new_49 OR fine_time_new_49; |
|
|
375 | 376 | |
|
|
376 | 377 | --SYNC_VALID_BIT_4 : SYNC_VALID_BIT |
|
|
377 | 378 | -- GENERIC MAP ( |
|
|
378 | 379 | -- NB_FF_OF_SYNC => 2) |
|
|
379 | 380 | -- PORT MAP ( |
|
|
380 | 381 | -- clk_in => clk24_576MHz, |
|
|
381 | 382 | -- rstn_in => resetn_24_576MHz, |
|
|
382 | 383 | -- clk_out => clk25MHz, |
|
|
383 | 384 | -- rstn_out => resetn_25MHz, |
|
|
384 | 385 | -- sin => time_new_49, |
|
|
385 | 386 | -- sout => time_new); |
|
|
386 | 387 | |
|
|
387 | 388 | time_new <= time_new_49; |
|
|
388 | 389 | |
|
|
389 | 390 | --PROCESS (clk25MHz, resetn_25MHz) |
|
|
390 | 391 | --BEGIN -- PROCESS |
|
|
391 | 392 | -- IF resetn_25MHz = '0' THEN -- asynchronous reset (active low) |
|
|
392 | 393 | -- fine_time_s <= (OTHERS => '0'); |
|
|
393 | 394 | -- coarse_time_s <= (OTHERS => '0'); |
|
|
394 | 395 | -- ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
|
395 | 396 | -- IF time_new = '1' THEN |
|
|
396 | 397 | -- END IF; |
|
|
397 | 398 | -- END IF; |
|
|
398 | 399 | --END PROCESS; |
|
|
399 | 400 | |
|
|
400 | 401 | fine_time_s <= fine_time_49; |
|
|
401 | 402 | coarse_time_s <= coarse_time_49; |
|
|
402 | 403 | |
|
|
403 | 404 | |
|
|
404 | 405 | rstn_LFR_TM <= '0' WHEN resetn_25MHz = '0' ELSE |
|
|
405 | 406 | '0' WHEN soft_reset = '1' ELSE |
|
|
406 | 407 | '1'; |
|
|
407 | 408 | |
|
|
408 | 409 | ----------------------------------------------------------------------------- |
|
|
409 | 410 | -- LFR_TIME_MANAGMENT |
|
|
410 | 411 | ----------------------------------------------------------------------------- |
|
|
411 | 412 | lfr_time_management_1 : lfr_time_management |
|
|
412 | 413 | GENERIC MAP ( |
|
|
413 | 414 | --FIRST_DIVISION => FIRST_DIVISION, |
|
|
414 | 415 | NB_SECOND_DESYNC => NB_SECOND_DESYNC) |
|
|
415 | 416 | PORT MAP ( |
|
|
416 | 417 | clk => clk25MHz, |
|
|
417 | 418 | rstn => rstn_LFR_TM, |
|
|
418 | 419 | |
|
|
419 | 420 | tick => new_timecode, |
|
|
420 | 421 | new_coarsetime => new_coarsetime, |
|
|
421 | 422 | coarsetime_reg => coarsetime_reg(30 DOWNTO 0), |
|
|
422 | 423 | |
|
|
423 | 424 | fine_time => fine_time_49, |
|
|
424 | 425 | fine_time_new => fine_time_new_49, |
|
|
425 | 426 | coarse_time => coarse_time_49, |
|
|
426 | 427 | coarse_time_new => coarse_time_new_49); |
|
|
427 | 428 | |
|
|
428 | 429 | |
|
|
429 | 430 | |
|
|
430 | 431 | ----------------------------------------------------------------------------- |
|
|
431 | 432 | -- HK |
|
|
432 | 433 | ----------------------------------------------------------------------------- |
|
|
433 | 434 | |
|
|
434 | 435 | PROCESS (clk25MHz, resetn_25MHz) |
|
|
435 | 436 | CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT) |
|
|
436 | 437 | -- for each HK, the update frequency is freq/3 |
|
|
437 | 438 | -- |
|
|
438 | 439 | -- for 14, the update frequency is |
|
|
439 | 440 | -- 4Hz and update for each |
|
|
440 | 441 | -- HK is 1.33Hz |
|
|
441 | 442 | BEGIN -- PROCESS |
|
|
442 | 443 | IF resetn_25MHz = '0' THEN -- asynchronous reset (active low) |
|
|
443 | 444 | |
|
|
444 | 445 | r.HK_temp_0 <= (OTHERS => '0'); |
|
|
445 | 446 | r.HK_temp_1 <= (OTHERS => '0'); |
|
|
446 | 447 | r.HK_temp_2 <= (OTHERS => '0'); |
|
|
447 | 448 | |
|
|
448 | 449 | HK_sel_s <= "00"; |
|
|
449 | 450 | |
|
|
450 | 451 | previous_fine_time_bit <= '0'; |
|
|
451 | 452 | |
|
|
452 | 453 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
|
453 | 454 | |
|
|
454 | 455 | IF HK_val = '1' THEN |
|
|
455 | 456 | IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN |
|
|
456 | 457 | previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE); |
|
|
457 | 458 | CASE HK_sel_s IS |
|
|
458 | 459 | WHEN "00" => |
|
|
459 | 460 | r.HK_temp_0 <= HK_sample; |
|
|
460 | 461 | HK_sel_s <= "01"; |
|
|
461 | 462 | WHEN "01" => |
|
|
462 | 463 | r.HK_temp_1 <= HK_sample; |
|
|
463 | 464 | HK_sel_s <= "10"; |
|
|
464 | 465 | WHEN "10" => |
|
|
465 | 466 | r.HK_temp_2 <= HK_sample; |
|
|
466 | 467 | HK_sel_s <= "00"; |
|
|
467 | 468 | WHEN OTHERS => NULL; |
|
|
468 | 469 | END CASE; |
|
|
469 | 470 | END IF; |
|
|
470 | 471 | END IF; |
|
|
471 | 472 | |
|
|
472 | 473 | END IF; |
|
|
473 | 474 | END PROCESS; |
|
|
474 | 475 | |
|
|
475 | 476 | HK_sel <= HK_sel_s; |
|
|
476 | 477 | |
|
|
477 | 478 | |
|
|
478 | 479 | |
|
|
479 | 480 | |
|
|
480 | 481 | |
|
|
481 | 482 | |
|
|
482 | 483 | |
|
|
483 | 484 | |
|
|
484 | 485 | |
|
|
485 | 486 | |
|
|
486 | 487 | |
|
|
487 | 488 | |
|
|
488 | 489 | |
|
|
489 | 490 | |
|
|
490 | 491 | ----------------------------------------------------------------------------- |
|
|
491 | 492 | -- DAC |
|
|
492 | 493 | ----------------------------------------------------------------------------- |
|
|
493 | 494 | cal : lfr_cal_driver |
|
|
494 | 495 | GENERIC MAP( |
|
|
495 | 496 | tech => tech, |
|
|
496 | 497 | PRESZ => PRESZ, |
|
|
497 | 498 | CPTSZ => CPTSZ, |
|
|
498 | 499 | datawidth => datawidth, |
|
|
499 | 500 | abits => abits |
|
|
500 | 501 | ) |
|
|
501 | 502 | PORT MAP( |
|
|
502 | 503 | clk => clk25MHz, |
|
|
503 | 504 | rstn => resetn_25MHz, |
|
|
504 | 505 | |
|
|
505 | 506 | pre => pre, |
|
|
506 | 507 | N => N, |
|
|
507 | 508 | Reload => Reload, |
|
|
508 | 509 | DATA_IN => DATA_IN, |
|
|
509 | 510 | WEN => WEN, |
|
|
510 | 511 | LOAD_ADDRESSN => LOAD_ADDRESSN, |
|
|
511 | 512 | ADDRESS_IN => ADDRESS_IN, |
|
|
512 | 513 | ADDRESS_OUT => ADDRESS_OUT, |
|
|
513 | 514 | INTERLEAVED => INTERLEAVED, |
|
|
514 | 515 | DAC_CFG => DAC_CFG, |
|
|
515 | 516 | |
|
|
516 | 517 | SYNC => DAC_SYNC, |
|
|
517 | 518 | DOUT => DAC_SDO, |
|
|
518 | 519 | SCLK => DAC_SCK, |
|
|
519 | 520 | SMPCLK => OPEN --DAC_SMPCLK |
|
|
520 | 521 | ); |
|
|
521 | 522 | |
|
|
522 | 523 | DAC_CAL_EN <= DAC_CAL_EN_s; |
|
|
523 | 524 | END Behavioral; |
| @@ -1,274 +1,301 | |||
|
|
1 | 1 | |
|
|
2 | 2 | LIBRARY IEEE; |
|
|
3 | 3 | USE IEEE.STD_LOGIC_1164.ALL; |
|
|
4 | 4 | USE IEEE.numeric_std.ALL; |
|
|
5 | 5 | LIBRARY lpp; |
|
|
6 | 6 | USE lpp.lpp_ad_conv.ALL; |
|
|
7 | 7 | USE lpp.general_purpose.SYNC_FF; |
|
|
8 | 8 | |
|
|
9 | 9 | ENTITY top_ad_conv_RHF1401_withFilter IS |
|
|
10 | 10 | GENERIC( |
|
|
11 | 11 | ChanelCount : INTEGER := 8; |
|
|
12 | 12 | ncycle_cnv_high : INTEGER := 25; |
|
|
13 | 13 | ncycle_cnv : INTEGER := 50; |
|
|
14 | 14 | FILTER_ENABLED : INTEGER := 16#FF# |
|
|
15 | 15 | ); |
|
|
16 | 16 | PORT ( |
|
|
17 | 17 | cnv_clk : IN STD_LOGIC; -- 24Mhz |
|
|
18 | 18 | cnv_rstn : IN STD_LOGIC; |
|
|
19 | 19 | |
|
|
20 | 20 | cnv : OUT STD_LOGIC; |
|
|
21 | 21 | |
|
|
22 | 22 | clk : IN STD_LOGIC; -- 25MHz |
|
|
23 | 23 | rstn : IN STD_LOGIC; |
|
|
24 | 24 | ADC_data : IN Samples14; |
|
|
25 | 25 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
|
|
26 | 26 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); |
|
|
27 | 27 | sample_val : OUT STD_LOGIC |
|
|
28 | 28 | ); |
|
|
29 | 29 | END top_ad_conv_RHF1401_withFilter; |
|
|
30 | 30 | |
|
|
31 | 31 | ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS |
|
|
32 | 32 | |
|
|
33 | 33 | SIGNAL cnv_cycle_counter : INTEGER; |
|
|
34 | 34 | SIGNAL cnv_s : STD_LOGIC; |
|
|
35 | 35 | SIGNAL cnv_s_reg : STD_LOGIC; |
|
|
36 | 36 | SIGNAL cnv_sync : STD_LOGIC; |
|
|
37 | 37 | SIGNAL cnv_sync_reg : STD_LOGIC; |
|
|
38 | 38 | SIGNAL cnv_sync_falling : STD_LOGIC; |
|
|
39 | 39 | |
|
|
40 | 40 | SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
|
|
41 | 41 | SIGNAL enable_ADC : STD_LOGIC; |
|
|
42 | 42 | |
|
|
43 | 43 | |
|
|
44 | 44 | SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0); |
|
|
45 | 45 | |
|
|
46 | 46 | SIGNAL channel_counter : INTEGER; |
|
|
47 | 47 | CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1; |
|
|
48 | 48 | |
|
|
49 | 49 | SIGNAL ADC_data_selected : Samples14; |
|
|
50 | 50 | SIGNAL ADC_data_result : Samples15; |
|
|
51 | 51 | |
|
|
52 | 52 | SIGNAL sample_counter : INTEGER; |
|
|
53 | 53 | CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9; |
|
|
54 | 54 | |
|
|
55 | 55 | CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount)); |
|
|
56 | 56 | |
|
|
57 | 57 | ----------------------------------------------------------------------------- |
|
|
58 | 58 | CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 1; |
|
|
59 |
CONSTANT DATA_CYCLE_VALID : INTEGER := |
|
|
|
59 | CONSTANT DATA_CYCLE_VALID : INTEGER := 2; | |
|
|
60 | 60 | |
|
|
61 | 61 | -- GEN OutPut Enable |
|
|
62 | 62 | TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE); |
|
|
63 | 63 | SIGNAL state_GEN_OEn : FSM_GEN_OEn_state; |
|
|
64 | 64 | SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1; |
|
|
65 | 65 | SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1 ; |
|
|
66 | 66 | SIGNAL ADC_data_valid : STD_LOGIC; |
|
|
67 | 67 | SIGNAL ADC_data_valid_s : STD_LOGIC; |
|
|
68 | 68 | SIGNAL ADC_data_reg : Samples14; |
|
|
69 | 69 | ----------------------------------------------------------------------------- |
|
|
70 | 70 | CONSTANT SAMPLE_DIVISION : INTEGER := 10; |
|
|
71 | 71 | SIGNAL sample_val_s : STD_LOGIC; |
|
|
72 | 72 |
SIGNAL sample_val_s2 |
|
|
73 | 73 | SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION; |
|
|
74 | 74 | BEGIN |
|
|
75 | 75 | |
|
|
76 | 76 | |
|
|
77 | 77 | ----------------------------------------------------------------------------- |
|
|
78 | 78 | -- CNV GEN |
|
|
79 | 79 | ----------------------------------------------------------------------------- |
|
|
80 | 80 | PROCESS (cnv_clk, cnv_rstn) |
|
|
81 | 81 | BEGIN -- PROCESS |
|
|
82 | 82 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) |
|
|
83 | 83 | cnv_cycle_counter <= 0; |
|
|
84 | 84 | cnv_s <= '0'; |
|
|
85 | 85 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge |
|
|
86 | 86 | IF cnv_cycle_counter < ncycle_cnv-1 THEN |
|
|
87 | 87 | cnv_cycle_counter <= cnv_cycle_counter + 1; |
|
|
88 | 88 | IF cnv_cycle_counter < ncycle_cnv_high-1 THEN |
|
|
89 | 89 | cnv_s <= '1'; |
|
|
90 | 90 | ELSE |
|
|
91 | 91 | cnv_s <= '0'; |
|
|
92 | 92 | END IF; |
|
|
93 | 93 | ELSE |
|
|
94 | 94 | cnv_s <= '1'; |
|
|
95 | 95 | cnv_cycle_counter <= 0; |
|
|
96 | 96 | END IF; |
|
|
97 | 97 | END IF; |
|
|
98 | 98 | END PROCESS; |
|
|
99 | 99 | |
|
|
100 | 100 | cnv <= cnv_s; |
|
|
101 | 101 | |
|
|
102 | 102 | PROCESS (cnv_clk, cnv_rstn) |
|
|
103 | 103 | BEGIN -- PROCESS |
|
|
104 | 104 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) |
|
|
105 | 105 | cnv_s_reg <= '0'; |
|
|
106 | 106 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge |
|
|
107 | 107 | cnv_s_reg <= cnv_s; |
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108 | 108 | END IF; |
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109 | 109 | END PROCESS; |
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110 | 110 | |
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111 | 111 | |
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112 | 112 | ----------------------------------------------------------------------------- |
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113 | 113 | -- SYNC CNV |
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114 | 114 | ----------------------------------------------------------------------------- |
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115 | 115 | |
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116 | 116 | SYNC_FF_cnv : SYNC_FF |
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117 | 117 | GENERIC MAP ( |
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118 | 118 | NB_FF_OF_SYNC => 2) |
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119 | 119 | PORT MAP ( |
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120 | 120 | clk => clk, |
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121 | 121 | rstn => rstn, |
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122 | 122 | A => cnv_s_reg, |
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123 | 123 | A_sync => cnv_sync); |
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124 | 124 | |
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125 | 125 | ----------------------------------------------------------------------------- |
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126 | 126 | -- |
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127 | 127 | ----------------------------------------------------------------------------- |
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128 | 128 | PROCESS (clk, rstn) |
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129 | 129 | BEGIN -- PROCESS |
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130 | 130 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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131 | 131 | cnv_sync_reg <= '0'; |
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132 | 132 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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133 | 133 | cnv_sync_reg <= cnv_sync; |
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134 | 134 | END IF; |
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135 | 135 | END PROCESS; |
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136 | 136 | |
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137 | 137 | cnv_sync_falling <= '1' WHEN cnv_sync = '0' AND cnv_sync_reg = '1' ELSE '0'; |
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138 | 138 | |
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139 | 139 | ----------------------------------------------------------------------------- |
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140 | 140 | -- GEN OutPut Enable |
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141 | 141 | ----------------------------------------------------------------------------- |
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142 | 142 | PROCESS (clk, rstn) |
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143 | 143 | BEGIN -- PROCESS |
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144 | 144 | IF rstn = '0' THEN |
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145 | 145 | ------------------------------------------------------------------------- |
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146 | 146 | ADC_nOE <= (OTHERS => '1'); |
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147 | 147 | ADC_current <= 0; |
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148 | 148 | ADC_current_cycle_enabled <= 0; |
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149 | 149 | state_GEN_OEn <= IDLE; |
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150 | 150 | ------------------------------------------------------------------------- |
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151 | 151 | ADC_data_reg <= (OTHERS => '0'); |
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152 | 152 | all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP |
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153 | 153 | sample_reg(I) <= (OTHERS => '0'); |
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154 | 154 | sample(I) <= (OTHERS => '0'); |
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155 | 155 | END LOOP all_channel_sample_reg_init; |
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156 | 156 | sample_val <= '0'; |
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157 | 157 | sample_val_s <= '0'; |
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158 | 158 | sample_val_counter <= 0; |
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159 | 159 | ------------------------------------------------------------------------- |
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160 | 160 | ELSIF clk'event AND clk = '1' THEN |
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161 | 161 | ------------------------------------------------------------------------- |
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162 | 162 | sample_val_s <= '0'; |
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163 | 163 | ADC_nOE <= (OTHERS => '1'); |
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164 | 164 | CASE state_GEN_OEn IS |
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165 | 165 | WHEN IDLE => |
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166 | 166 | IF cnv_sync_falling = '1' THEN |
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167 | 167 | --ADC_nOE(0) <= '1'; |
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168 | 168 | state_GEN_OEn <= GEN_OE; |
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169 | 169 | ADC_current <= 0; |
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170 | 170 | ADC_current_cycle_enabled <= 1; |
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171 | 171 | END IF; |
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172 | 172 | |
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173 | 173 | WHEN GEN_OE => |
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174 | 174 | ADC_nOE(ADC_current) <= '0'; |
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175 | 175 | |
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176 | 176 | ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1; |
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177 | 177 | |
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178 | 178 | IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN |
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179 | 179 | state_GEN_OEn <= WAIT_CYCLE; |
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180 | 180 | END IF; |
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181 | 181 | |
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182 | 182 | WHEN WAIT_CYCLE => |
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183 | 183 | ADC_current_cycle_enabled <= 1; |
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184 | 184 | IF ADC_current = ChanelCount-1 THEN |
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185 | 185 | state_GEN_OEn <= IDLE; |
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186 | 186 | sample_val_s <= '1'; |
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187 | 187 | ELSE |
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188 | 188 | ADC_current <= ADC_current + 1; |
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189 | 189 | state_GEN_OEn <= GEN_OE; |
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190 | 190 | END IF; |
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191 | 191 | WHEN OTHERS => NULL; |
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192 | 192 | END CASE; |
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193 | 193 | ------------------------------------------------------------------------- |
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194 | 194 | ADC_data_reg <= ADC_data; |
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195 | 195 | |
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196 | 196 | all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP |
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197 | 197 | IF ADC_data_valid = '1' AND ADC_current = I THEN |
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198 | 198 | sample_reg(I) <= ADC_data_result(14 DOWNTO 1); |
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199 | 199 | ELSE |
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200 | 200 | sample_reg(I) <= sample_reg(I); |
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201 | 201 | END IF; |
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202 | 202 | END LOOP all_channel_sample_reg; |
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203 | 203 | ------------------------------------------------------------------------- |
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204 | 204 | sample_val <= '0'; |
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205 | 205 | IF sample_val_s2 = '1' THEN |
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206 | 206 | IF sample_val_counter = SAMPLE_DIVISION-1 THEN |
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207 | 207 | sample_val_counter <= 0; |
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208 | 208 | sample_val <= '1'; -- TODO |
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209 | 209 | sample <= sample_reg; |
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210 | 210 | ELSE |
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211 | 211 | sample_val_counter <= sample_val_counter + 1; |
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212 | 212 | sample_val <= '0'; |
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213 | 213 | END IF; |
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214 | 214 | END IF; |
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215 | 215 | |
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216 | 216 | END IF; |
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217 | 217 | END PROCESS; |
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218 | 218 | |
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219 | 219 | |
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220 | ||
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221 | REG_ADC_DATA_valid: IF DATA_CYCLE_VALID = OE_NB_CYCLE_ENABLED GENERATE | |
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220 | 222 | ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0'; |
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221 | 223 | |
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222 | REG_ADC_DATA_valid: IF DATA_CYCLE_VALID = OE_NB_CYCLE_ENABLED GENERATE | |
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223 | 224 |
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224 | 225 | BEGIN -- PROCESS |
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225 | 226 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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226 | 227 | ADC_data_valid <= '0'; |
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227 | 228 | sample_val_s2 <= '0'; |
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228 | 229 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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229 | 230 | ADC_data_valid <= ADC_data_valid_s; |
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230 | 231 | sample_val_s2 <= sample_val_s; |
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231 | 232 | END IF; |
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232 | 233 | END PROCESS; |
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233 | 234 | |
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234 | 235 | END GENERATE REG_ADC_DATA_valid; |
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235 | 236 | |
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236 | 237 | noREG_ADC_DATA_valid: IF DATA_CYCLE_VALID < OE_NB_CYCLE_ENABLED GENERATE |
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238 | ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0'; | |
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239 | ||
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237 | 240 |
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238 | 241 | sample_val_s2 <= sample_val_s; |
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239 | 242 | END GENERATE noREG_ADC_DATA_valid; |
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240 | 243 | |
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244 | REGm_ADC_DATA_valid: IF DATA_CYCLE_VALID > OE_NB_CYCLE_ENABLED GENERATE | |
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245 | ||
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246 | ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED + 1 ELSE '0'; | |
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247 | ||
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248 | REG_1: SYNC_FF | |
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249 | GENERIC MAP ( | |
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250 | NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1) | |
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251 | PORT MAP ( | |
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252 | clk => clk, | |
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253 | rstn => rstn, | |
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254 | A => ADC_data_valid_s, | |
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255 | A_sync => ADC_data_valid); | |
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256 | ||
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257 | REG_2: SYNC_FF | |
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258 | GENERIC MAP ( | |
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259 | NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1) | |
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260 | PORT MAP ( | |
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261 | clk => clk, | |
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262 | rstn => rstn, | |
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263 | A => sample_val_s, | |
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264 | A_sync => sample_val_s2); | |
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265 | END GENERATE REGm_ADC_DATA_valid; | |
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266 | ||
|
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267 | ||
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241 | 268 | |
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242 | 269 | WITH ADC_current SELECT |
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243 | 270 | ADC_data_selected <= sample_reg(0) WHEN 0, |
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244 | 271 | sample_reg(1) WHEN 1, |
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245 | 272 | sample_reg(2) WHEN 2, |
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246 | 273 | sample_reg(3) WHEN 3, |
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247 | 274 | sample_reg(4) WHEN 4, |
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248 | 275 | sample_reg(5) WHEN 5, |
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249 | 276 | sample_reg(6) WHEN 6, |
|
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250 | 277 | sample_reg(7) WHEN 7, |
|
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251 | 278 | sample_reg(8) WHEN OTHERS ; |
|
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252 | 279 | |
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253 | 280 | ADC_data_result <= std_logic_vector(( |
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254 | 281 | signed( ADC_data_selected(13) & ADC_data_selected) + |
|
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255 | 282 | signed( ADC_data_reg(13) & ADC_data_reg) |
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256 | 283 | )); |
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257 | 284 | |
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258 | 285 | -- sample <= sample_reg; |
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259 | 286 | |
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260 | 287 | END ar_top_ad_conv_RHF1401; |
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261 | 288 | |
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262 | 289 | |
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263 | 290 | |
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264 | 291 | |
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265 | 292 | |
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266 | 293 | |
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267 | 294 | |
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268 | 295 | |
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269 | 296 | |
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270 | 297 | |
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271 | 298 | |
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272 | 299 | |
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273 | 300 | |
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274 | 301 | |
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