##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

SVG Fichiers Simu
martin -
r189:1c5a43d81f5c martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,295
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34
35
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 --USE work.config.ALL;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 use lpp.lpp_demux.all;
46 use lpp.lpp_dma_pkg.all;
47 use lpp.lpp_Header.all;
48 use lpp.lpp_fft.all;
49 use lpp.lpp_matrix.all;
50
51
52 ENTITY TestBench IS
53 END;
54
55 ARCHITECTURE Behavioral OF TestBench IS
56
57
58 component TestModule_ADS7886 IS
59 GENERIC (
60 freq : INTEGER ;
61 amplitude : INTEGER ;
62 impulsion : INTEGER
63 );
64 PORT (
65 -- CONV --
66 cnv_run : IN STD_LOGIC;
67 cnv : IN STD_LOGIC;
68
69 -- DATA --
70 sck : IN STD_LOGIC;
71 sdo : OUT STD_LOGIC
72 );
73 END component;
74
75 SIGNAL clk49_152MHz : STD_LOGIC := '0';
76 SIGNAL clkm : STD_LOGIC := '0';
77 SIGNAL rstn : STD_LOGIC := '0';
78 SIGNAL coarse_time_0 : STD_LOGIC := '0';
79
80 -- -- ADC interface
81 -- SIGNAL bias_fail_sw : STD_LOGIC; -- OUT
82 -- SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
83 -- SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
84 -- SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
85
86 --
87 SIGNAL apbi : apb_slv_in_type;
88 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
89 SIGNAL ahbmi : ahb_mst_in_type;
90 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
91
92 -- -- internal
93 -- SIGNAL sample : Samples14v(7 DOWNTO 0);
94 -- SIGNAL sample_val : STD_LOGIC;
95
96 -- ACQ
97 signal CNV_CH1 : STD_LOGIC;
98 signal SCK_CH1 : STD_LOGIC;
99 signal SDO_CH1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
100 signal Bias_Fails : std_logic;
101 signal sample_val : STD_LOGIC;
102 signal sample : Samples(8-1 DOWNTO 0);
103
104 signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
106 signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
108 signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
110 -- FIFOs
111 signal FifoF0_Empty : std_logic_vector(4 downto 0);
112 signal FifoF0_Data : std_logic_vector(79 downto 0);
113 signal FifoF1_Empty : std_logic_vector(4 downto 0);
114 signal FifoF1_Data : std_logic_vector(79 downto 0);
115 signal FifoF3_Empty : std_logic_vector(4 downto 0);
116 signal FifoF3_Data : std_logic_vector(79 downto 0);
117 signal FifoINT_Full : std_logic_vector(4 downto 0);
118 signal FifoINT_Data : std_logic_vector(79 downto 0);
119 signal FifoOUT_Full : std_logic_vector(1 downto 0);
120 signal FifoOUT_Empty : std_logic_vector(1 downto 0);
121 signal FifoOUT_Data : std_logic_vector(63 downto 0);
122 -- MATRICE SPECTRALE
123 signal SM_FlagError : std_logic;
124 signal SM_Pong : std_logic;
125 signal SM_Wen : std_logic;
126 signal SM_Read : std_logic_vector(4 downto 0);
127 signal SM_Write : std_logic_vector(1 downto 0);
128 signal SM_ReUse : std_logic_vector(4 downto 0);
129 signal SM_Param : std_logic_vector(3 downto 0);
130 signal SM_Data : std_logic_vector(63 downto 0);
131 -- FFT
132 signal FFT_Load : std_logic;
133 signal FFT_Read : std_logic_vector(4 downto 0);
134 signal FFT_Write : std_logic_vector(4 downto 0);
135 signal FFT_ReUse : std_logic_vector(4 downto 0);
136 signal FFT_Data : std_logic_vector(79 downto 0);
137 -- DEMUX
138 signal DMUX_Read : std_logic_vector(14 downto 0);
139 signal DMUX_Empty : std_logic_vector(4 downto 0);
140 signal DMUX_Data : std_logic_vector(79 downto 0);
141 signal DMUX_WorkFreq : std_logic_vector(1 downto 0);
142 -- Header
143 signal Head_Read : std_logic_vector(1 downto 0);
144 signal Head_Data : std_logic_vector(31 downto 0);
145 signal Head_Empty : std_logic;
146 signal Head_Header : std_logic_vector(31 DOWNTO 0);
147 signal Head_Valid : std_logic;
148 signal Head_Val : std_logic;
149 --DMA
150 signal DMA_Read : std_logic;
151 signal DMA_ack : std_logic;
152 signal AHB_Master_In : AHB_Mst_In_Type;
153 signal AHB_Master_Out : AHB_Mst_Out_Type;
154
155
156 BEGIN
157
158 -----------------------------------------------------------------------------
159
160 -- MODULE_RHF1401: FOR I IN 0 TO 7 GENERATE
161 -- TestModule_RHF1401_1: TestModule_RHF1401
162 -- GENERIC MAP (
163 -- freq => 24*(I+1),
164 -- amplitude => 8000/(I+1),
165 -- impulsion => 0)
166 -- PORT MAP (
167 -- ADC_smpclk => ADC_smpclk,
168 -- ADC_OEB_bar => ADC_OEB_bar_CH(I),
169 -- ADC_data => ADC_data);
170 -- END GENERATE MODULE_RHF1401;
171
172 MODULE_ADS7886: FOR I IN 0 TO 7 GENERATE
173 TestModule_ADS7886_0 : TestModule_ADS7886
174 GENERIC MAP (
175 freq => 24*(I+1),
176 amplitude => 8000/(I+1),
177 impulsion => 0)
178 PORT MAP(
179 -- CONV --
180 cnv_run => '1',
181 cnv => CNV_CH1,
182 -- DATA --
183 sck => SCK_CH1,
184 sdo => SDO_CH1(I));
185 END GENERATE MODULE_ADS7886;
186
187
188 -----------------------------------------------------------------------------
189
190 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
191 clkm <= NOT clkm AFTER 20 ns; -- 25 MHz
192 coarse_time_0 <= NOT coarse_time_0 AFTER 100 ms;
193
194 -----------------------------------------------------------------------------
195 -- waveform generation
196 WaveGen_Proc : PROCESS
197 BEGIN
198 WAIT UNTIL clkm = '1';
199 apbi <= apb_slv_in_none;
200 rstn <= '0';
201 -- cnv_rstn <= '0';
202 -- run_cnv <= '0';
203 WAIT UNTIL clkm = '1';
204 WAIT UNTIL clkm = '1';
205 WAIT UNTIL clkm = '1';
206 rstn <= '1';
207 -- cnv_rstn <= '1';
208 WAIT UNTIL clkm = '1';
209 WAIT UNTIL clkm = '1';
210 WAIT UNTIL clkm = '1';
211
212 WAIT;
213
214 END PROCESS WaveGen_Proc;
215
216
217 ahbmi.HGRANT(2) <= '1';
218 ahbmi.HREADY <= '1';
219 ahbmi.HRESP <= HRESP_OKAY;
220
221
222
223 -------------------------------------------------------------------------------
224 -------------------------------------------------------------------------------
225 -- DUT ------------------------------------------------------------------------
226 -------------------------------------------------------------------------------
227 -------------------------------------------------------------------------------
228 ACQ0 : lpp_top_acq
229 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk49_152MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3);
230
231 Bias_Fails <= '0';
232 --- FIFO IN -------------------------------------------------------------
233
234 Memf0 : lppFIFOxN
235 generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
236 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
237
238 Memf1 : lppFIFOxN
239 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
240 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
241
242 Memf3 : lppFIFOxN
243 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
244 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
245
246 --- DEMUX -------------------------------------------------------------
247
248 DMUX0 : DEMUX
249 generic map(Data_sz => 16)
250 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data);
251
252 --- FFT -------------------------------------------------------------
253
254 FFT0 : FFT
255 generic map(Data_sz => 16,NbData => 256)
256 port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
257
258 ----- LINK MEMORY -------------------------------------------------------
259
260 MemInt : lppFIFOxN
261 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1')
262 port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
263
264 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
265
266 SM0 : MatriceSpectrale
267 generic map(Input_SZ => 16,Result_SZ => 32)
268 port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
269
270 MemOut : lppFIFOxN
271 generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0')
272 port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty);
273
274 ----- Header -------------------------------------------------------
275
276 Head0 : HeaderBuilder
277 generic map(Data_sz => 32)
278 port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
279
280 ----- DMA -------------------------------------------------------
281
282 DMA0 : lpp_dma
283 generic map(
284 tech =>inferred,
285 hindex => 2,
286 pindex => 9,
287 paddr => 9,
288 pmask => 16#fff#,
289 pirq => 0)
290 port map(clkm,rstn,apbi,apbo(9),AHB_Master_In,AHB_Master_Out,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
291
292 -------------------------------------------------------------------------------
293 -------------------------------------------------------------------------------
294
295 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,33
1
2
3 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd
4 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd
5 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
6 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actar.vhd
7 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actram.vhd
8 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftDp.vhd
9 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftSm.vhd
10 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fft_components.vhd
11 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
12 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/primitives.vhd
13 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/twiddle.vhd
14 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd
15
16 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd
17 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd
18 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd
19 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd
20 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd
21 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd
22 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd
23 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd
24 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd
25 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd
26 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd
27
28 vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_Header/HeaderBuilder.vhd
29
30 vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/TestModule_ADS7886.vhd
31 vcom -quiet -93 -work work TestBench.vhd
32
33 vsim work.testbench No newline at end of file
Show file before | Show file after | Hide comments
@@ -12,6 +12,7
12 ./lpp_cna
12 ./lpp_cna
13 ./lpp_demux
13 ./lpp_demux
14 ./lpp_dma
14 ./lpp_dma
15 ./lpp_Header
15 ./lpp_matrix
16 ./lpp_matrix
16 ./lpp_memory
17 ./lpp_memory
17 ./lpp_top_lfr
18 ./lpp_top_lfr
Show file before | Show file after | Hide comments
@@ -22,8 +22,9
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.fft_components.all;
25 library lpp;
26 use lpp.lpp_fft.all;
26 use lpp.lpp_fft.all;
27 use lpp.fft_components.all;
27
28
28 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau"
29 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau"
29
30
Show file before | Show file after | Hide comments
@@ -22,7 +22,8
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
25 library lpp;
26 use lpp.FFT_config.all;
26
27
27 --! Programme qui va permettre de g�n�rer des flags utilis�s au niveau du driver C
28 --! Programme qui va permettre de g�n�rer des flags utilis�s au niveau du driver C
28
29
Show file before | Show file after | Hide comments
@@ -101,6 +101,7 Matrix_Param <= std_logic_vector(to_unsi
101
101
102 header(1 downto 0) <= Matrix_Type;
102 header(1 downto 0) <= Matrix_Type;
103 header(5 downto 2) <= Matrix_Param;
103 header(5 downto 2) <= Matrix_Param;
104 header(31 downto 6) <= (others => '0');
104
105
105 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
106 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
106 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
107 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
Show file before | Show file after | Hide comments
@@ -167,11 +167,11 BEGIN
167 debug_info: PROCESS (HCLK, HRESETn)
167 debug_info: PROCESS (HCLK, HRESETn)
168 BEGIN -- PROCESS debug_info
168 BEGIN -- PROCESS debug_info
169 IF HRESETn = '0' THEN -- asynchronous reset (active low)
169 IF HRESETn = '0' THEN -- asynchronous reset (active low)
170 debug_reg <= (OTHERS => '0');
170 debug_reg_s <= (OTHERS => '0');
171 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
171 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
172 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
172 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
173 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
173 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
174 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
174 IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF;
175 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
175 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
176 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
176 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
177 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
177 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
@@ -349,4 +349,4 BEGIN
349 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
349 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
350 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
350 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
351
351
352 END Behavioral;
352 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -22,6 +22,7
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 use lpp.general_purpose.all;
26 use lpp.general_purpose.all;
26
27
27 --! Driver de l'ALU
28 --! Driver de l'ALU
Show file before | Show file after | Hide comments
@@ -22,8 +22,8
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 --library lpp;
25 library lpp;
26 --use lpp.lpp_matrix.all;
26 use lpp.lpp_matrix.all;
27
27
28 entity MatriceSpectrale is
28 entity MatriceSpectrale is
29 generic(
29 generic(
@@ -64,19 +64,19 signal TopSM_Data2 : std_logic_vect
64
64
65 begin
65 begin
66
66
67 CTRL0 : entity work.ReUse_CTRLR
67 CTRL0 : ReUse_CTRLR
68 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
68 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
69
69
70
70
71 TopSM : entity work.TopSpecMatrix
71 TopSM : TopSpecMatrix
72 generic map (Input_SZ)
72 generic map (Input_SZ)
73 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
73 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
74
74
75 SM : entity work.SpectralMatrix
75 SM : SpectralMatrix
76 generic map (Input_SZ,Result_SZ)
76 generic map (Input_SZ,Result_SZ)
77 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
77 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
78
78
79 DISP : entity work.Dispatch
79 DISP : Dispatch
80 generic map(Result_SZ)
80 generic map(Result_SZ)
81 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
81 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
82
82
Show file before | Show file after | Hide comments
@@ -22,6 +22,7
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 use lpp.lpp_matrix.all;
26 use lpp.lpp_matrix.all;
26
27
27 entity SpectralMatrix is
28 entity SpectralMatrix is
General Comments 0
You need to be logged in to leave comments. Login now