# HG changeset patch # User martin # Date 2013-07-05 09:22:08 # Node ID 1c5a43d81f5c4c963a9be2fd3d02993d1c03d3c8 # Parent 168d889db49dbabff6efb522b2edca1799d66548 SVG Fichiers Simu diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/TestBench.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon/TestBench.vhd new file mode 100644 --- /dev/null +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon/TestBench.vhd @@ -0,0 +1,295 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE + + +LIBRARY esa; +USE esa.memoryctrl.ALL; +--USE work.config.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +use lpp.lpp_demux.all; +use lpp.lpp_dma_pkg.all; +use lpp.lpp_Header.all; +use lpp.lpp_fft.all; +use lpp.lpp_matrix.all; + + +ENTITY TestBench IS +END; + +ARCHITECTURE Behavioral OF TestBench IS + + + component TestModule_ADS7886 IS + GENERIC ( + freq : INTEGER ; + amplitude : INTEGER ; + impulsion : INTEGER + ); + PORT ( + -- CONV -- + cnv_run : IN STD_LOGIC; + cnv : IN STD_LOGIC; + + -- DATA -- + sck : IN STD_LOGIC; + sdo : OUT STD_LOGIC + ); + END component; + + SIGNAL clk49_152MHz : STD_LOGIC := '0'; + SIGNAL clkm : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + SIGNAL coarse_time_0 : STD_LOGIC := '0'; + +-- -- ADC interface +-- SIGNAL bias_fail_sw : STD_LOGIC; -- OUT +-- SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT +-- SIGNAL ADC_smpclk : STD_LOGIC; -- OUT +-- SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN + + -- + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); + +-- -- internal +-- SIGNAL sample : Samples14v(7 DOWNTO 0); +-- SIGNAL sample_val : STD_LOGIC; + +-- ACQ +signal CNV_CH1 : STD_LOGIC; +signal SCK_CH1 : STD_LOGIC; +signal SDO_CH1 : STD_LOGIC_VECTOR(7 DOWNTO 0); +signal Bias_Fails : std_logic; +signal sample_val : STD_LOGIC; +signal sample : Samples(8-1 DOWNTO 0); + +signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); +signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); +signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- FIFOs +signal FifoF0_Empty : std_logic_vector(4 downto 0); +signal FifoF0_Data : std_logic_vector(79 downto 0); +signal FifoF1_Empty : std_logic_vector(4 downto 0); +signal FifoF1_Data : std_logic_vector(79 downto 0); +signal FifoF3_Empty : std_logic_vector(4 downto 0); +signal FifoF3_Data : std_logic_vector(79 downto 0); +signal FifoINT_Full : std_logic_vector(4 downto 0); +signal FifoINT_Data : std_logic_vector(79 downto 0); +signal FifoOUT_Full : std_logic_vector(1 downto 0); +signal FifoOUT_Empty : std_logic_vector(1 downto 0); +signal FifoOUT_Data : std_logic_vector(63 downto 0); +-- MATRICE SPECTRALE +signal SM_FlagError : std_logic; +signal SM_Pong : std_logic; +signal SM_Wen : std_logic; +signal SM_Read : std_logic_vector(4 downto 0); +signal SM_Write : std_logic_vector(1 downto 0); +signal SM_ReUse : std_logic_vector(4 downto 0); +signal SM_Param : std_logic_vector(3 downto 0); +signal SM_Data : std_logic_vector(63 downto 0); +-- FFT +signal FFT_Load : std_logic; +signal FFT_Read : std_logic_vector(4 downto 0); +signal FFT_Write : std_logic_vector(4 downto 0); +signal FFT_ReUse : std_logic_vector(4 downto 0); +signal FFT_Data : std_logic_vector(79 downto 0); +-- DEMUX +signal DMUX_Read : std_logic_vector(14 downto 0); +signal DMUX_Empty : std_logic_vector(4 downto 0); +signal DMUX_Data : std_logic_vector(79 downto 0); +signal DMUX_WorkFreq : std_logic_vector(1 downto 0); +-- Header +signal Head_Read : std_logic_vector(1 downto 0); +signal Head_Data : std_logic_vector(31 downto 0); +signal Head_Empty : std_logic; +signal Head_Header : std_logic_vector(31 DOWNTO 0); +signal Head_Valid : std_logic; +signal Head_Val : std_logic; +--DMA +signal DMA_Read : std_logic; +signal DMA_ack : std_logic; +signal AHB_Master_In : AHB_Mst_In_Type; +signal AHB_Master_Out : AHB_Mst_Out_Type; + + +BEGIN + + ----------------------------------------------------------------------------- + +-- MODULE_RHF1401: FOR I IN 0 TO 7 GENERATE +-- TestModule_RHF1401_1: TestModule_RHF1401 +-- GENERIC MAP ( +-- freq => 24*(I+1), +-- amplitude => 8000/(I+1), +-- impulsion => 0) +-- PORT MAP ( +-- ADC_smpclk => ADC_smpclk, +-- ADC_OEB_bar => ADC_OEB_bar_CH(I), +-- ADC_data => ADC_data); +-- END GENERATE MODULE_RHF1401; + +MODULE_ADS7886: FOR I IN 0 TO 7 GENERATE +TestModule_ADS7886_0 : TestModule_ADS7886 + GENERIC MAP ( + freq => 24*(I+1), + amplitude => 8000/(I+1), + impulsion => 0) + PORT MAP( + -- CONV -- + cnv_run => '1', + cnv => CNV_CH1, + -- DATA -- + sck => SCK_CH1, + sdo => SDO_CH1(I)); + END GENERATE MODULE_ADS7886; + + + ----------------------------------------------------------------------------- + + clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz + clkm <= NOT clkm AFTER 20 ns; -- 25 MHz + coarse_time_0 <= NOT coarse_time_0 AFTER 100 ms; + + ----------------------------------------------------------------------------- + -- waveform generation + WaveGen_Proc : PROCESS + BEGIN + WAIT UNTIL clkm = '1'; + apbi <= apb_slv_in_none; + rstn <= '0'; +-- cnv_rstn <= '0'; +-- run_cnv <= '0'; + WAIT UNTIL clkm = '1'; + WAIT UNTIL clkm = '1'; + WAIT UNTIL clkm = '1'; + rstn <= '1'; +-- cnv_rstn <= '1'; + WAIT UNTIL clkm = '1'; + WAIT UNTIL clkm = '1'; + WAIT UNTIL clkm = '1'; + + WAIT; + + END PROCESS WaveGen_Proc; + + + ahbmi.HGRANT(2) <= '1'; + ahbmi.HREADY <= '1'; + ahbmi.HRESP <= HRESP_OKAY; + + + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- DUT ------------------------------------------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + ACQ0 : lpp_top_acq + port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk49_152MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3); + + Bias_Fails <= '0'; +--- FIFO IN ------------------------------------------------------------- + + Memf0 : lppFIFOxN + generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); + + Memf1 : lppFIFOxN + generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); + + Memf3 : lppFIFOxN + generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); + +--- DEMUX ------------------------------------------------------------- + + DMUX0 : DEMUX + generic map(Data_sz => 16) + port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data); + +--- FFT ------------------------------------------------------------- + + FFT0 : FFT + generic map(Data_sz => 16,NbData => 256) + port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); + +----- LINK MEMORY ------------------------------------------------------- + + MemInt : lppFIFOxN + generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1') + port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); + +----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- + + SM0 : MatriceSpectrale + generic map(Input_SZ => 16,Result_SZ => 32) + port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); + + MemOut : lppFIFOxN + generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty); + +----- Header ------------------------------------------------------- + + Head0 : HeaderBuilder + generic map(Data_sz => 32) + port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); + +----- DMA ------------------------------------------------------- + + DMA0 : lpp_dma + generic map( + tech =>inferred, + hindex => 2, + pindex => 9, + paddr => 9, + pmask => 16#fff#, + pirq => 0) + port map(clkm,rstn,apbi,apbo(9),AHB_Master_In,AHB_Master_Out,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +END Behavioral; \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/run_simu.do b/designs/Projet-LeonLFR-A3P3K-Sheldon/run_simu.do new file mode 100644 --- /dev/null +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon/run_simu.do @@ -0,0 +1,33 @@ + + +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actar.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actram.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftDp.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftSm.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fft_components.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/primitives.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/twiddle.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd + +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd +# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd + + vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_Header/HeaderBuilder.vhd + +vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/TestModule_ADS7886.vhd +vcom -quiet -93 -work work TestBench.vhd + +vsim work.testbench \ No newline at end of file diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt --- a/lib/lpp/dirs.txt +++ b/lib/lpp/dirs.txt @@ -12,6 +12,7 @@ ./lpp_cna ./lpp_demux ./lpp_dma +./lpp_Header ./lpp_matrix ./lpp_memory ./lpp_top_lfr diff --git a/lib/lpp/dsp/lpp_fft/FFT.vhd b/lib/lpp/dsp/lpp_fft/FFT.vhd --- a/lib/lpp/dsp/lpp_fft/FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/FFT.vhd @@ -1,94 +1,95 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.fft_components.all; -use lpp.lpp_fft.all; - --- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau" - -entity FFT is - generic( - Data_sz : integer := 16; - NbData : integer := 256); - port( - clkm : in std_logic; - rstn : in std_logic; - FifoIN_Empty : in std_logic_vector(4 downto 0); - FifoIN_Data : in std_logic_vector(79 downto 0); - FifoOUT_Full : in std_logic_vector(4 downto 0); - Load : out std_logic; - Read : out std_logic_vector(4 downto 0); - Write : out std_logic_vector(4 downto 0); - ReUse : out std_logic_vector(4 downto 0); - Data : out std_logic_vector(79 downto 0) - ); -end entity; - - -architecture ar_FFT of FFT is - -signal Drive_Write : std_logic; -signal Drive_DataRE : std_logic_vector(15 downto 0); -signal Drive_DataIM : std_logic_vector(15 downto 0); - -signal Start : std_logic; -signal FFT_Load : std_logic; -signal FFT_Ready : std_logic; -signal FFT_Valid : std_logic; -signal FFT_DataRE : std_logic_vector(15 downto 0); -signal FFT_DataIM : std_logic_vector(15 downto 0); - -signal Link_Read : std_logic; - -begin - -Start <= '0'; -Load <= FFT_Load; - - DRIVE : Driver_FFT - generic map(Data_sz,NbData) - port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM); - - FFT0 : CoreFFT - generic map( - LOGPTS => gLOGPTS, - LOGLOGPTS => gLOGLOGPTS, - WSIZE => gWSIZE, - TWIDTH => gTWIDTH, - DWIDTH => gDWIDTH, - TDWIDTH => gTDWIDTH, - RND_MODE => gRND_MODE, - SCALE_MODE => gSCALE_MODE, - PTS => gPTS, - HALFPTS => gHALFPTS, - inBuf_RWDLY => gInBuf_RWDLY) - port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); - - - LINK : Linker_FFT - generic map(Data_sz,NbData) - port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); - - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_fft.all; +use lpp.fft_components.all; + +-- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau" + +entity FFT is + generic( + Data_sz : integer := 16; + NbData : integer := 256); + port( + clkm : in std_logic; + rstn : in std_logic; + FifoIN_Empty : in std_logic_vector(4 downto 0); + FifoIN_Data : in std_logic_vector(79 downto 0); + FifoOUT_Full : in std_logic_vector(4 downto 0); + Load : out std_logic; + Read : out std_logic_vector(4 downto 0); + Write : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Data : out std_logic_vector(79 downto 0) + ); +end entity; + + +architecture ar_FFT of FFT is + +signal Drive_Write : std_logic; +signal Drive_DataRE : std_logic_vector(15 downto 0); +signal Drive_DataIM : std_logic_vector(15 downto 0); + +signal Start : std_logic; +signal FFT_Load : std_logic; +signal FFT_Ready : std_logic; +signal FFT_Valid : std_logic; +signal FFT_DataRE : std_logic_vector(15 downto 0); +signal FFT_DataIM : std_logic_vector(15 downto 0); + +signal Link_Read : std_logic; + +begin + +Start <= '0'; +Load <= FFT_Load; + + DRIVE : Driver_FFT + generic map(Data_sz,NbData) + port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM); + + FFT0 : CoreFFT + generic map( + LOGPTS => gLOGPTS, + LOGLOGPTS => gLOGLOGPTS, + WSIZE => gWSIZE, + TWIDTH => gTWIDTH, + DWIDTH => gDWIDTH, + TDWIDTH => gTDWIDTH, + RND_MODE => gRND_MODE, + SCALE_MODE => gSCALE_MODE, + PTS => gPTS, + HALFPTS => gHALFPTS, + inBuf_RWDLY => gInBuf_RWDLY) + port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); + + + LINK : Linker_FFT + generic map(Data_sz,NbData) + port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); + + end architecture; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd b/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd --- a/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd +++ b/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd @@ -1,72 +1,73 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.FFT_config.all; - ---! Programme qui va permettre de g�n�rer des flags utilis�s au niveau du driver C - -entity Flag_Extremum is - port( - clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant - load : in std_logic; --! Signal en provenance de CoreFFT - y_rdy : in std_logic; --! Signal en provenance de CoreFFT - fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C) - ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C) - ); -end Flag_Extremum; - ---! @details Flags g�n�r�s a partir de signaux fourni par l'IP FFT d'actel - -architecture ar_Flag_Extremum of Flag_Extremum is - -begin - process (clk,raz) - begin - if(raz='0')then - fill <= '0'; - ready <= '0'; - - elsif(clk' event and clk='1')then - - if(load='1' and y_rdy='0')then - fill <= '1'; - ready <= '0'; - - elsif(y_rdy='1')then - fill <= '0'; - ready <= '1'; - - else - fill <= '0'; - ready <= '0'; - - end if; - end if; - end process; - -end ar_Flag_Extremum; - - - - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.FFT_config.all; + +--! Programme qui va permettre de g�n�rer des flags utilis�s au niveau du driver C + +entity Flag_Extremum is + port( + clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant + load : in std_logic; --! Signal en provenance de CoreFFT + y_rdy : in std_logic; --! Signal en provenance de CoreFFT + fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C) + ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C) + ); +end Flag_Extremum; + +--! @details Flags g�n�r�s a partir de signaux fourni par l'IP FFT d'actel + +architecture ar_Flag_Extremum of Flag_Extremum is + +begin + process (clk,raz) + begin + if(raz='0')then + fill <= '0'; + ready <= '0'; + + elsif(clk' event and clk='1')then + + if(load='1' and y_rdy='0')then + fill <= '1'; + ready <= '0'; + + elsif(y_rdy='1')then + fill <= '0'; + ready <= '1'; + + else + fill <= '0'; + ready <= '0'; + + end if; + end if; + end process; + +end ar_Flag_Extremum; + + + + diff --git a/lib/lpp/lpp_Header/HeaderBuilder.vhd b/lib/lpp/lpp_Header/HeaderBuilder.vhd --- a/lib/lpp/lpp_Header/HeaderBuilder.vhd +++ b/lib/lpp/lpp_Header/HeaderBuilder.vhd @@ -43,9 +43,9 @@ entity HeaderBuilder is dataOUT : out std_logic_vector(Data_sz-1 downto 0); emptyOUT : out std_logic; RenIN : in std_logic; - - header : out std_logic_vector(Data_sz-1 DOWNTO 0); - header_val : out std_logic; + + header : out std_logic_vector(Data_sz-1 DOWNTO 0); + header_val : out std_logic; header_ack : in std_logic ); end entity; @@ -101,6 +101,7 @@ Matrix_Param <= std_logic_vector(to_unsi header(1 downto 0) <= Matrix_Type; header(5 downto 2) <= Matrix_Param; +header(31 downto 6) <= (others => '0'); dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz); emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1); diff --git a/lib/lpp/lpp_dma/lpp_dma_ip.vhd b/lib/lpp/lpp_dma/lpp_dma_ip.vhd --- a/lib/lpp/lpp_dma/lpp_dma_ip.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_ip.vhd @@ -1,352 +1,352 @@ - ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com -------------------------------------------------------------------------------- --- 1.0 - initial version --- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) -------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; ---USE GRLIB.DMA2AHB_TestPackage.ALL; -LIBRARY lpp; -USE lpp.lpp_amba.ALL; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_dma_pkg.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - - -ENTITY lpp_dma_ip IS - GENERIC ( - tech : INTEGER := inferred; - hindex : INTEGER := 2 - ); - PORT ( - -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - - -- fifo interface - fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fifo_empty : IN STD_LOGIC; - fifo_ren : OUT STD_LOGIC; - - -- header - header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - header_val : IN STD_LOGIC; - header_ack : OUT STD_LOGIC; - - -- Reg out - ready_matrix_f0_0 : OUT STD_LOGIC; - ready_matrix_f0_1 : OUT STD_LOGIC; - ready_matrix_f1 : OUT STD_LOGIC; - ready_matrix_f2 : OUT STD_LOGIC; - error_anticipating_empty_fifo : OUT STD_LOGIC; - error_bad_component_error : OUT STD_LOGIC; - debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - -- Reg In - status_ready_matrix_f0_0 :IN STD_LOGIC; - status_ready_matrix_f0_1 :IN STD_LOGIC; - status_ready_matrix_f1 :IN STD_LOGIC; - status_ready_matrix_f2 :IN STD_LOGIC; - status_error_anticipating_empty_fifo :IN STD_LOGIC; - status_error_bad_component_error :IN STD_LOGIC; - - config_active_interruption_onNewMatrix : IN STD_LOGIC; - config_active_interruption_onError : IN STD_LOGIC; - addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF lpp_dma_ip IS - ----------------------------------------------------------------------------- - SIGNAL DMAIn : DMA_In_Type; - SIGNAL header_dmai : DMA_In_Type; - SIGNAL component_dmai : DMA_In_Type; - SIGNAL DMAOut : DMA_OUt_Type; - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- - TYPE state_DMAWriteBurst IS (IDLE, - TRASH_FIFO, - WAIT_HEADER_ACK, - SEND_DATA, - WAIT_DATA_ACK, - CHECK_LENGTH - ); - SIGNAL state : state_DMAWriteBurst := IDLE; - - SIGNAL nbSend : INTEGER; - SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL header_check_ok : STD_LOGIC; - SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL send_matrix : STD_LOGIC; - SIGNAL request : STD_LOGIC; - SIGNAL remaining_data_request : INTEGER; - SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); - ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- - SIGNAL header_select : STD_LOGIC; - - SIGNAL header_send : STD_LOGIC; - SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL header_send_ok : STD_LOGIC; - SIGNAL header_send_ko : STD_LOGIC; - - SIGNAL component_send : STD_LOGIC; - SIGNAL component_send_ok : STD_LOGIC; - SIGNAL component_send_ko : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL fifo_ren_trash : STD_LOGIC; - SIGNAL component_fifo_ren : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------------- - -- DMA to AHB interface - ----------------------------------------------------------------------------- - - DMA2AHB_1 : DMA2AHB - GENERIC MAP ( - hindex => hindex, - vendorid => VENDOR_LPP, - deviceid => 0, - version => 0, - syncrst => 1, - boundary => 1) -- FIX 11/01/2013 - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - DMAIn => DMAIn, - DMAOut => DMAOut, - AHBIn => AHB_Master_In, - AHBOut => AHB_Master_Out); - - debug_reg <= debug_reg_s; - - debug_info: PROCESS (HCLK, HRESETn) - BEGIN -- PROCESS debug_info - IF HRESETn = '0' THEN -- asynchronous reset (active low) - debug_reg <= (OTHERS => '0'); - ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge - debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry ); - debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ; - IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF; - debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko); - debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok); - debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko); - debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok); - - debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1'); - END IF; - END PROCESS debug_info; - - - matrix_type <= header(1 DOWNTO 0); - component_type <= header(5 DOWNTO 2); - - send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE - '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE - '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE - '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE - '0'; - - header_check_ok <= '0' WHEN component_type = "1111" ELSE - '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE - '1' WHEN component_type = component_type_pre + "0001" ELSE - '0'; - - address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE - addr_matrix_f0_1 WHEN matrix_type = "01" ELSE - addr_matrix_f1 WHEN matrix_type = "10" ELSE - addr_matrix_f2 WHEN matrix_type = "11" ELSE - (OTHERS => '0'); - - ----------------------------------------------------------------------------- - -- DMA control - ----------------------------------------------------------------------------- - DMAWriteFSM_p : PROCESS (HCLK, HRESETn) - BEGIN -- PROCESS DMAWriteBurst_p - IF HRESETn = '0' THEN -- asynchronous reset (active low) - state <= IDLE; - header_ack <= '0'; - ready_matrix_f0_0 <= '0'; - ready_matrix_f0_1 <= '0'; - ready_matrix_f1 <= '0'; - ready_matrix_f2 <= '0'; - error_anticipating_empty_fifo <= '0'; - error_bad_component_error <= '0'; - component_type_pre <= "1110"; - fifo_ren_trash <= '1'; - component_send <= '0'; - address <= (OTHERS => '0'); - header_select <= '0'; - header_send <= '0'; - header_data <= (OTHERS => '0'); - ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - - CASE state IS - WHEN IDLE => - ready_matrix_f0_0 <= '0'; - ready_matrix_f0_1 <= '0'; - ready_matrix_f1 <= '0'; - ready_matrix_f2 <= '0'; - error_bad_component_error <= '0'; - header_select <= '1'; - IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN - IF header_check_ok = '1' THEN - header_data <= header; - component_type_pre <= header(5 DOWNTO 2); - header_ack <= '1'; - -- - header_send <= '1'; - IF component_type = "0000" THEN - address <= address_matrix; - END IF; - header_data <= header; - -- - state <= WAIT_HEADER_ACK; - ELSE - error_bad_component_error <= '1'; - component_type_pre <= "1110"; - header_ack <= '1'; - state <= TRASH_FIFO; - END IF; - END IF; - - WHEN TRASH_FIFO => - error_bad_component_error <= '0'; - error_anticipating_empty_fifo <= '0'; - IF fifo_empty = '1' THEN - state <= IDLE; - fifo_ren_trash <= '1'; - ELSE - fifo_ren_trash <= '0'; - END IF; - - WHEN WAIT_HEADER_ACK => - header_send <= '0'; - IF header_send_ko = '1' THEN - state <= TRASH_FIFO; - error_anticipating_empty_fifo <= '1'; - -- TODO : error sending header - ELSIF header_send_ok = '1' THEN - header_select <= '0'; - state <= SEND_DATA; - address <= address + 4; - END IF; - - WHEN SEND_DATA => - IF fifo_empty = '1' THEN - state <= IDLE; - IF component_type = "1110" THEN - CASE matrix_type IS - WHEN "00" => ready_matrix_f0_0 <= '1'; - WHEN "01" => ready_matrix_f0_1 <= '1'; - WHEN "10" => ready_matrix_f1 <= '1'; - WHEN "11" => ready_matrix_f2 <= '1'; - WHEN OTHERS => NULL; - END CASE; - END IF; - ELSE - component_send <= '1'; - address <= address; - state <= WAIT_DATA_ACK; - END IF; - - WHEN WAIT_DATA_ACK => - component_send <= '0'; - IF component_send_ok = '1' THEN - address <= address + 64; - state <= SEND_DATA; - ELSIF component_send_ko = '1' THEN - error_anticipating_empty_fifo <= '0'; - state <= TRASH_FIFO; - END IF; - - WHEN CHECK_LENGTH => - state <= IDLE; - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS DMAWriteFSM_p; - - ----------------------------------------------------------------------------- - -- SEND 1 word by DMA - ----------------------------------------------------------------------------- - lpp_dma_send_1word_1 : lpp_dma_send_1word - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - DMAIn => header_dmai, - DMAOut => DMAOut, - - send => header_send, - address => address, - data => header_data, - send_ok => header_send_ok, - send_ko => header_send_ko - ); - - ----------------------------------------------------------------------------- - -- SEND 16 word by DMA (in burst mode) - ----------------------------------------------------------------------------- - lpp_dma_send_16word_1 : lpp_dma_send_16word - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - DMAIn => component_dmai, - DMAOut => DMAOut, - - send => component_send, - address => address, - data => fifo_data, - ren => component_fifo_ren, - send_ok => component_send_ok, - send_ko => component_send_ko); - - DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; - fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; - -END Behavioral; + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +-- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +--USE GRLIB.DMA2AHB_TestPackage.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_dma_ip IS + GENERIC ( + tech : INTEGER := inferred; + hindex : INTEGER := 2 + ); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + -- fifo interface + fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fifo_empty : IN STD_LOGIC; + fifo_ren : OUT STD_LOGIC; + + -- header + header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + header_val : IN STD_LOGIC; + header_ack : OUT STD_LOGIC; + + -- Reg out + ready_matrix_f0_0 : OUT STD_LOGIC; + ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Reg In + status_ready_matrix_f0_0 :IN STD_LOGIC; + status_ready_matrix_f0_1 :IN STD_LOGIC; + status_ready_matrix_f1 :IN STD_LOGIC; + status_ready_matrix_f2 :IN STD_LOGIC; + status_error_anticipating_empty_fifo :IN STD_LOGIC; + status_error_bad_component_error :IN STD_LOGIC; + + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_dma_ip IS + ----------------------------------------------------------------------------- + SIGNAL DMAIn : DMA_In_Type; + SIGNAL header_dmai : DMA_In_Type; + SIGNAL component_dmai : DMA_In_Type; + SIGNAL DMAOut : DMA_OUt_Type; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + TYPE state_DMAWriteBurst IS (IDLE, + TRASH_FIFO, + WAIT_HEADER_ACK, + SEND_DATA, + WAIT_DATA_ACK, + CHECK_LENGTH + ); + SIGNAL state : state_DMAWriteBurst := IDLE; + + SIGNAL nbSend : INTEGER; + SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL header_check_ok : STD_LOGIC; + SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL send_matrix : STD_LOGIC; + SIGNAL request : STD_LOGIC; + SIGNAL remaining_data_request : INTEGER; + SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + SIGNAL header_select : STD_LOGIC; + + SIGNAL header_send : STD_LOGIC; + SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL header_send_ok : STD_LOGIC; + SIGNAL header_send_ko : STD_LOGIC; + + SIGNAL component_send : STD_LOGIC; + SIGNAL component_send_ok : STD_LOGIC; + SIGNAL component_send_ko : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL fifo_ren_trash : STD_LOGIC; + SIGNAL component_fifo_ren : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + -- DMA to AHB interface + ----------------------------------------------------------------------------- + + DMA2AHB_1 : DMA2AHB + GENERIC MAP ( + hindex => hindex, + vendorid => VENDOR_LPP, + deviceid => 0, + version => 0, + syncrst => 1, + boundary => 1) -- FIX 11/01/2013 + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => DMAIn, + DMAOut => DMAOut, + AHBIn => AHB_Master_In, + AHBOut => AHB_Master_Out); + + debug_reg <= debug_reg_s; + + debug_info: PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS debug_info + IF HRESETn = '0' THEN -- asynchronous reset (active low) + debug_reg_s <= (OTHERS => '0'); + ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge + debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry ); + debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ; + IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF; + debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko); + debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok); + debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko); + debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok); + + debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1'); + END IF; + END PROCESS debug_info; + + + matrix_type <= header(1 DOWNTO 0); + component_type <= header(5 DOWNTO 2); + + send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE + '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE + '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE + '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE + '0'; + + header_check_ok <= '0' WHEN component_type = "1111" ELSE + '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE + '1' WHEN component_type = component_type_pre + "0001" ELSE + '0'; + + address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE + addr_matrix_f0_1 WHEN matrix_type = "01" ELSE + addr_matrix_f1 WHEN matrix_type = "10" ELSE + addr_matrix_f2 WHEN matrix_type = "11" ELSE + (OTHERS => '0'); + + ----------------------------------------------------------------------------- + -- DMA control + ----------------------------------------------------------------------------- + DMAWriteFSM_p : PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS DMAWriteBurst_p + IF HRESETn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + header_ack <= '0'; + ready_matrix_f0_0 <= '0'; + ready_matrix_f0_1 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; + error_anticipating_empty_fifo <= '0'; + error_bad_component_error <= '0'; + component_type_pre <= "1110"; + fifo_ren_trash <= '1'; + component_send <= '0'; + address <= (OTHERS => '0'); + header_select <= '0'; + header_send <= '0'; + header_data <= (OTHERS => '0'); + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + CASE state IS + WHEN IDLE => + ready_matrix_f0_0 <= '0'; + ready_matrix_f0_1 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; + error_bad_component_error <= '0'; + header_select <= '1'; + IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN + IF header_check_ok = '1' THEN + header_data <= header; + component_type_pre <= header(5 DOWNTO 2); + header_ack <= '1'; + -- + header_send <= '1'; + IF component_type = "0000" THEN + address <= address_matrix; + END IF; + header_data <= header; + -- + state <= WAIT_HEADER_ACK; + ELSE + error_bad_component_error <= '1'; + component_type_pre <= "1110"; + header_ack <= '1'; + state <= TRASH_FIFO; + END IF; + END IF; + + WHEN TRASH_FIFO => + error_bad_component_error <= '0'; + error_anticipating_empty_fifo <= '0'; + IF fifo_empty = '1' THEN + state <= IDLE; + fifo_ren_trash <= '1'; + ELSE + fifo_ren_trash <= '0'; + END IF; + + WHEN WAIT_HEADER_ACK => + header_send <= '0'; + IF header_send_ko = '1' THEN + state <= TRASH_FIFO; + error_anticipating_empty_fifo <= '1'; + -- TODO : error sending header + ELSIF header_send_ok = '1' THEN + header_select <= '0'; + state <= SEND_DATA; + address <= address + 4; + END IF; + + WHEN SEND_DATA => + IF fifo_empty = '1' THEN + state <= IDLE; + IF component_type = "1110" THEN + CASE matrix_type IS + WHEN "00" => ready_matrix_f0_0 <= '1'; + WHEN "01" => ready_matrix_f0_1 <= '1'; + WHEN "10" => ready_matrix_f1 <= '1'; + WHEN "11" => ready_matrix_f2 <= '1'; + WHEN OTHERS => NULL; + END CASE; + END IF; + ELSE + component_send <= '1'; + address <= address; + state <= WAIT_DATA_ACK; + END IF; + + WHEN WAIT_DATA_ACK => + component_send <= '0'; + IF component_send_ok = '1' THEN + address <= address + 64; + state <= SEND_DATA; + ELSIF component_send_ko = '1' THEN + error_anticipating_empty_fifo <= '0'; + state <= TRASH_FIFO; + END IF; + + WHEN CHECK_LENGTH => + state <= IDLE; + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS DMAWriteFSM_p; + + ----------------------------------------------------------------------------- + -- SEND 1 word by DMA + ----------------------------------------------------------------------------- + lpp_dma_send_1word_1 : lpp_dma_send_1word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => header_dmai, + DMAOut => DMAOut, + + send => header_send, + address => address, + data => header_data, + send_ok => header_send_ok, + send_ko => header_send_ko + ); + + ----------------------------------------------------------------------------- + -- SEND 16 word by DMA (in burst mode) + ----------------------------------------------------------------------------- + lpp_dma_send_16word_1 : lpp_dma_send_16word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => component_dmai, + DMAOut => DMAOut, + + send => component_send, + address => address, + data => fifo_data, + ren => component_fifo_ren, + send_ok => component_send_ok, + send_ko => component_send_ko); + + DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; + fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; + +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/ALU_Driver.vhd b/lib/lpp/lpp_matrix/ALU_Driver.vhd --- a/lib/lpp/lpp_matrix/ALU_Driver.vhd +++ b/lib/lpp/lpp_matrix/ALU_Driver.vhd @@ -1,216 +1,217 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -use lpp.general_purpose.all; - ---! Driver de l'ALU - -entity ALU_Driver is - generic( - Input_SZ_1 : integer := 16; - Input_SZ_2 : integer := 16); - port( - clk : in std_logic; --! Horloge du composant - reset : in std_logic; --! Reset general du composant - IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e - IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e - Take : in std_logic; --! Flag, op�rande r�cup�r� - Received : in std_logic; --! Flag, R�sultat bien ressu - Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu� - Valid : out std_logic; --! Flag, R�sultat disponible - Read : out std_logic; --! Flag, op�rande disponible - CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e - COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes - OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande - OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande -); -end ALU_Driver; - ---! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es - -architecture ar_ALU_Driver of ALU_Driver is - -signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0); -signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0); -signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0); -signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0); - -signal go_st : std_logic; -signal Take_reg : std_logic; -signal Received_reg : std_logic; - -type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW); -signal ect : etat; -signal st : etat; - -begin - process(clk,reset) - begin - - if(reset='0')then - ect <= eX; - st <= e0; - go_st <= '0'; - CTRL <= ctrl_CLRMAC; - COMP <= "00"; -- pas de complement - Read <= '0'; - Valid <= '0'; - Take_reg <= '0'; - Received_reg <= '0'; - - elsif(clk'event and clk='1')then - Take_reg <= Take; - Received_reg <= Received; - - case ect is - when eX => - go_st <= '0'; - Read <= '1'; - CTRL <= ctrl_CLRMAC; - ect <= e0; - - when e0 => - OP1re <= IN1; - if(Conjugate='1')then -- - OP2re <= IN1; -- - else -- - OP2re <= IN2; -- modif 23/06/11 - end if; -- - if(Take_reg='0' and Take='1')then - read <= '0'; - ect <= e1; - end if; - - when e1 => - OP1 <= OP1re; - OP2 <= OP2re; - CTRL <= ctrl_MAC; - Read <= '1'; - ect <= eY; - - when eY => - OP1im <= IN1; - if(Conjugate='1')then -- - OP2im <= IN1; -- - else -- - OP2im <= IN2; -- modif 23/06/11 - end if; -- - CTRL <= ctrl_IDLE; - if(Take_reg='1' and Take='0')then - Read <= '0'; - ect <= e2; - end if; - - when e2 => - OP1 <= OP1im; - OP2 <= OP2im; - CTRL <= ctrl_MAC; - ect <= eZ; - - when eZ => - CTRL <= ctrl_IDLE; - go_st <= '1'; - if(Received_reg='0' and Received='1')then - if(Conjugate='1')then - ect <= eX; - else - ect <= e3; - end if; - end if; - - when e3 => - CTRL <= ctrl_CLRMAC; - go_st <= '0'; - ect <= e4; - - when e4 => - OP1 <= OP1im; - OP2 <= OP2re; - CTRL <= ctrl_MAC; - ect <= e5; - - when e5 => - OP1 <= OP1re; - OP2 <= OP2im; - COMP <= "10"; - ect <= eW; - - when eW => - CTRL <= ctrl_IDLE; - COMP <= "00"; - go_st <= '1'; - if(Received_reg='1' and Received='0')then - ect <= eX; - end if; - end case; ---------------------------------------------------------------------------------- - case st is - when e0 => - if(go_st='1')then - st <= e1; - end if; - - when e1 => - Valid <= '1'; - st <= e2; - - when e2 => - if(Received_reg='0' and Received='1')then - Valid <= '0'; - if(Conjugate='1')then - st <= eY; - else - st <= eX; - end if; - end if; - - when eX => - st <= e3; - - when e3 => - if(go_st='1')then - st <= e4; - end if; - - when e4 => - Valid <= '1'; - st <= e5; - - when e5 => - if(Received_reg='1' and Received='0')then - Valid <= '0'; - st <= eY; - end if; - - when eY => - st <= e0; - - when others => - null; - end case; - - end if; - end process; - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.general_purpose.all; + +--! Driver de l'ALU + +entity ALU_Driver is + generic( + Input_SZ_1 : integer := 16; + Input_SZ_2 : integer := 16); + port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e + IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e + Take : in std_logic; --! Flag, op�rande r�cup�r� + Received : in std_logic; --! Flag, R�sultat bien ressu + Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu� + Valid : out std_logic; --! Flag, R�sultat disponible + Read : out std_logic; --! Flag, op�rande disponible + CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e + COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes + OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande + OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande +); +end ALU_Driver; + +--! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es + +architecture ar_ALU_Driver of ALU_Driver is + +signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0); +signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0); +signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0); +signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0); + +signal go_st : std_logic; +signal Take_reg : std_logic; +signal Received_reg : std_logic; + +type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW); +signal ect : etat; +signal st : etat; + +begin + process(clk,reset) + begin + + if(reset='0')then + ect <= eX; + st <= e0; + go_st <= '0'; + CTRL <= ctrl_CLRMAC; + COMP <= "00"; -- pas de complement + Read <= '0'; + Valid <= '0'; + Take_reg <= '0'; + Received_reg <= '0'; + + elsif(clk'event and clk='1')then + Take_reg <= Take; + Received_reg <= Received; + + case ect is + when eX => + go_st <= '0'; + Read <= '1'; + CTRL <= ctrl_CLRMAC; + ect <= e0; + + when e0 => + OP1re <= IN1; + if(Conjugate='1')then -- + OP2re <= IN1; -- + else -- + OP2re <= IN2; -- modif 23/06/11 + end if; -- + if(Take_reg='0' and Take='1')then + read <= '0'; + ect <= e1; + end if; + + when e1 => + OP1 <= OP1re; + OP2 <= OP2re; + CTRL <= ctrl_MAC; + Read <= '1'; + ect <= eY; + + when eY => + OP1im <= IN1; + if(Conjugate='1')then -- + OP2im <= IN1; -- + else -- + OP2im <= IN2; -- modif 23/06/11 + end if; -- + CTRL <= ctrl_IDLE; + if(Take_reg='1' and Take='0')then + Read <= '0'; + ect <= e2; + end if; + + when e2 => + OP1 <= OP1im; + OP2 <= OP2im; + CTRL <= ctrl_MAC; + ect <= eZ; + + when eZ => + CTRL <= ctrl_IDLE; + go_st <= '1'; + if(Received_reg='0' and Received='1')then + if(Conjugate='1')then + ect <= eX; + else + ect <= e3; + end if; + end if; + + when e3 => + CTRL <= ctrl_CLRMAC; + go_st <= '0'; + ect <= e4; + + when e4 => + OP1 <= OP1im; + OP2 <= OP2re; + CTRL <= ctrl_MAC; + ect <= e5; + + when e5 => + OP1 <= OP1re; + OP2 <= OP2im; + COMP <= "10"; + ect <= eW; + + when eW => + CTRL <= ctrl_IDLE; + COMP <= "00"; + go_st <= '1'; + if(Received_reg='1' and Received='0')then + ect <= eX; + end if; + end case; +--------------------------------------------------------------------------------- + case st is + when e0 => + if(go_st='1')then + st <= e1; + end if; + + when e1 => + Valid <= '1'; + st <= e2; + + when e2 => + if(Received_reg='0' and Received='1')then + Valid <= '0'; + if(Conjugate='1')then + st <= eY; + else + st <= eX; + end if; + end if; + + when eX => + st <= e3; + + when e3 => + if(go_st='1')then + st <= e4; + end if; + + when e4 => + Valid <= '1'; + st <= e5; + + when e5 => + if(Received_reg='1' and Received='0')then + Valid <= '0'; + st <= eY; + end if; + + when eY => + st <= e0; + + when others => + null; + end case; + + end if; + end process; + end ar_ALU_Driver; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd --- a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd +++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd @@ -1,87 +1,87 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; ---library lpp; ---use lpp.lpp_matrix.all; - -entity MatriceSpectrale is - generic( - Input_SZ : integer := 16; - Result_SZ : integer := 32); - port( - clkm : in std_logic; - rstn : in std_logic; - - FifoIN_Full : in std_logic_vector(4 downto 0); - SetReUse : in std_logic_vector(4 downto 0); --- FifoOUT_Full : in std_logic_vector(1 downto 0); - Valid : in std_logic; - Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); - ACQ : in std_logic; - SM_Write : out std_logic; - FlagError : out std_logic; - Pong : out std_logic; - Statu : out std_logic_vector(3 downto 0); - Write : out std_logic_vector(1 downto 0); - Read : out std_logic_vector(4 downto 0); - ReUse : out std_logic_vector(4 downto 0); - Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) - ); -end entity; - - -architecture ar_MatriceSpectrale of MatriceSpectrale is - -signal Matrix_Write : std_logic; -signal Matrix_Read : std_logic_vector(1 downto 0); -signal Matrix_Result : std_logic_vector(31 downto 0); - -signal TopSM_Start : std_logic; -signal TopSM_Statu : std_logic_vector(3 downto 0); -signal TopSM_Data1 : std_logic_vector(15 downto 0); -signal TopSM_Data2 : std_logic_vector(15 downto 0); - -begin - - CTRL0 : entity work.ReUse_CTRLR - port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); - - - TopSM : entity work.TopSpecMatrix - generic map (Input_SZ) - port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); - - SM : entity work.SpectralMatrix - generic map (Input_SZ,Result_SZ) - port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); - - DISP : entity work.Dispatch - generic map(Result_SZ) - port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError); - -Statu <= TopSM_Statu; -SM_Write <= Matrix_Write; - -end architecture; - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_matrix.all; + +entity MatriceSpectrale is + generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); + port( + clkm : in std_logic; + rstn : in std_logic; + + FifoIN_Full : in std_logic_vector(4 downto 0); + SetReUse : in std_logic_vector(4 downto 0); +-- FifoOUT_Full : in std_logic_vector(1 downto 0); + Valid : in std_logic; + Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); + ACQ : in std_logic; + SM_Write : out std_logic; + FlagError : out std_logic; + Pong : out std_logic; + Statu : out std_logic_vector(3 downto 0); + Write : out std_logic_vector(1 downto 0); + Read : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) + ); +end entity; + + +architecture ar_MatriceSpectrale of MatriceSpectrale is + +signal Matrix_Write : std_logic; +signal Matrix_Read : std_logic_vector(1 downto 0); +signal Matrix_Result : std_logic_vector(31 downto 0); + +signal TopSM_Start : std_logic; +signal TopSM_Statu : std_logic_vector(3 downto 0); +signal TopSM_Data1 : std_logic_vector(15 downto 0); +signal TopSM_Data2 : std_logic_vector(15 downto 0); + +begin + + CTRL0 : ReUse_CTRLR + port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); + + + TopSM : TopSpecMatrix + generic map (Input_SZ) + port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); + + SM : SpectralMatrix + generic map (Input_SZ,Result_SZ) + port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); + + DISP : Dispatch + generic map(Result_SZ) + port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError); + +Statu <= TopSM_Statu; +SM_Write <= Matrix_Write; + +end architecture; + diff --git a/lib/lpp/lpp_matrix/SpectralMatrix.vhd b/lib/lpp/lpp_matrix/SpectralMatrix.vhd --- a/lib/lpp/lpp_matrix/SpectralMatrix.vhd +++ b/lib/lpp/lpp_matrix/SpectralMatrix.vhd @@ -1,84 +1,85 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -use lpp.lpp_matrix.all; - -entity SpectralMatrix is -generic( - Input_SZ : integer := 16; - Result_SZ : integer := 32); -port( - clk : in std_logic; - reset : in std_logic; - Start : in std_logic; - FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); - FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); - Statu : in std_logic_vector(3 downto 0); --- FullFIFO : in std_logic; - ReadFIFO : out std_logic_vector(1 downto 0); - WriteFIFO : out std_logic; - Result : out std_logic_vector(Result_SZ-1 downto 0) -); -end SpectralMatrix; - - -architecture ar_SpectralMatrix of SpectralMatrix is - -signal RaZ : std_logic; -signal Read_int : std_logic; -signal Take_int : std_logic; -signal Received_int : std_logic; -signal Valid_int : std_logic; -signal Conjugate_int : std_logic; - -signal Resultat : std_logic_vector(Result_SZ-1 downto 0); - - -begin - -RaZ <= reset and Start; - -IN1 : DriveInputs - port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO); - - -CALC0 : Matrix - generic map(Input_SZ) - port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat); - - -RES0 : GetResult - generic map(Result_SZ) - port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO - - -With Statu select - Conjugate_int <= '1' when "0001", - '1' when "0011", - '1' when "0110", - '1' when "1010", - '1' when "1111", - '0' when others; - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.lpp_matrix.all; + +entity SpectralMatrix is +generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); +port( + clk : in std_logic; + reset : in std_logic; + Start : in std_logic; + FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + Statu : in std_logic_vector(3 downto 0); +-- FullFIFO : in std_logic; + ReadFIFO : out std_logic_vector(1 downto 0); + WriteFIFO : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) +); +end SpectralMatrix; + + +architecture ar_SpectralMatrix of SpectralMatrix is + +signal RaZ : std_logic; +signal Read_int : std_logic; +signal Take_int : std_logic; +signal Received_int : std_logic; +signal Valid_int : std_logic; +signal Conjugate_int : std_logic; + +signal Resultat : std_logic_vector(Result_SZ-1 downto 0); + + +begin + +RaZ <= reset and Start; + +IN1 : DriveInputs + port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO); + + +CALC0 : Matrix + generic map(Input_SZ) + port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat); + + +RES0 : GetResult + generic map(Result_SZ) + port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO + + +With Statu select + Conjugate_int <= '1' when "0001", + '1' when "0011", + '1' when "0110", + '1' when "1010", + '1' when "1111", + '0' when others; + end ar_SpectralMatrix; \ No newline at end of file