##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

SVG Fichiers Simu
martin -
r189:1c5a43d81f5c martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,295
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34
35
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 --USE work.config.ALL;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 use lpp.lpp_demux.all;
46 use lpp.lpp_dma_pkg.all;
47 use lpp.lpp_Header.all;
48 use lpp.lpp_fft.all;
49 use lpp.lpp_matrix.all;
50
51
52 ENTITY TestBench IS
53 END;
54
55 ARCHITECTURE Behavioral OF TestBench IS
56
57
58 component TestModule_ADS7886 IS
59 GENERIC (
60 freq : INTEGER ;
61 amplitude : INTEGER ;
62 impulsion : INTEGER
63 );
64 PORT (
65 -- CONV --
66 cnv_run : IN STD_LOGIC;
67 cnv : IN STD_LOGIC;
68
69 -- DATA --
70 sck : IN STD_LOGIC;
71 sdo : OUT STD_LOGIC
72 );
73 END component;
74
75 SIGNAL clk49_152MHz : STD_LOGIC := '0';
76 SIGNAL clkm : STD_LOGIC := '0';
77 SIGNAL rstn : STD_LOGIC := '0';
78 SIGNAL coarse_time_0 : STD_LOGIC := '0';
79
80 -- -- ADC interface
81 -- SIGNAL bias_fail_sw : STD_LOGIC; -- OUT
82 -- SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
83 -- SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
84 -- SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
85
86 --
87 SIGNAL apbi : apb_slv_in_type;
88 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
89 SIGNAL ahbmi : ahb_mst_in_type;
90 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
91
92 -- -- internal
93 -- SIGNAL sample : Samples14v(7 DOWNTO 0);
94 -- SIGNAL sample_val : STD_LOGIC;
95
96 -- ACQ
97 signal CNV_CH1 : STD_LOGIC;
98 signal SCK_CH1 : STD_LOGIC;
99 signal SDO_CH1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
100 signal Bias_Fails : std_logic;
101 signal sample_val : STD_LOGIC;
102 signal sample : Samples(8-1 DOWNTO 0);
103
104 signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
106 signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
108 signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
110 -- FIFOs
111 signal FifoF0_Empty : std_logic_vector(4 downto 0);
112 signal FifoF0_Data : std_logic_vector(79 downto 0);
113 signal FifoF1_Empty : std_logic_vector(4 downto 0);
114 signal FifoF1_Data : std_logic_vector(79 downto 0);
115 signal FifoF3_Empty : std_logic_vector(4 downto 0);
116 signal FifoF3_Data : std_logic_vector(79 downto 0);
117 signal FifoINT_Full : std_logic_vector(4 downto 0);
118 signal FifoINT_Data : std_logic_vector(79 downto 0);
119 signal FifoOUT_Full : std_logic_vector(1 downto 0);
120 signal FifoOUT_Empty : std_logic_vector(1 downto 0);
121 signal FifoOUT_Data : std_logic_vector(63 downto 0);
122 -- MATRICE SPECTRALE
123 signal SM_FlagError : std_logic;
124 signal SM_Pong : std_logic;
125 signal SM_Wen : std_logic;
126 signal SM_Read : std_logic_vector(4 downto 0);
127 signal SM_Write : std_logic_vector(1 downto 0);
128 signal SM_ReUse : std_logic_vector(4 downto 0);
129 signal SM_Param : std_logic_vector(3 downto 0);
130 signal SM_Data : std_logic_vector(63 downto 0);
131 -- FFT
132 signal FFT_Load : std_logic;
133 signal FFT_Read : std_logic_vector(4 downto 0);
134 signal FFT_Write : std_logic_vector(4 downto 0);
135 signal FFT_ReUse : std_logic_vector(4 downto 0);
136 signal FFT_Data : std_logic_vector(79 downto 0);
137 -- DEMUX
138 signal DMUX_Read : std_logic_vector(14 downto 0);
139 signal DMUX_Empty : std_logic_vector(4 downto 0);
140 signal DMUX_Data : std_logic_vector(79 downto 0);
141 signal DMUX_WorkFreq : std_logic_vector(1 downto 0);
142 -- Header
143 signal Head_Read : std_logic_vector(1 downto 0);
144 signal Head_Data : std_logic_vector(31 downto 0);
145 signal Head_Empty : std_logic;
146 signal Head_Header : std_logic_vector(31 DOWNTO 0);
147 signal Head_Valid : std_logic;
148 signal Head_Val : std_logic;
149 --DMA
150 signal DMA_Read : std_logic;
151 signal DMA_ack : std_logic;
152 signal AHB_Master_In : AHB_Mst_In_Type;
153 signal AHB_Master_Out : AHB_Mst_Out_Type;
154
155
156 BEGIN
157
158 -----------------------------------------------------------------------------
159
160 -- MODULE_RHF1401: FOR I IN 0 TO 7 GENERATE
161 -- TestModule_RHF1401_1: TestModule_RHF1401
162 -- GENERIC MAP (
163 -- freq => 24*(I+1),
164 -- amplitude => 8000/(I+1),
165 -- impulsion => 0)
166 -- PORT MAP (
167 -- ADC_smpclk => ADC_smpclk,
168 -- ADC_OEB_bar => ADC_OEB_bar_CH(I),
169 -- ADC_data => ADC_data);
170 -- END GENERATE MODULE_RHF1401;
171
172 MODULE_ADS7886: FOR I IN 0 TO 7 GENERATE
173 TestModule_ADS7886_0 : TestModule_ADS7886
174 GENERIC MAP (
175 freq => 24*(I+1),
176 amplitude => 8000/(I+1),
177 impulsion => 0)
178 PORT MAP(
179 -- CONV --
180 cnv_run => '1',
181 cnv => CNV_CH1,
182 -- DATA --
183 sck => SCK_CH1,
184 sdo => SDO_CH1(I));
185 END GENERATE MODULE_ADS7886;
186
187
188 -----------------------------------------------------------------------------
189
190 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
191 clkm <= NOT clkm AFTER 20 ns; -- 25 MHz
192 coarse_time_0 <= NOT coarse_time_0 AFTER 100 ms;
193
194 -----------------------------------------------------------------------------
195 -- waveform generation
196 WaveGen_Proc : PROCESS
197 BEGIN
198 WAIT UNTIL clkm = '1';
199 apbi <= apb_slv_in_none;
200 rstn <= '0';
201 -- cnv_rstn <= '0';
202 -- run_cnv <= '0';
203 WAIT UNTIL clkm = '1';
204 WAIT UNTIL clkm = '1';
205 WAIT UNTIL clkm = '1';
206 rstn <= '1';
207 -- cnv_rstn <= '1';
208 WAIT UNTIL clkm = '1';
209 WAIT UNTIL clkm = '1';
210 WAIT UNTIL clkm = '1';
211
212 WAIT;
213
214 END PROCESS WaveGen_Proc;
215
216
217 ahbmi.HGRANT(2) <= '1';
218 ahbmi.HREADY <= '1';
219 ahbmi.HRESP <= HRESP_OKAY;
220
221
222
223 -------------------------------------------------------------------------------
224 -------------------------------------------------------------------------------
225 -- DUT ------------------------------------------------------------------------
226 -------------------------------------------------------------------------------
227 -------------------------------------------------------------------------------
228 ACQ0 : lpp_top_acq
229 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk49_152MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3);
230
231 Bias_Fails <= '0';
232 --- FIFO IN -------------------------------------------------------------
233
234 Memf0 : lppFIFOxN
235 generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
236 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
237
238 Memf1 : lppFIFOxN
239 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
240 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
241
242 Memf3 : lppFIFOxN
243 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
244 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
245
246 --- DEMUX -------------------------------------------------------------
247
248 DMUX0 : DEMUX
249 generic map(Data_sz => 16)
250 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data);
251
252 --- FFT -------------------------------------------------------------
253
254 FFT0 : FFT
255 generic map(Data_sz => 16,NbData => 256)
256 port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
257
258 ----- LINK MEMORY -------------------------------------------------------
259
260 MemInt : lppFIFOxN
261 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1')
262 port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
263
264 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
265
266 SM0 : MatriceSpectrale
267 generic map(Input_SZ => 16,Result_SZ => 32)
268 port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
269
270 MemOut : lppFIFOxN
271 generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0')
272 port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty);
273
274 ----- Header -------------------------------------------------------
275
276 Head0 : HeaderBuilder
277 generic map(Data_sz => 32)
278 port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
279
280 ----- DMA -------------------------------------------------------
281
282 DMA0 : lpp_dma
283 generic map(
284 tech =>inferred,
285 hindex => 2,
286 pindex => 9,
287 paddr => 9,
288 pmask => 16#fff#,
289 pirq => 0)
290 port map(clkm,rstn,apbi,apbo(9),AHB_Master_In,AHB_Master_Out,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
291
292 -------------------------------------------------------------------------------
293 -------------------------------------------------------------------------------
294
295 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,33
1
2
3 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd
4 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd
5 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
6 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actar.vhd
7 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actram.vhd
8 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftDp.vhd
9 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftSm.vhd
10 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fft_components.vhd
11 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
12 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/primitives.vhd
13 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/twiddle.vhd
14 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd
15
16 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd
17 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd
18 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd
19 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd
20 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd
21 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd
22 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd
23 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd
24 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd
25 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd
26 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd
27
28 vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_Header/HeaderBuilder.vhd
29
30 vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/TestModule_ADS7886.vhd
31 vcom -quiet -93 -work work TestBench.vhd
32
33 vsim work.testbench No newline at end of file
Show file before | Show file after | Hide comments
@@ -12,6 +12,7
12 12 ./lpp_cna
13 13 ./lpp_demux
14 14 ./lpp_dma
15 ./lpp_Header
15 16 ./lpp_matrix
16 17 ./lpp_memory
17 18 ./lpp_top_lfr
Show file before | Show file after | Hide comments
@@ -1,94 +1,95
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.fft_components.all;
26 use lpp.lpp_fft.all;
27
28 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau"
29
30 entity FFT is
31 generic(
32 Data_sz : integer := 16;
33 NbData : integer := 256);
34 port(
35 clkm : in std_logic;
36 rstn : in std_logic;
37 FifoIN_Empty : in std_logic_vector(4 downto 0);
38 FifoIN_Data : in std_logic_vector(79 downto 0);
39 FifoOUT_Full : in std_logic_vector(4 downto 0);
40 Load : out std_logic;
41 Read : out std_logic_vector(4 downto 0);
42 Write : out std_logic_vector(4 downto 0);
43 ReUse : out std_logic_vector(4 downto 0);
44 Data : out std_logic_vector(79 downto 0)
45 );
46 end entity;
47
48
49 architecture ar_FFT of FFT is
50
51 signal Drive_Write : std_logic;
52 signal Drive_DataRE : std_logic_vector(15 downto 0);
53 signal Drive_DataIM : std_logic_vector(15 downto 0);
54
55 signal Start : std_logic;
56 signal FFT_Load : std_logic;
57 signal FFT_Ready : std_logic;
58 signal FFT_Valid : std_logic;
59 signal FFT_DataRE : std_logic_vector(15 downto 0);
60 signal FFT_DataIM : std_logic_vector(15 downto 0);
61
62 signal Link_Read : std_logic;
63
64 begin
65
66 Start <= '0';
67 Load <= FFT_Load;
68
69 DRIVE : Driver_FFT
70 generic map(Data_sz,NbData)
71 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
72
73 FFT0 : CoreFFT
74 generic map(
75 LOGPTS => gLOGPTS,
76 LOGLOGPTS => gLOGLOGPTS,
77 WSIZE => gWSIZE,
78 TWIDTH => gTWIDTH,
79 DWIDTH => gDWIDTH,
80 TDWIDTH => gTDWIDTH,
81 RND_MODE => gRND_MODE,
82 SCALE_MODE => gSCALE_MODE,
83 PTS => gPTS,
84 HALFPTS => gHALFPTS,
85 inBuf_RWDLY => gInBuf_RWDLY)
86 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
87
88
89 LINK : Linker_FFT
90 generic map(Data_sz,NbData)
91 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
92
93
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_fft.all;
27 use lpp.fft_components.all;
28
29 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau"
30
31 entity FFT is
32 generic(
33 Data_sz : integer := 16;
34 NbData : integer := 256);
35 port(
36 clkm : in std_logic;
37 rstn : in std_logic;
38 FifoIN_Empty : in std_logic_vector(4 downto 0);
39 FifoIN_Data : in std_logic_vector(79 downto 0);
40 FifoOUT_Full : in std_logic_vector(4 downto 0);
41 Load : out std_logic;
42 Read : out std_logic_vector(4 downto 0);
43 Write : out std_logic_vector(4 downto 0);
44 ReUse : out std_logic_vector(4 downto 0);
45 Data : out std_logic_vector(79 downto 0)
46 );
47 end entity;
48
49
50 architecture ar_FFT of FFT is
51
52 signal Drive_Write : std_logic;
53 signal Drive_DataRE : std_logic_vector(15 downto 0);
54 signal Drive_DataIM : std_logic_vector(15 downto 0);
55
56 signal Start : std_logic;
57 signal FFT_Load : std_logic;
58 signal FFT_Ready : std_logic;
59 signal FFT_Valid : std_logic;
60 signal FFT_DataRE : std_logic_vector(15 downto 0);
61 signal FFT_DataIM : std_logic_vector(15 downto 0);
62
63 signal Link_Read : std_logic;
64
65 begin
66
67 Start <= '0';
68 Load <= FFT_Load;
69
70 DRIVE : Driver_FFT
71 generic map(Data_sz,NbData)
72 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
73
74 FFT0 : CoreFFT
75 generic map(
76 LOGPTS => gLOGPTS,
77 LOGLOGPTS => gLOGLOGPTS,
78 WSIZE => gWSIZE,
79 TWIDTH => gTWIDTH,
80 DWIDTH => gDWIDTH,
81 TDWIDTH => gTDWIDTH,
82 RND_MODE => gRND_MODE,
83 SCALE_MODE => gSCALE_MODE,
84 PTS => gPTS,
85 HALFPTS => gHALFPTS,
86 inBuf_RWDLY => gInBuf_RWDLY)
87 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
88
89
90 LINK : Linker_FFT
91 generic map(Data_sz,NbData)
92 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
93
94
94 95 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,72 +1,73
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
26
27 --! Programme qui va permettre de gοΏ½nοΏ½rer des flags utilisοΏ½s au niveau du driver C
28
29 entity Flag_Extremum is
30 port(
31 clk,raz : in std_logic; --! Horloge et Reset gοΏ½nοΏ½ral du composant
32 load : in std_logic; --! Signal en provenance de CoreFFT
33 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
34 fill : out std_logic; --! Flag, Va permettre d'autoriser l'οΏ½criture (Driver C)
35 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
36 );
37 end Flag_Extremum;
38
39 --! @details Flags gοΏ½nοΏ½rοΏ½s a partir de signaux fourni par l'IP FFT d'actel
40
41 architecture ar_Flag_Extremum of Flag_Extremum is
42
43 begin
44 process (clk,raz)
45 begin
46 if(raz='0')then
47 fill <= '0';
48 ready <= '0';
49
50 elsif(clk' event and clk='1')then
51
52 if(load='1' and y_rdy='0')then
53 fill <= '1';
54 ready <= '0';
55
56 elsif(y_rdy='1')then
57 fill <= '0';
58 ready <= '1';
59
60 else
61 fill <= '0';
62 ready <= '0';
63
64 end if;
65 end if;
66 end process;
67
68 end ar_Flag_Extremum;
69
70
71
72
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.FFT_config.all;
27
28 --! Programme qui va permettre de gοΏ½nοΏ½rer des flags utilisοΏ½s au niveau du driver C
29
30 entity Flag_Extremum is
31 port(
32 clk,raz : in std_logic; --! Horloge et Reset gοΏ½nοΏ½ral du composant
33 load : in std_logic; --! Signal en provenance de CoreFFT
34 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
35 fill : out std_logic; --! Flag, Va permettre d'autoriser l'οΏ½criture (Driver C)
36 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
37 );
38 end Flag_Extremum;
39
40 --! @details Flags gοΏ½nοΏ½rοΏ½s a partir de signaux fourni par l'IP FFT d'actel
41
42 architecture ar_Flag_Extremum of Flag_Extremum is
43
44 begin
45 process (clk,raz)
46 begin
47 if(raz='0')then
48 fill <= '0';
49 ready <= '0';
50
51 elsif(clk' event and clk='1')then
52
53 if(load='1' and y_rdy='0')then
54 fill <= '1';
55 ready <= '0';
56
57 elsif(y_rdy='1')then
58 fill <= '0';
59 ready <= '1';
60
61 else
62 fill <= '0';
63 ready <= '0';
64
65 end if;
66 end if;
67 end process;
68
69 end ar_Flag_Extremum;
70
71
72
73
Show file before | Show file after | Hide comments
@@ -43,9 +43,9 entity HeaderBuilder is
43 43 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
44 44 emptyOUT : out std_logic;
45 45 RenIN : in std_logic;
46
47 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
48 header_val : out std_logic;
46
47 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
48 header_val : out std_logic;
49 49 header_ack : in std_logic
50 50 );
51 51 end entity;
@@ -101,6 +101,7 Matrix_Param <= std_logic_vector(to_unsi
101 101
102 102 header(1 downto 0) <= Matrix_Type;
103 103 header(5 downto 2) <= Matrix_Param;
104 header(31 downto 6) <= (others => '0');
104 105
105 106 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
106 107 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (704 lines changed) Show them Hide them
@@ -1,352 +1,352
1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
36 LIBRARY lpp;
37 USE lpp.lpp_amba.ALL;
38 USE lpp.apb_devices_list.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_dma_pkg.ALL;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
43
44
45 ENTITY lpp_dma_ip IS
46 GENERIC (
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
49 );
50 PORT (
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
59 -- fifo interface
60 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 fifo_empty : IN STD_LOGIC;
62 fifo_ren : OUT STD_LOGIC;
63
64 -- header
65 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 header_val : IN STD_LOGIC;
67 header_ack : OUT STD_LOGIC;
68
69 -- Reg out
70 ready_matrix_f0_0 : OUT STD_LOGIC;
71 ready_matrix_f0_1 : OUT STD_LOGIC;
72 ready_matrix_f1 : OUT STD_LOGIC;
73 ready_matrix_f2 : OUT STD_LOGIC;
74 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 error_bad_component_error : OUT STD_LOGIC;
76 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77
78 -- Reg In
79 status_ready_matrix_f0_0 :IN STD_LOGIC;
80 status_ready_matrix_f0_1 :IN STD_LOGIC;
81 status_ready_matrix_f1 :IN STD_LOGIC;
82 status_ready_matrix_f2 :IN STD_LOGIC;
83 status_error_anticipating_empty_fifo :IN STD_LOGIC;
84 status_error_bad_component_error :IN STD_LOGIC;
85
86 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 config_active_interruption_onError : IN STD_LOGIC;
88 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 );
93 END;
94
95 ARCHITECTURE Behavioral OF lpp_dma_ip IS
96 -----------------------------------------------------------------------------
97 SIGNAL DMAIn : DMA_In_Type;
98 SIGNAL header_dmai : DMA_In_Type;
99 SIGNAL component_dmai : DMA_In_Type;
100 SIGNAL DMAOut : DMA_OUt_Type;
101 -----------------------------------------------------------------------------
102
103 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
105 TYPE state_DMAWriteBurst IS (IDLE,
106 TRASH_FIFO,
107 WAIT_HEADER_ACK,
108 SEND_DATA,
109 WAIT_DATA_ACK,
110 CHECK_LENGTH
111 );
112 SIGNAL state : state_DMAWriteBurst := IDLE;
113
114 SIGNAL nbSend : INTEGER;
115 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL header_check_ok : STD_LOGIC;
119 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL send_matrix : STD_LOGIC;
121 SIGNAL request : STD_LOGIC;
122 SIGNAL remaining_data_request : INTEGER;
123 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
126 SIGNAL header_select : STD_LOGIC;
127
128 SIGNAL header_send : STD_LOGIC;
129 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL header_send_ok : STD_LOGIC;
131 SIGNAL header_send_ko : STD_LOGIC;
132
133 SIGNAL component_send : STD_LOGIC;
134 SIGNAL component_send_ok : STD_LOGIC;
135 SIGNAL component_send_ko : STD_LOGIC;
136 -----------------------------------------------------------------------------
137 SIGNAL fifo_ren_trash : STD_LOGIC;
138 SIGNAL component_fifo_ren : STD_LOGIC;
139
140 -----------------------------------------------------------------------------
141 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
142
143 BEGIN
144
145 -----------------------------------------------------------------------------
146 -- DMA to AHB interface
147 -----------------------------------------------------------------------------
148
149 DMA2AHB_1 : DMA2AHB
150 GENERIC MAP (
151 hindex => hindex,
152 vendorid => VENDOR_LPP,
153 deviceid => 0,
154 version => 0,
155 syncrst => 1,
156 boundary => 1) -- FIX 11/01/2013
157 PORT MAP (
158 HCLK => HCLK,
159 HRESETn => HRESETn,
160 DMAIn => DMAIn,
161 DMAOut => DMAOut,
162 AHBIn => AHB_Master_In,
163 AHBOut => AHB_Master_Out);
164
165 debug_reg <= debug_reg_s;
166
167 debug_info: PROCESS (HCLK, HRESETn)
168 BEGIN -- PROCESS debug_info
169 IF HRESETn = '0' THEN -- asynchronous reset (active low)
170 debug_reg <= (OTHERS => '0');
171 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
172 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
173 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
174 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
175 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
176 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
177 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
178 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
179
180 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
181 END IF;
182 END PROCESS debug_info;
183
184
185 matrix_type <= header(1 DOWNTO 0);
186 component_type <= header(5 DOWNTO 2);
187
188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
190 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
192 '0';
193
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE
195 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
196 '1' WHEN component_type = component_type_pre + "0001" ELSE
197 '0';
198
199 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
200 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
201 addr_matrix_f1 WHEN matrix_type = "10" ELSE
202 addr_matrix_f2 WHEN matrix_type = "11" ELSE
203 (OTHERS => '0');
204
205 -----------------------------------------------------------------------------
206 -- DMA control
207 -----------------------------------------------------------------------------
208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
209 BEGIN -- PROCESS DMAWriteBurst_p
210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
211 state <= IDLE;
212 header_ack <= '0';
213 ready_matrix_f0_0 <= '0';
214 ready_matrix_f0_1 <= '0';
215 ready_matrix_f1 <= '0';
216 ready_matrix_f2 <= '0';
217 error_anticipating_empty_fifo <= '0';
218 error_bad_component_error <= '0';
219 component_type_pre <= "1110";
220 fifo_ren_trash <= '1';
221 component_send <= '0';
222 address <= (OTHERS => '0');
223 header_select <= '0';
224 header_send <= '0';
225 header_data <= (OTHERS => '0');
226 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
227
228 CASE state IS
229 WHEN IDLE =>
230 ready_matrix_f0_0 <= '0';
231 ready_matrix_f0_1 <= '0';
232 ready_matrix_f1 <= '0';
233 ready_matrix_f2 <= '0';
234 error_bad_component_error <= '0';
235 header_select <= '1';
236 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
237 IF header_check_ok = '1' THEN
238 header_data <= header;
239 component_type_pre <= header(5 DOWNTO 2);
240 header_ack <= '1';
241 --
242 header_send <= '1';
243 IF component_type = "0000" THEN
244 address <= address_matrix;
245 END IF;
246 header_data <= header;
247 --
248 state <= WAIT_HEADER_ACK;
249 ELSE
250 error_bad_component_error <= '1';
251 component_type_pre <= "1110";
252 header_ack <= '1';
253 state <= TRASH_FIFO;
254 END IF;
255 END IF;
256
257 WHEN TRASH_FIFO =>
258 error_bad_component_error <= '0';
259 error_anticipating_empty_fifo <= '0';
260 IF fifo_empty = '1' THEN
261 state <= IDLE;
262 fifo_ren_trash <= '1';
263 ELSE
264 fifo_ren_trash <= '0';
265 END IF;
266
267 WHEN WAIT_HEADER_ACK =>
268 header_send <= '0';
269 IF header_send_ko = '1' THEN
270 state <= TRASH_FIFO;
271 error_anticipating_empty_fifo <= '1';
272 -- TODO : error sending header
273 ELSIF header_send_ok = '1' THEN
274 header_select <= '0';
275 state <= SEND_DATA;
276 address <= address + 4;
277 END IF;
278
279 WHEN SEND_DATA =>
280 IF fifo_empty = '1' THEN
281 state <= IDLE;
282 IF component_type = "1110" THEN
283 CASE matrix_type IS
284 WHEN "00" => ready_matrix_f0_0 <= '1';
285 WHEN "01" => ready_matrix_f0_1 <= '1';
286 WHEN "10" => ready_matrix_f1 <= '1';
287 WHEN "11" => ready_matrix_f2 <= '1';
288 WHEN OTHERS => NULL;
289 END CASE;
290 END IF;
291 ELSE
292 component_send <= '1';
293 address <= address;
294 state <= WAIT_DATA_ACK;
295 END IF;
296
297 WHEN WAIT_DATA_ACK =>
298 component_send <= '0';
299 IF component_send_ok = '1' THEN
300 address <= address + 64;
301 state <= SEND_DATA;
302 ELSIF component_send_ko = '1' THEN
303 error_anticipating_empty_fifo <= '0';
304 state <= TRASH_FIFO;
305 END IF;
306
307 WHEN CHECK_LENGTH =>
308 state <= IDLE;
309 WHEN OTHERS => NULL;
310 END CASE;
311
312 END IF;
313 END PROCESS DMAWriteFSM_p;
314
315 -----------------------------------------------------------------------------
316 -- SEND 1 word by DMA
317 -----------------------------------------------------------------------------
318 lpp_dma_send_1word_1 : lpp_dma_send_1word
319 PORT MAP (
320 HCLK => HCLK,
321 HRESETn => HRESETn,
322 DMAIn => header_dmai,
323 DMAOut => DMAOut,
324
325 send => header_send,
326 address => address,
327 data => header_data,
328 send_ok => header_send_ok,
329 send_ko => header_send_ko
330 );
331
332 -----------------------------------------------------------------------------
333 -- SEND 16 word by DMA (in burst mode)
334 -----------------------------------------------------------------------------
335 lpp_dma_send_16word_1 : lpp_dma_send_16word
336 PORT MAP (
337 HCLK => HCLK,
338 HRESETn => HRESETn,
339 DMAIn => component_dmai,
340 DMAOut => DMAOut,
341
342 send => component_send,
343 address => address,
344 data => fifo_data,
345 ren => component_fifo_ren,
346 send_ok => component_send_ok,
347 send_ko => component_send_ko);
348
349 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
350 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
351
352 END Behavioral;
1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
36 LIBRARY lpp;
37 USE lpp.lpp_amba.ALL;
38 USE lpp.apb_devices_list.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_dma_pkg.ALL;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
43
44
45 ENTITY lpp_dma_ip IS
46 GENERIC (
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
49 );
50 PORT (
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
59 -- fifo interface
60 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 fifo_empty : IN STD_LOGIC;
62 fifo_ren : OUT STD_LOGIC;
63
64 -- header
65 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 header_val : IN STD_LOGIC;
67 header_ack : OUT STD_LOGIC;
68
69 -- Reg out
70 ready_matrix_f0_0 : OUT STD_LOGIC;
71 ready_matrix_f0_1 : OUT STD_LOGIC;
72 ready_matrix_f1 : OUT STD_LOGIC;
73 ready_matrix_f2 : OUT STD_LOGIC;
74 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 error_bad_component_error : OUT STD_LOGIC;
76 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77
78 -- Reg In
79 status_ready_matrix_f0_0 :IN STD_LOGIC;
80 status_ready_matrix_f0_1 :IN STD_LOGIC;
81 status_ready_matrix_f1 :IN STD_LOGIC;
82 status_ready_matrix_f2 :IN STD_LOGIC;
83 status_error_anticipating_empty_fifo :IN STD_LOGIC;
84 status_error_bad_component_error :IN STD_LOGIC;
85
86 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 config_active_interruption_onError : IN STD_LOGIC;
88 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 );
93 END;
94
95 ARCHITECTURE Behavioral OF lpp_dma_ip IS
96 -----------------------------------------------------------------------------
97 SIGNAL DMAIn : DMA_In_Type;
98 SIGNAL header_dmai : DMA_In_Type;
99 SIGNAL component_dmai : DMA_In_Type;
100 SIGNAL DMAOut : DMA_OUt_Type;
101 -----------------------------------------------------------------------------
102
103 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
105 TYPE state_DMAWriteBurst IS (IDLE,
106 TRASH_FIFO,
107 WAIT_HEADER_ACK,
108 SEND_DATA,
109 WAIT_DATA_ACK,
110 CHECK_LENGTH
111 );
112 SIGNAL state : state_DMAWriteBurst := IDLE;
113
114 SIGNAL nbSend : INTEGER;
115 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL header_check_ok : STD_LOGIC;
119 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL send_matrix : STD_LOGIC;
121 SIGNAL request : STD_LOGIC;
122 SIGNAL remaining_data_request : INTEGER;
123 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
126 SIGNAL header_select : STD_LOGIC;
127
128 SIGNAL header_send : STD_LOGIC;
129 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL header_send_ok : STD_LOGIC;
131 SIGNAL header_send_ko : STD_LOGIC;
132
133 SIGNAL component_send : STD_LOGIC;
134 SIGNAL component_send_ok : STD_LOGIC;
135 SIGNAL component_send_ko : STD_LOGIC;
136 -----------------------------------------------------------------------------
137 SIGNAL fifo_ren_trash : STD_LOGIC;
138 SIGNAL component_fifo_ren : STD_LOGIC;
139
140 -----------------------------------------------------------------------------
141 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
142
143 BEGIN
144
145 -----------------------------------------------------------------------------
146 -- DMA to AHB interface
147 -----------------------------------------------------------------------------
148
149 DMA2AHB_1 : DMA2AHB
150 GENERIC MAP (
151 hindex => hindex,
152 vendorid => VENDOR_LPP,
153 deviceid => 0,
154 version => 0,
155 syncrst => 1,
156 boundary => 1) -- FIX 11/01/2013
157 PORT MAP (
158 HCLK => HCLK,
159 HRESETn => HRESETn,
160 DMAIn => DMAIn,
161 DMAOut => DMAOut,
162 AHBIn => AHB_Master_In,
163 AHBOut => AHB_Master_Out);
164
165 debug_reg <= debug_reg_s;
166
167 debug_info: PROCESS (HCLK, HRESETn)
168 BEGIN -- PROCESS debug_info
169 IF HRESETn = '0' THEN -- asynchronous reset (active low)
170 debug_reg_s <= (OTHERS => '0');
171 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
172 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
173 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
174 IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF;
175 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
176 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
177 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
178 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
179
180 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
181 END IF;
182 END PROCESS debug_info;
183
184
185 matrix_type <= header(1 DOWNTO 0);
186 component_type <= header(5 DOWNTO 2);
187
188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
190 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
192 '0';
193
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE
195 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
196 '1' WHEN component_type = component_type_pre + "0001" ELSE
197 '0';
198
199 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
200 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
201 addr_matrix_f1 WHEN matrix_type = "10" ELSE
202 addr_matrix_f2 WHEN matrix_type = "11" ELSE
203 (OTHERS => '0');
204
205 -----------------------------------------------------------------------------
206 -- DMA control
207 -----------------------------------------------------------------------------
208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
209 BEGIN -- PROCESS DMAWriteBurst_p
210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
211 state <= IDLE;
212 header_ack <= '0';
213 ready_matrix_f0_0 <= '0';
214 ready_matrix_f0_1 <= '0';
215 ready_matrix_f1 <= '0';
216 ready_matrix_f2 <= '0';
217 error_anticipating_empty_fifo <= '0';
218 error_bad_component_error <= '0';
219 component_type_pre <= "1110";
220 fifo_ren_trash <= '1';
221 component_send <= '0';
222 address <= (OTHERS => '0');
223 header_select <= '0';
224 header_send <= '0';
225 header_data <= (OTHERS => '0');
226 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
227
228 CASE state IS
229 WHEN IDLE =>
230 ready_matrix_f0_0 <= '0';
231 ready_matrix_f0_1 <= '0';
232 ready_matrix_f1 <= '0';
233 ready_matrix_f2 <= '0';
234 error_bad_component_error <= '0';
235 header_select <= '1';
236 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
237 IF header_check_ok = '1' THEN
238 header_data <= header;
239 component_type_pre <= header(5 DOWNTO 2);
240 header_ack <= '1';
241 --
242 header_send <= '1';
243 IF component_type = "0000" THEN
244 address <= address_matrix;
245 END IF;
246 header_data <= header;
247 --
248 state <= WAIT_HEADER_ACK;
249 ELSE
250 error_bad_component_error <= '1';
251 component_type_pre <= "1110";
252 header_ack <= '1';
253 state <= TRASH_FIFO;
254 END IF;
255 END IF;
256
257 WHEN TRASH_FIFO =>
258 error_bad_component_error <= '0';
259 error_anticipating_empty_fifo <= '0';
260 IF fifo_empty = '1' THEN
261 state <= IDLE;
262 fifo_ren_trash <= '1';
263 ELSE
264 fifo_ren_trash <= '0';
265 END IF;
266
267 WHEN WAIT_HEADER_ACK =>
268 header_send <= '0';
269 IF header_send_ko = '1' THEN
270 state <= TRASH_FIFO;
271 error_anticipating_empty_fifo <= '1';
272 -- TODO : error sending header
273 ELSIF header_send_ok = '1' THEN
274 header_select <= '0';
275 state <= SEND_DATA;
276 address <= address + 4;
277 END IF;
278
279 WHEN SEND_DATA =>
280 IF fifo_empty = '1' THEN
281 state <= IDLE;
282 IF component_type = "1110" THEN
283 CASE matrix_type IS
284 WHEN "00" => ready_matrix_f0_0 <= '1';
285 WHEN "01" => ready_matrix_f0_1 <= '1';
286 WHEN "10" => ready_matrix_f1 <= '1';
287 WHEN "11" => ready_matrix_f2 <= '1';
288 WHEN OTHERS => NULL;
289 END CASE;
290 END IF;
291 ELSE
292 component_send <= '1';
293 address <= address;
294 state <= WAIT_DATA_ACK;
295 END IF;
296
297 WHEN WAIT_DATA_ACK =>
298 component_send <= '0';
299 IF component_send_ok = '1' THEN
300 address <= address + 64;
301 state <= SEND_DATA;
302 ELSIF component_send_ko = '1' THEN
303 error_anticipating_empty_fifo <= '0';
304 state <= TRASH_FIFO;
305 END IF;
306
307 WHEN CHECK_LENGTH =>
308 state <= IDLE;
309 WHEN OTHERS => NULL;
310 END CASE;
311
312 END IF;
313 END PROCESS DMAWriteFSM_p;
314
315 -----------------------------------------------------------------------------
316 -- SEND 1 word by DMA
317 -----------------------------------------------------------------------------
318 lpp_dma_send_1word_1 : lpp_dma_send_1word
319 PORT MAP (
320 HCLK => HCLK,
321 HRESETn => HRESETn,
322 DMAIn => header_dmai,
323 DMAOut => DMAOut,
324
325 send => header_send,
326 address => address,
327 data => header_data,
328 send_ok => header_send_ok,
329 send_ko => header_send_ko
330 );
331
332 -----------------------------------------------------------------------------
333 -- SEND 16 word by DMA (in burst mode)
334 -----------------------------------------------------------------------------
335 lpp_dma_send_16word_1 : lpp_dma_send_16word
336 PORT MAP (
337 HCLK => HCLK,
338 HRESETn => HRESETn,
339 DMAIn => component_dmai,
340 DMAOut => DMAOut,
341
342 send => component_send,
343 address => address,
344 data => fifo_data,
345 ren => component_fifo_ren,
346 send_ok => component_send_ok,
347 send_ko => component_send_ko);
348
349 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
350 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
351
352 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,216 +1,217
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.general_purpose.all;
26
27 --! Driver de l'ALU
28
29 entity ALU_Driver is
30 generic(
31 Input_SZ_1 : integer := 16;
32 Input_SZ_2 : integer := 16);
33 port(
34 clk : in std_logic; --! Horloge du composant
35 reset : in std_logic; --! Reset general du composant
36 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
37 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
38 Take : in std_logic; --! Flag, opοΏ½rande rοΏ½cupοΏ½rοΏ½
39 Received : in std_logic; --! Flag, RοΏ½sultat bien ressu
40 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjuguοΏ½
41 Valid : out std_logic; --! Flag, RοΏ½sultat disponible
42 Read : out std_logic; --! Flag, opοΏ½rande disponible
43 CTRL : out std_logic_vector(2 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e
44 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de complοΏ½menter les opοΏ½randes
45 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande
46 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second OpοΏ½rande
47 );
48 end ALU_Driver;
49
50 --! @details Les opοΏ½randes sont issue des donnοΏ½es d'entrοΏ½es et associοΏ½ aux bonnes valeurs sur CTRL, les diffοΏ½rentes opοΏ½rations sont effectuοΏ½es
51
52 architecture ar_ALU_Driver of ALU_Driver is
53
54 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
55 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
56 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
57 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
58
59 signal go_st : std_logic;
60 signal Take_reg : std_logic;
61 signal Received_reg : std_logic;
62
63 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
64 signal ect : etat;
65 signal st : etat;
66
67 begin
68 process(clk,reset)
69 begin
70
71 if(reset='0')then
72 ect <= eX;
73 st <= e0;
74 go_st <= '0';
75 CTRL <= ctrl_CLRMAC;
76 COMP <= "00"; -- pas de complement
77 Read <= '0';
78 Valid <= '0';
79 Take_reg <= '0';
80 Received_reg <= '0';
81
82 elsif(clk'event and clk='1')then
83 Take_reg <= Take;
84 Received_reg <= Received;
85
86 case ect is
87 when eX =>
88 go_st <= '0';
89 Read <= '1';
90 CTRL <= ctrl_CLRMAC;
91 ect <= e0;
92
93 when e0 =>
94 OP1re <= IN1;
95 if(Conjugate='1')then --
96 OP2re <= IN1; --
97 else --
98 OP2re <= IN2; -- modif 23/06/11
99 end if; --
100 if(Take_reg='0' and Take='1')then
101 read <= '0';
102 ect <= e1;
103 end if;
104
105 when e1 =>
106 OP1 <= OP1re;
107 OP2 <= OP2re;
108 CTRL <= ctrl_MAC;
109 Read <= '1';
110 ect <= eY;
111
112 when eY =>
113 OP1im <= IN1;
114 if(Conjugate='1')then --
115 OP2im <= IN1; --
116 else --
117 OP2im <= IN2; -- modif 23/06/11
118 end if; --
119 CTRL <= ctrl_IDLE;
120 if(Take_reg='1' and Take='0')then
121 Read <= '0';
122 ect <= e2;
123 end if;
124
125 when e2 =>
126 OP1 <= OP1im;
127 OP2 <= OP2im;
128 CTRL <= ctrl_MAC;
129 ect <= eZ;
130
131 when eZ =>
132 CTRL <= ctrl_IDLE;
133 go_st <= '1';
134 if(Received_reg='0' and Received='1')then
135 if(Conjugate='1')then
136 ect <= eX;
137 else
138 ect <= e3;
139 end if;
140 end if;
141
142 when e3 =>
143 CTRL <= ctrl_CLRMAC;
144 go_st <= '0';
145 ect <= e4;
146
147 when e4 =>
148 OP1 <= OP1im;
149 OP2 <= OP2re;
150 CTRL <= ctrl_MAC;
151 ect <= e5;
152
153 when e5 =>
154 OP1 <= OP1re;
155 OP2 <= OP2im;
156 COMP <= "10";
157 ect <= eW;
158
159 when eW =>
160 CTRL <= ctrl_IDLE;
161 COMP <= "00";
162 go_st <= '1';
163 if(Received_reg='1' and Received='0')then
164 ect <= eX;
165 end if;
166 end case;
167 ---------------------------------------------------------------------------------
168 case st is
169 when e0 =>
170 if(go_st='1')then
171 st <= e1;
172 end if;
173
174 when e1 =>
175 Valid <= '1';
176 st <= e2;
177
178 when e2 =>
179 if(Received_reg='0' and Received='1')then
180 Valid <= '0';
181 if(Conjugate='1')then
182 st <= eY;
183 else
184 st <= eX;
185 end if;
186 end if;
187
188 when eX =>
189 st <= e3;
190
191 when e3 =>
192 if(go_st='1')then
193 st <= e4;
194 end if;
195
196 when e4 =>
197 Valid <= '1';
198 st <= e5;
199
200 when e5 =>
201 if(Received_reg='1' and Received='0')then
202 Valid <= '0';
203 st <= eY;
204 end if;
205
206 when eY =>
207 st <= e0;
208
209 when others =>
210 null;
211 end case;
212
213 end if;
214 end process;
215
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28 --! Driver de l'ALU
29
30 entity ALU_Driver is
31 generic(
32 Input_SZ_1 : integer := 16;
33 Input_SZ_2 : integer := 16);
34 port(
35 clk : in std_logic; --! Horloge du composant
36 reset : in std_logic; --! Reset general du composant
37 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
38 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
39 Take : in std_logic; --! Flag, opοΏ½rande rοΏ½cupοΏ½rοΏ½
40 Received : in std_logic; --! Flag, RοΏ½sultat bien ressu
41 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjuguοΏ½
42 Valid : out std_logic; --! Flag, RοΏ½sultat disponible
43 Read : out std_logic; --! Flag, opοΏ½rande disponible
44 CTRL : out std_logic_vector(2 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e
45 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de complοΏ½menter les opοΏ½randes
46 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande
47 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second OpοΏ½rande
48 );
49 end ALU_Driver;
50
51 --! @details Les opοΏ½randes sont issue des donnοΏ½es d'entrοΏ½es et associοΏ½ aux bonnes valeurs sur CTRL, les diffοΏ½rentes opοΏ½rations sont effectuοΏ½es
52
53 architecture ar_ALU_Driver of ALU_Driver is
54
55 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
56 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
57 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
58 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
59
60 signal go_st : std_logic;
61 signal Take_reg : std_logic;
62 signal Received_reg : std_logic;
63
64 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
65 signal ect : etat;
66 signal st : etat;
67
68 begin
69 process(clk,reset)
70 begin
71
72 if(reset='0')then
73 ect <= eX;
74 st <= e0;
75 go_st <= '0';
76 CTRL <= ctrl_CLRMAC;
77 COMP <= "00"; -- pas de complement
78 Read <= '0';
79 Valid <= '0';
80 Take_reg <= '0';
81 Received_reg <= '0';
82
83 elsif(clk'event and clk='1')then
84 Take_reg <= Take;
85 Received_reg <= Received;
86
87 case ect is
88 when eX =>
89 go_st <= '0';
90 Read <= '1';
91 CTRL <= ctrl_CLRMAC;
92 ect <= e0;
93
94 when e0 =>
95 OP1re <= IN1;
96 if(Conjugate='1')then --
97 OP2re <= IN1; --
98 else --
99 OP2re <= IN2; -- modif 23/06/11
100 end if; --
101 if(Take_reg='0' and Take='1')then
102 read <= '0';
103 ect <= e1;
104 end if;
105
106 when e1 =>
107 OP1 <= OP1re;
108 OP2 <= OP2re;
109 CTRL <= ctrl_MAC;
110 Read <= '1';
111 ect <= eY;
112
113 when eY =>
114 OP1im <= IN1;
115 if(Conjugate='1')then --
116 OP2im <= IN1; --
117 else --
118 OP2im <= IN2; -- modif 23/06/11
119 end if; --
120 CTRL <= ctrl_IDLE;
121 if(Take_reg='1' and Take='0')then
122 Read <= '0';
123 ect <= e2;
124 end if;
125
126 when e2 =>
127 OP1 <= OP1im;
128 OP2 <= OP2im;
129 CTRL <= ctrl_MAC;
130 ect <= eZ;
131
132 when eZ =>
133 CTRL <= ctrl_IDLE;
134 go_st <= '1';
135 if(Received_reg='0' and Received='1')then
136 if(Conjugate='1')then
137 ect <= eX;
138 else
139 ect <= e3;
140 end if;
141 end if;
142
143 when e3 =>
144 CTRL <= ctrl_CLRMAC;
145 go_st <= '0';
146 ect <= e4;
147
148 when e4 =>
149 OP1 <= OP1im;
150 OP2 <= OP2re;
151 CTRL <= ctrl_MAC;
152 ect <= e5;
153
154 when e5 =>
155 OP1 <= OP1re;
156 OP2 <= OP2im;
157 COMP <= "10";
158 ect <= eW;
159
160 when eW =>
161 CTRL <= ctrl_IDLE;
162 COMP <= "00";
163 go_st <= '1';
164 if(Received_reg='1' and Received='0')then
165 ect <= eX;
166 end if;
167 end case;
168 ---------------------------------------------------------------------------------
169 case st is
170 when e0 =>
171 if(go_st='1')then
172 st <= e1;
173 end if;
174
175 when e1 =>
176 Valid <= '1';
177 st <= e2;
178
179 when e2 =>
180 if(Received_reg='0' and Received='1')then
181 Valid <= '0';
182 if(Conjugate='1')then
183 st <= eY;
184 else
185 st <= eX;
186 end if;
187 end if;
188
189 when eX =>
190 st <= e3;
191
192 when e3 =>
193 if(go_st='1')then
194 st <= e4;
195 end if;
196
197 when e4 =>
198 Valid <= '1';
199 st <= e5;
200
201 when e5 =>
202 if(Received_reg='1' and Received='0')then
203 Valid <= '0';
204 st <= eY;
205 end if;
206
207 when eY =>
208 st <= e0;
209
210 when others =>
211 null;
212 end case;
213
214 end if;
215 end process;
216
216 217 end ar_ALU_Driver; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,87 +1,87
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 --library lpp;
26 --use lpp.lpp_matrix.all;
27
28 entity MatriceSpectrale is
29 generic(
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
32 port(
33 clkm : in std_logic;
34 rstn : in std_logic;
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
38 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
39 Valid : in std_logic;
40 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
41 ACQ : in std_logic;
42 SM_Write : out std_logic;
43 FlagError : out std_logic;
44 Pong : out std_logic;
45 Statu : out std_logic_vector(3 downto 0);
46 Write : out std_logic_vector(1 downto 0);
47 Read : out std_logic_vector(4 downto 0);
48 ReUse : out std_logic_vector(4 downto 0);
49 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
50 );
51 end entity;
52
53
54 architecture ar_MatriceSpectrale of MatriceSpectrale is
55
56 signal Matrix_Write : std_logic;
57 signal Matrix_Read : std_logic_vector(1 downto 0);
58 signal Matrix_Result : std_logic_vector(31 downto 0);
59
60 signal TopSM_Start : std_logic;
61 signal TopSM_Statu : std_logic_vector(3 downto 0);
62 signal TopSM_Data1 : std_logic_vector(15 downto 0);
63 signal TopSM_Data2 : std_logic_vector(15 downto 0);
64
65 begin
66
67 CTRL0 : entity work.ReUse_CTRLR
68 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
69
70
71 TopSM : entity work.TopSpecMatrix
72 generic map (Input_SZ)
73 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
74
75 SM : entity work.SpectralMatrix
76 generic map (Input_SZ,Result_SZ)
77 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
78
79 DISP : entity work.Dispatch
80 generic map(Result_SZ)
81 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
82
83 Statu <= TopSM_Statu;
84 SM_Write <= Matrix_Write;
85
86 end architecture;
87
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_matrix.all;
27
28 entity MatriceSpectrale is
29 generic(
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
32 port(
33 clkm : in std_logic;
34 rstn : in std_logic;
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
38 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
39 Valid : in std_logic;
40 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
41 ACQ : in std_logic;
42 SM_Write : out std_logic;
43 FlagError : out std_logic;
44 Pong : out std_logic;
45 Statu : out std_logic_vector(3 downto 0);
46 Write : out std_logic_vector(1 downto 0);
47 Read : out std_logic_vector(4 downto 0);
48 ReUse : out std_logic_vector(4 downto 0);
49 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
50 );
51 end entity;
52
53
54 architecture ar_MatriceSpectrale of MatriceSpectrale is
55
56 signal Matrix_Write : std_logic;
57 signal Matrix_Read : std_logic_vector(1 downto 0);
58 signal Matrix_Result : std_logic_vector(31 downto 0);
59
60 signal TopSM_Start : std_logic;
61 signal TopSM_Statu : std_logic_vector(3 downto 0);
62 signal TopSM_Data1 : std_logic_vector(15 downto 0);
63 signal TopSM_Data2 : std_logic_vector(15 downto 0);
64
65 begin
66
67 CTRL0 : ReUse_CTRLR
68 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
69
70
71 TopSM : TopSpecMatrix
72 generic map (Input_SZ)
73 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
74
75 SM : SpectralMatrix
76 generic map (Input_SZ,Result_SZ)
77 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
78
79 DISP : Dispatch
80 generic map(Result_SZ)
81 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
82
83 Statu <= TopSM_Statu;
84 SM_Write <= Matrix_Write;
85
86 end architecture;
87
Show file before | Show file after | Hide comments
@@ -1,84 +1,85
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26
27 entity SpectralMatrix is
28 generic(
29 Input_SZ : integer := 16;
30 Result_SZ : integer := 32);
31 port(
32 clk : in std_logic;
33 reset : in std_logic;
34 Start : in std_logic;
35 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
36 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
37 Statu : in std_logic_vector(3 downto 0);
38 -- FullFIFO : in std_logic;
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 WriteFIFO : out std_logic;
41 Result : out std_logic_vector(Result_SZ-1 downto 0)
42 );
43 end SpectralMatrix;
44
45
46 architecture ar_SpectralMatrix of SpectralMatrix is
47
48 signal RaZ : std_logic;
49 signal Read_int : std_logic;
50 signal Take_int : std_logic;
51 signal Received_int : std_logic;
52 signal Valid_int : std_logic;
53 signal Conjugate_int : std_logic;
54
55 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
56
57
58 begin
59
60 RaZ <= reset and Start;
61
62 IN1 : DriveInputs
63 port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO);
64
65
66 CALC0 : Matrix
67 generic map(Input_SZ)
68 port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
69
70
71 RES0 : GetResult
72 generic map(Result_SZ)
73 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO
74
75
76 With Statu select
77 Conjugate_int <= '1' when "0001",
78 '1' when "0011",
79 '1' when "0110",
80 '1' when "1010",
81 '1' when "1111",
82 '0' when others;
83
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.lpp_matrix.all;
27
28 entity SpectralMatrix is
29 generic(
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
32 port(
33 clk : in std_logic;
34 reset : in std_logic;
35 Start : in std_logic;
36 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
37 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
38 Statu : in std_logic_vector(3 downto 0);
39 -- FullFIFO : in std_logic;
40 ReadFIFO : out std_logic_vector(1 downto 0);
41 WriteFIFO : out std_logic;
42 Result : out std_logic_vector(Result_SZ-1 downto 0)
43 );
44 end SpectralMatrix;
45
46
47 architecture ar_SpectralMatrix of SpectralMatrix is
48
49 signal RaZ : std_logic;
50 signal Read_int : std_logic;
51 signal Take_int : std_logic;
52 signal Received_int : std_logic;
53 signal Valid_int : std_logic;
54 signal Conjugate_int : std_logic;
55
56 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
57
58
59 begin
60
61 RaZ <= reset and Start;
62
63 IN1 : DriveInputs
64 port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO);
65
66
67 CALC0 : Matrix
68 generic map(Input_SZ)
69 port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
70
71
72 RES0 : GetResult
73 generic map(Result_SZ)
74 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO
75
76
77 With Statu select
78 Conjugate_int <= '1' when "0001",
79 '1' when "0011",
80 '1' when "0110",
81 '1' when "1010",
82 '1' when "1111",
83 '0' when others;
84
84 85 end ar_SpectralMatrix; No newline at end of file
General Comments 0
You need to be logged in to leave comments. Login now