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LFR-EQM 2.1.83...
pellion -
r601:1b6a99d2ea09 (LFR-EQM) 2-1-83 simu_with_Leon3
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@@ -450,7 +450,7 BEGIN -- beh
450 450 pirq_ms => 6,
451 451 pirq_wfp => 14,
452 452 hindex => 2,
453 top_lfr_version => X"020152", -- aa.bb.cc version
453 top_lfr_version => X"020153", -- aa.bb.cc version
454 454 -- AA : BOARD NUMBER
455 455 -- 0 => MINI_LFR
456 456 -- 1 => EM
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@@ -9,8 +9,8 USE lpp.general_purpose.SYNC_FF;
9 9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 10 GENERIC(
11 11 ChanelCount : INTEGER := 8;
12 ncycle_cnv_high : INTEGER := 25;
13 ncycle_cnv : INTEGER := 50;
12 ncycle_cnv_high : INTEGER := 13;
13 ncycle_cnv : INTEGER := 25;
14 14 FILTER_ENABLED : INTEGER := 16#FF#
15 15 );
16 16 PORT (
@@ -34,8 +34,7 ARCHITECTURE ar_top_ad_conv_RHF1401 OF t
34 34 SIGNAL cnv_s : STD_LOGIC;
35 35 SIGNAL cnv_s_reg : STD_LOGIC;
36 36 SIGNAL cnv_sync : STD_LOGIC;
37 SIGNAL cnv_sync_reg : STD_LOGIC;
38 SIGNAL cnv_sync_falling : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
39 38
40 39 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
41 40 SIGNAL enable_ADC : STD_LOGIC;
@@ -53,24 +52,7 ARCHITECTURE ar_top_ad_conv_RHF1401 OF t
53 52 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
54 53
55 54 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
56
57 -----------------------------------------------------------------------------
58 CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 1;
59 CONSTANT DATA_CYCLE_VALID : INTEGER := 2;
60 55
61 -- GEN OutPut Enable
62 TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE);
63 SIGNAL state_GEN_OEn : FSM_GEN_OEn_state;
64 SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1;
65 SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1 ;
66 SIGNAL ADC_data_valid : STD_LOGIC;
67 SIGNAL ADC_data_valid_s : STD_LOGIC;
68 SIGNAL ADC_data_reg : Samples14;
69 -----------------------------------------------------------------------------
70 CONSTANT SAMPLE_DIVISION : INTEGER := 10;
71 SIGNAL sample_val_s : STD_LOGIC;
72 SIGNAL sample_val_s2 : STD_LOGIC;
73 SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION;
74 56 BEGIN
75 57
76 58
@@ -85,7 +67,7 BEGIN
85 67 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
86 68 IF cnv_cycle_counter < ncycle_cnv-1 THEN
87 69 cnv_cycle_counter <= cnv_cycle_counter + 1;
88 IF cnv_cycle_counter < ncycle_cnv_high-1 THEN
70 IF cnv_cycle_counter < ncycle_cnv_high THEN
89 71 cnv_s <= '1';
90 72 ELSE
91 73 cnv_s <= '0';
@@ -122,167 +104,111 BEGIN
122 104 A => cnv_s_reg,
123 105 A_sync => cnv_sync);
124 106
107
125 108 -----------------------------------------------------------------------------
126 --
109 -- DATA GEN Output Enable
110 -----------------------------------------------------------------------------
111 PROCESS (clk, rstn)
112 BEGIN -- PROCESS
113 IF rstn = '0' THEN -- asynchronous reset (active low)
114 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
115 cnv_sync_pre <= '0';
116 enable_ADC <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 cnv_sync_pre <= cnv_sync;
119 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
120 enable_ADC <= '1';
121 ADC_nOE_reg(0) <= '0';
122 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
123 ELSE
124 enable_ADC <= NOT enable_ADC;
125 IF enable_ADC = '0' THEN
126 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
127 END IF;
128 END IF;
129
130 END IF;
131 END PROCESS;
132
133 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
134
135 -----------------------------------------------------------------------------
136 -- ADC READ DATA
127 137 -----------------------------------------------------------------------------
128 138 PROCESS (clk, rstn)
129 139 BEGIN -- PROCESS
130 140 IF rstn = '0' THEN -- asynchronous reset (active low)
131 cnv_sync_reg <= '0';
141 channel_counter <= MAX_COUNTER;
142
143 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
144 sample_reg(I) <= (OTHERS => '0');
145 END LOOP all_sample_reg_init;
146
147 sample_val <= '0';
148 sample_counter <= 0;
132 149 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
133 cnv_sync_reg <= cnv_sync;
134 END IF;
135 END PROCESS;
136
137 cnv_sync_falling <= '1' WHEN cnv_sync = '0' AND cnv_sync_reg = '1' ELSE '0';
138
139 -----------------------------------------------------------------------------
140 -- GEN OutPut Enable
141 -----------------------------------------------------------------------------
142 PROCESS (clk, rstn)
143 BEGIN -- PROCESS
144 IF rstn = '0' THEN
145 -------------------------------------------------------------------------
146 ADC_nOE <= (OTHERS => '1');
147 ADC_current <= 0;
148 ADC_current_cycle_enabled <= 0;
149 state_GEN_OEn <= IDLE;
150 -------------------------------------------------------------------------
151 ADC_data_reg <= (OTHERS => '0');
152 all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP
153 sample_reg(I) <= (OTHERS => '0');
154 sample(I) <= (OTHERS => '0');
155 END LOOP all_channel_sample_reg_init;
150 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
151 channel_counter <= 0;
152 ELSE
153 IF channel_counter < MAX_COUNTER THEN
154 channel_counter <= channel_counter + 1;
155 END IF;
156 END IF;
156 157 sample_val <= '0';
157 sample_val_s <= '0';
158 sample_val_counter <= 0;
159 -------------------------------------------------------------------------
160 ELSIF clk'event AND clk = '1' THEN
161 -------------------------------------------------------------------------
162 sample_val_s <= '0';
163 ADC_nOE <= (OTHERS => '1');
164 CASE state_GEN_OEn IS
165 WHEN IDLE =>
166 IF cnv_sync_falling = '1' THEN
167 --ADC_nOE(0) <= '1';
168 state_GEN_OEn <= GEN_OE;
169 ADC_current <= 0;
170 ADC_current_cycle_enabled <= 1;
158
159 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
160 IF channel_counter = I*2 THEN
161 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
162 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
163 ELSE
164 sample_reg(I) <= ADC_data;
171 165 END IF;
172
173 WHEN GEN_OE =>
174 ADC_nOE(ADC_current) <= '0';
175
176 ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1;
177
178 IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN
179 state_GEN_OEn <= WAIT_CYCLE;
180 END IF;
181
182 WHEN WAIT_CYCLE =>
183 ADC_current_cycle_enabled <= 1;
184 IF ADC_current = ChanelCount-1 THEN
185 state_GEN_OEn <= IDLE;
186 sample_val_s <= '1';
187 ELSE
188 ADC_current <= ADC_current + 1;
189 state_GEN_OEn <= GEN_OE;
190 END IF;
191 WHEN OTHERS => NULL;
192 END CASE;
193 -------------------------------------------------------------------------
194 ADC_data_reg <= ADC_data;
166 END IF;
167 END LOOP all_sample_reg;
195 168
196 all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP
197 IF ADC_data_valid = '1' AND ADC_current = I THEN
198 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
169 IF channel_counter = (ChanelCount-1)*2 THEN
170
171 IF sample_counter = MAX_SAMPLE_COUNTER THEN
172 sample_counter <= 0 ;
173 sample_val <= '1';
199 174 ELSE
200 sample_reg(I) <= sample_reg(I);
175 sample_counter <= sample_counter +1;
201 176 END IF;
202 END LOOP all_channel_sample_reg;
203 -------------------------------------------------------------------------
204 sample_val <= '0';
205 IF sample_val_s2 = '1' THEN
206 IF sample_val_counter = SAMPLE_DIVISION-1 THEN
207 sample_val_counter <= 0;
208 sample_val <= '1'; -- TODO
209 sample <= sample_reg;
210 ELSE
211 sample_val_counter <= sample_val_counter + 1;
212 sample_val <= '0';
213 END IF;
214 END IF;
215
177
178 END IF;
216 179 END IF;
217 180 END PROCESS;
218 181
182 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
183 -- BEGIN -- PROCESS mux_adc
184 -- CASE channel_counter IS
185 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
186 -- END CASE;
187 -- END PROCESS mux_adc;
219 188
220 189
221 REG_ADC_DATA_valid: IF DATA_CYCLE_VALID = OE_NB_CYCLE_ENABLED GENERATE
222 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0';
223
224 PROCESS (clk, rstn)
225 BEGIN -- PROCESS
226 IF rstn = '0' THEN -- asynchronous reset (active low)
227 ADC_data_valid <= '0';
228 sample_val_s2 <= '0';
229 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
230 ADC_data_valid <= ADC_data_valid_s;
231 sample_val_s2 <= sample_val_s;
232 END IF;
233 END PROCESS;
234
235 END GENERATE REG_ADC_DATA_valid;
190 -----------------------------------------------------------------------------
191 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
192 -----------------------------------------------------------------------------
236 193
237 noREG_ADC_DATA_valid: IF DATA_CYCLE_VALID < OE_NB_CYCLE_ENABLED GENERATE
238 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0';
239
240 ADC_data_valid <= ADC_data_valid_s;
241 sample_val_s2 <= sample_val_s;
242 END GENERATE noREG_ADC_DATA_valid;
243
244 REGm_ADC_DATA_valid: IF DATA_CYCLE_VALID > OE_NB_CYCLE_ENABLED GENERATE
245
246 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED + 1 ELSE '0';
247
248 REG_1: SYNC_FF
249 GENERIC MAP (
250 NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1)
251 PORT MAP (
252 clk => clk,
253 rstn => rstn,
254 A => ADC_data_valid_s,
255 A_sync => ADC_data_valid);
256
257 REG_2: SYNC_FF
258 GENERIC MAP (
259 NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1)
260 PORT MAP (
261 clk => clk,
262 rstn => rstn,
263 A => sample_val_s,
264 A_sync => sample_val_s2);
265 END GENERATE REGm_ADC_DATA_valid;
266
267
268
269 WITH ADC_current SELECT
270 ADC_data_selected <= sample_reg(0) WHEN 0,
271 sample_reg(1) WHEN 1,
272 sample_reg(2) WHEN 2,
273 sample_reg(3) WHEN 3,
274 sample_reg(4) WHEN 4,
275 sample_reg(5) WHEN 5,
276 sample_reg(6) WHEN 6,
277 sample_reg(7) WHEN 7,
194 WITH channel_counter SELECT
195 ADC_data_selected <= sample_reg(0) WHEN 0*2,
196 sample_reg(1) WHEN 1*2,
197 sample_reg(2) WHEN 2*2,
198 sample_reg(3) WHEN 3*2,
199 sample_reg(4) WHEN 4*2,
200 sample_reg(5) WHEN 5*2,
201 sample_reg(6) WHEN 6*2,
202 sample_reg(7) WHEN 7*2,
278 203 sample_reg(8) WHEN OTHERS ;
279 204
280 ADC_data_result <= std_logic_vector((
281 signed( ADC_data_selected(13) & ADC_data_selected) +
282 signed( ADC_data_reg(13) & ADC_data_reg)
283 ));
205 -----------------------------------------------------------------------------
206 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
207 -----------------------------------------------------------------------------
284 208
285 -- sample <= sample_reg;
209 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
210
211 sample <= sample_reg;
286 212
287 213 END ar_top_ad_conv_RHF1401;
288 214
@@ -299,3 +225,4 END ar_top_ad_conv_RHF1401;
299 225
300 226
301 227
228
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