diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd --- a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd @@ -450,7 +450,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"020152", -- aa.bb.cc version + top_lfr_version => X"020153", -- aa.bb.cc version -- AA : BOARD NUMBER -- 0 => MINI_LFR -- 1 => EM diff --git a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd --- a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd +++ b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd @@ -9,8 +9,8 @@ USE lpp.general_purpose.SYNC_FF; ENTITY top_ad_conv_RHF1401_withFilter IS GENERIC( ChanelCount : INTEGER := 8; - ncycle_cnv_high : INTEGER := 25; - ncycle_cnv : INTEGER := 50; + ncycle_cnv_high : INTEGER := 13; + ncycle_cnv : INTEGER := 25; FILTER_ENABLED : INTEGER := 16#FF# ); PORT ( @@ -34,8 +34,7 @@ ARCHITECTURE ar_top_ad_conv_RHF1401 OF t SIGNAL cnv_s : STD_LOGIC; SIGNAL cnv_s_reg : STD_LOGIC; SIGNAL cnv_sync : STD_LOGIC; - SIGNAL cnv_sync_reg : STD_LOGIC; - SIGNAL cnv_sync_falling : STD_LOGIC; + SIGNAL cnv_sync_pre : STD_LOGIC; SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); SIGNAL enable_ADC : STD_LOGIC; @@ -53,24 +52,7 @@ ARCHITECTURE ar_top_ad_conv_RHF1401 OF t CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9; CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount)); - - ----------------------------------------------------------------------------- - CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 1; - CONSTANT DATA_CYCLE_VALID : INTEGER := 2; - -- GEN OutPut Enable - TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE); - SIGNAL state_GEN_OEn : FSM_GEN_OEn_state; - SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1; - SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1 ; - SIGNAL ADC_data_valid : STD_LOGIC; - SIGNAL ADC_data_valid_s : STD_LOGIC; - SIGNAL ADC_data_reg : Samples14; - ----------------------------------------------------------------------------- - CONSTANT SAMPLE_DIVISION : INTEGER := 10; - SIGNAL sample_val_s : STD_LOGIC; - SIGNAL sample_val_s2 : STD_LOGIC; - SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION; BEGIN @@ -85,7 +67,7 @@ BEGIN ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge IF cnv_cycle_counter < ncycle_cnv-1 THEN cnv_cycle_counter <= cnv_cycle_counter + 1; - IF cnv_cycle_counter < ncycle_cnv_high-1 THEN + IF cnv_cycle_counter < ncycle_cnv_high THEN cnv_s <= '1'; ELSE cnv_s <= '0'; @@ -122,167 +104,111 @@ BEGIN A => cnv_s_reg, A_sync => cnv_sync); + ----------------------------------------------------------------------------- - -- + -- DATA GEN Output Enable + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1'); + cnv_sync_pre <= '0'; + enable_ADC <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + cnv_sync_pre <= cnv_sync; + IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN + enable_ADC <= '1'; + ADC_nOE_reg(0) <= '0'; + ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1'); + ELSE + enable_ADC <= NOT enable_ADC; + IF enable_ADC = '0' THEN + ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1'; + END IF; + END IF; + + END IF; + END PROCESS; + + ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg; + + ----------------------------------------------------------------------------- + -- ADC READ DATA ----------------------------------------------------------------------------- PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - cnv_sync_reg <= '0'; + channel_counter <= MAX_COUNTER; + + all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP + sample_reg(I) <= (OTHERS => '0'); + END LOOP all_sample_reg_init; + + sample_val <= '0'; + sample_counter <= 0; ELSIF clk'event AND clk = '1' THEN -- rising clock edge - cnv_sync_reg <= cnv_sync; - END IF; - END PROCESS; - - cnv_sync_falling <= '1' WHEN cnv_sync = '0' AND cnv_sync_reg = '1' ELSE '0'; - - ----------------------------------------------------------------------------- - -- GEN OutPut Enable - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN - ------------------------------------------------------------------------- - ADC_nOE <= (OTHERS => '1'); - ADC_current <= 0; - ADC_current_cycle_enabled <= 0; - state_GEN_OEn <= IDLE; - ------------------------------------------------------------------------- - ADC_data_reg <= (OTHERS => '0'); - all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP - sample_reg(I) <= (OTHERS => '0'); - sample(I) <= (OTHERS => '0'); - END LOOP all_channel_sample_reg_init; + IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN + channel_counter <= 0; + ELSE + IF channel_counter < MAX_COUNTER THEN + channel_counter <= channel_counter + 1; + END IF; + END IF; sample_val <= '0'; - sample_val_s <= '0'; - sample_val_counter <= 0; - ------------------------------------------------------------------------- - ELSIF clk'event AND clk = '1' THEN - ------------------------------------------------------------------------- - sample_val_s <= '0'; - ADC_nOE <= (OTHERS => '1'); - CASE state_GEN_OEn IS - WHEN IDLE => - IF cnv_sync_falling = '1' THEN - --ADC_nOE(0) <= '1'; - state_GEN_OEn <= GEN_OE; - ADC_current <= 0; - ADC_current_cycle_enabled <= 1; + + all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP + IF channel_counter = I*2 THEN + IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN + sample_reg(I) <= ADC_data_result(14 DOWNTO 1); + ELSE + sample_reg(I) <= ADC_data; END IF; - - WHEN GEN_OE => - ADC_nOE(ADC_current) <= '0'; - - ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1; - - IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN - state_GEN_OEn <= WAIT_CYCLE; - END IF; - - WHEN WAIT_CYCLE => - ADC_current_cycle_enabled <= 1; - IF ADC_current = ChanelCount-1 THEN - state_GEN_OEn <= IDLE; - sample_val_s <= '1'; - ELSE - ADC_current <= ADC_current + 1; - state_GEN_OEn <= GEN_OE; - END IF; - WHEN OTHERS => NULL; - END CASE; - ------------------------------------------------------------------------- - ADC_data_reg <= ADC_data; + END IF; + END LOOP all_sample_reg; - all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP - IF ADC_data_valid = '1' AND ADC_current = I THEN - sample_reg(I) <= ADC_data_result(14 DOWNTO 1); + IF channel_counter = (ChanelCount-1)*2 THEN + + IF sample_counter = MAX_SAMPLE_COUNTER THEN + sample_counter <= 0 ; + sample_val <= '1'; ELSE - sample_reg(I) <= sample_reg(I); + sample_counter <= sample_counter +1; END IF; - END LOOP all_channel_sample_reg; - ------------------------------------------------------------------------- - sample_val <= '0'; - IF sample_val_s2 = '1' THEN - IF sample_val_counter = SAMPLE_DIVISION-1 THEN - sample_val_counter <= 0; - sample_val <= '1'; -- TODO - sample <= sample_reg; - ELSE - sample_val_counter <= sample_val_counter + 1; - sample_val <= '0'; - END IF; - END IF; - + + END IF; END IF; END PROCESS; +-- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg) +-- BEGIN -- PROCESS mux_adc +-- CASE channel_counter IS +-- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2); +-- END CASE; +-- END PROCESS mux_adc; - REG_ADC_DATA_valid: IF DATA_CYCLE_VALID = OE_NB_CYCLE_ENABLED GENERATE - ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0'; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - ADC_data_valid <= '0'; - sample_val_s2 <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - ADC_data_valid <= ADC_data_valid_s; - sample_val_s2 <= sample_val_s; - END IF; - END PROCESS; - - END GENERATE REG_ADC_DATA_valid; + ----------------------------------------------------------------------------- + -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/ + ----------------------------------------------------------------------------- - noREG_ADC_DATA_valid: IF DATA_CYCLE_VALID < OE_NB_CYCLE_ENABLED GENERATE - ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0'; - - ADC_data_valid <= ADC_data_valid_s; - sample_val_s2 <= sample_val_s; - END GENERATE noREG_ADC_DATA_valid; - - REGm_ADC_DATA_valid: IF DATA_CYCLE_VALID > OE_NB_CYCLE_ENABLED GENERATE - - ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED + 1 ELSE '0'; - - REG_1: SYNC_FF - GENERIC MAP ( - NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1) - PORT MAP ( - clk => clk, - rstn => rstn, - A => ADC_data_valid_s, - A_sync => ADC_data_valid); - - REG_2: SYNC_FF - GENERIC MAP ( - NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1) - PORT MAP ( - clk => clk, - rstn => rstn, - A => sample_val_s, - A_sync => sample_val_s2); - END GENERATE REGm_ADC_DATA_valid; - - - - WITH ADC_current SELECT - ADC_data_selected <= sample_reg(0) WHEN 0, - sample_reg(1) WHEN 1, - sample_reg(2) WHEN 2, - sample_reg(3) WHEN 3, - sample_reg(4) WHEN 4, - sample_reg(5) WHEN 5, - sample_reg(6) WHEN 6, - sample_reg(7) WHEN 7, + WITH channel_counter SELECT + ADC_data_selected <= sample_reg(0) WHEN 0*2, + sample_reg(1) WHEN 1*2, + sample_reg(2) WHEN 2*2, + sample_reg(3) WHEN 3*2, + sample_reg(4) WHEN 4*2, + sample_reg(5) WHEN 5*2, + sample_reg(6) WHEN 6*2, + sample_reg(7) WHEN 7*2, sample_reg(8) WHEN OTHERS ; - ADC_data_result <= std_logic_vector(( - signed( ADC_data_selected(13) & ADC_data_selected) + - signed( ADC_data_reg(13) & ADC_data_reg) - )); + ----------------------------------------------------------------------------- + -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\ + ----------------------------------------------------------------------------- --- sample <= sample_reg; + ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) ); + + sample <= sample_reg; END ar_top_ad_conv_RHF1401; @@ -299,3 +225,4 @@ END ar_top_ad_conv_RHF1401; +