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1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=testbench
4 TOP=TB
5 BOARD=LFR-EQM
5 BOARD=LFR-FM
6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=
8 UCF=
9 QSF=
9 QSF=
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT=
12 SYNPOPT=
13 VHDLSYNFILES=
13 VHDLSYNFILES=
14 VHDLSIMFILES= tb.vhd
14 VHDLSIMFILES= TB.vhd
15 SIMTOP=TB
15 SIMTOP=tb
16 CLEAN=soft-clean
16 CLEAN=soft-clean
17
17
18 TECHLIBS = axcelerator
18 TECHLIBS = axcelerator
19
19
20 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
20 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi
21 tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi
22
22
23 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
23 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
24 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
24 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
25 grlfpc \
25 grlfpc \
26 ./dsp/lpp_fft_rtax \
26 ./dsp/lpp_fft_rtax \
27 ./amba_lcd_16x2_ctrlr \
27 ./amba_lcd_16x2_ctrlr \
28 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_AMR \
29 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_balise \
30 ./general_purpose/lpp_delay \
30 ./general_purpose/lpp_delay \
31 ./lpp_bootloader \
31 ./lpp_bootloader \
32 ./lpp_sim/CY7C1061DV33 \
32 ./lpp_sim/CY7C1061DV33 \
33 ./lpp_uart \
33 ./lpp_uart \
34 ./lpp_usb \
34 ./lpp_usb \
35 ./dsp/lpp_fft \
35 ./dsp/lpp_fft \
36 ./lpp_leon3_soc \
36 ./lpp_leon3_soc \
37 ./lpp_debug_lfr
37 ./lpp_debug_lfr
38
38
39 FILESKIP = i2cmst.vhd \
39 FILESKIP = i2cmst.vhd \
40 APB_MULTI_DIODE.vhd \
40 APB_MULTI_DIODE.vhd \
41 APB_MULTI_DIODE.vhd \
41 APB_MULTI_DIODE.vhd \
42 Top_MatrixSpec.vhd \
42 Top_MatrixSpec.vhd \
43 APB_FFT.vhd \
43 APB_FFT.vhd \
44 lpp_lfr_ms_FFT.vhd \
44 lpp_lfr_ms_FFT.vhd \
45 lpp_lfr_apbreg.vhd \
45 lpp_lfr_apbreg.vhd \
46 CoreFFT.vhd \
46 CoreFFT.vhd \
47 lpp_lfr_ms.vhd \
47 lpp_lfr_ms.vhd \
48 lpp_lfr_sim_pkg.vhd \
48 lpp_lfr_sim_pkg.vhd \
49 mtie_maps.vhd \
49 mtie_maps.vhd \
50 ftsrctrlc.vhd \
50 ftsrctrlc.vhd \
51 ftsdctrl.vhd \
51 ftsdctrl.vhd \
52 ftsrctrl8.vhd \
52 ftsrctrl8.vhd \
53 ftmctrl.vhd \
53 ftmctrl.vhd \
54 ftsdctrl64.vhd \
54 ftsdctrl64.vhd \
55 ftahbram.vhd \
55 ftahbram.vhd \
56 ftahbram2.vhd \
56 ftahbram2.vhd \
57 sramft.vhd \
57 sramft.vhd \
58 nandfctrlx.vhd
58 nandfctrlx.vhd
59
59
60 include $(GRLIB)/bin/Makefile
60 include $(GRLIB)/bin/Makefile
61 include $(GRLIB)/software/leon3/Makefile
61 include $(GRLIB)/software/leon3/Makefile
62
62
63 ################## project specific targets ##########################
63 ################## project specific targets ##########################
64 distclean:myclean
64 distclean:myclean
65 vsim:cp_for_vsim
65 vsim:cp_for_vsim
66
66
67 myclean:
67 myclean:
68 rm -f input.txt output_fx.txt *.log
68 rm -f input.txt output_fx.txt *.log
69 rm -rf ./2016*
69 rm -rf ./2016*
70
70
71 generate :
71 generate :
72 # python ./generate.py
72 # python ./generate.py
73
73
74 cp_for_vsim: generate
74 cp_for_vsim: generate
75 # cp ./input.txt simulation/
75 # cp ./input.txt simulation/
76
76
77 archivate:
77 archivate:
78 xonsh ./archivate.xsh
78 xonsh ./archivate.xsh
79
79
80 test: | generate ghdl ghdl-run archivate
80 test: | generate ghdl ghdl-run archivate
81
81
82
82
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@@ -1,361 +1,423
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 use ieee.std_logic_textio.all;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
27 use std.textio.all;
28
26
29
27 LIBRARY grlib;
30 LIBRARY grlib;
28 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
31
34
32 LIBRARY lpp;
35 LIBRARY lpp;
33 USE lpp.lpp_lfr_management.ALL;
36 USE lpp.lpp_lfr_management.ALL;
34
37
35 ENTITY TB IS
38 ENTITY TB IS
36
39
37 PORT (
40 PORT (
38 SIM_OK : OUT STD_LOGIC
41 SIM_OK : OUT STD_LOGIC
39 );
42 );
40
43
41 END TB;
44 END TB;
42
45
43
46
44 ARCHITECTURE beh OF TB IS
47 ARCHITECTURE beh OF TB IS
45
48
46 SIGNAL clk25MHz : STD_LOGIC := '0';
49 SIGNAL clk25MHz : STD_LOGIC := '0';
47
50
48 SIGNAL resetn : STD_LOGIC;
51 SIGNAL resetn : STD_LOGIC;
49 SIGNAL grspw_tick : STD_LOGIC;
52 SIGNAL grspw_tick : STD_LOGIC;
50 SIGNAL apbi : apb_slv_in_type;
53 SIGNAL apbi : apb_slv_in_type;
51 SIGNAL apbo : apb_slv_out_type;
54 SIGNAL apbo : apb_slv_out_type;
52 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
55 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
53 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
56 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
54
57
55 SIGNAL TB_string : STRING(1 TO 8):= "12345678";
58 SIGNAL TB_string : STRING(1 TO 8):= "12345678";
56
59
57 SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
60 SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
61 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
59 SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
62 SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
60 SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
63 SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
61 SIGNAL tick_ongoing : STD_LOGIC;
64 SIGNAL tick_ongoing : STD_LOGIC;
62
65
63 SIGNAL ASSERTION_1 : STD_LOGIC;
66 SIGNAL ASSERTION_1 : STD_LOGIC;
64 SIGNAL ASSERTION_2 : STD_LOGIC;
67 SIGNAL ASSERTION_2 : STD_LOGIC;
65 SIGNAL ASSERTION_3 : STD_LOGIC;
68 SIGNAL ASSERTION_3 : STD_LOGIC;
69 SIGNAL ASSERTION_3_ERROR : STD_LOGIC;
70
71 SIGNAL end_of_simu : STD_LOGIC := '0';
66
72
67 BEGIN -- beh
73 BEGIN -- beh
68
74
69 apb_lfr_management_1: apb_lfr_management
75 apb_lfr_management_1: apb_lfr_management
70 GENERIC MAP (
76 GENERIC MAP (
71 tech => 0,
77 tech => 0,
72 pindex => 0,
78 pindex => 0,
73 paddr => 0,
79 paddr => 0,
74 pmask => 16#fff#,
80 pmask => 16#fff#,
75 -- FIRST_DIVISION => 20,
81 -- FIRST_DIVISION => 20,
76 NB_SECOND_DESYNC => 4)
82 NB_SECOND_DESYNC => 4)
77 PORT MAP (
83 PORT MAP (
78 clk25MHz => clk25MHz,
84 clk25MHz => clk25MHz,
79 resetn_25MHz => resetn,
85 resetn_25MHz => resetn,
80
86
81 grspw_tick => grspw_tick,
87 grspw_tick => grspw_tick,
82 apbi => apbi,
88 apbi => apbi,
83 apbo => apbo,
89 apbo => apbo,
84
90
85 HK_sample => (others => '0'),
91 HK_sample => (others => '0'),
86 HK_val => '0',
92 HK_val => '0',
87 HK_sel => OPEN,
93 HK_sel => OPEN,
88
94
89 DAC_SDO => OPEN,
95 DAC_SDO => OPEN,
90 DAC_SCK => OPEN,
96 DAC_SCK => OPEN,
91 DAC_SYNC => OPEN,
97 DAC_SYNC => OPEN,
92 DAC_CAL_EN => OPEN,
98 DAC_CAL_EN => OPEN,
93
99
94 coarse_time => coarse_time,
100 coarse_time => coarse_time,
95 fine_time => fine_time,
101 fine_time => fine_time,
96
102
97 LFR_soft_rstn => OPEN);
103 LFR_soft_rstn => OPEN);
98
104
99 clk25MHz <= NOT clk25MHz AFTER 20000 ps;
105 -----------------------------------------------------------------------------
106 -- CLOCK GEN
107 PROCESS IS
108 BEGIN -- PROCESS
109 IF end_of_simu /= '1' THEN
110 clk25MHz <= NOT clk25MHz;
111 WAIT FOR 20000 ps;
112 ELSE
113 WAIT FOR 20 ps;
114 ASSERT false REPORT "END OF TEST" SEVERITY note;
115 WAIT;
116 END IF;
117 END PROCESS;
118 -----------------------------------------------------------------------------
119
100
120
101 PROCESS
121 PROCESS
102 BEGIN -- PROCESS
122 BEGIN -- PROCESS
103 WAIT UNTIL clk25MHz = '1';
123 WAIT UNTIL clk25MHz = '1';
104 TB_string <= "RESET ";
124 TB_string <= "RESET "; REPORT "RESET" SEVERITY note;
105
125
106 resetn <= '0';
126 resetn <= '0';
107
127
108 apbi.psel(0) <= '0';
128 apbi.psel(0) <= '0';
109 apbi.pwrite <= '0';
129 apbi.pwrite <= '0';
110 apbi.penable <= '0';
130 apbi.penable <= '0';
111 apbi.paddr <= (OTHERS => '0');
131 apbi.paddr <= (OTHERS => '0');
112 apbi.pwdata <= (OTHERS => '0');
132 apbi.pwdata <= (OTHERS => '0');
113 grspw_tick <= '0';
133 grspw_tick <= '0';
114 WAIT UNTIL clk25MHz = '1';
134 WAIT UNTIL clk25MHz = '1';
115 WAIT UNTIL clk25MHz = '1';
135 WAIT UNTIL clk25MHz = '1';
116 resetn <= '1';
136 resetn <= '1';
117 WAIT FOR 60 ms;
137 WAIT FOR 60 ms;
118 ---------------------------------------------------------------------------
138 ---------------------------------------------------------------------------
119 -- DESYNC TO SYNC
139 -- DESYNC TO SYNC
120 ---------------------------------------------------------------------------
140 ---------------------------------------------------------------------------
121 WAIT UNTIL clk25MHz = '1';
141 WAIT UNTIL clk25MHz = '1';
122 TB_string <= "TICK 1 ";
142 TB_string <= "TICK 1 "; REPORT "Tick 1" SEVERITY note;
123 grspw_tick <= '1';------------------------------------------------------1
143 grspw_tick <= '1';------------------------------------------------------1
124 WAIT UNTIL clk25MHz = '1';
144 WAIT UNTIL clk25MHz = '1';
125 grspw_tick <= '0';
145 grspw_tick <= '0';
126 WAIT FOR 53333 us;
146 WAIT FOR 53333 us;
127 WAIT UNTIL clk25MHz = '1';
147 WAIT UNTIL clk25MHz = '1';
128 TB_string <= "TICK 2 ";
148 TB_string <= "TICK 2 "; REPORT "Tick 2" SEVERITY note;
129 grspw_tick <= '1';------------------------------------------------------2
149 grspw_tick <= '1';------------------------------------------------------2
130 WAIT UNTIL clk25MHz = '1';
150 WAIT UNTIL clk25MHz = '1';
131 grspw_tick <= '0';
151 grspw_tick <= '0';
132 WAIT FOR 56000 us;
152 WAIT FOR 56000 us;
133 WAIT UNTIL clk25MHz = '1';
153 WAIT UNTIL clk25MHz = '1';
134 TB_string <= "TICK 3 ";
154 TB_string <= "TICK 3 "; REPORT "Tick 3" SEVERITY note;
135 grspw_tick <= '1';------------------------------------------------------3
155 grspw_tick <= '1';------------------------------------------------------3
136 WAIT UNTIL clk25MHz = '1';
156 WAIT UNTIL clk25MHz = '1';
137 grspw_tick <= '0';
157 grspw_tick <= '0';
138 WAIT FOR 200 ms;
158 WAIT FOR 200 ms;
139 WAIT UNTIL clk25MHz = '1';
159 WAIT UNTIL clk25MHz = '1';
140 TB_string <= "CT new ";
160 TB_string <= "CT new "; REPORT "CT new" SEVERITY note;
141 -- WRITE NEW COARSE_TIME
161 -- WRITE NEW COARSE_TIME
142 apbi.psel(0) <= '1';
162 apbi.psel(0) <= '1';
143 apbi.pwrite <= '1';
163 apbi.pwrite <= '1';
144 apbi.penable <= '1';
164 apbi.penable <= '1';
145 apbi.paddr <= X"00000004";
165 apbi.paddr <= X"00000004";
146 apbi.pwdata <= X"00001234";
166 apbi.pwdata <= X"00001234";
147 WAIT UNTIL clk25MHz = '1';
167 WAIT UNTIL clk25MHz = '1';
148 apbi.psel(0) <= '0';
168 apbi.psel(0) <= '0';
149 apbi.pwrite <= '0';
169 apbi.pwrite <= '0';
150 apbi.penable <= '0';
170 apbi.penable <= '0';
151 apbi.paddr <= (OTHERS => '0');
171 apbi.paddr <= (OTHERS => '0');
152 apbi.pwdata <= (OTHERS => '0');
172 apbi.pwdata <= (OTHERS => '0');
153 WAIT UNTIL clk25MHz = '1';
173 WAIT UNTIL clk25MHz = '1';
154
174
155 WAIT FOR 10 ms;
175 WAIT FOR 10 ms;
156 WAIT UNTIL clk25MHz = '1';
176 WAIT UNTIL clk25MHz = '1';
157 TB_string <= "TICK 4 ";
177 TB_string <= "TICK 4 "; REPORT "Tick 4" SEVERITY note;
158 grspw_tick <= '1';------------------------------------------------------3
178 grspw_tick <= '1';------------------------------------------------------3
159 WAIT UNTIL clk25MHz = '1';
179 WAIT UNTIL clk25MHz = '1';
160 grspw_tick <= '0';
180 grspw_tick <= '0';
161
181
162
182
163 WAIT FOR 250 ms;
183 WAIT FOR 250 ms;
164 WAIT UNTIL clk25MHz = '1';
184 WAIT UNTIL clk25MHz = '1';
165 TB_string <= "CT new ";
185 TB_string <= "CT new "; REPORT "CT new" SEVERITY note;
166 -- WRITE NEW COARSE_TIME
186 -- WRITE NEW COARSE_TIME
167 apbi.psel(0) <= '1';
187 apbi.psel(0) <= '1';
168 apbi.pwrite <= '1';
188 apbi.pwrite <= '1';
169 apbi.penable <= '1';
189 apbi.penable <= '1';
170 apbi.paddr <= X"00000004";
190 apbi.paddr <= X"00000004";
171 apbi.pwdata <= X"80005678";
191 apbi.pwdata <= X"80005678";
172 WAIT UNTIL clk25MHz = '1';
192 WAIT UNTIL clk25MHz = '1';
173 apbi.psel(0) <= '0';
193 apbi.psel(0) <= '0';
174 apbi.pwrite <= '0';
194 apbi.pwrite <= '0';
175 apbi.penable <= '0';
195 apbi.penable <= '0';
176 apbi.paddr <= (OTHERS => '0');
196 apbi.paddr <= (OTHERS => '0');
177 apbi.pwdata <= (OTHERS => '0');
197 apbi.pwdata <= (OTHERS => '0');
178 WAIT UNTIL clk25MHz = '1';
198 WAIT UNTIL clk25MHz = '1';
179
199
180 WAIT FOR 10 ms;
200 WAIT FOR 10 ms;
181 WAIT UNTIL clk25MHz = '1';
201 WAIT UNTIL clk25MHz = '1';
182 TB_string <= "TICK 5 ";
202 TB_string <= "TICK 5 "; REPORT "Tick 5" SEVERITY note;
183 grspw_tick <= '1';------------------------------------------------------3
203 grspw_tick <= '1';------------------------------------------------------3
184 WAIT UNTIL clk25MHz = '1';
204 WAIT UNTIL clk25MHz = '1';
185 grspw_tick <= '0';
205 grspw_tick <= '0';
186
206
187
207
188 WAIT FOR 20 ms;
208 WAIT FOR 20 ms;
189 WAIT UNTIL clk25MHz = '1';
209 WAIT UNTIL clk25MHz = '1';
190 TB_string <= "CT new ";
210 TB_string <= "CT new "; REPORT "CT new" SEVERITY note;
191 -- WRITE NEW COARSE_TIME
211 -- WRITE NEW COARSE_TIME
192 apbi.psel(0) <= '1';
212 apbi.psel(0) <= '1';
193 apbi.pwrite <= '1';
213 apbi.pwrite <= '1';
194 apbi.penable <= '1';
214 apbi.penable <= '1';
195 apbi.paddr <= X"00000004";
215 apbi.paddr <= X"00000004";
196 apbi.pwdata <= X"00005678";
216 apbi.pwdata <= X"00005678";
197 WAIT UNTIL clk25MHz = '1';
217 WAIT UNTIL clk25MHz = '1';
198 apbi.psel(0) <= '0';
218 apbi.psel(0) <= '0';
199 apbi.pwrite <= '0';
219 apbi.pwrite <= '0';
200 apbi.penable <= '0';
220 apbi.penable <= '0';
201 apbi.paddr <= (OTHERS => '0');
221 apbi.paddr <= (OTHERS => '0');
202 apbi.pwdata <= (OTHERS => '0');
222 apbi.pwdata <= (OTHERS => '0');
203 WAIT UNTIL clk25MHz = '1';
223 WAIT UNTIL clk25MHz = '1';
204
224
205 WAIT FOR 25 ms;
225 WAIT FOR 25 ms;
206 WAIT UNTIL clk25MHz = '1';
226 WAIT UNTIL clk25MHz = '1';
207 TB_string <= "Soft RST";
227 TB_string <= "Soft RST"; REPORT "Soft Reset" SEVERITY note;
208 -- WRITE SOFT RESET
228 -- WRITE SOFT RESET
209 apbi.psel(0) <= '1';
229 apbi.psel(0) <= '1';
210 apbi.pwrite <= '1';
230 apbi.pwrite <= '1';
211 apbi.penable <= '1';
231 apbi.penable <= '1';
212 apbi.paddr <= X"00000000";
232 apbi.paddr <= X"00000000";
213 apbi.pwdata <= X"00000002";
233 apbi.pwdata <= X"00000002";
214 WAIT UNTIL clk25MHz = '1';
234 WAIT UNTIL clk25MHz = '1';
215 apbi.psel(0) <= '0';
235 apbi.psel(0) <= '0';
216 apbi.pwrite <= '0';
236 apbi.pwrite <= '0';
217 apbi.penable <= '0';
237 apbi.penable <= '0';
218 apbi.paddr <= (OTHERS => '0');
238 apbi.paddr <= (OTHERS => '0');
219 apbi.pwdata <= (OTHERS => '0');
239 apbi.pwdata <= (OTHERS => '0');
220 WAIT UNTIL clk25MHz = '1';
240 WAIT UNTIL clk25MHz = '1';
221
241
222 WAIT FOR 250 ms;
242 WAIT FOR 250 ms;
223 TB_string <= "READ 1 ";
243 TB_string <= "READ 1 "; REPORT "Read 1" SEVERITY note;
244 apbi.psel(0) <= '1';
245 apbi.pwrite <= '0';
246 apbi.penable <= '1';
247 apbi.paddr <= X"00000008";
248 WAIT UNTIL clk25MHz = '1';
249 apbi.psel(0) <= '0';
250 apbi.pwrite <= '0';
251 apbi.penable <= '0';
252 apbi.paddr <= (OTHERS => '0');
253 WAIT UNTIL clk25MHz = '1';
254 WAIT FOR 250 ms;
255 TB_string <= "READ 2 "; REPORT "Read 2" SEVERITY note;
224 apbi.psel(0) <= '1';
256 apbi.psel(0) <= '1';
225 apbi.pwrite <= '0';
257 apbi.pwrite <= '0';
226 apbi.penable <= '1';
258 apbi.penable <= '1';
227 apbi.paddr <= X"00000008";
259 apbi.paddr <= X"00000008";
228 WAIT UNTIL clk25MHz = '1';
260 WAIT UNTIL clk25MHz = '1';
229 apbi.psel(0) <= '0';
261 apbi.psel(0) <= '0';
230 apbi.pwrite <= '0';
262 apbi.pwrite <= '0';
231 apbi.penable <= '0';
263 apbi.penable <= '0';
232 apbi.paddr <= (OTHERS => '0');
264 apbi.paddr <= (OTHERS => '0');
233 WAIT UNTIL clk25MHz = '1';
265 WAIT UNTIL clk25MHz = '1';
234 WAIT FOR 250 ms;
266 WAIT FOR 250 ms;
235 TB_string <= "READ 2 ";
267 TB_string <= "READ 3 "; REPORT "Read 3" SEVERITY note;
236 apbi.psel(0) <= '1';
268 apbi.psel(0) <= '1';
237 apbi.pwrite <= '0';
269 apbi.pwrite <= '0';
238 apbi.penable <= '1';
270 apbi.penable <= '1';
239 apbi.paddr <= X"00000008";
271 apbi.paddr <= X"00000008";
240 WAIT UNTIL clk25MHz = '1';
272 WAIT UNTIL clk25MHz = '1';
241 apbi.psel(0) <= '0';
273 apbi.psel(0) <= '0';
242 apbi.pwrite <= '0';
274 apbi.pwrite <= '0';
243 apbi.penable <= '0';
275 apbi.penable <= '0';
244 apbi.paddr <= (OTHERS => '0');
276 apbi.paddr <= (OTHERS => '0');
245 WAIT UNTIL clk25MHz = '1';
277 WAIT UNTIL clk25MHz = '1';
246 WAIT FOR 250 ms;
278 WAIT FOR 10 ps;
247 TB_string <= "READ 3 ";
279 end_of_simu <= '1';
248 apbi.psel(0) <= '1';
280 REPORT "end_of_simu set to 1" SEVERITY note;
249 apbi.pwrite <= '0';
281
250 apbi.penable <= '1';
282 IF ASSERTION_1 = '1' THEN
251 apbi.paddr <= X"00000008";
283 REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** OK" SEVERITY note;
252 WAIT UNTIL clk25MHz = '1';
284 ELSE
253 apbi.psel(0) <= '0';
285 REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** !! FAILED !!" SEVERITY note;
254 apbi.pwrite <= '0';
286 END IF;
255 apbi.penable <= '0';
287
256 apbi.paddr <= (OTHERS => '0');
288 IF ASSERTION_2 = '1' THEN
257 WAIT UNTIL clk25MHz = '1';
289 REPORT "ASSERTION 2 : **Tick => NEXT(fineTime) = RESET(fineTime) OK" SEVERITY note;
290 ELSE
291 REPORT "ASSERTION 2 : **Tick => NEXT(fineTime) = RESET(fineTime) !! FAILED !!" SEVERITY note;
292 END IF;
293
294 IF ASSERTION_3 = '1' THEN
295 REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** OK" SEVERITY note;
296 ELSE
297 REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** !! FAILED !!" SEVERITY note;
298 END IF;
258
299
259
300
260
301
261 REPORT "*** END simulation ***" SEVERITY failure;
302
303 ASSERT false REPORT "*** END simulation ***" SEVERITY note;
262 WAIT;
304 WAIT;
263
305
264 END PROCESS;
306 END PROCESS;
265
307
266
308
267 -----------------------------------------------------------------------------
309 -----------------------------------------------------------------------------
268 --
310 --
269 -----------------------------------------------------------------------------
311 -----------------------------------------------------------------------------
270
312
271 global_time <= coarse_time & fine_time;
313 global_time <= coarse_time & fine_time;
272
314
273 PROCESS (clk25MHz, resetn)
315 PROCESS (clk25MHz, resetn)
274 BEGIN -- PROCESS
316 BEGIN -- PROCESS
275 IF resetn = '0' THEN -- asynchronous reset (active low)
317 IF resetn = '0' THEN -- asynchronous reset (active low)
276 coarse_time_reg <= (OTHERS => '0');
318 coarse_time_reg <= (OTHERS => '0');
277 fine_time_reg <= (OTHERS => '0');
319 fine_time_reg <= (OTHERS => '0');
278 global_time_reg <= (OTHERS => '0');
320 global_time_reg <= (OTHERS => '0');
279 tick_ongoing <= '0';
321 tick_ongoing <= '0';
280 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
322 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
281 global_time_reg <= global_time;
323 global_time_reg <= global_time;
282 coarse_time_reg <= coarse_time;
324 coarse_time_reg <= coarse_time;
283 fine_time_reg <= fine_time;
325 fine_time_reg <= fine_time;
284 IF grspw_tick ='1' THEN
326 IF grspw_tick ='1' THEN
285 tick_ongoing <= '1';
327 tick_ongoing <= '1';
286 ELSIF tick_ongoing = '1' THEN
328 ELSIF tick_ongoing = '1' THEN
287 IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN
329 IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN
288 tick_ongoing <= '0';
330 tick_ongoing <= '0';
289 END IF;
331 END IF;
290 END IF;
332 END IF;
291
333
292 END IF;
334 END IF;
293 END PROCESS;
335 END PROCESS;
294
336
295 -----------------------------------------------------------------------------
337 -----------------------------------------------------------------------------
296 -- ASSERTION 1 :
338 -- ASSERTION 1 :
297 -- Coarse_time "changed" => FINE_TIME = 0
339 -- Coarse_time "changed" => FINE_TIME = 0
298 -- False after a TRANSITION !
340 -- False after a TRANSITION !
299 -----------------------------------------------------------------------------
341 -----------------------------------------------------------------------------
300 PROCESS (clk25MHz, resetn)
342 PROCESS (clk25MHz, resetn)
343 VARIABLE coarse_time_integer : INTEGER;
301 BEGIN -- PROCESS
344 BEGIN -- PROCESS
302 IF resetn = '0' THEN -- asynchronous reset (active low)
345 IF resetn = '0' THEN -- asynchronous reset (active low)
303 ASSERTION_1 <= '1';
346 ASSERTION_1 <= '1';
304 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
347 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
348 coarse_time_integer := to_integer(UNSIGNED(coarse_time));
349
305 IF coarse_time /= coarse_time_reg THEN
350 IF coarse_time /= coarse_time_reg THEN
306 IF fine_time /= X"0000" THEN
351 IF fine_time /= X"0000" THEN
307 IF fine_time /= X"0041" THEN
352 IF fine_time /= X"0041" THEN
308 ASSERTION_1 <= '0';
353 ASSERTION_1 <= '0';
354 REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** !! FAILED !! " SEVERITY note;
309 ELSE
355 ELSE
356 REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** false after a transition" SEVERITY note;
310 ASSERTION_1 <= 'U';
357 ASSERTION_1 <= 'U';
311 END IF;
358 END IF;
359 REPORT "COARSE_TIME_REG= " & integer'IMAGE(to_integer(UNSIGNED(coarse_time_reg))) SEVERITY note;
360 REPORT "COARSE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(coarse_time ))) SEVERITY note;
361 REPORT "FINE_TIME_REG = " & integer'IMAGE(to_integer(UNSIGNED(fine_time_reg ))) SEVERITY note;
362 REPORT "FINE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(fine_time ))) SEVERITY note;
312 ELSE
363 ELSE
313 ASSERTION_1 <= '1';
364 ASSERTION_1 <= '1';
314 END IF;
365 END IF;
315 END IF;
366 END IF;
316 END IF;
367 END IF;
317 END PROCESS;
368 END PROCESS;
318
369
319 -----------------------------------------------------------------------------
370 -----------------------------------------------------------------------------
320 -- ASSERTION 2 :
371 -- ASSERTION 2 :
321 -- tick => next(FINE_TIME) = 0
372 -- tick => next(FINE_TIME) = 0
322 -----------------------------------------------------------------------------
373 -----------------------------------------------------------------------------
323 PROCESS (clk25MHz, resetn)
374 PROCESS (clk25MHz, resetn)
324 BEGIN -- PROCESS
375 BEGIN -- PROCESS
325 IF resetn = '0' THEN -- asynchronous reset (active low)
376 IF resetn = '0' THEN -- asynchronous reset (active low)
326 ASSERTION_2 <= '1';
377 ASSERTION_2 <= '1';
327 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
378 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
328 IF tick_ongoing = '1' THEN
379 IF tick_ongoing = '1' THEN
329 IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN
380 IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN
330 IF fine_time /= X"0000" THEN
381 IF fine_time /= X"0000" THEN
382 REPORT "ASSERTION 2 : **Tick => NEXT(fineTime) = RESET(fineTime) !! FAILED !! " SEVERITY note;
331 ASSERTION_2 <= '0';
383 ASSERTION_2 <= '0';
384 REPORT "COARSE_TIME_REG= " & integer'IMAGE(to_integer(UNSIGNED(coarse_time_reg))) SEVERITY note;
385 REPORT "COARSE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(coarse_time ))) SEVERITY note;
386 REPORT "FINE_TIME_REG = " & integer'IMAGE(to_integer(UNSIGNED(fine_time_reg ))) SEVERITY note;
387 REPORT "FINE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(fine_time ))) SEVERITY note;
332 END IF;
388 END IF;
333 END IF;
389 END IF;
334 END IF;
390 END IF;
335 END IF;
391 END IF;
336 END PROCESS;
392 END PROCESS;
337
393
338 -----------------------------------------------------------------------------
394 -----------------------------------------------------------------------------
339 -- ASSERTION 3 :
395 -- ASSERTION 3 :
340 -- next(TIME) > TIME
396 -- next(TIME) > TIME
341 -- false if resynchro, or new coarse_time
397 -- false if resynchro, or new coarse_time
342 -----------------------------------------------------------------------------
398 -----------------------------------------------------------------------------
343 PROCESS (clk25MHz, resetn)
399 PROCESS (clk25MHz, resetn)
344 BEGIN -- PROCESS
400 BEGIN -- PROCESS
345 IF resetn = '0' THEN -- asynchronous reset (active low)
401 IF resetn = '0' THEN -- asynchronous reset (active low)
346 ASSERTION_3 <= '1';
402 ASSERTION_3 <= '1';
347 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
403 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
348 ASSERTION_3 <= '1';
404 ASSERTION_3 <= '1';
349 IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN
405 IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN
350 IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN
406 IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN
407 REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** can be false after a resynchro" SEVERITY note;
351 ASSERTION_3 <= 'U'; -- RESYNCHRO ....
408 ASSERTION_3 <= 'U'; -- RESYNCHRO ....
352 ELSE
409 ELSE
410 REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** can be false after a NEW coarse time" SEVERITY note;
353 ASSERTION_3 <= '0';
411 ASSERTION_3 <= '0';
354 END IF;
412 END IF;
413 REPORT "COARSE_TIME_REG= " & integer'IMAGE(to_integer(UNSIGNED(coarse_time_reg))) SEVERITY note;
414 REPORT "COARSE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(coarse_time ))) SEVERITY note;
415 REPORT "FINE_TIME_REG = " & integer'IMAGE(to_integer(UNSIGNED(fine_time_reg ))) SEVERITY note;
416 REPORT "FINE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(fine_time ))) SEVERITY note;
355 END IF;
417 END IF;
356 END IF;
418 END IF;
357 END PROCESS;
419 END PROCESS;
358
420
359
421
360 END beh;
422 END beh;
361
423
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