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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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use ieee.std_logic_textio.all;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use std.textio.all;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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LIBRARY lpp;
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USE lpp.lpp_lfr_management.ALL;
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ENTITY TB IS
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PORT (
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SIM_OK : OUT STD_LOGIC
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);
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END TB;
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ARCHITECTURE beh OF TB IS
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SIGNAL clk25MHz : STD_LOGIC := '0';
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SIGNAL resetn : STD_LOGIC;
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SIGNAL grspw_tick : STD_LOGIC;
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SIGNAL apbi : apb_slv_in_type;
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SIGNAL apbo : apb_slv_out_type;
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL TB_string : STRING(1 TO 8):= "12345678";
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SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL tick_ongoing : STD_LOGIC;
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SIGNAL ASSERTION_1 : STD_LOGIC;
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SIGNAL ASSERTION_2 : STD_LOGIC;
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SIGNAL ASSERTION_3 : STD_LOGIC;
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SIGNAL ASSERTION_3_ERROR : STD_LOGIC;
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SIGNAL end_of_simu : STD_LOGIC := '0';
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BEGIN -- beh
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apb_lfr_management_1: apb_lfr_management
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GENERIC MAP (
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tech => 0,
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pindex => 0,
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paddr => 0,
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pmask => 16#fff#,
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-- FIRST_DIVISION => 20,
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NB_SECOND_DESYNC => 4)
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PORT MAP (
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clk25MHz => clk25MHz,
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resetn_25MHz => resetn,
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grspw_tick => grspw_tick,
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apbi => apbi,
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apbo => apbo,
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HK_sample => (others => '0'),
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HK_val => '0',
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HK_sel => OPEN,
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DAC_SDO => OPEN,
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DAC_SCK => OPEN,
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DAC_SYNC => OPEN,
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DAC_CAL_EN => OPEN,
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coarse_time => coarse_time,
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fine_time => fine_time,
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LFR_soft_rstn => OPEN);
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-----------------------------------------------------------------------------
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-- CLOCK GEN
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PROCESS IS
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BEGIN -- PROCESS
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IF end_of_simu /= '1' THEN
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clk25MHz <= NOT clk25MHz;
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WAIT FOR 20000 ps;
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ELSE
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WAIT FOR 20 ps;
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ASSERT false REPORT "END OF TEST" SEVERITY note;
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WAIT;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "RESET "; REPORT "RESET" SEVERITY note;
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resetn <= '0';
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apbi.psel(0) <= '0';
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apbi.pwrite <= '0';
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apbi.penable <= '0';
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apbi.paddr <= (OTHERS => '0');
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apbi.pwdata <= (OTHERS => '0');
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grspw_tick <= '0';
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WAIT UNTIL clk25MHz = '1';
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WAIT UNTIL clk25MHz = '1';
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resetn <= '1';
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WAIT FOR 60 ms;
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---------------------------------------------------------------------------
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-- DESYNC TO SYNC
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---------------------------------------------------------------------------
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "TICK 1 "; REPORT "Tick 1" SEVERITY note;
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grspw_tick <= '1';------------------------------------------------------1
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WAIT UNTIL clk25MHz = '1';
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grspw_tick <= '0';
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WAIT FOR 53333 us;
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "TICK 2 "; REPORT "Tick 2" SEVERITY note;
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grspw_tick <= '1';------------------------------------------------------2
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WAIT UNTIL clk25MHz = '1';
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grspw_tick <= '0';
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WAIT FOR 56000 us;
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "TICK 3 "; REPORT "Tick 3" SEVERITY note;
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grspw_tick <= '1';------------------------------------------------------3
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WAIT UNTIL clk25MHz = '1';
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grspw_tick <= '0';
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WAIT FOR 200 ms;
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "CT new "; REPORT "CT new" SEVERITY note;
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-- WRITE NEW COARSE_TIME
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apbi.psel(0) <= '1';
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apbi.pwrite <= '1';
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apbi.penable <= '1';
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apbi.paddr <= X"00000004";
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apbi.pwdata <= X"00001234";
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WAIT UNTIL clk25MHz = '1';
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apbi.psel(0) <= '0';
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apbi.pwrite <= '0';
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apbi.penable <= '0';
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apbi.paddr <= (OTHERS => '0');
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apbi.pwdata <= (OTHERS => '0');
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WAIT UNTIL clk25MHz = '1';
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WAIT FOR 10 ms;
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "TICK 4 "; REPORT "Tick 4" SEVERITY note;
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grspw_tick <= '1';------------------------------------------------------3
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WAIT UNTIL clk25MHz = '1';
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grspw_tick <= '0';
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WAIT FOR 250 ms;
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "CT new "; REPORT "CT new" SEVERITY note;
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-- WRITE NEW COARSE_TIME
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apbi.psel(0) <= '1';
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apbi.pwrite <= '1';
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apbi.penable <= '1';
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apbi.paddr <= X"00000004";
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apbi.pwdata <= X"80005678";
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WAIT UNTIL clk25MHz = '1';
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apbi.psel(0) <= '0';
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apbi.pwrite <= '0';
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apbi.penable <= '0';
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apbi.paddr <= (OTHERS => '0');
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apbi.pwdata <= (OTHERS => '0');
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WAIT UNTIL clk25MHz = '1';
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WAIT FOR 10 ms;
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "TICK 5 "; REPORT "Tick 5" SEVERITY note;
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grspw_tick <= '1';------------------------------------------------------3
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WAIT UNTIL clk25MHz = '1';
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grspw_tick <= '0';
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WAIT FOR 20 ms;
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "CT new "; REPORT "CT new" SEVERITY note;
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-- WRITE NEW COARSE_TIME
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apbi.psel(0) <= '1';
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apbi.pwrite <= '1';
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apbi.penable <= '1';
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apbi.paddr <= X"00000004";
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apbi.pwdata <= X"00005678";
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WAIT UNTIL clk25MHz = '1';
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apbi.psel(0) <= '0';
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apbi.pwrite <= '0';
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apbi.penable <= '0';
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apbi.paddr <= (OTHERS => '0');
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apbi.pwdata <= (OTHERS => '0');
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WAIT UNTIL clk25MHz = '1';
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WAIT FOR 25 ms;
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WAIT UNTIL clk25MHz = '1';
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TB_string <= "Soft RST"; REPORT "Soft Reset" SEVERITY note;
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-- WRITE SOFT RESET
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apbi.psel(0) <= '1';
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apbi.pwrite <= '1';
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apbi.penable <= '1';
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apbi.paddr <= X"00000000";
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apbi.pwdata <= X"00000002";
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WAIT UNTIL clk25MHz = '1';
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apbi.psel(0) <= '0';
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apbi.pwrite <= '0';
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apbi.penable <= '0';
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apbi.paddr <= (OTHERS => '0');
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apbi.pwdata <= (OTHERS => '0');
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WAIT UNTIL clk25MHz = '1';
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WAIT FOR 250 ms;
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TB_string <= "READ 1 "; REPORT "Read 1" SEVERITY note;
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apbi.psel(0) <= '1';
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apbi.pwrite <= '0';
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apbi.penable <= '1';
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apbi.paddr <= X"00000008";
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WAIT UNTIL clk25MHz = '1';
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apbi.psel(0) <= '0';
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apbi.pwrite <= '0';
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apbi.penable <= '0';
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apbi.paddr <= (OTHERS => '0');
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WAIT UNTIL clk25MHz = '1';
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WAIT FOR 250 ms;
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TB_string <= "READ 2 "; REPORT "Read 2" SEVERITY note;
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apbi.psel(0) <= '1';
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apbi.pwrite <= '0';
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apbi.penable <= '1';
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apbi.paddr <= X"00000008";
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WAIT UNTIL clk25MHz = '1';
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apbi.psel(0) <= '0';
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apbi.pwrite <= '0';
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apbi.penable <= '0';
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apbi.paddr <= (OTHERS => '0');
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WAIT UNTIL clk25MHz = '1';
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WAIT FOR 250 ms;
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TB_string <= "READ 3 "; REPORT "Read 3" SEVERITY note;
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apbi.psel(0) <= '1';
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apbi.pwrite <= '0';
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apbi.penable <= '1';
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apbi.paddr <= X"00000008";
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WAIT UNTIL clk25MHz = '1';
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apbi.psel(0) <= '0';
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apbi.pwrite <= '0';
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apbi.penable <= '0';
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apbi.paddr <= (OTHERS => '0');
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WAIT UNTIL clk25MHz = '1';
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WAIT FOR 10 ps;
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end_of_simu <= '1';
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REPORT "end_of_simu set to 1" SEVERITY note;
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IF ASSERTION_1 = '1' THEN
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REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** OK" SEVERITY note;
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ELSE
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REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** !! FAILED !!" SEVERITY note;
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END IF;
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IF ASSERTION_2 = '1' THEN
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REPORT "ASSERTION 2 : **Tick => NEXT(fineTime) = RESET(fineTime) OK" SEVERITY note;
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ELSE
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REPORT "ASSERTION 2 : **Tick => NEXT(fineTime) = RESET(fineTime) !! FAILED !!" SEVERITY note;
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END IF;
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IF ASSERTION_3 = '1' THEN
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REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** OK" SEVERITY note;
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ELSE
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REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** !! FAILED !!" SEVERITY note;
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END IF;
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ASSERT false REPORT "*** END simulation ***" SEVERITY note;
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WAIT;
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END PROCESS;
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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global_time <= coarse_time & fine_time;
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PROCESS (clk25MHz, resetn)
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BEGIN -- PROCESS
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IF resetn = '0' THEN -- asynchronous reset (active low)
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coarse_time_reg <= (OTHERS => '0');
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fine_time_reg <= (OTHERS => '0');
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global_time_reg <= (OTHERS => '0');
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tick_ongoing <= '0';
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ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
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global_time_reg <= global_time;
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coarse_time_reg <= coarse_time;
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fine_time_reg <= fine_time;
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IF grspw_tick ='1' THEN
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tick_ongoing <= '1';
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ELSIF tick_ongoing = '1' THEN
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IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN
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tick_ongoing <= '0';
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- ASSERTION 1 :
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-- Coarse_time "changed" => FINE_TIME = 0
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-- False after a TRANSITION !
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-----------------------------------------------------------------------------
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PROCESS (clk25MHz, resetn)
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VARIABLE coarse_time_integer : INTEGER;
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BEGIN -- PROCESS
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IF resetn = '0' THEN -- asynchronous reset (active low)
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ASSERTION_1 <= '1';
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ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
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coarse_time_integer := to_integer(UNSIGNED(coarse_time));
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IF coarse_time /= coarse_time_reg THEN
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IF fine_time /= X"0000" THEN
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IF fine_time /= X"0041" THEN
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ASSERTION_1 <= '0';
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REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** !! FAILED !! " SEVERITY note;
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ELSE
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REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** false after a transition" SEVERITY note;
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ASSERTION_1 <= 'U';
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END IF;
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REPORT "COARSE_TIME_REG= " & integer'IMAGE(to_integer(UNSIGNED(coarse_time_reg))) SEVERITY note;
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REPORT "COARSE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(coarse_time ))) SEVERITY note;
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REPORT "FINE_TIME_REG = " & integer'IMAGE(to_integer(UNSIGNED(fine_time_reg ))) SEVERITY note;
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REPORT "FINE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(fine_time ))) SEVERITY note;
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ELSE
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ASSERTION_1 <= '1';
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- ASSERTION 2 :
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-- tick => next(FINE_TIME) = 0
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-----------------------------------------------------------------------------
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PROCESS (clk25MHz, resetn)
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BEGIN -- PROCESS
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IF resetn = '0' THEN -- asynchronous reset (active low)
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ASSERTION_2 <= '1';
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ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
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IF tick_ongoing = '1' THEN
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IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN
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IF fine_time /= X"0000" THEN
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REPORT "ASSERTION 2 : **Tick => NEXT(fineTime) = RESET(fineTime) !! FAILED !! " SEVERITY note;
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ASSERTION_2 <= '0';
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REPORT "COARSE_TIME_REG= " & integer'IMAGE(to_integer(UNSIGNED(coarse_time_reg))) SEVERITY note;
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REPORT "COARSE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(coarse_time ))) SEVERITY note;
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REPORT "FINE_TIME_REG = " & integer'IMAGE(to_integer(UNSIGNED(fine_time_reg ))) SEVERITY note;
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REPORT "FINE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(fine_time ))) SEVERITY note;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- ASSERTION 3 :
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-- next(TIME) > TIME
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-- false if resynchro, or new coarse_time
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|
|
-----------------------------------------------------------------------------
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PROCESS (clk25MHz, resetn)
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BEGIN -- PROCESS
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IF resetn = '0' THEN -- asynchronous reset (active low)
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ASSERTION_3 <= '1';
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ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
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ASSERTION_3 <= '1';
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IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN
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IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN
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REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** can be false after a resynchro" SEVERITY note;
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ASSERTION_3 <= 'U'; -- RESYNCHRO ....
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ELSE
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REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** can be false after a NEW coarse time" SEVERITY note;
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ASSERTION_3 <= '0';
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END IF;
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REPORT "COARSE_TIME_REG= " & integer'IMAGE(to_integer(UNSIGNED(coarse_time_reg))) SEVERITY note;
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REPORT "COARSE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(coarse_time ))) SEVERITY note;
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REPORT "FINE_TIME_REG = " & integer'IMAGE(to_integer(UNSIGNED(fine_time_reg ))) SEVERITY note;
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REPORT "FINE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(fine_time ))) SEVERITY note;
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END IF;
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END IF;
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END PROCESS;
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END beh;
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