@@ -1,82 +1,82 | |||
|
1 | 1 | VHDLIB=../.. |
|
2 | 2 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
|
3 | 3 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
|
4 | TOP=testbench | |
|
5 |
BOARD=LFR- |
|
|
4 | TOP=TB | |
|
5 | BOARD=LFR-FM | |
|
6 | 6 | include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc |
|
7 | 7 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) |
|
8 | 8 | UCF= |
|
9 | 9 | QSF= |
|
10 | 10 | EFFORT=high |
|
11 | 11 | XSTOPT= |
|
12 | 12 | SYNPOPT= |
|
13 | 13 | VHDLSYNFILES= |
|
14 |
VHDLSIMFILES= |
|
|
15 |
SIMTOP= |
|
|
14 | VHDLSIMFILES= TB.vhd | |
|
15 | SIMTOP=tb | |
|
16 | 16 | CLEAN=soft-clean |
|
17 | 17 | |
|
18 | 18 | TECHLIBS = axcelerator |
|
19 | 19 | |
|
20 | 20 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
|
21 | 21 | tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi |
|
22 | 22 | |
|
23 | 23 | DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \ |
|
24 | 24 | pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \ |
|
25 | 25 | grlfpc \ |
|
26 | 26 | ./dsp/lpp_fft_rtax \ |
|
27 | 27 | ./amba_lcd_16x2_ctrlr \ |
|
28 | 28 | ./general_purpose/lpp_AMR \ |
|
29 | 29 | ./general_purpose/lpp_balise \ |
|
30 | 30 | ./general_purpose/lpp_delay \ |
|
31 | 31 | ./lpp_bootloader \ |
|
32 | 32 | ./lpp_sim/CY7C1061DV33 \ |
|
33 | 33 | ./lpp_uart \ |
|
34 | 34 | ./lpp_usb \ |
|
35 | 35 | ./dsp/lpp_fft \ |
|
36 | 36 | ./lpp_leon3_soc \ |
|
37 | 37 | ./lpp_debug_lfr |
|
38 | 38 | |
|
39 | 39 | FILESKIP = i2cmst.vhd \ |
|
40 | 40 | APB_MULTI_DIODE.vhd \ |
|
41 | 41 | APB_MULTI_DIODE.vhd \ |
|
42 | 42 | Top_MatrixSpec.vhd \ |
|
43 | 43 | APB_FFT.vhd \ |
|
44 | 44 | lpp_lfr_ms_FFT.vhd \ |
|
45 | 45 | lpp_lfr_apbreg.vhd \ |
|
46 | 46 | CoreFFT.vhd \ |
|
47 | 47 | lpp_lfr_ms.vhd \ |
|
48 | 48 | lpp_lfr_sim_pkg.vhd \ |
|
49 | 49 | mtie_maps.vhd \ |
|
50 | 50 | ftsrctrlc.vhd \ |
|
51 | 51 | ftsdctrl.vhd \ |
|
52 | 52 | ftsrctrl8.vhd \ |
|
53 | 53 | ftmctrl.vhd \ |
|
54 | 54 | ftsdctrl64.vhd \ |
|
55 | 55 | ftahbram.vhd \ |
|
56 | 56 | ftahbram2.vhd \ |
|
57 | 57 | sramft.vhd \ |
|
58 | 58 | nandfctrlx.vhd |
|
59 | 59 | |
|
60 | 60 | include $(GRLIB)/bin/Makefile |
|
61 | 61 | include $(GRLIB)/software/leon3/Makefile |
|
62 | 62 | |
|
63 | 63 | ################## project specific targets ########################## |
|
64 | 64 | distclean:myclean |
|
65 | 65 | vsim:cp_for_vsim |
|
66 | 66 | |
|
67 | 67 | myclean: |
|
68 | 68 | rm -f input.txt output_fx.txt *.log |
|
69 | 69 | rm -rf ./2016* |
|
70 | 70 | |
|
71 | 71 | generate : |
|
72 | 72 | # python ./generate.py |
|
73 | 73 | |
|
74 | 74 | cp_for_vsim: generate |
|
75 | 75 | # cp ./input.txt simulation/ |
|
76 | 76 | |
|
77 | 77 | archivate: |
|
78 | 78 | xonsh ./archivate.xsh |
|
79 | 79 | |
|
80 | 80 | test: | generate ghdl ghdl-run archivate |
|
81 | 81 | |
|
82 | 82 |
@@ -1,361 +1,423 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | |
|
23 | 23 | LIBRARY IEEE; |
|
24 | use ieee.std_logic_textio.all; | |
|
24 | 25 | USE IEEE.STD_LOGIC_1164.ALL; |
|
25 | 26 | USE IEEE.NUMERIC_STD.ALL; |
|
27 | use std.textio.all; | |
|
28 | ||
|
26 | 29 |
|
|
27 | 30 | LIBRARY grlib; |
|
28 | 31 | USE grlib.amba.ALL; |
|
29 | 32 | USE grlib.stdlib.ALL; |
|
30 | 33 | USE grlib.devices.ALL; |
|
31 | 34 | |
|
32 | 35 | LIBRARY lpp; |
|
33 | 36 | USE lpp.lpp_lfr_management.ALL; |
|
34 | 37 | |
|
35 | 38 | ENTITY TB IS |
|
36 | 39 | |
|
37 | 40 | PORT ( |
|
38 | 41 | SIM_OK : OUT STD_LOGIC |
|
39 | 42 | ); |
|
40 | 43 | |
|
41 | 44 | END TB; |
|
42 | 45 | |
|
43 | 46 | |
|
44 | 47 | ARCHITECTURE beh OF TB IS |
|
45 | 48 | |
|
46 | 49 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
|
47 | 50 | |
|
48 | 51 | SIGNAL resetn : STD_LOGIC; |
|
49 | 52 | SIGNAL grspw_tick : STD_LOGIC; |
|
50 | 53 | SIGNAL apbi : apb_slv_in_type; |
|
51 | 54 | SIGNAL apbo : apb_slv_out_type; |
|
52 | 55 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
53 | 56 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
54 | 57 | |
|
55 | 58 | SIGNAL TB_string : STRING(1 TO 8):= "12345678"; |
|
56 | 59 | |
|
57 | 60 | SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | 61 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
59 | 62 | SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
60 | 63 | SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
61 | 64 | SIGNAL tick_ongoing : STD_LOGIC; |
|
62 | 65 | |
|
63 | 66 | SIGNAL ASSERTION_1 : STD_LOGIC; |
|
64 | 67 | SIGNAL ASSERTION_2 : STD_LOGIC; |
|
65 | 68 | SIGNAL ASSERTION_3 : STD_LOGIC; |
|
66 | ||
|
69 | SIGNAL ASSERTION_3_ERROR : STD_LOGIC; | |
|
70 | ||
|
71 | SIGNAL end_of_simu : STD_LOGIC := '0'; | |
|
72 | ||
|
67 | 73 | BEGIN -- beh |
|
68 | 74 | |
|
69 | 75 | apb_lfr_management_1: apb_lfr_management |
|
70 | 76 | GENERIC MAP ( |
|
71 | 77 | tech => 0, |
|
72 | 78 | pindex => 0, |
|
73 | 79 | paddr => 0, |
|
74 | 80 | pmask => 16#fff#, |
|
75 | 81 | -- FIRST_DIVISION => 20, |
|
76 | 82 | NB_SECOND_DESYNC => 4) |
|
77 | 83 | PORT MAP ( |
|
78 | 84 | clk25MHz => clk25MHz, |
|
79 | 85 | resetn_25MHz => resetn, |
|
80 | 86 | |
|
81 | 87 | grspw_tick => grspw_tick, |
|
82 | 88 | apbi => apbi, |
|
83 | 89 | apbo => apbo, |
|
84 | 90 | |
|
85 | 91 | HK_sample => (others => '0'), |
|
86 | 92 | HK_val => '0', |
|
87 | 93 | HK_sel => OPEN, |
|
88 | 94 | |
|
89 | 95 | DAC_SDO => OPEN, |
|
90 | 96 | DAC_SCK => OPEN, |
|
91 | 97 | DAC_SYNC => OPEN, |
|
92 | 98 | DAC_CAL_EN => OPEN, |
|
93 | 99 | |
|
94 | 100 | coarse_time => coarse_time, |
|
95 | 101 | fine_time => fine_time, |
|
96 | 102 | |
|
97 | 103 | LFR_soft_rstn => OPEN); |
|
104 | ||
|
105 | ----------------------------------------------------------------------------- | |
|
106 | -- CLOCK GEN | |
|
107 | PROCESS IS | |
|
108 | BEGIN -- PROCESS | |
|
109 | IF end_of_simu /= '1' THEN | |
|
110 | clk25MHz <= NOT clk25MHz; | |
|
111 | WAIT FOR 20000 ps; | |
|
112 | ELSE | |
|
113 | WAIT FOR 20 ps; | |
|
114 | ASSERT false REPORT "END OF TEST" SEVERITY note; | |
|
115 | WAIT; | |
|
116 | END IF; | |
|
117 | END PROCESS; | |
|
118 | ----------------------------------------------------------------------------- | |
|
98 | 119 | |
|
99 | clk25MHz <= NOT clk25MHz AFTER 20000 ps; | |
|
100 | 120 |
|
|
101 | 121 |
|
|
102 | 122 | BEGIN -- PROCESS |
|
103 | 123 | WAIT UNTIL clk25MHz = '1'; |
|
104 | TB_string <= "RESET "; | |
|
105 | ||
|
124 | TB_string <= "RESET "; REPORT "RESET" SEVERITY note; | |
|
125 | ||
|
106 | 126 | resetn <= '0'; |
|
107 | 127 | |
|
108 | 128 | apbi.psel(0) <= '0'; |
|
109 | 129 | apbi.pwrite <= '0'; |
|
110 | 130 | apbi.penable <= '0'; |
|
111 | 131 | apbi.paddr <= (OTHERS => '0'); |
|
112 | 132 | apbi.pwdata <= (OTHERS => '0'); |
|
113 | 133 | grspw_tick <= '0'; |
|
114 | 134 | WAIT UNTIL clk25MHz = '1'; |
|
115 | 135 | WAIT UNTIL clk25MHz = '1'; |
|
116 | 136 | resetn <= '1'; |
|
117 | 137 | WAIT FOR 60 ms; |
|
118 | 138 | --------------------------------------------------------------------------- |
|
119 | 139 | -- DESYNC TO SYNC |
|
120 | 140 | --------------------------------------------------------------------------- |
|
121 | 141 | WAIT UNTIL clk25MHz = '1'; |
|
122 | TB_string <= "TICK 1 "; | |
|
142 | TB_string <= "TICK 1 "; REPORT "Tick 1" SEVERITY note; | |
|
123 | 143 | grspw_tick <= '1';------------------------------------------------------1 |
|
124 | 144 | WAIT UNTIL clk25MHz = '1'; |
|
125 | 145 | grspw_tick <= '0'; |
|
126 | 146 | WAIT FOR 53333 us; |
|
127 | 147 | WAIT UNTIL clk25MHz = '1'; |
|
128 | TB_string <= "TICK 2 "; | |
|
148 | TB_string <= "TICK 2 "; REPORT "Tick 2" SEVERITY note; | |
|
129 | 149 | grspw_tick <= '1';------------------------------------------------------2 |
|
130 | 150 | WAIT UNTIL clk25MHz = '1'; |
|
131 | 151 | grspw_tick <= '0'; |
|
132 | 152 | WAIT FOR 56000 us; |
|
133 | 153 | WAIT UNTIL clk25MHz = '1'; |
|
134 | TB_string <= "TICK 3 "; | |
|
154 | TB_string <= "TICK 3 "; REPORT "Tick 3" SEVERITY note; | |
|
135 | 155 | grspw_tick <= '1';------------------------------------------------------3 |
|
136 | 156 | WAIT UNTIL clk25MHz = '1'; |
|
137 | 157 | grspw_tick <= '0'; |
|
138 | 158 | WAIT FOR 200 ms; |
|
139 | 159 | WAIT UNTIL clk25MHz = '1'; |
|
140 | TB_string <= "CT new "; | |
|
160 | TB_string <= "CT new "; REPORT "CT new" SEVERITY note; | |
|
141 | 161 | -- WRITE NEW COARSE_TIME |
|
142 | 162 | apbi.psel(0) <= '1'; |
|
143 | 163 | apbi.pwrite <= '1'; |
|
144 | 164 | apbi.penable <= '1'; |
|
145 | 165 | apbi.paddr <= X"00000004"; |
|
146 | 166 | apbi.pwdata <= X"00001234"; |
|
147 | 167 | WAIT UNTIL clk25MHz = '1'; |
|
148 | 168 | apbi.psel(0) <= '0'; |
|
149 | 169 | apbi.pwrite <= '0'; |
|
150 | 170 | apbi.penable <= '0'; |
|
151 | 171 | apbi.paddr <= (OTHERS => '0'); |
|
152 | 172 | apbi.pwdata <= (OTHERS => '0'); |
|
153 | 173 | WAIT UNTIL clk25MHz = '1'; |
|
154 | 174 | |
|
155 | 175 | WAIT FOR 10 ms; |
|
156 | 176 | WAIT UNTIL clk25MHz = '1'; |
|
157 | TB_string <= "TICK 4 "; | |
|
177 | TB_string <= "TICK 4 "; REPORT "Tick 4" SEVERITY note; | |
|
158 | 178 | grspw_tick <= '1';------------------------------------------------------3 |
|
159 | 179 | WAIT UNTIL clk25MHz = '1'; |
|
160 | 180 | grspw_tick <= '0'; |
|
161 | 181 | |
|
162 | 182 | |
|
163 | 183 | WAIT FOR 250 ms; |
|
164 | 184 | WAIT UNTIL clk25MHz = '1'; |
|
165 | TB_string <= "CT new "; | |
|
185 | TB_string <= "CT new "; REPORT "CT new" SEVERITY note; | |
|
166 | 186 | -- WRITE NEW COARSE_TIME |
|
167 | 187 | apbi.psel(0) <= '1'; |
|
168 | 188 | apbi.pwrite <= '1'; |
|
169 | 189 | apbi.penable <= '1'; |
|
170 | 190 | apbi.paddr <= X"00000004"; |
|
171 | 191 | apbi.pwdata <= X"80005678"; |
|
172 | 192 | WAIT UNTIL clk25MHz = '1'; |
|
173 | 193 | apbi.psel(0) <= '0'; |
|
174 | 194 | apbi.pwrite <= '0'; |
|
175 | 195 | apbi.penable <= '0'; |
|
176 | 196 | apbi.paddr <= (OTHERS => '0'); |
|
177 | 197 | apbi.pwdata <= (OTHERS => '0'); |
|
178 | 198 | WAIT UNTIL clk25MHz = '1'; |
|
179 | 199 | |
|
180 | 200 | WAIT FOR 10 ms; |
|
181 | 201 | WAIT UNTIL clk25MHz = '1'; |
|
182 | TB_string <= "TICK 5 "; | |
|
202 | TB_string <= "TICK 5 "; REPORT "Tick 5" SEVERITY note; | |
|
183 | 203 | grspw_tick <= '1';------------------------------------------------------3 |
|
184 | 204 | WAIT UNTIL clk25MHz = '1'; |
|
185 | 205 | grspw_tick <= '0'; |
|
186 | 206 | |
|
187 | 207 | |
|
188 | 208 | WAIT FOR 20 ms; |
|
189 | 209 | WAIT UNTIL clk25MHz = '1'; |
|
190 | TB_string <= "CT new "; | |
|
210 | TB_string <= "CT new "; REPORT "CT new" SEVERITY note; | |
|
191 | 211 | -- WRITE NEW COARSE_TIME |
|
192 | 212 | apbi.psel(0) <= '1'; |
|
193 | 213 | apbi.pwrite <= '1'; |
|
194 | 214 | apbi.penable <= '1'; |
|
195 | 215 | apbi.paddr <= X"00000004"; |
|
196 | 216 | apbi.pwdata <= X"00005678"; |
|
197 | 217 | WAIT UNTIL clk25MHz = '1'; |
|
198 | 218 | apbi.psel(0) <= '0'; |
|
199 | 219 | apbi.pwrite <= '0'; |
|
200 | 220 | apbi.penable <= '0'; |
|
201 | 221 | apbi.paddr <= (OTHERS => '0'); |
|
202 | 222 | apbi.pwdata <= (OTHERS => '0'); |
|
203 | 223 | WAIT UNTIL clk25MHz = '1'; |
|
204 | 224 | |
|
205 | 225 | WAIT FOR 25 ms; |
|
206 | 226 | WAIT UNTIL clk25MHz = '1'; |
|
207 | TB_string <= "Soft RST"; | |
|
227 | TB_string <= "Soft RST"; REPORT "Soft Reset" SEVERITY note; | |
|
208 | 228 | -- WRITE SOFT RESET |
|
209 | 229 | apbi.psel(0) <= '1'; |
|
210 | 230 | apbi.pwrite <= '1'; |
|
211 | 231 | apbi.penable <= '1'; |
|
212 | 232 | apbi.paddr <= X"00000000"; |
|
213 | 233 | apbi.pwdata <= X"00000002"; |
|
214 | 234 | WAIT UNTIL clk25MHz = '1'; |
|
215 | 235 | apbi.psel(0) <= '0'; |
|
216 | 236 | apbi.pwrite <= '0'; |
|
217 | 237 | apbi.penable <= '0'; |
|
218 | 238 | apbi.paddr <= (OTHERS => '0'); |
|
219 | 239 | apbi.pwdata <= (OTHERS => '0'); |
|
220 | 240 | WAIT UNTIL clk25MHz = '1'; |
|
221 | 241 | |
|
222 | 242 | WAIT FOR 250 ms; |
|
223 | TB_string <= "READ 1 "; | |
|
243 | TB_string <= "READ 1 "; REPORT "Read 1" SEVERITY note; | |
|
244 | apbi.psel(0) <= '1'; | |
|
245 | apbi.pwrite <= '0'; | |
|
246 | apbi.penable <= '1'; | |
|
247 | apbi.paddr <= X"00000008"; | |
|
248 | WAIT UNTIL clk25MHz = '1'; | |
|
249 | apbi.psel(0) <= '0'; | |
|
250 | apbi.pwrite <= '0'; | |
|
251 | apbi.penable <= '0'; | |
|
252 | apbi.paddr <= (OTHERS => '0'); | |
|
253 | WAIT UNTIL clk25MHz = '1'; | |
|
254 | WAIT FOR 250 ms; | |
|
255 | TB_string <= "READ 2 "; REPORT "Read 2" SEVERITY note; | |
|
224 | 256 | apbi.psel(0) <= '1'; |
|
225 | 257 | apbi.pwrite <= '0'; |
|
226 | 258 | apbi.penable <= '1'; |
|
227 | 259 | apbi.paddr <= X"00000008"; |
|
228 | 260 | WAIT UNTIL clk25MHz = '1'; |
|
229 | 261 | apbi.psel(0) <= '0'; |
|
230 | 262 | apbi.pwrite <= '0'; |
|
231 | 263 | apbi.penable <= '0'; |
|
232 | 264 | apbi.paddr <= (OTHERS => '0'); |
|
233 | 265 | WAIT UNTIL clk25MHz = '1'; |
|
234 | 266 | WAIT FOR 250 ms; |
|
235 |
TB_string <= "READ |
|
|
267 | TB_string <= "READ 3 "; REPORT "Read 3" SEVERITY note; | |
|
236 | 268 | apbi.psel(0) <= '1'; |
|
237 | 269 | apbi.pwrite <= '0'; |
|
238 | 270 | apbi.penable <= '1'; |
|
239 | 271 | apbi.paddr <= X"00000008"; |
|
240 | 272 | WAIT UNTIL clk25MHz = '1'; |
|
241 | 273 | apbi.psel(0) <= '0'; |
|
242 | 274 | apbi.pwrite <= '0'; |
|
243 | 275 | apbi.penable <= '0'; |
|
244 | 276 | apbi.paddr <= (OTHERS => '0'); |
|
245 | 277 | WAIT UNTIL clk25MHz = '1'; |
|
246 |
WAIT FOR |
|
|
247 | TB_string <= "READ 3 "; | |
|
248 | apbi.psel(0) <= '1'; | |
|
249 | apbi.pwrite <= '0'; | |
|
250 | apbi.penable <= '1'; | |
|
251 | apbi.paddr <= X"00000008"; | |
|
252 | WAIT UNTIL clk25MHz = '1'; | |
|
253 | apbi.psel(0) <= '0'; | |
|
254 | apbi.pwrite <= '0'; | |
|
255 | apbi.penable <= '0'; | |
|
256 | apbi.paddr <= (OTHERS => '0'); | |
|
257 | WAIT UNTIL clk25MHz = '1'; | |
|
278 | WAIT FOR 10 ps; | |
|
279 | end_of_simu <= '1'; | |
|
280 | REPORT "end_of_simu set to 1" SEVERITY note; | |
|
281 | ||
|
282 | IF ASSERTION_1 = '1' THEN | |
|
283 | REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** OK" SEVERITY note; | |
|
284 | ELSE | |
|
285 | REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** !! FAILED !!" SEVERITY note; | |
|
286 | END IF; | |
|
258 | 287 | |
|
288 | IF ASSERTION_2 = '1' THEN | |
|
289 | REPORT "ASSERTION 2 : **Tick => NEXT(fineTime) = RESET(fineTime) OK" SEVERITY note; | |
|
290 | ELSE | |
|
291 | REPORT "ASSERTION 2 : **Tick => NEXT(fineTime) = RESET(fineTime) !! FAILED !!" SEVERITY note; | |
|
292 | END IF; | |
|
293 | ||
|
294 | IF ASSERTION_3 = '1' THEN | |
|
295 | REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** OK" SEVERITY note; | |
|
296 | ELSE | |
|
297 | REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** !! FAILED !!" SEVERITY note; | |
|
298 | END IF; | |
|
259 | 299 | |
|
260 |
|
|
|
261 | REPORT "*** END simulation ***" SEVERITY failure; | |
|
300 | ||
|
301 | ||
|
302 | ||
|
303 | ASSERT false REPORT "*** END simulation ***" SEVERITY note; | |
|
262 | 304 | WAIT; |
|
263 | 305 | |
|
264 | 306 | END PROCESS; |
|
265 | 307 | |
|
266 | 308 | |
|
267 | 309 | ----------------------------------------------------------------------------- |
|
268 | 310 | -- |
|
269 | 311 | ----------------------------------------------------------------------------- |
|
270 | 312 | |
|
271 | 313 | global_time <= coarse_time & fine_time; |
|
272 | 314 | |
|
273 | 315 | PROCESS (clk25MHz, resetn) |
|
274 | 316 | BEGIN -- PROCESS |
|
275 | 317 | IF resetn = '0' THEN -- asynchronous reset (active low) |
|
276 | 318 | coarse_time_reg <= (OTHERS => '0'); |
|
277 | 319 | fine_time_reg <= (OTHERS => '0'); |
|
278 | 320 | global_time_reg <= (OTHERS => '0'); |
|
279 | 321 | tick_ongoing <= '0'; |
|
280 | 322 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge |
|
281 | 323 | global_time_reg <= global_time; |
|
282 | 324 | coarse_time_reg <= coarse_time; |
|
283 | 325 | fine_time_reg <= fine_time; |
|
284 | 326 | IF grspw_tick ='1' THEN |
|
285 | 327 | tick_ongoing <= '1'; |
|
286 | 328 | ELSIF tick_ongoing = '1' THEN |
|
287 | 329 | IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN |
|
288 | 330 | tick_ongoing <= '0'; |
|
289 | 331 | END IF; |
|
290 | 332 | END IF; |
|
291 | 333 | |
|
292 | 334 | END IF; |
|
293 | 335 | END PROCESS; |
|
294 | 336 | |
|
295 | 337 | ----------------------------------------------------------------------------- |
|
296 | 338 | -- ASSERTION 1 : |
|
297 | 339 | -- Coarse_time "changed" => FINE_TIME = 0 |
|
298 | 340 | -- False after a TRANSITION ! |
|
299 | 341 | ----------------------------------------------------------------------------- |
|
300 | 342 | PROCESS (clk25MHz, resetn) |
|
343 | VARIABLE coarse_time_integer : INTEGER; | |
|
301 | 344 | BEGIN -- PROCESS |
|
302 | 345 | IF resetn = '0' THEN -- asynchronous reset (active low) |
|
303 | 346 | ASSERTION_1 <= '1'; |
|
304 | 347 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge |
|
348 | coarse_time_integer := to_integer(UNSIGNED(coarse_time)); | |
|
349 | ||
|
305 | 350 |
|
|
306 | 351 | IF fine_time /= X"0000" THEN |
|
307 | 352 | IF fine_time /= X"0041" THEN |
|
308 | 353 | ASSERTION_1 <= '0'; |
|
354 | REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** !! FAILED !! " SEVERITY note; | |
|
309 | 355 | ELSE |
|
356 | REPORT "ASSERTION 1 : **UPDATE(CoarseTime) => RESET(fineTime)** false after a transition" SEVERITY note; | |
|
310 | 357 | ASSERTION_1 <= 'U'; |
|
311 | 358 | END IF; |
|
359 | REPORT "COARSE_TIME_REG= " & integer'IMAGE(to_integer(UNSIGNED(coarse_time_reg))) SEVERITY note; | |
|
360 | REPORT "COARSE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(coarse_time ))) SEVERITY note; | |
|
361 | REPORT "FINE_TIME_REG = " & integer'IMAGE(to_integer(UNSIGNED(fine_time_reg ))) SEVERITY note; | |
|
362 | REPORT "FINE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(fine_time ))) SEVERITY note; | |
|
312 | 363 | ELSE |
|
313 | 364 | ASSERTION_1 <= '1'; |
|
314 | 365 | END IF; |
|
315 | 366 | END IF; |
|
316 | 367 | END IF; |
|
317 | 368 | END PROCESS; |
|
318 | 369 | |
|
319 | 370 | ----------------------------------------------------------------------------- |
|
320 | 371 | -- ASSERTION 2 : |
|
321 | 372 | -- tick => next(FINE_TIME) = 0 |
|
322 | 373 | ----------------------------------------------------------------------------- |
|
323 | 374 | PROCESS (clk25MHz, resetn) |
|
324 | 375 | BEGIN -- PROCESS |
|
325 | 376 | IF resetn = '0' THEN -- asynchronous reset (active low) |
|
326 | 377 | ASSERTION_2 <= '1'; |
|
327 | 378 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge |
|
328 | 379 | IF tick_ongoing = '1' THEN |
|
329 | 380 | IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN |
|
330 | 381 | IF fine_time /= X"0000" THEN |
|
382 | REPORT "ASSERTION 2 : **Tick => NEXT(fineTime) = RESET(fineTime) !! FAILED !! " SEVERITY note; | |
|
331 | 383 | ASSERTION_2 <= '0'; |
|
384 | REPORT "COARSE_TIME_REG= " & integer'IMAGE(to_integer(UNSIGNED(coarse_time_reg))) SEVERITY note; | |
|
385 | REPORT "COARSE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(coarse_time ))) SEVERITY note; | |
|
386 | REPORT "FINE_TIME_REG = " & integer'IMAGE(to_integer(UNSIGNED(fine_time_reg ))) SEVERITY note; | |
|
387 | REPORT "FINE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(fine_time ))) SEVERITY note; | |
|
332 | 388 | END IF; |
|
333 | 389 | END IF; |
|
334 | 390 | END IF; |
|
335 | 391 | END IF; |
|
336 | 392 | END PROCESS; |
|
337 | 393 | |
|
338 | 394 | ----------------------------------------------------------------------------- |
|
339 | 395 | -- ASSERTION 3 : |
|
340 | 396 | -- next(TIME) > TIME |
|
341 | 397 | -- false if resynchro, or new coarse_time |
|
342 | 398 | ----------------------------------------------------------------------------- |
|
343 | 399 | PROCESS (clk25MHz, resetn) |
|
344 | 400 | BEGIN -- PROCESS |
|
345 | 401 | IF resetn = '0' THEN -- asynchronous reset (active low) |
|
346 | ASSERTION_3 <= '1'; | |
|
402 | ASSERTION_3 <= '1'; | |
|
347 | 403 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge |
|
348 | 404 | ASSERTION_3 <= '1'; |
|
349 | 405 | IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN |
|
350 | 406 | IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN |
|
407 | REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** can be false after a resynchro" SEVERITY note; | |
|
351 | 408 | ASSERTION_3 <= 'U'; -- RESYNCHRO .... |
|
352 | 409 | ELSE |
|
410 | REPORT "ASSERTION 3 : **NEXT(TIME) > TIME ** can be false after a NEW coarse time" SEVERITY note; | |
|
353 | 411 | ASSERTION_3 <= '0'; |
|
354 | 412 | END IF; |
|
413 | REPORT "COARSE_TIME_REG= " & integer'IMAGE(to_integer(UNSIGNED(coarse_time_reg))) SEVERITY note; | |
|
414 | REPORT "COARSE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(coarse_time ))) SEVERITY note; | |
|
415 | REPORT "FINE_TIME_REG = " & integer'IMAGE(to_integer(UNSIGNED(fine_time_reg ))) SEVERITY note; | |
|
416 | REPORT "FINE_TIME = " & integer'IMAGE(to_integer(UNSIGNED(fine_time ))) SEVERITY note; | |
|
355 | 417 | END IF; |
|
356 | 418 | END IF; |
|
357 | 419 | END PROCESS; |
|
358 | 420 | |
|
359 | 421 | |
|
360 | 422 | END beh; |
|
361 | 423 |
General Comments 0
You need to be logged in to leave comments.
Login now