@@ -32,7 +32,8 port( | |||||
32 | Acq : in std_logic; |
|
32 | Acq : in std_logic; | |
33 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
33 | Data : in std_logic_vector(Data_SZ-1 downto 0); | |
34 | Write : in std_logic; |
|
34 | Write : in std_logic; | |
35 |
|
|
35 | Valid : in std_logic; | |
|
36 | -- Full : in std_logic_vector(1 downto 0); | |||
36 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
37 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); | |
37 | FifoWrite : out std_logic_vector(1 downto 0); |
|
38 | FifoWrite : out std_logic_vector(1 downto 0); | |
38 | Pong : out std_logic; |
|
39 | Pong : out std_logic; | |
@@ -47,7 +48,7 type etat is (eX,e0,e1,e2); | |||||
47 | signal ect : etat; |
|
48 | signal ect : etat; | |
48 |
|
49 | |||
49 | signal Pong_int : std_logic; |
|
50 | signal Pong_int : std_logic; | |
50 | signal FifoCpt : integer range 0 to 1 := 0; |
|
51 | --signal FifoCpt : integer range 0 to 1 := 0; | |
51 |
|
52 | |||
52 | begin |
|
53 | begin | |
53 |
|
54 | |||
@@ -63,7 +64,8 begin | |||||
63 | case ect is |
|
64 | case ect is | |
64 |
|
65 | |||
65 | when e0 => |
|
66 | when e0 => | |
66 | if(Full(FifoCpt) = '1')then |
|
67 | -- if(Full(FifoCpt) = '1')then | |
|
68 | if(Valid = '1')then | |||
67 | Pong_int <= not Pong_int; |
|
69 | Pong_int <= not Pong_int; | |
68 | ect <= e1; |
|
70 | ect <= e1; | |
69 | end if; |
|
71 | end if; | |
@@ -88,7 +90,7 begin | |||||
88 | FifoData <= Data & Data; |
|
90 | FifoData <= Data & Data; | |
89 | Pong <= Pong_int; |
|
91 | Pong <= Pong_int; | |
90 |
|
92 | |||
91 | FifoCpt <= 0 when Pong_int='0' else 1; |
|
93 | --FifoCpt <= 0 when Pong_int='0' else 1; | |
92 |
|
94 | |||
93 | FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; |
|
95 | FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; | |
94 |
|
96 |
@@ -35,9 +35,11 entity MatriceSpectrale is | |||||
35 |
|
35 | |||
36 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
36 | FifoIN_Full : in std_logic_vector(4 downto 0); | |
37 | SetReUse : in std_logic_vector(4 downto 0); |
|
37 | SetReUse : in std_logic_vector(4 downto 0); | |
38 | FifoOUT_Full : in std_logic_vector(1 downto 0); |
|
38 | -- FifoOUT_Full : in std_logic_vector(1 downto 0); | |
|
39 | Valid : in std_logic; | |||
39 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
40 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
40 | ACQ : in std_logic; |
|
41 | ACQ : in std_logic; | |
|
42 | SM_Write : out std_logic; | |||
41 | FlagError : out std_logic; |
|
43 | FlagError : out std_logic; | |
42 | Pong : out std_logic; |
|
44 | Pong : out std_logic; | |
43 | Statu : out std_logic_vector(3 downto 0); |
|
45 | Statu : out std_logic_vector(3 downto 0); | |
@@ -76,9 +78,10 begin | |||||
76 |
|
78 | |||
77 | DISP : entity work.Dispatch |
|
79 | DISP : entity work.Dispatch | |
78 | generic map(Result_SZ) |
|
80 | generic map(Result_SZ) | |
79 |
port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write, |
|
81 | port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError); | |
80 |
|
82 | |||
81 | Statu <= TopSM_Statu; |
|
83 | Statu <= TopSM_Statu; | |
|
84 | SM_Write <= Matrix_Write; | |||
82 |
|
85 | |||
83 | end architecture; |
|
86 | end architecture; | |
84 |
|
87 |
@@ -66,9 +66,11 component MatriceSpectrale is | |||||
66 |
|
66 | |||
67 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
67 | FifoIN_Full : in std_logic_vector(4 downto 0); | |
68 | SetReUse : in std_logic_vector(4 downto 0); |
|
68 | SetReUse : in std_logic_vector(4 downto 0); | |
69 | FifoOUT_Full : in std_logic_vector(1 downto 0); |
|
69 | -- FifoOUT_Full : in std_logic_vector(1 downto 0); | |
|
70 | Valid : in std_logic; | |||
70 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
71 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
71 | ACQ : in std_logic; |
|
72 | ACQ : in std_logic; | |
|
73 | SM_Write : out std_logic; | |||
72 | FlagError : out std_logic; |
|
74 | FlagError : out std_logic; | |
73 | Pong : out std_logic; |
|
75 | Pong : out std_logic; | |
74 | Statu : out std_logic_vector(3 downto 0); |
|
76 | Statu : out std_logic_vector(3 downto 0); | |
@@ -200,7 +202,8 port( | |||||
200 | Acq : in std_logic; |
|
202 | Acq : in std_logic; | |
201 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
203 | Data : in std_logic_vector(Data_SZ-1 downto 0); | |
202 | Write : in std_logic; |
|
204 | Write : in std_logic; | |
203 |
|
|
205 | Valid : in std_logic; | |
|
206 | -- Full : in std_logic_vector(1 downto 0); | |||
204 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
207 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); | |
205 | FifoWrite : out std_logic_vector(1 downto 0); |
|
208 | FifoWrite : out std_logic_vector(1 downto 0); | |
206 | Pong : out std_logic; |
|
209 | Pong : out std_logic; |
General Comments 0
You need to be logged in to leave comments.
Login now