# HG changeset patch
# User martin
# Date 2013-05-10 12:02:38
# Node ID 168d889db49dbabff6efb522b2edca1799d66548
# Parent  fe54b5dba7c3305ad7ea3b6316f30daeed3e7860

UP

diff --git a/lib/lpp/lpp_matrix/Dispatch.vhd b/lib/lpp/lpp_matrix/Dispatch.vhd
--- a/lib/lpp/lpp_matrix/Dispatch.vhd
+++ b/lib/lpp/lpp_matrix/Dispatch.vhd
@@ -32,7 +32,8 @@ port(
     Acq         : in std_logic;
     Data        : in std_logic_vector(Data_SZ-1 downto 0);
     Write       : in std_logic;
-    Full        : in std_logic_vector(1 downto 0);
+    Valid       : in std_logic;
+--    Full        : in std_logic_vector(1 downto 0);
     FifoData    : out std_logic_vector(2*Data_SZ-1 downto 0);
     FifoWrite   : out std_logic_vector(1 downto 0);
     Pong        : out std_logic;
@@ -47,7 +48,7 @@ type etat is (eX,e0,e1,e2);
 signal ect : etat;
 
 signal Pong_int : std_logic;
-signal FifoCpt : integer range 0 to 1 := 0;
+--signal FifoCpt : integer range 0 to 1 := 0;
 
 begin
 
@@ -63,7 +64,8 @@ begin
             case ect is
 
                 when e0 =>
-                    if(Full(FifoCpt) = '1')then
+--                    if(Full(FifoCpt) = '1')then
+                    if(Valid = '1')then
                         Pong_int <= not Pong_int;
                         ect <= e1;
                     end if;
@@ -88,7 +90,7 @@ begin
 FifoData <= Data & Data;
 Pong <= Pong_int;
 
-FifoCpt <= 0 when Pong_int='0' else 1;
+--FifoCpt <= 0 when Pong_int='0' else 1;
 
 FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1';
                     
diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
--- a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
+++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
@@ -35,9 +35,11 @@ entity MatriceSpectrale is
 
         FifoIN_Full     : in std_logic_vector(4 downto 0);
         SetReUse        : in std_logic_vector(4 downto 0);
-        FifoOUT_Full    : in std_logic_vector(1 downto 0);
+--        FifoOUT_Full    : in std_logic_vector(1 downto 0);
+        Valid           : in std_logic;
         Data_IN         : in std_logic_vector((5*Input_SZ)-1 downto 0);
         ACQ             : in std_logic;
+        SM_Write        : out std_logic;
         FlagError       : out std_logic;
         Pong            : out std_logic;
         Statu           : out std_logic_vector(3 downto 0);
@@ -76,9 +78,10 @@ begin
 
     DISP : entity work.Dispatch
         generic map(Result_SZ)
-        port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
+        port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
 
 Statu <= TopSM_Statu;
+SM_Write <= Matrix_Write;
 
 end architecture;
 
diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd
--- a/lib/lpp/lpp_matrix/lpp_matrix.vhd
+++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd
@@ -66,9 +66,11 @@ component MatriceSpectrale is
 
         FifoIN_Full     : in std_logic_vector(4 downto 0);
         SetReUse        : in std_logic_vector(4 downto 0);
-        FifoOUT_Full    : in std_logic_vector(1 downto 0);
+--        FifoOUT_Full    : in std_logic_vector(1 downto 0);
+        Valid           : in std_logic;
         Data_IN         : in std_logic_vector((5*Input_SZ)-1 downto 0);
         ACQ             : in std_logic;
+        SM_Write        : out std_logic;
         FlagError       : out std_logic;
         Pong            : out std_logic;
         Statu           : out std_logic_vector(3 downto 0);
@@ -200,7 +202,8 @@ port(
     Acq         : in std_logic;
     Data        : in std_logic_vector(Data_SZ-1 downto 0);
     Write       : in std_logic;
-    Full        : in std_logic_vector(1 downto 0);
+    Valid       : in std_logic;
+--    Full        : in std_logic_vector(1 downto 0);
     FifoData    : out std_logic_vector(2*Data_SZ-1 downto 0);
     FifoWrite   : out std_logic_vector(1 downto 0);
     Pong        : out std_logic;