HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r175:168d889db49d

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r175:168d889db49d

lib/lpp/lpp_matrix/Dispatch.vhd +6 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                   Mail : martin.morlot@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
             entity Dispatch is
             generic(
                 Data_SZ  : integer := 32);
             port(
                 clk         : in std_logic;
                 reset       : in std_logic;
                 Acq         : in std_logic;
                 Data        : in std_logic_vector(Data_SZ-1 downto 0);
                 Write       : in std_logic;
-                Full        : in std_logic_vector(1 downto 0);
+                Valid       : in std_logic;
+            --    Full        : in std_logic_vector(1 downto 0);
                 FifoData    : out std_logic_vector(2*Data_SZ-1 downto 0);
                 FifoWrite   : out std_logic_vector(1 downto 0);
                 Pong        : out std_logic;
                 Error       : out std_logic
             );
             end entity;
             architecture ar_Dispatch of Dispatch is
             type etat is (eX,e0,e1,e2);
             signal ect : etat;
             signal Pong_int : std_logic;
-            signal FifoCpt : integer range 0 to 1 := 0;
+            --signal FifoCpt : integer range 0 to 1 := 0;
             begin
              process (clk,reset)
                 begin
                     if(reset='0')then
                         Pong_int    <= '0';
                         Error   <= '0';
                         ect <= e0;
                     elsif(clk' event and clk='1')then
                         case ect is
                             when e0 =>
-                                if(Full(FifoCpt) = '1')then
+            --                    if(Full(FifoCpt) = '1')then
+                                if(Valid = '1')then
                                     Pong_int <= not Pong_int;
                                     ect <= e1;
                                 end if;
                             when e1 =>
                                 if(Acq = '0')then
                                     Error <= '1';
                                     ect <= e1;
                                 else
                                     Error <= '0';
                                     ect <= e0;
                                 end if;
                             when others =>
                                 null;
                         end case;
                     end if;
                 end process;
             FifoData <= Data & Data;
             Pong <= Pong_int;
-            FifoCpt <= 0 when Pong_int='0' else 1;
+            --FifoCpt <= 0 when Pong_int='0' else 1;
             FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1';
             end architecture;

lib/lpp/lpp_matrix/MatriceSpectrale.vhd +5 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
             --library lpp;
             --use lpp.lpp_matrix.all;
             entity MatriceSpectrale is
               generic(
                   Input_SZ  : integer := 16;
                   Result_SZ : integer := 32);
                 port(
                     clkm            : in std_logic;
                     rstn            : in std_logic;
                     FifoIN_Full     : in std_logic_vector(4 downto 0);
                     SetReUse        : in std_logic_vector(4 downto 0);
-                    FifoOUT_Full    : in std_logic_vector(1 downto 0);
+            --        FifoOUT_Full    : in std_logic_vector(1 downto 0);
+                    Valid           : in std_logic;
                     Data_IN         : in std_logic_vector((5*Input_SZ)-1 downto 0);
                     ACQ             : in std_logic;
+                    SM_Write        : out std_logic;
                     FlagError       : out std_logic;
                     Pong            : out std_logic;
                     Statu           : out std_logic_vector(3 downto 0);
                     Write           : out std_logic_vector(1 downto 0);
                     Read            : out std_logic_vector(4 downto 0);
                     ReUse           : out std_logic_vector(4 downto 0);
                     Data_OUT        : out std_logic_vector((2*Result_SZ)-1 downto 0)
                     );
             end entity;
             architecture ar_MatriceSpectrale of MatriceSpectrale is
             signal Matrix_Write     : std_logic;
             signal Matrix_Read      : std_logic_vector(1 downto 0);
             signal Matrix_Result    : std_logic_vector(31 downto 0);
             signal TopSM_Start      : std_logic;
             signal TopSM_Statu      : std_logic_vector(3 downto 0);
             signal TopSM_Data1      : std_logic_vector(15 downto 0);
             signal TopSM_Data2      : std_logic_vector(15 downto 0);
             begin
                 CTRL0 : entity work.ReUse_CTRLR
                     port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
                 TopSM : entity work.TopSpecMatrix
                     generic map (Input_SZ)
                     port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
                 SM : entity work.SpectralMatrix
                     generic map (Input_SZ,Result_SZ)
                     port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
                 DISP : entity work.Dispatch
                     generic map(Result_SZ)
-                    port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
+                    port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
             Statu <= TopSM_Statu;
+            SM_Write <= Matrix_Write;
             end architecture;

lib/lpp/lpp_matrix/lpp_matrix.vhd +5 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_matrix is
             component APB_Matrix is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8;
                 Input_SZ : integer := 16;
                 Result_SZ : integer := 32);
               port (
                 clk       : in std_logic;
                 rst     : in std_logic;
                 FIFO1     : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2     : in std_logic_vector(Input_SZ-1 downto 0);
                 Full      : in std_logic_vector(1 downto 0);
                 Empty     : in std_logic_vector(1 downto 0);
                 ReadFIFO  : out std_logic_vector(1 downto 0);
                 FullFIFO  : in std_logic;
                 WriteFIFO : out std_logic;
                 Result    : out std_logic_vector(Result_SZ-1 downto 0);
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
             );
             end component;
             component MatriceSpectrale is
               generic(
                   Input_SZ  : integer := 16;
                   Result_SZ : integer := 32);
                 port(
                     clkm            : in std_logic;
                     rstn            : in std_logic;
                     FifoIN_Full     : in std_logic_vector(4 downto 0);
                     SetReUse        : in std_logic_vector(4 downto 0);
-                    FifoOUT_Full    : in std_logic_vector(1 downto 0);
+            --        FifoOUT_Full    : in std_logic_vector(1 downto 0);
+                    Valid           : in std_logic;
                     Data_IN         : in std_logic_vector((5*Input_SZ)-1 downto 0);
                     ACQ             : in std_logic;
+                    SM_Write        : out std_logic;
                     FlagError       : out std_logic;
                     Pong            : out std_logic;
                     Statu           : out std_logic_vector(3 downto 0);
                     Write           : out std_logic_vector(1 downto 0);
                     Read            : out std_logic_vector(4 downto 0);
                     ReUse           : out std_logic_vector(4 downto 0);
                     Data_OUT        : out std_logic_vector((2*Result_SZ)-1 downto 0)
                     );
             end component;
             component TopSpecMatrix is
             generic(
                 Input_SZ  : integer := 16);
             port(
                 clk         : in std_logic;
                 rstn       : in std_logic;
                 Write       : in std_logic;
                 ReadIn      : in std_logic_vector(1 downto 0);
                 Full        : in std_logic_vector(4 downto 0);
                 Data        : in std_logic_vector((5*Input_SZ)-1 downto 0);
                 Start       : out std_logic;
                 ReadOut     : out std_logic_vector(4 downto 0);
                 Statu       : out std_logic_vector(3 downto 0);
                 DATA1       : out std_logic_vector(Input_SZ-1 downto 0);
                 DATA2       : out std_logic_vector(Input_SZ-1 downto 0)
             );
             end component;
             component Top_MatrixSpec is
             generic(
                 Input_SZ  : integer := 16;
                 Result_SZ : integer := 32);
             port(
                 clk       : in std_logic;
                 reset     : in std_logic;
                 Statu     : in std_logic_vector(3 downto 0);
                 FIFO1     : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2     : in std_logic_vector(Input_SZ-1 downto 0);
                 Full      : in std_logic_vector(1 downto 0);
                 Empty     : in std_logic_vector(1 downto 0);
                 ReadFIFO  : out std_logic_vector(1 downto 0);
                 FullFIFO  : in std_logic;
                 WriteFIFO : out std_logic;
                 Result    : out std_logic_vector(Result_SZ-1 downto 0)
             );
             end component;
             component SpectralMatrix is
             generic(
                 Input_SZ  : integer := 16;
                 Result_SZ : integer := 32);
             port(
                 clk        : in std_logic;
                 reset      : in std_logic;
                 Start      : in std_logic;
                 FIFO1      : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2      : in std_logic_vector(Input_SZ-1 downto 0);
                 Statu      : in std_logic_vector(3 downto 0);
             --    FullFIFO   : in std_logic;
                 ReadFIFO   : out std_logic_vector(1 downto 0);
                 WriteFIFO  : out std_logic;
                 Result     : out std_logic_vector(Result_SZ-1 downto 0)
             );
             end component;
             component Matrix is
               generic(
                   Input_SZ : integer := 16);
               port(
                   clk        : in std_logic;
                   raz        : in std_logic;
                   IN1        : in std_logic_vector(Input_SZ-1 downto 0);
                   IN2        : in std_logic_vector(Input_SZ-1 downto 0);
                   Take       : in std_logic;
                   Received   : in std_logic;
                   Conjugate  : in std_logic;
                   Valid      : out std_logic;
                   Read       : out std_logic;
                   Result     : out std_logic_vector(2*Input_SZ-1 downto 0)
             );
             end component;
             component GetResult is
             generic(
                 Result_SZ : integer := 32);
             port(
                 clk       : in  std_logic;
                 raz       : in  std_logic;
                 Valid     : in  std_logic;
                 Conjugate : in  std_logic;
                 Res       : in std_logic_vector(Result_SZ-1 downto 0);
             --    Full      : in std_logic;
                 WriteFIFO : out std_logic;
                 Received  : out std_logic;
                 Result    : out std_logic_vector(Result_SZ-1 downto 0)
             );
             end component;
             component TopMatrix_PDR is
             generic(
                 Input_SZ  : integer := 16;
                 Result_SZ : integer := 32);
             port(
                 clk         : in std_logic;
                 reset       : in std_logic;
                 Data        : in std_logic_vector((5*Input_SZ)-1 downto 0);
                 FULLin      : in std_logic_vector(4 downto 0);
                 READin      : in std_logic_vector(1 downto 0);
                 WRITEin     : in std_logic;
                 FIFO1       : out std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2       : out std_logic_vector(Input_SZ-1 downto 0);
                 Start       : out std_logic;
                 Read        : out std_logic_vector(4 downto 0);
                 Statu       : out std_logic_vector(3 downto 0)
             );
             end component;
             component Dispatch is
             generic(
                 Data_SZ  : integer := 32);
             port(
                 clk         : in std_logic;
                 reset       : in std_logic;
                 Acq         : in std_logic;
                 Data        : in std_logic_vector(Data_SZ-1 downto 0);
                 Write       : in std_logic;
-                Full        : in std_logic_vector(1 downto 0);
+                Valid       : in std_logic;
+            --    Full        : in std_logic_vector(1 downto 0);
                 FifoData    : out std_logic_vector(2*Data_SZ-1 downto 0);
                 FifoWrite   : out std_logic_vector(1 downto 0);
                 Pong        : out std_logic;
                 Error       : out std_logic
             );
             end component;
             component DriveInputs is
             port(
                 clk     : in  std_logic;
                 raz     : in  std_logic;
                 Read    : in  std_logic;
                 Conjugate : in std_logic;
                 Take    : out std_logic;
                 ReadFIFO : out std_logic_vector(1 downto 0)
             );
             end component;
             component Starter is
             port(
                 clk     : in  std_logic;
                 raz     : in  std_logic;
                 Full    : in  std_logic_vector(1 downto 0);
                 Empty   : in  std_logic_vector(1 downto 0);
                 Statu   : in std_logic_vector(3 downto 0);
                 Write   : in std_logic;
                 Start   : out std_logic
             );
             end component;
             component ALU_Driver is
               generic(
                   Input_SZ_1      :   integer := 16;
                   Input_SZ_2      :   integer := 16);
               port(
                   clk       :   in std_logic;
                   reset     :   in std_logic;
                   IN1       :   in std_logic_vector(Input_SZ_1-1 downto 0);
                   IN2       :   in std_logic_vector(Input_SZ_2-1 downto 0);
                   Take      :   in std_logic;
                   Received  :   in std_logic;
                   Conjugate :   in std_logic;
                   Valid     :   out std_logic;
                   Read      :   out std_logic;
                   CTRL      :   out std_logic_vector(2 downto 0);
                   COMP      :   out  std_logic_vector(1 downto 0);
                   OP1       :   out std_logic_vector(Input_SZ_1-1 downto 0);
                   OP2       :   out std_logic_vector(Input_SZ_2-1 downto 0)
             );
             end component;
             component ReUse_CTRLR is
                 port(
                     clk         : in std_logic;
                     reset       : in std_logic;
                     SetReUse    : in std_logic_vector(4 downto 0);
                     Statu       : in std_logic_vector(3 downto 0);
                     ReUse       : out std_logic_vector(4 downto 0)
                 );
             end component;
             end;

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