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martin
- Fri, 10 May 2013 12:02:38
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lib/lpp/lpp_matrix/Dispatch.vhd
+6
-4
@@
-32,7
+32,8
port(
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Acq : in std_logic ;
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Data : in std_logic_vector ( Data_SZ - 1 downto 0 );
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Write : in std_logic ;
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Full : in std_logic_vector (1 downto 0);
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Valid : in std_logic ;
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-- Full : in std_logic_vector(1 downto 0);
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FifoData : out std_logic_vector ( 2 * Data_SZ - 1 downto 0 );
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FifoWrite : out std_logic_vector ( 1 downto 0 );
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Pong : out std_logic ;
@@
-47,7
+48,7
type etat is (eX,e0,e1,e2);
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signal ect : etat ;
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signal Pong_int : std_logic ;
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signal FifoCpt : integer range 0 to 1 := 0 ;
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-- signal FifoCpt : integer range 0 to 1 := 0;
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begin
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@@
-63,7
+64,8
begin
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case ect is
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when e0 =>
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if ( Full ( FifoCpt ) = '1' ) then
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-- if(Full(FifoCpt) = '1')then
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if ( Valid = '1' ) then
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Pong_int <= not Pong_int ;
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ect <= e1 ;
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end if ;
@@
-88,7
+90,7
begin
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FifoData <= Data & Data ;
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Pong <= Pong_int ;
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FifoCpt <= 0 when Pong_int = '0' else 1 ;
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-- FifoCpt <= 0 when Pong_int='0' else 1;
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FifoWrite <= '1' & not Write when Pong_int = '0' else not Write & '1' ;
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0
lib/lpp/lpp_matrix/MatriceSpectrale.vhd
+5
-2
@@
-35,9
+35,11
entity MatriceSpectrale is
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FifoIN_Full : in std_logic_vector ( 4 downto 0 );
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SetReUse : in std_logic_vector ( 4 downto 0 );
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FifoOUT_Full : in std_logic_vector ( 1 downto 0 );
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-- FifoOUT_Full : in std_logic_vector(1 downto 0);
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Valid : in std_logic ;
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Data_IN : in std_logic_vector (( 5 * Input_SZ ) - 1 downto 0 );
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ACQ : in std_logic ;
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SM_Write : out std_logic ;
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FlagError : out std_logic ;
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Pong : out std_logic ;
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Statu : out std_logic_vector ( 3 downto 0 );
@@
-76,9
+78,10
begin
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DISP : entity work . Dispatch
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generic map ( Result_SZ )
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port map ( clkm , rstn , ACQ , Matrix_Result , Matrix_Write , FifoOUT_Full, Data_OUT , Write , Pong , FlagError );
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port map ( clkm , rstn , ACQ , Matrix_Result , Matrix_Write , Valid , Data_OUT , Write , Pong , FlagError );
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Statu <= TopSM_Statu ;
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SM_Write <= Matrix_Write ;
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end architecture ;
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0
lib/lpp/lpp_matrix/lpp_matrix.vhd
+5
-2
@@
-66,9
+66,11
component MatriceSpectrale is
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FifoIN_Full : in std_logic_vector ( 4 downto 0 );
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SetReUse : in std_logic_vector ( 4 downto 0 );
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FifoOUT_Full : in std_logic_vector ( 1 downto 0 );
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-- FifoOUT_Full : in std_logic_vector(1 downto 0);
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Valid : in std_logic ;
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Data_IN : in std_logic_vector (( 5 * Input_SZ ) - 1 downto 0 );
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ACQ : in std_logic ;
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SM_Write : out std_logic ;
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FlagError : out std_logic ;
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Pong : out std_logic ;
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Statu : out std_logic_vector ( 3 downto 0 );
@@
-200,7
+202,8
port(
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Acq : in std_logic ;
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Data : in std_logic_vector ( Data_SZ - 1 downto 0 );
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Write : in std_logic ;
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Full : in std_logic_vector (1 downto 0);
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Valid : in std_logic ;
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-- Full : in std_logic_vector(1 downto 0);
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FifoData : out std_logic_vector ( 2 * Data_SZ - 1 downto 0 );
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FifoWrite : out std_logic_vector ( 1 downto 0 );
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Pong : out std_logic ;
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