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add custom AHB DMA
pellion -
r575:125577122712 simu_double_DMA
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
33
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.general_purpose.ALL;
40 --USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
43
44
45 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
46 GENERIC (
47 hindex : INTEGER := 2;
48 vendorid : IN INTEGER := 0;
49 deviceid : IN INTEGER := 0;
50 version : IN INTEGER := 0
51 );
52 PORT (
53 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
55
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59
60 -- FIFO Interface
61 ren : OUT STD_LOGIC;
62 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63
64 -- Controls
65 send : IN STD_LOGIC;
66 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
67 done : OUT STD_LOGIC;
68 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
69 );
70 END;
71
72 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
73
74 CONSTANT HConfig : AHB_Config_Type := (
75 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
76 OTHERS => (OTHERS => '0'));
77
78 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
79 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
80
81 SIGNAL address_counter_reset : STD_LOGIC;
82 SIGNAL address_counter_add1 : STD_LOGIC;
83
84 SIGNAL REQ_ON_GOING : STD_LOGIC;
85 SIGNAL DATA_ON_GOING : STD_LOGIC;
86 SIGNAL DATA_ON_GOING_s : STD_LOGIC;
87 SIGNAL TRANSACTION_ON_GOING : STD_LOGIC;
88 SIGNAL internal_send : STD_LOGIC;
89
90 BEGIN
91
92 -----------------------------------------------------------------------------
93 AHB_Master_Out.HCONFIG <= HConfig;
94 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
95 AHB_Master_Out.HINDEX <= hindex;
96 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
97 AHB_Master_Out.HIRQ <= (OTHERS => '0');
98 AHB_Master_Out.HBURST <= "001"; -- INCR --"111"; --INCR16
99 AHB_Master_Out.HWRITE <= '1';
100 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
101
102 AHB_Master_Out.HBUSREQ <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
103 AHB_Master_Out.HLOCK <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
104 -----------------------------------------------------------------------------
105
106 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
107 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
108
109
110 -----------------------------------------------------------------------------
111 -- REN GEN
112 -----------------------------------------------------------------------------
113 ren <= NOT (AHB_Master_In.HREADY AND DATA_ON_GOING);
114
115 -----------------------------------------------------------------------------
116 -- ADDR GEN
117 -----------------------------------------------------------------------------
118 PROCESS (clk, rstn)
119 BEGIN -- PROCESS
120 IF rstn = '0' THEN -- asynchronous reset (active low)
121 address_counter_reg <= (OTHERS => '0');
122 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
123 IF DATA_ON_GOING = '0' THEN
124 address_counter_reg <= (OTHERS => '0');
125 ELSE
126 address_counter_reg <= address_counter;
127 END IF;
128 END IF;
129 END PROCESS;
130
131 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN AHB_Master_In.HGRANT(hindex) = '1' AND REQ_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
132 -- address_counter_reg;
133 address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN DATA_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
134 address_counter_reg;
135
136 -----------------------------------------------------------------------------
137 --
138 -----------------------------------------------------------------------------
139 PROCESS (clk, rstn)
140 BEGIN -- PROCESS
141 IF rstn = '0' THEN -- asynchronous reset (active low)
142 REQ_ON_GOING <= '0';
143 done <= '0';
144 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
145 done <= '0';
146 IF send = '1' THEN --send = '1' THEN
147 REQ_ON_GOING <= '1';
148 ELSE
149 IF address_counter = "1111" AND AHB_Master_In.HREADY = '1' THEN
150 REQ_ON_GOING <= '0';
151 done <= '1';
152 END IF;
153 END IF;
154 END IF;
155 END PROCESS;
156
157 -----------------------------------------------------------------------------
158 --
159 -----------------------------------------------------------------------------
160 PROCESS (clk, rstn)
161 BEGIN -- PROCESS
162 IF rstn = '0' THEN -- asynchronous reset (active low)
163 DATA_ON_GOING <= '0';
164 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
165 IF REQ_ON_GOING = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
166 DATA_ON_GOING <= '1';
167 ELSE
168 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
169 DATA_ON_GOING <= '0';
170 END IF;
171 -- DATA_ON_GOING_s <= REQ_ON_GOING ;
172 END IF;
173 END IF;
174 END PROCESS;
175 --DATA_ON_GOING <= DATA_ON_GOING_s AND REQ_ON_GOING;
176
177
178 END Behavioral;
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 --library proasic3l;
49 49 --use proasic3l.all;
50 50
51 51 ENTITY LFR_EQM IS
52 52 --GENERIC (
53 53 -- Mem_use : INTEGER := use_RAM);
54 54
55 55 PORT (
56 56 clk50MHz : IN STD_ULOGIC;
57 57 clk49_152MHz : IN STD_ULOGIC;
58 58 reset : IN STD_ULOGIC;
59 59
60 60 -- TAG --------------------------------------------------------------------
61 61 TAG1 : IN STD_ULOGIC; -- DSU rx data
62 62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
63 63 -- UART APB ---------------------------------------------------------------
64 64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 66 -- RAM --------------------------------------------------------------------
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
67 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
68 68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69
70 70 nSRAM_MBE : INOUT STD_LOGIC; -- new
71 71 nSRAM_E1 : OUT STD_LOGIC; -- new
72 72 nSRAM_E2 : OUT STD_LOGIC; -- new
73 73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
74 74 nSRAM_W : OUT STD_LOGIC; -- new
75 75 nSRAM_G : OUT STD_LOGIC; -- new
76 76 nSRAM_BUSY : IN STD_LOGIC; -- new
77 77 -- SPW --------------------------------------------------------------------
78 78 spw1_en : OUT STD_LOGIC; -- new
79 79 spw1_din : IN STD_LOGIC;
80 80 spw1_sin : IN STD_LOGIC;
81 81 spw1_dout : OUT STD_LOGIC;
82 82 spw1_sout : OUT STD_LOGIC;
83 83 spw2_en : OUT STD_LOGIC; -- new
84 84 spw2_din : IN STD_LOGIC;
85 85 spw2_sin : IN STD_LOGIC;
86 86 spw2_dout : OUT STD_LOGIC;
87 87 spw2_sout : OUT STD_LOGIC;
88 88 -- ADC --------------------------------------------------------------------
89 89 bias_fail_sw : OUT STD_LOGIC;
90 90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
91 91 ADC_smpclk : OUT STD_LOGIC;
92 92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
93 93 -- DAC --------------------------------------------------------------------
94 94 DAC_SDO : OUT STD_LOGIC;
95 95 DAC_SCK : OUT STD_LOGIC;
96 96 DAC_SYNC : OUT STD_LOGIC;
97 97 DAC_CAL_EN : OUT STD_LOGIC;
98 98 -- HK ---------------------------------------------------------------------
99 99 HK_smpclk : OUT STD_LOGIC;
100 100 ADC_OEB_bar_HK : OUT STD_LOGIC;
101 101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 102 ---------------------------------------------------------------------------
103 103 TAG8 : OUT STD_LOGIC
104 104 );
105 105
106 106 END LFR_EQM;
107 107
108 108
109 109 ARCHITECTURE beh OF LFR_EQM IS
110 110
111 111 SIGNAL clk_25 : STD_LOGIC := '0';
112 112 SIGNAL clk_24 : STD_LOGIC := '0';
113 113 -----------------------------------------------------------------------------
114 114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116 116
117 117 -- CONSTANTS
118 118 CONSTANT CFG_PADTECH : INTEGER := inferred;
119 119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
120 120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
121 121 CONSTANT NB_AHB_MASTER : INTEGER := 3; -- 2 = grspw + waveform picker
122 122
123 123 SIGNAL apbi_ext : apb_slv_in_type;
124 124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
125 125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
126 126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
127 127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
128 128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
129 129
130 130 -- Spacewire signals
131 131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 134 SIGNAL spw_rxtxclk : STD_ULOGIC;
135 135 SIGNAL spw_rxclkn : STD_ULOGIC;
136 136 SIGNAL spw_clk : STD_LOGIC;
137 137 SIGNAL swni : grspw_in_type;
138 138 SIGNAL swno : grspw_out_type;
139 139
140 140 --GPIO
141 141 SIGNAL gpioi : gpio_in_type;
142 142 SIGNAL gpioo : gpio_out_type;
143 143
144 144 -- AD Converter ADS7886
145 145 SIGNAL sample : Samples14v(8 DOWNTO 0);
146 146 SIGNAL sample_s : Samples(8 DOWNTO 0);
147 147 SIGNAL sample_val : STD_LOGIC;
148 148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
149 149
150 150 -----------------------------------------------------------------------------
151 151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152
153 153 -----------------------------------------------------------------------------
154 154 SIGNAL rstn_25 : STD_LOGIC;
155 155 SIGNAL rstn_24 : STD_LOGIC;
156 156
157 157 SIGNAL LFR_soft_rstn : STD_LOGIC;
158 158 SIGNAL LFR_rstn : STD_LOGIC;
159 159
160 160 SIGNAL ADC_smpclk_s : STD_LOGIC;
161 161
162 162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
163 163
164 164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
165 165 SIGNAL clk_25_int : STD_LOGIC := '0';
166 166
167 167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168 168
169 169 BEGIN -- beh
170 170
171 171 -----------------------------------------------------------------------------
172 172 -- CLK
173 173 -----------------------------------------------------------------------------
174 174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
175 175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
176 176
177 177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
178 178 clk50MHz_int <= clk50MHz;
179 179
180 180 PROCESS(clk50MHz_int)
181 181 BEGIN
182 182 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
183 183 --clk_25_int <= NOT clk_25_int;
184 184 clk_25 <= NOT clk_25;
185 185 END IF;
186 186 END PROCESS;
187 187 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
188 188
189 189 PROCESS(clk49_152MHz)
190 190 BEGIN
191 191 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 192 clk_24 <= NOT clk_24;
193 193 END IF;
194 194 END PROCESS;
195 195
196 196 -----------------------------------------------------------------------------
197 197 --
198 198 leon3_soc_1 : leon3_soc
199 199 GENERIC MAP (
200 200 fabtech => apa3l,
201 201 memtech => apa3l,
202 202 padtech => inferred,
203 203 clktech => inferred,
204 204 disas => 0,
205 205 dbguart => 0,
206 206 pclow => 2,
207 207 clk_freq => 25000,
208 208 IS_RADHARD => 0,
209 209 NB_CPU => 1,
210 210 ENABLE_FPU => 1,
211 211 FPU_NETLIST => 0,
212 212 ENABLE_DSU => 1,
213 213 ENABLE_AHB_UART => 1,
214 214 ENABLE_APB_UART => 1,
215 215 ENABLE_IRQMP => 1,
216 216 ENABLE_GPT => 1,
217 217 NB_AHB_MASTER => NB_AHB_MASTER,
218 218 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 219 NB_APB_SLAVE => NB_APB_SLAVE,
220 ADDRESS_SIZE => 19,
221 USES_IAP_MEMCTRLR => 1,
220 ADDRESS_SIZE => 20,
221 USES_IAP_MEMCTRLR => 0,
222 222 BYPASS_EDAC_MEMCTRLR => '0',
223 223 SRBANKSZ => 8)
224 224 PORT MAP (
225 225 clk => clk_25,
226 226 reset => rstn_25,
227 227 errorn => OPEN,
228 228
229 229 ahbrxd => TAG1,
230 230 ahbtxd => TAG3,
231 231 urxd1 => TAG2,
232 232 utxd1 => TAG4,
233 233
234 234 address => address,
235 235 data => data,
236 236 nSRAM_BE0 => OPEN,
237 237 nSRAM_BE1 => OPEN,
238 238 nSRAM_BE2 => OPEN,
239 239 nSRAM_BE3 => OPEN,
240 240 nSRAM_WE => nSRAM_W,
241 241 nSRAM_CE => nSRAM_CE,
242 242 nSRAM_OE => nSRAM_G,
243 243 nSRAM_READY => nSRAM_BUSY,
244 244 SRAM_MBE => nSRAM_MBE,
245 245
246 246 apbi_ext => apbi_ext,
247 247 apbo_ext => apbo_ext,
248 248 ahbi_s_ext => ahbi_s_ext,
249 249 ahbo_s_ext => ahbo_s_ext,
250 250 ahbi_m_ext => ahbi_m_ext,
251 251 ahbo_m_ext => ahbo_m_ext);
252 252
253 253
254 254 nSRAM_E1 <= nSRAM_CE(0);
255 255 nSRAM_E2 <= nSRAM_CE(1);
256 256
257 257 -------------------------------------------------------------------------------
258 258 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
259 259 -------------------------------------------------------------------------------
260 260 apb_lfr_management_1 : apb_lfr_management
261 261 GENERIC MAP (
262 262 tech => apa3l,
263 263 pindex => 6,
264 264 paddr => 6,
265 265 pmask => 16#fff#,
266 266 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
267 267 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
268 268 PORT MAP (
269 269 clk25MHz => clk_25,
270 270 resetn_25MHz => rstn_25, -- TODO
271 271 --clk24_576MHz => clk_24, -- 49.152MHz/2
272 272 --resetn_24_576MHz => rstn_24, -- TODO
273 273
274 274 grspw_tick => swno.tickout,
275 275 apbi => apbi_ext,
276 276 apbo => apbo_ext(6),
277 277
278 278 HK_sample => sample_s(8),
279 279 HK_val => sample_val,
280 280 HK_sel => HK_SEL,
281 281
282 282 DAC_SDO => DAC_SDO,
283 283 DAC_SCK => DAC_SCK,
284 284 DAC_SYNC => DAC_SYNC,
285 285 DAC_CAL_EN => DAC_CAL_EN,
286 286
287 287 coarse_time => coarse_time,
288 288 fine_time => fine_time,
289 289 LFR_soft_rstn => LFR_soft_rstn
290 290 );
291 291
292 292 -----------------------------------------------------------------------
293 293 --- SpaceWire --------------------------------------------------------
294 294 -----------------------------------------------------------------------
295 295
296 296 ------------------------------------------------------------------------------
297 297 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
298 298 ------------------------------------------------------------------------------
299 299 spw1_en <= '1';
300 300 spw2_en <= '1';
301 301 ------------------------------------------------------------------------------
302 302 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
303 303 ------------------------------------------------------------------------------
304 304
305 305 --spw_clk <= clk50MHz;
306 306 --spw_rxtxclk <= spw_clk;
307 307 --spw_rxclkn <= NOT spw_rxtxclk;
308 308
309 309 -- PADS for SPW1
310 310 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
311 311 PORT MAP (spw1_din, dtmp(0));
312 312 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
313 313 PORT MAP (spw1_sin, stmp(0));
314 314 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
315 315 PORT MAP (spw1_dout, swno.d(0));
316 316 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
317 317 PORT MAP (spw1_sout, swno.s(0));
318 318 -- PADS FOR SPW2
319 319 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
320 320 PORT MAP (spw2_din, dtmp(1));
321 321 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
322 322 PORT MAP (spw2_sin, stmp(1));
323 323 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
324 324 PORT MAP (spw2_dout, swno.d(1));
325 325 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
326 326 PORT MAP (spw2_sout, swno.s(1));
327 327
328 328 -- GRSPW PHY
329 329 --spw1_input: if CFG_SPW_GRSPW = 1 generate
330 330 spw_inputloop : FOR j IN 0 TO 1 GENERATE
331 331 spw_phy0 : grspw_phy
332 332 GENERIC MAP(
333 333 tech => apa3l,
334 334 rxclkbuftype => 1,
335 335 scantest => 0)
336 336 PORT MAP(
337 337 rxrst => swno.rxrst,
338 338 di => dtmp(j),
339 339 si => stmp(j),
340 340 rxclko => spw_rxclk(j),
341 341 do => swni.d(j),
342 342 ndo => swni.nd(j*5+4 DOWNTO j*5),
343 343 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
344 344 END GENERATE spw_inputloop;
345 345
346 346 -- SPW core
347 347 sw0 : grspwm GENERIC MAP(
348 348 tech => apa3l,
349 349 hindex => 1,
350 350 pindex => 5,
351 351 paddr => 5,
352 352 pirq => 11,
353 353 sysfreq => 25000, -- CPU_FREQ
354 354 rmap => 1,
355 355 rmapcrc => 1,
356 356 fifosize1 => 16,
357 357 fifosize2 => 16,
358 358 rxclkbuftype => 1,
359 359 rxunaligned => 0,
360 360 rmapbufs => 4,
361 361 ft => 0,
362 362 netlist => 0,
363 363 ports => 2,
364 364 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
365 365 memtech => apa3l,
366 366 destkey => 2,
367 367 spwcore => 1
368 368 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
369 369 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
370 370 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
371 371 )
372 372 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
373 373 spw_rxclk(1),
374 374 clk50MHz_int,
375 375 clk50MHz_int,
376 376 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
377 377 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
378 378 swni, swno);
379 379
380 380 swni.tickin <= '0';
381 381 swni.rmapen <= '1';
382 382 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
383 383 swni.tickinraw <= '0';
384 384 swni.timein <= (OTHERS => '0');
385 385 swni.dcrstval <= (OTHERS => '0');
386 386 swni.timerrstval <= (OTHERS => '0');
387 387
388 388 -------------------------------------------------------------------------------
389 389 -- LFR ------------------------------------------------------------------------
390 390 -------------------------------------------------------------------------------
391 391 LFR_rstn <= LFR_soft_rstn AND rstn_25;
392 392
393 393 lpp_lfr_1 : lpp_lfr
394 394 GENERIC MAP (
395 395 Mem_use => use_RAM,
396 396 nb_data_by_buffer_size => 32,
397 397 --nb_word_by_buffer_size => 30,
398 398 nb_snapshot_param_size => 32,
399 399 delta_vector_size => 32,
400 400 delta_vector_size_f0_2 => 7, -- log2(96)
401 401 pindex => 15,
402 402 paddr => 15,
403 403 pmask => 16#fff#,
404 404 pirq_ms => 6,
405 405 pirq_wfp => 14,
406 406 hindex => 2,
407 407 top_lfr_version => X"020145") -- aa.bb.cc version
408 408 -- AA : BOARD NUMBER
409 409 -- 0 => MINI_LFR
410 410 -- 1 => EM
411 411 -- 2 => EQM (with A3PE3000)
412 412 PORT MAP (
413 413 clk => clk_25,
414 414 rstn => LFR_rstn,
415 415 sample_B => sample_s(2 DOWNTO 0),
416 416 sample_E => sample_s(7 DOWNTO 3),
417 417 sample_val => sample_val,
418 418 apbi => apbi_ext,
419 419 apbo => apbo_ext(15),
420 420 ahbi => ahbi_m_ext,
421 421 ahbo => ahbo_m_ext(2),
422 422 coarse_time => coarse_time,
423 423 fine_time => fine_time,
424 424 data_shaping_BW => bias_fail_sw,
425 425 debug_vector => OPEN,
426 426 debug_vector_ms => OPEN); --,
427 427
428 428 lpp_lfr_2 : lpp_lfr
429 429 GENERIC MAP (
430 430 Mem_use => use_RAM,
431 431 nb_data_by_buffer_size => 32,
432 432 --nb_word_by_buffer_size => 30,
433 433 nb_snapshot_param_size => 32,
434 434 delta_vector_size => 32,
435 435 delta_vector_size_f0_2 => 7, -- log2(96)
436 436 pindex => 14,
437 437 paddr => 14,
438 438 pmask => 16#fff#,
439 439 pirq_ms => 6,
440 440 pirq_wfp => 14,
441 441 hindex => 3,
442 442 top_lfr_version => X"020145") -- aa.bb.cc version
443 443 -- AA : BOARD NUMBER
444 444 -- 0 => MINI_LFR
445 445 -- 1 => EM
446 446 -- 2 => EQM (with A3PE3000)
447 447 PORT MAP (
448 448 clk => clk_25,
449 449 rstn => LFR_rstn,
450 450 sample_B => sample_s(2 DOWNTO 0),
451 451 sample_E => sample_s(7 DOWNTO 3),
452 452 sample_val => sample_val,
453 453
454 454 apbi => apbi_ext,
455 455 apbo => apbo_ext(14),
456 456
457 457 ahbi => ahbi_m_ext,
458 458 ahbo => ahbo_m_ext(3),
459 459 coarse_time => coarse_time,
460 460 fine_time => fine_time,
461 461 data_shaping_BW => OPEN,--bias_fail_sw,
462 462 debug_vector => OPEN,
463 463 debug_vector_ms => OPEN); --,
464 464 --observation_vector_0 => OPEN,
465 465 --observation_vector_1 => OPEN,
466 466 --observation_reg => observation_reg);
467 467
468 468
469 469 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
470 470 sample_s(I) <= sample(I) & '0' & '0';
471 471 END GENERATE all_sample;
472 472 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
473 473
474 474 -----------------------------------------------------------------------------
475 475 --
476 476 -----------------------------------------------------------------------------
477 477 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
478 478 GENERIC MAP (
479 479 ChanelCount => 9,
480 480 ncycle_cnv_high => 13,
481 481 ncycle_cnv => 25,
482 482 FILTER_ENABLED => 16#FF#)
483 483 PORT MAP (
484 484 cnv_clk => clk_24,
485 485 cnv_rstn => rstn_24,
486 486 cnv => ADC_smpclk_s,
487 487 clk => clk_25,
488 488 rstn => rstn_25,
489 489 ADC_data => ADC_data,
490 490 ADC_nOE => ADC_OEB_bar_CH_s,
491 491 sample => sample,
492 492 sample_val => sample_val);
493 493
494 494 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
495 495
496 496 ADC_smpclk <= ADC_smpclk_s;
497 497 HK_smpclk <= ADC_smpclk_s;
498 498
499 499 TAG8 <= nSRAM_BUSY;
500 500
501 501 -----------------------------------------------------------------------------
502 502 -- HK
503 503 -----------------------------------------------------------------------------
504 504 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
505 505
506 506 END beh;
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@@ -1,201 +1,226
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 USE lpp.apb_devices_list.ALL;
6 7 USE lpp.lpp_ad_conv.ALL;
7 8 USE lpp.iir_filter.ALL;
8 9 USE lpp.FILTERcfg.ALL;
9 10 USE lpp.lpp_memory.ALL;
10 11 --USE lpp.lpp_waveform_pkg.ALL;
11 12 USE lpp.lpp_dma_pkg.ALL;
12 13 --USE lpp.lpp_top_lfr_pkg.ALL;
13 14 --USE lpp.lpp_lfr_pkg.ALL;
14 15 USE lpp.general_purpose.ALL;
15 16
16 17 LIBRARY techmap;
17 18 USE techmap.gencomp.ALL;
18 19
19 20 LIBRARY grlib;
20 21 USE grlib.amba.ALL;
21 22 USE grlib.stdlib.ALL;
22 23 USE grlib.devices.ALL;
23 24 USE GRLIB.DMA2AHB_Package.ALL;
24 25
25 26 ENTITY DMA_SubSystem IS
26 27
27 28 GENERIC (
28 hindex : INTEGER := 2);
29 hindex : INTEGER := 2;
30 CUSTOM_DMA : INTEGER := 1);
29 31
30 32 PORT (
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 run : IN STD_LOGIC;
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
35 run : IN STD_LOGIC;
34 36 -- AHB
35 ahbi : IN AHB_Mst_In_Type;
36 ahbo : OUT AHB_Mst_Out_Type;
37 ahbi : IN AHB_Mst_In_Type;
38 ahbo : OUT AHB_Mst_Out_Type;
37 39 ---------------------------------------------------------------------------
38 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
40 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
40 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
41 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
42 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 43 ---------------------------------------------------------------------------
42 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
44 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
45 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
44 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
45 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
46 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
47 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
48 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 49 ---------------------------------------------------------------------------
48 grant_error : OUT STD_LOGIC --
50 grant_error : OUT STD_LOGIC --
49 51
50 52 );
51 53
52 54 END DMA_SubSystem;
53 55
54 56
55 57 ARCHITECTURE beh OF DMA_SubSystem IS
56 58
57 59 COMPONENT DMA_SubSystem_GestionBuffer
58 60 GENERIC (
59 61 BUFFER_ADDR_SIZE : INTEGER;
60 62 BUFFER_LENGTH_SIZE : INTEGER);
61 63 PORT (
62 64 clk : IN STD_LOGIC;
63 65 rstn : IN STD_LOGIC;
64 66 run : IN STD_LOGIC;
65 67 buffer_new : IN STD_LOGIC;
66 68 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
67 69 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
68 70 buffer_full : OUT STD_LOGIC;
69 71 buffer_full_err : OUT STD_LOGIC;
70 72 burst_send : IN STD_LOGIC;
71 73 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
72 74 END COMPONENT;
73 75
74 76 COMPONENT DMA_SubSystem_Arbiter
75 77 PORT (
76 78 clk : IN STD_LOGIC;
77 79 rstn : IN STD_LOGIC;
78 80 run : IN STD_LOGIC;
79 81 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 82 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
81 83 END COMPONENT;
82 84
83 85 COMPONENT DMA_SubSystem_MUX
84 86 PORT (
85 87 clk : IN STD_LOGIC;
86 88 rstn : IN STD_LOGIC;
87 89 run : IN STD_LOGIC;
88 90 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
89 91 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
90 92 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
91 93 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
92 94 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
93 95 dma_send : OUT STD_LOGIC;
94 96 dma_valid_burst : OUT STD_LOGIC;
95 97 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 98 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 99 dma_ren : IN STD_LOGIC;
98 100 dma_done : IN STD_LOGIC;
99 101 grant_error : OUT STD_LOGIC);
100 102 END COMPONENT;
101
103
102 104 -----------------------------------------------------------------------------
103 105 SIGNAL dma_send : STD_LOGIC;
104 106 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
105 107 SIGNAL dma_done : STD_LOGIC;
106 108 SIGNAL dma_ren : STD_LOGIC;
107 109 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 110 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 111 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
112 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
112 114
113 115
114 116 BEGIN -- beh
115 117
116 118 -----------------------------------------------------------------------------
117 119 -- DMA
118 120 -----------------------------------------------------------------------------
119 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
120 GENERIC MAP (
121 tech => inferred,
122 hindex => hindex)
123 PORT MAP (
124 HCLK => clk,
125 HRESETn => rstn,
126 run => run,
127 AHB_Master_In => ahbi,
128 AHB_Master_Out => ahbo,
121 GR_DMA : IF CUSTOM_DMA = 0 GENERATE
122 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
123 GENERIC MAP (
124 tech => inferred,
125 hindex => hindex)
126 PORT MAP (
127 HCLK => clk,
128 HRESETn => rstn,
129 run => run,
130 AHB_Master_In => ahbi,
131 AHB_Master_Out => ahbo,
132
133 send => dma_send,
134 valid_burst => dma_valid_burst,
135 done => dma_done,
136 ren => dma_ren,
137 address => dma_address,
138 data => dma_data);
139 END GENERATE GR_DMA;
129 140
130 send => dma_send,
131 valid_burst => dma_valid_burst,
132 done => dma_done,
133 ren => dma_ren,
134 address => dma_address,
135 data => dma_data);
141 LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
142 lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
143 GENERIC MAP (
144 hindex => hindex,
145 vendorid => VENDOR_LPP,
146 deviceid => 10,
147 version => 0)
148 PORT MAP (
149 clk => clk,
150 rstn => rstn,
151 AHB_Master_In => ahbi,
152 AHB_Master_Out => ahbo,
136 153
137
154 ren => dma_ren,
155 data => dma_data,
156 send => dma_send,
157 valid_burst => dma_valid_burst,
158 done => dma_done,
159 address => dma_address);
160 END GENERATE LPP_DMA_IP;
161
162
138 163 -----------------------------------------------------------------------------
139 164 -- RoundRobin Selection Channel For DMA
140 165 -----------------------------------------------------------------------------
141 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
166 DMA_SubSystem_Arbiter_1 : DMA_SubSystem_Arbiter
142 167 PORT MAP (
143 168 clk => clk,
144 169 rstn => rstn,
145 170 run => run,
146 171 data_burst_valid => fifo_burst_valid,
147 172 data_burst_valid_grant => fifo_grant);
148 173
149 174
150 175 -----------------------------------------------------------------------------
151 176 -- Mux between the channel from Waveform Picker and Spectral Matrix
152 177 -----------------------------------------------------------------------------
153 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
178 DMA_SubSystem_MUX_1 : DMA_SubSystem_MUX
154 179 PORT MAP (
155 clk => clk,
156 rstn => rstn,
157 run => run,
158
180 clk => clk,
181 rstn => rstn,
182 run => run,
183
159 184 fifo_grant => fifo_grant,
160 185 fifo_data => fifo_data,
161 186 fifo_address => fifo_address,
162 187 fifo_ren => fifo_ren,
163 188 fifo_burst_done => burst_send,
164
189
165 190 dma_send => dma_send,
166 191 dma_valid_burst => dma_valid_burst,
167 192 dma_address => dma_address,
168 193 dma_data => dma_data,
169 194 dma_ren => dma_ren,
170 195 dma_done => dma_done,
171
172 grant_error => grant_error);
173
174
196
197 grant_error => grant_error);
198
199
175 200 -----------------------------------------------------------------------------
176 201 -- GEN ADDR
177 202 -----------------------------------------------------------------------------
178 203 all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
179 204 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
180 205 GENERIC MAP (
181 206 BUFFER_ADDR_SIZE => 32,
182 207 BUFFER_LENGTH_SIZE => 26)
183 208 PORT MAP (
184 209 clk => clk,
185 210 rstn => rstn,
186 211 run => run,
187 212
188 213 buffer_new => buffer_new(I),
189 214 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
190 215 buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
191 216 buffer_full => buffer_full(I),
192 217 buffer_full_err => buffer_full_err(I),
193 218
194 219 burst_send => burst_send(I),
195 220 burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
196 221 );
197 222 END GENERATE all_buffer;
198 223
199 224
200 225
201 226 END beh;
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@@ -1,289 +1,309
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE std.textio.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34 --LIBRARY lpp;
35 35 --USE lpp.lpp_amba.ALL;
36 36 --USE lpp.apb_devices_list.ALL;
37 37 --USE lpp.lpp_memory.ALL;
38 38
39 39 PACKAGE lpp_dma_pkg IS
40 40
41 41 COMPONENT lpp_dma
42 42 GENERIC (
43 43 tech : INTEGER;
44 44 hindex : INTEGER;
45 45 pindex : INTEGER;
46 46 paddr : INTEGER;
47 47 pmask : INTEGER;
48 48 pirq : INTEGER);
49 49 PORT (
50 50 HCLK : IN STD_ULOGIC;
51 51 HRESETn : IN STD_ULOGIC;
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 AHB_Master_In : IN AHB_Mst_In_Type;
55 55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 56 -- fifo interface
57 57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58 fifo_empty : IN STD_LOGIC;
59 59 fifo_ren : OUT STD_LOGIC;
60 60 -- header
61 61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62 header_val : IN STD_LOGIC;
63 63 header_ack : OUT STD_LOGIC);
64 64 END COMPONENT;
65 65
66 66 COMPONENT fifo_test_dma
67 67 GENERIC (
68 68 tech : INTEGER;
69 69 pindex : INTEGER;
70 70 paddr : INTEGER;
71 71 pmask : INTEGER);
72 72 PORT (
73 73 HCLK : IN STD_ULOGIC;
74 74 HRESETn : IN STD_ULOGIC;
75 75 apbi : IN apb_slv_in_type;
76 76 apbo : OUT apb_slv_out_type;
77 77 -- fifo interface
78 78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fifo_empty : OUT STD_LOGIC;
80 80 fifo_ren : IN STD_LOGIC;
81 81 -- header
82 82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 header_val : OUT STD_LOGIC;
84 84 header_ack : IN STD_LOGIC
85 85 );
86 86 END COMPONENT;
87 87
88 88 COMPONENT lpp_dma_apbreg
89 89 GENERIC (
90 90 pindex : INTEGER;
91 91 paddr : INTEGER;
92 92 pmask : INTEGER;
93 93 pirq : INTEGER);
94 94 PORT (
95 95 HCLK : IN STD_ULOGIC;
96 96 HRESETn : IN STD_ULOGIC;
97 97 apbi : IN apb_slv_in_type;
98 98 apbo : OUT apb_slv_out_type;
99 99 -- IN
100 100 ready_matrix_f0_0 : IN STD_LOGIC;
101 101 ready_matrix_f0_1 : IN STD_LOGIC;
102 102 ready_matrix_f1 : IN STD_LOGIC;
103 103 ready_matrix_f2 : IN STD_LOGIC;
104 104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 105 error_bad_component_error : IN STD_LOGIC;
106 106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107
108 108 -- OUT
109 109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 114 status_error_bad_component_error : OUT STD_LOGIC;
115 115
116 116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 117 config_active_interruption_onError : OUT STD_LOGIC;
118 118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 122 );
123 123 END COMPONENT;
124 124
125 125 COMPONENT lpp_dma_send_1word
126 126 PORT (
127 127 HCLK : IN STD_ULOGIC;
128 128 HRESETn : IN STD_ULOGIC;
129 129 DMAIn : OUT DMA_In_Type;
130 130 DMAOut : IN DMA_OUt_Type;
131 131 send : IN STD_LOGIC;
132 132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 134 ren : OUT STD_LOGIC;
135 135 send_ok : OUT STD_LOGIC;
136 136 send_ko : OUT STD_LOGIC);
137 137 END COMPONENT;
138 138
139 139 COMPONENT lpp_dma_send_16word
140 140 PORT (
141 141 HCLK : IN STD_ULOGIC;
142 142 HRESETn : IN STD_ULOGIC;
143 143 DMAIn : OUT DMA_In_Type;
144 144 DMAOut : IN DMA_OUt_Type;
145 145 send : IN STD_LOGIC;
146 146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 148 ren : OUT STD_LOGIC;
149 149 send_ok : OUT STD_LOGIC;
150 150 send_ko : OUT STD_LOGIC);
151 151 END COMPONENT;
152 152
153 153 COMPONENT fifo_latency_correction
154 154 PORT (
155 155 HCLK : IN STD_ULOGIC;
156 156 HRESETn : IN STD_ULOGIC;
157 157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 fifo_empty : IN STD_LOGIC;
159 159 fifo_ren : OUT STD_LOGIC;
160 160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 161 dma_empty : OUT STD_LOGIC;
162 162 dma_ren : IN STD_LOGIC);
163 163 END COMPONENT;
164 164
165 165 COMPONENT lpp_dma_ip
166 166 GENERIC (
167 167 tech : INTEGER;
168 168 hindex : INTEGER);
169 169 PORT (
170 170 HCLK : IN STD_ULOGIC;
171 171 HRESETn : IN STD_ULOGIC;
172 172 AHB_Master_In : IN AHB_Mst_In_Type;
173 173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
174 174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 fifo_empty : IN STD_LOGIC;
176 176 fifo_ren : OUT STD_LOGIC;
177 177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178 header_val : IN STD_LOGIC;
179 179 header_ack : OUT STD_LOGIC;
180 180 ready_matrix_f0_0 : OUT STD_LOGIC;
181 181 ready_matrix_f0_1 : OUT STD_LOGIC;
182 182 ready_matrix_f1 : OUT STD_LOGIC;
183 183 ready_matrix_f2 : OUT STD_LOGIC;
184 184 error_anticipating_empty_fifo : OUT STD_LOGIC;
185 185 error_bad_component_error : OUT STD_LOGIC;
186 186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 status_ready_matrix_f0_0 : IN STD_LOGIC;
188 188 status_ready_matrix_f0_1 : IN STD_LOGIC;
189 189 status_ready_matrix_f1 : IN STD_LOGIC;
190 190 status_ready_matrix_f2 : IN STD_LOGIC;
191 191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
192 192 status_error_bad_component_error : IN STD_LOGIC;
193 193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
194 194 config_active_interruption_onError : IN STD_LOGIC;
195 195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
198 198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
199 199 END COMPONENT;
200 200
201 201 COMPONENT lpp_dma_singleOrBurst
202 202 GENERIC (
203 203 tech : INTEGER;
204 204 hindex : INTEGER);
205 205 PORT (
206 206 HCLK : IN STD_ULOGIC;
207 207 HRESETn : IN STD_ULOGIC;
208 208 run : IN STD_LOGIC;
209 209 AHB_Master_In : IN AHB_Mst_In_Type;
210 210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
211 211 send : IN STD_LOGIC;
212 212 valid_burst : IN STD_LOGIC;
213 213 done : OUT STD_LOGIC;
214 214 ren : OUT STD_LOGIC;
215 215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 debug_dmaout_okay : OUT STD_LOGIC);
218 218 END COMPONENT;
219 219
220 220
221 221 -----------------------------------------------------------------------------
222 222 -- DMA_SubSystem
223 223 -----------------------------------------------------------------------------
224 224 COMPONENT DMA_SubSystem
225 225 GENERIC (
226 hindex : INTEGER);
226 hindex : INTEGER;
227 CUSTOM_DMA : INTEGER := 1);
227 228 PORT (
228 229 clk : IN STD_LOGIC;
229 230 rstn : IN STD_LOGIC;
230 231 run : IN STD_LOGIC;
231 232 ahbi : IN AHB_Mst_In_Type;
232 233 ahbo : OUT AHB_Mst_Out_Type;
233 234 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
234 235 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
235 236 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
236 237 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
237 238 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
238 239 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
239 240 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
240 241 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
241 242 grant_error : OUT STD_LOGIC);
242 243 END COMPONENT;
243 244
244 245 COMPONENT DMA_SubSystem_GestionBuffer
245 246 GENERIC (
246 247 BUFFER_ADDR_SIZE : INTEGER;
247 248 BUFFER_LENGTH_SIZE : INTEGER);
248 249 PORT (
249 250 clk : IN STD_LOGIC;
250 251 rstn : IN STD_LOGIC;
251 252 run : IN STD_LOGIC;
252 253 buffer_new : IN STD_LOGIC;
253 254 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
254 255 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
255 256 buffer_full : OUT STD_LOGIC;
256 257 buffer_full_err : OUT STD_LOGIC;
257 258 burst_send : IN STD_LOGIC;
258 259 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
259 260 END COMPONENT;
260 261
261 262 COMPONENT DMA_SubSystem_Arbiter
262 263 PORT (
263 264 clk : IN STD_LOGIC;
264 265 rstn : IN STD_LOGIC;
265 266 run : IN STD_LOGIC;
266 267 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
267 268 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
268 269 END COMPONENT;
269 270
270 271 COMPONENT DMA_SubSystem_MUX
271 272 PORT (
272 273 clk : IN STD_LOGIC;
273 274 rstn : IN STD_LOGIC;
274 275 run : IN STD_LOGIC;
275 276 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
276 277 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
277 278 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
278 279 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
279 280 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
280 281 dma_send : OUT STD_LOGIC;
281 282 dma_valid_burst : OUT STD_LOGIC;
282 283 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 284 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 285 dma_ren : IN STD_LOGIC;
285 286 dma_done : IN STD_LOGIC;
286 287 grant_error : OUT STD_LOGIC);
287 288 END COMPONENT;
289
290 COMPONENT lpp_dma_SEND16B_FIFO2DMA
291 GENERIC (
292 hindex : INTEGER;
293 vendorid : in Integer;
294 deviceid : in Integer;
295 version : in Integer);
296 PORT (
297 clk : IN STD_LOGIC;
298 rstn : IN STD_LOGIC;
299 AHB_Master_In : IN AHB_Mst_In_Type;
300 AHB_Master_Out : OUT AHB_Mst_Out_Type;
301 ren : OUT STD_LOGIC;
302 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
303 send : IN STD_LOGIC;
304 valid_burst : IN STD_LOGIC;
305 done : OUT STD_LOGIC;
306 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
307 END COMPONENT;
288 308
289 309 END;
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@@ -1,11 +1,12
1 1 lpp_dma_pkg.vhd
2 2 fifo_latency_correction.vhd
3 3 lpp_dma.vhd
4 4 lpp_dma_ip.vhd
5 5 lpp_dma_send_16word.vhd
6 6 lpp_dma_send_1word.vhd
7 7 lpp_dma_singleOrBurst.vhd
8 8 DMA_SubSystem.vhd
9 9 DMA_SubSystem_GestionBuffer.vhd
10 10 DMA_SubSystem_Arbiter.vhd
11 11 DMA_SubSystem_MUX.vhd
12 lpp_dma_SEND16B_FIFO2DMA.vhd
Show file before | Show file after | Hide comments
@@ -1,572 +1,574
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 43 LIBRARY iap;
44 44 USE iap.memctrl.ALL;
45 45
46 46
47 47 ENTITY leon3_soc IS
48 48 GENERIC (
49 49 fabtech : INTEGER := apa3e;
50 50 memtech : INTEGER := apa3e;
51 51 padtech : INTEGER := inferred;
52 52 clktech : INTEGER := inferred;
53 53 disas : INTEGER := 0; -- Enable disassembly to console
54 54 dbguart : INTEGER := 0; -- Print UART on console
55 55 pclow : INTEGER := 2;
56 56 --
57 57 clk_freq : INTEGER := 25000; --kHz
58 58 --
59 59 IS_RADHARD : INTEGER := 0;
60 60 --
61 61 NB_CPU : INTEGER := 1;
62 62 ENABLE_FPU : INTEGER := 1;
63 63 FPU_NETLIST : INTEGER := 1;
64 64 ENABLE_DSU : INTEGER := 1;
65 65 ENABLE_AHB_UART : INTEGER := 1;
66 66 ENABLE_APB_UART : INTEGER := 1;
67 67 ENABLE_IRQMP : INTEGER := 1;
68 68 ENABLE_GPT : INTEGER := 1;
69 69 --
70 70 NB_AHB_MASTER : INTEGER := 1;
71 71 NB_AHB_SLAVE : INTEGER := 1;
72 72 NB_APB_SLAVE : INTEGER := 1;
73 73 --
74 74 ADDRESS_SIZE : INTEGER := 20;
75 75 USES_IAP_MEMCTRLR : INTEGER := 0;
76 76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 77 SRBANKSZ : INTEGER := 8
78 78
79 79 );
80 80 PORT (
81 81 clk : IN STD_ULOGIC;
82 82 reset : IN STD_ULOGIC;
83 83
84 84 errorn : OUT STD_ULOGIC;
85 85
86 86 -- UART AHB ---------------------------------------------------------------
87 87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
88 88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
89 89
90 90 -- UART APB ---------------------------------------------------------------
91 91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
92 92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
93 93
94 94 -- RAM --------------------------------------------------------------------
95 95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
96 96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 nSRAM_BE0 : OUT STD_LOGIC;
98 98 nSRAM_BE1 : OUT STD_LOGIC;
99 99 nSRAM_BE2 : OUT STD_LOGIC;
100 100 nSRAM_BE3 : OUT STD_LOGIC;
101 101 nSRAM_WE : OUT STD_LOGIC;
102 102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
103 103 nSRAM_OE : OUT STD_LOGIC;
104 104 nSRAM_READY : IN STD_LOGIC;
105 105 SRAM_MBE : INOUT STD_LOGIC;
106 106 -- APB --------------------------------------------------------------------
107 107 apbi_ext : OUT apb_slv_in_type;
108 108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
109 109 -- AHB_Slave --------------------------------------------------------------
110 110 ahbi_s_ext : OUT ahb_slv_in_type;
111 111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
112 112 -- AHB_Master -------------------------------------------------------------
113 113 ahbi_m_ext : OUT AHB_Mst_In_Type;
114 114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
115 115
116 116 );
117 117 END;
118 118
119 119 ARCHITECTURE Behavioral OF leon3_soc IS
120 120
121 121 -----------------------------------------------------------------------------
122 122 -- CONFIG -------------------------------------------------------------------
123 123 -----------------------------------------------------------------------------
124 124
125 125 -- Clock generator
126 126 CONSTANT CFG_CLKMUL : INTEGER := (1);
127 127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
128 128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
129 129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
130 130 -- LEON3 processor core
131 131 CONSTANT CFG_LEON3 : INTEGER := 1;
132 132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
133 133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
134 134 CONSTANT CFG_V8 : INTEGER := 0;
135 135 CONSTANT CFG_MAC : INTEGER := 0;
136 136 CONSTANT CFG_SVT : INTEGER := 0;
137 137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
138 138 CONSTANT CFG_LDDEL : INTEGER := (1);
139 139 CONSTANT CFG_NWP : INTEGER := (0);
140 140 CONSTANT CFG_PWD : INTEGER := 1*2;
141 141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
142 142 -- 1*(8 + 16 * 0) => grfpu-light
143 143 -- 1*(8 + 16 * 1) => netlist
144 144 -- 0*(8 + 16 * 0) => No FPU
145 145 -- 0*(8 + 16 * 1) => No FPU;
146 146 CONSTANT CFG_ICEN : INTEGER := 1;
147 147 CONSTANT CFG_ISETS : INTEGER := 1;
148 148 CONSTANT CFG_ISETSZ : INTEGER := 4;
149 149 CONSTANT CFG_ILINE : INTEGER := 4;
150 150 CONSTANT CFG_IREPL : INTEGER := 0;
151 151 CONSTANT CFG_ILOCK : INTEGER := 0;
152 152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
153 153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
154 154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
155 155 CONSTANT CFG_DCEN : INTEGER := 1;
156 156 CONSTANT CFG_DSETS : INTEGER := 1;
157 157 CONSTANT CFG_DSETSZ : INTEGER := 4;
158 158 CONSTANT CFG_DLINE : INTEGER := 4;
159 159 CONSTANT CFG_DREPL : INTEGER := 0;
160 160 CONSTANT CFG_DLOCK : INTEGER := 0;
161 161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
162 162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
163 163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
164 164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
165 165 CONSTANT CFG_MMUEN : INTEGER := 0;
166 166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
167 167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
168 168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
169 169 CONSTANT CFG_TLB_REP : INTEGER := 1;
170 170
171 171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
172 172 CONSTANT CFG_ITBSZ : INTEGER := 0;
173 173 CONSTANT CFG_ATBSZ : INTEGER := 0;
174 174
175 175 -- AMBA settings
176 176 CONSTANT CFG_DEFMST : INTEGER := (0);
177 177 CONSTANT CFG_RROBIN : INTEGER := 1;
178 178 CONSTANT CFG_SPLIT : INTEGER := 0;
179 179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
180 180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
181 181
182 182 -- DSU UART
183 183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
184 184
185 185 -- LEON2 memory controller
186 186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
187 187
188 188 -- UART 1
189 189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
190 190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
191 191
192 192 -- LEON3 interrupt controller
193 193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
194 194
195 195 -- Modular timer
196 196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
197 197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
198 198 CONSTANT CFG_GPT_SW : INTEGER := (8);
199 199 CONSTANT CFG_GPT_TW : INTEGER := (32);
200 200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
201 201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
202 202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
203 203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
204 204 -----------------------------------------------------------------------------
205 205
206 206 -----------------------------------------------------------------------------
207 207 -- SIGNALs
208 208 -----------------------------------------------------------------------------
209 209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
210 210 -- CLK & RST --
211 211 SIGNAL clk2x : STD_ULOGIC;
212 212 SIGNAL clkmn : STD_ULOGIC;
213 213 SIGNAL clkm : STD_ULOGIC;
214 214 SIGNAL rstn : STD_ULOGIC;
215 215 SIGNAL rstraw : STD_ULOGIC;
216 216 SIGNAL pciclk : STD_ULOGIC;
217 217 SIGNAL sdclkl : STD_ULOGIC;
218 218 SIGNAL cgi : clkgen_in_type;
219 219 SIGNAL cgo : clkgen_out_type;
220 220 --- AHB / APB
221 221 SIGNAL apbi : apb_slv_in_type;
222 222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
223 223 SIGNAL ahbsi : ahb_slv_in_type;
224 224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
225 225 SIGNAL ahbmi : ahb_mst_in_type;
226 226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
227 227 --UART
228 228 SIGNAL ahbuarti : uart_in_type;
229 229 SIGNAL ahbuarto : uart_out_type;
230 230 SIGNAL apbuarti : uart_in_type;
231 231 SIGNAL apbuarto : uart_out_type;
232 232 --MEM CTRLR
233 233 SIGNAL memi : memory_in_type;
234 234 SIGNAL memo : memory_out_type;
235 235 SIGNAL wpo : wprot_out_type;
236 236 SIGNAL sdo : sdram_out_type;
237 237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
238 238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
239 239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
240 240 SIGNAL nSRAM_OE_s : STD_LOGIC;
241 241 --IRQ
242 242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
243 243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
244 244 --Timer
245 245 SIGNAL gpti : gptimer_in_type;
246 246 SIGNAL gpto : gptimer_out_type;
247 247 --DSU
248 248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
249 249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
250 250 SIGNAL dsui : dsu_in_type;
251 251 SIGNAL dsuo : dsu_out_type;
252 252 -----------------------------------------------------------------------------
253 253
254 254
255 255 BEGIN
256 256
257 257
258 258 ----------------------------------------------------------------------
259 259 --- Reset and Clock generation -------------------------------------
260 260 ----------------------------------------------------------------------
261 261
262 262 cgi.pllctrl <= "00";
263 263 cgi.pllrst <= rstraw;
264 264
265 265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
266 266
267 267 clkgen0 : clkgen -- clock generator
268 268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
269 269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
270 270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
271 271
272 272 ----------------------------------------------------------------------
273 273 --- LEON3 processor / DSU / IRQ ------------------------------------
274 274 ----------------------------------------------------------------------
275 275
276 276 l3 : IF CFG_LEON3 = 1 GENERATE
277 277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
278 278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
279 279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
280 280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
281 281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
282 282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
283 283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
284 284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
285 285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
286 286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
287 287 irqi(i), irqo(i), dbgi(i), dbgo(i));
288 288 END GENERATE leon3_non_radhard;
289 289
290 290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
291 291 cpu : ENTITY gaisler.leon3ft
292 292 GENERIC MAP (
293 293 HINDEX => i, --: integer; --CPU_HINDEX,
294 294 FABTECH => fabtech, --CFG_TECH,
295 295 MEMTECH => memtech, --CFG_TECH,
296 296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
297 297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
298 298 FPU => CFG_FPU, --CFG_FPU,
299 299 V8 => CFG_V8, --CFG_V8,
300 300 CP => 0, --CFG_CP,
301 301 MAC => CFG_MAC, --CFG_MAC,
302 302 PCLOW => pclow, --CFG_PCLOW,
303 303 NOTAG => 0, --CFG_NOTAG,
304 304 NWP => CFG_NWP, --CFG_NWP,
305 305 ICEN => CFG_ICEN, --CFG_ICEN,
306 306 IREPL => CFG_IREPL, --CFG_IREPL,
307 307 ISETS => CFG_ISETS, --CFG_ISETS,
308 308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
309 309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
310 310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
311 311 DCEN => CFG_DCEN, --CFG_DCEN,
312 312 DREPL => CFG_DREPL, --CFG_DREPL,
313 313 DSETS => CFG_DSETS, --CFG_DSETS,
314 314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
315 315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
316 316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
317 317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
318 318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
319 319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
320 320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
321 321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
322 322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
323 323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
324 324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
325 325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
326 326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
327 327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
328 328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
329 329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
330 330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
331 331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
332 332 PWD => CFG_PWD, --CFG_PWD,
333 333 SVT => CFG_SVT, --CFG_SVT,
334 334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
335 335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
336 336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
337 337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
338 338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
339 339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
340 340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
341 341 CACHED => 0, --: integer; --CFG_DFIXED,
342 342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
343 343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
344 344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
345 345 BP => 1) --CFG_BP
346 346 PORT MAP ( --
347 347 rstn => rstn, --rst_n,
348 348 clk => clkm, --clk,
349 349 ahbi => ahbmi, --ahbmi,
350 350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
351 351 ahbsi => ahbsi, --ahbsi,
352 352 ahbso => ahbso, --ahbso,
353 353 irqi => irqi(i), --irqi(CPU_HINDEX),
354 354 irqo => irqo(i), --irqo(CPU_HINDEX),
355 355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
356 356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
357 357 gclk => clkm --clk
358 358 );
359 359 END GENERATE leon3_radhard_i;
360 360
361 361 END GENERATE;
362 362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
363 363
364 364 dsugen : IF CFG_DSU = 1 GENERATE
365
365 366 dsu0 : dsu3 -- LEON3 Debug Support Unit
366 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
367 GENERIC MAP (hindex => 2, -- TODO : hindex => 2
367 368 haddr => 16#900#, hmask => 16#F00#,
368 369 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
369 370 irq => 0, kbytes => CFG_ATBSZ)
370 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
371 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2),-- TODO :ahbso(2)
371 372 dbgo, dbgi, dsui, dsuo);
372 373 dsui.enable <= '1';
373 374 dsui.break <= '0';
375
374 376 END GENERATE;
375 377 END GENERATE;
376 378
377 379 nodsu : IF CFG_DSU = 0 GENERATE
378 380 ahbso(2) <= ahbs_none;
379 381 dsuo.tstop <= '0';
380 382 dsuo.active <= '0';
381 383 END GENERATE;
382 384
383 385 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
384 386 irqctrl0 : irqmp -- interrupt controller
385 387 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
386 388 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
387 389 END GENERATE;
388 390 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
389 391 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
390 392 irqi(i).irl <= "0000";
391 393 END GENERATE;
392 394 apbo(2) <= apb_none;
393 395 END GENERATE;
394 396
395 397 ----------------------------------------------------------------------
396 398 --- Memory controllers ---------------------------------------------
397 399 ----------------------------------------------------------------------
398 400 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
399 401 memctrlr : mctrl GENERIC MAP (
400 402 hindex => 0,
401 403 pindex => 0,
402 404 paddr => 0,
403 405 srbanks => 1
404 406 )
405 407 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
406 408 memi.bexcn <= '1';
407 409 memi.brdyn <= '1';
408 410
409 411 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
410 412 nSRAM_OE_s <= memo.ramoen(0);
411 413 END GENERATE;
412 414
413 415 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
414 416 memctrlr : srctrle_0ws
415 417 GENERIC MAP(
416 418 hindex => 2, -- TODO : hindex => 0
417 419 pindex => 0,
418 420 paddr => 0,
419 421 srbanks => 2,
420 422 banksz => SRBANKSZ, --512k * 32
421 423 rmw => 1,
422 424 --Aeroflex memory generics:
423 mbpbusy => BYPASS_EDAC_MEMCTRLR,
425 mbpedac => BYPASS_EDAC_MEMCTRLR,
424 426 mprog => 1, -- program memory by default values after reset
425 427 mpsrate => 15, -- default scrub rate period
426 428 mpb2s => 14, -- default busy to scrub delay
427 429 mpapb => 1, -- instantiate apb register
428 430 mchipcnt => 2,
429 431 mpenall => 1 -- when 0 program only E1 chip, else program all dies
430 432 )
431 433 PORT MAP (
432 434 rst => rstn,
433 435 clk => clkm,
434 436 ahbsi => ahbsi,
435 437 ahbso => ahbso(2), -- TODO :ahbso(0),
436 438 apbi => apbi,
437 439 apbo => apbo(0),
438 440 sri => memi,
439 441 sro => memo,
440 442 --Aeroflex memory signals:
441 443 ucerr => OPEN, -- uncorrectable error signal
442 444 mbe => mbe, -- enable memory programming
443 445 mbe_drive => mbe_drive -- drive the MBE memory signal
444 446 );
445 447
446 448 memi.brdyn <= nSRAM_READY;
447 449
448 450 mbe_pad : iopad
449 451 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
450 452 PORT MAP(pad => SRAM_MBE,
451 453 i => mbe,
452 454 en => mbe_drive,
453 455 o => memi.bexcn);
454 456
455 457 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
456 458 nSRAM_OE_s <= memo.oen;
457 459
458 460 END GENERATE;
459 461
460 462
461 463 memi.writen <= '1';
462 464 memi.wrn <= "1111";
463 465 memi.bwidth <= "10";
464 466
465 467 bdr : FOR i IN 0 TO 3 GENERATE
466 468 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
467 469 PORT MAP (
468 470 data(31-i*8 DOWNTO 24-i*8),
469 471 memo.data(31-i*8 DOWNTO 24-i*8),
470 472 memo.bdrive(i),
471 473 memi.data(31-i*8 DOWNTO 24-i*8));
472 474 END GENERATE;
473 475
474 476 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
475 477 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
476 478 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
477 479 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
478 480 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
479 481 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
480 482 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
481 483 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
482 484 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
483 485
484 486
485 487
486 488 ----------------------------------------------------------------------
487 489 --- AHB CONTROLLER -------------------------------------------------
488 490 ----------------------------------------------------------------------
489 491 ahb0 : ahbctrl -- AHB arbiter/multiplexer
490 492 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
491 493 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
492 494 ioen => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
493 495 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
494 496
495 497 ----------------------------------------------------------------------
496 498 --- AHB UART -------------------------------------------------------
497 499 ----------------------------------------------------------------------
498 500 dcomgen : IF CFG_AHB_UART = 1 GENERATE
499 501 dcom0 : ahbuart
500 502 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
501 503 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
502 504 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
503 505 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
504 506 END GENERATE;
505 507 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
506 508
507 509 ----------------------------------------------------------------------
508 510 --- APB Bridge -----------------------------------------------------
509 511 ----------------------------------------------------------------------
510 512 apb0 : apbctrl -- AHB/APB bridge
511 513 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
512 514 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
513 515
514 516 ----------------------------------------------------------------------
515 517 --- GPT Timer ------------------------------------------------------
516 518 ----------------------------------------------------------------------
517 519 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
518 520 timer0 : gptimer -- timer unit
519 521 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
520 522 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
521 523 nbits => CFG_GPT_TW)
522 524 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
523 525 gpti.dhalt <= dsuo.tstop;
524 526 gpti.extclk <= '0';
525 527 END GENERATE;
526 528 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
527 529
528 530
529 531 ----------------------------------------------------------------------
530 532 --- APB UART -------------------------------------------------------
531 533 ----------------------------------------------------------------------
532 534 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
533 535 uart1 : apbuart -- UART 1
534 536 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
535 537 fifosize => CFG_UART1_FIFO)
536 538 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
537 539 apbuarti.rxd <= urxd1;
538 540 apbuarti.extclk <= '0';
539 541 utxd1 <= apbuarto.txd;
540 542 apbuarti.ctsn <= '0';
541 543 END GENERATE;
542 544 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
543 545
544 546 -------------------------------------------------------------------------------
545 547 -- AMBA BUS -------------------------------------------------------------------
546 548 -------------------------------------------------------------------------------
547 549
548 550 -- APB --------------------------------------------------------------------
549 551 apbi_ext <= apbi;
550 552 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
551 553 max_16_apb : IF I + 5 < 16 GENERATE
552 554 apbo(I+5) <= apbo_ext(I+5);
553 555 END GENERATE max_16_apb;
554 556 END GENERATE all_apb;
555 557 -- AHB_Slave --------------------------------------------------------------
556 558 ahbi_s_ext <= ahbsi;
557 559 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
558 560 max_16_ahbs : IF I + 3 < 16 GENERATE
559 561 ahbso(I+3) <= ahbo_s_ext(I+3);
560 562 END GENERATE max_16_ahbs;
561 563 END GENERATE all_ahbs;
562 564 -- AHB_Master -------------------------------------------------------------
563 565 ahbi_m_ext <= ahbmi;
564 566 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
565 567 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
566 568 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
567 569 END GENERATE max_16_ahbm;
568 570 END GENERATE all_ahbm;
569 571
570 572
571 573
572 574 END Behavioral;
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@@ -1,542 +1,542
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_snapshot_param_size : INTEGER := 11;
30 30 delta_vector_size : INTEGER := 20;
31 31 delta_vector_size_f0_2 : INTEGER := 7;
32 32
33 33 pindex : INTEGER := 4;
34 34 paddr : INTEGER := 4;
35 35 pmask : INTEGER := 16#fff#;
36 36 pirq_ms : INTEGER := 0;
37 37 pirq_wfp : INTEGER := 1;
38 38
39 39 hindex : INTEGER := 2;
40 40
41 41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 42
43 43 );
44 44 PORT (
45 45 clk : IN STD_LOGIC;
46 46 rstn : IN STD_LOGIC;
47 47 -- SAMPLE
48 48 sample_B : IN Samples(2 DOWNTO 0);
49 49 sample_E : IN Samples(4 DOWNTO 0);
50 50 sample_val : IN STD_LOGIC;
51 51 -- APB
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 -- AHB
55 55 ahbi : IN AHB_Mst_In_Type;
56 56 ahbo : OUT AHB_Mst_Out_Type;
57 57 -- TIME
58 58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 60 --
61 61 data_shaping_BW : OUT STD_LOGIC;
62 62 --
63 63 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
64 64 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
65 65 );
66 66 END lpp_lfr;
67 67
68 68 ARCHITECTURE beh OF lpp_lfr IS
69 69 SIGNAL sample_s : Samples(7 DOWNTO 0);
70 70 --
71 71 SIGNAL data_shaping_SP0 : STD_LOGIC;
72 72 SIGNAL data_shaping_SP1 : STD_LOGIC;
73 73 SIGNAL data_shaping_R0 : STD_LOGIC;
74 74 SIGNAL data_shaping_R1 : STD_LOGIC;
75 75 SIGNAL data_shaping_R2 : STD_LOGIC;
76 76 --
77 77 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 78 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
79 79 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 80 --
81 81 SIGNAL sample_f0_val : STD_LOGIC;
82 82 SIGNAL sample_f1_val : STD_LOGIC;
83 83 SIGNAL sample_f2_val : STD_LOGIC;
84 84 SIGNAL sample_f3_val : STD_LOGIC;
85 85 --
86 86 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 87 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
88 88 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
89 89 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
90 90 --
91 91 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
92 92 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
93 93 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
94 94
95 95 -- SM
96 96 SIGNAL ready_matrix_f0 : STD_LOGIC;
97 97 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
98 98 SIGNAL ready_matrix_f1 : STD_LOGIC;
99 99 SIGNAL ready_matrix_f2 : STD_LOGIC;
100 100 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
101 101 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
102 102 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
103 103 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
104 104 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 105 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 106 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
108 108 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
109 109 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
110 110
111 111 -- WFP
112 112 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
113 113 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 114 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 115 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 116 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 117 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 118
119 119 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
120 120 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121 121 SIGNAL enable_f0 : STD_LOGIC;
122 122 SIGNAL enable_f1 : STD_LOGIC;
123 123 SIGNAL enable_f2 : STD_LOGIC;
124 124 SIGNAL enable_f3 : STD_LOGIC;
125 125 SIGNAL burst_f0 : STD_LOGIC;
126 126 SIGNAL burst_f1 : STD_LOGIC;
127 127 SIGNAL burst_f2 : STD_LOGIC;
128 128
129 129 --SIGNAL run : STD_LOGIC;
130 130 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
131 131
132 132 -----------------------------------------------------------------------------
133 133 --
134 134 -----------------------------------------------------------------------------
135 135 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 136 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
137 137 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
138 138 --f1
139 139 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 140 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
141 141 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
142 142 --f2
143 143 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 144 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
145 145 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
146 146 --f3
147 147 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 148 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
149 149 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
150 150
151 151 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 152 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
153 153 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
154 154 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 155 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
156 156 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 157 -----------------------------------------------------------------------------
158 158 -- DMA RR
159 159 -----------------------------------------------------------------------------
160 160 -- SIGNAL dma_sel_valid : STD_LOGIC;
161 161 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 162 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 163 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 164 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 165
166 166 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 167 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 168
169 169 -----------------------------------------------------------------------------
170 170 -- DMA_REG
171 171 -----------------------------------------------------------------------------
172 172 -- SIGNAL ongoing_reg : STD_LOGIC;
173 173 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 174 -- SIGNAL dma_send_reg : STD_LOGIC;
175 175 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
176 176 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 177 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178
179 179
180 180 -----------------------------------------------------------------------------
181 181 -- DMA
182 182 -----------------------------------------------------------------------------
183 183 -- SIGNAL dma_send : STD_LOGIC;
184 184 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
185 185 -- SIGNAL dma_done : STD_LOGIC;
186 186 -- SIGNAL dma_ren : STD_LOGIC;
187 187 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 188 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 189 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 190
191 191 -----------------------------------------------------------------------------
192 192 -- MS
193 193 -----------------------------------------------------------------------------
194 194
195 195 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 196 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 197 -- SIGNAL data_ms_valid : STD_LOGIC;
198 198 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
199 199 -- SIGNAL data_ms_ren : STD_LOGIC;
200 200 -- SIGNAL data_ms_done : STD_LOGIC;
201 201 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
202 202
203 203 -- SIGNAL run_ms : STD_LOGIC;
204 204 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
205 205
206 206 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
207 207 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
208 208 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
209 209 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
210 210
211 211
212 212 SIGNAL error_buffer_full : STD_LOGIC;
213 213 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
214 214
215 215 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 216 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217
218 218 -----------------------------------------------------------------------------
219 219 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
220 220 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
221 221 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 222 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 223 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
224 224 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
225 225 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
226 226 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
227 227 SIGNAL dma_grant_error : STD_LOGIC;
228 228
229 229 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
230 230 -----------------------------------------------------------------------------
231 231 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 232 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 233 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 234 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 235 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 236
237 237 BEGIN
238 238
239 239 debug_vector <= apb_reg_debug_vector;
240 240 -----------------------------------------------------------------------------
241 241
242 242 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
243 243 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
244 244 sample_time <= coarse_time & fine_time;
245 245
246 246 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
247 247 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
248 248 --END GENERATE all_channel;
249 249
250 250 -----------------------------------------------------------------------------
251 251 lpp_lfr_filter_1 : lpp_lfr_filter
252 252 GENERIC MAP (
253 253 Mem_use => Mem_use)
254 254 PORT MAP (
255 255 sample => sample_s,
256 256 sample_val => sample_val,
257 257 sample_time => sample_time,
258 258 clk => clk,
259 259 rstn => rstn,
260 260 data_shaping_SP0 => data_shaping_SP0,
261 261 data_shaping_SP1 => data_shaping_SP1,
262 262 data_shaping_R0 => data_shaping_R0,
263 263 data_shaping_R1 => data_shaping_R1,
264 264 data_shaping_R2 => data_shaping_R2,
265 265 sample_f0_val => sample_f0_val,
266 266 sample_f1_val => sample_f1_val,
267 267 sample_f2_val => sample_f2_val,
268 268 sample_f3_val => sample_f3_val,
269 269 sample_f0_wdata => sample_f0_data,
270 270 sample_f1_wdata => sample_f1_data,
271 271 sample_f2_wdata => sample_f2_data,
272 272 sample_f3_wdata => sample_f3_data,
273 273 sample_f0_time => sample_f0_time,
274 274 sample_f1_time => sample_f1_time,
275 275 sample_f2_time => sample_f2_time,
276 276 sample_f3_time => sample_f3_time
277 277 );
278 278
279 279 -----------------------------------------------------------------------------
280 280 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
281 281 GENERIC MAP (
282 282 nb_data_by_buffer_size => nb_data_by_buffer_size,
283 283 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
284 284 nb_snapshot_param_size => nb_snapshot_param_size,
285 285 delta_vector_size => delta_vector_size,
286 286 delta_vector_size_f0_2 => delta_vector_size_f0_2,
287 287 pindex => pindex,
288 288 paddr => paddr,
289 289 pmask => pmask,
290 290 pirq_ms => pirq_ms,
291 291 pirq_wfp => pirq_wfp,
292 292 top_lfr_version => top_lfr_version)
293 293 PORT MAP (
294 294 HCLK => clk,
295 295 HRESETn => rstn,
296 296 apbi => apbi,
297 297 apbo => apbo,
298 298
299 299 run_ms => OPEN,--run_ms,
300 300
301 301 ready_matrix_f0 => ready_matrix_f0,
302 302 ready_matrix_f1 => ready_matrix_f1,
303 303 ready_matrix_f2 => ready_matrix_f2,
304 304 error_buffer_full => error_buffer_full, -- TODO
305 305 error_input_fifo_write => error_input_fifo_write, -- TODO
306 306 status_ready_matrix_f0 => status_ready_matrix_f0,
307 307 status_ready_matrix_f1 => status_ready_matrix_f1,
308 308 status_ready_matrix_f2 => status_ready_matrix_f2,
309 309
310 310 matrix_time_f0 => matrix_time_f0,
311 311 matrix_time_f1 => matrix_time_f1,
312 312 matrix_time_f2 => matrix_time_f2,
313 313
314 314 addr_matrix_f0 => addr_matrix_f0,
315 315 addr_matrix_f1 => addr_matrix_f1,
316 316 addr_matrix_f2 => addr_matrix_f2,
317 317
318 318 length_matrix_f0 => length_matrix_f0,
319 319 length_matrix_f1 => length_matrix_f1,
320 320 length_matrix_f2 => length_matrix_f2,
321 321 -------------------------------------------------------------------------
322 322 --status_full => status_full, -- TODo
323 323 --status_full_ack => status_full_ack, -- TODo
324 324 --status_full_err => status_full_err, -- TODo
325 325 status_new_err => status_new_err,
326 326 data_shaping_BW => data_shaping_BW,
327 327 data_shaping_SP0 => data_shaping_SP0,
328 328 data_shaping_SP1 => data_shaping_SP1,
329 329 data_shaping_R0 => data_shaping_R0,
330 330 data_shaping_R1 => data_shaping_R1,
331 331 data_shaping_R2 => data_shaping_R2,
332 332 delta_snapshot => delta_snapshot,
333 333 delta_f0 => delta_f0,
334 334 delta_f0_2 => delta_f0_2,
335 335 delta_f1 => delta_f1,
336 336 delta_f2 => delta_f2,
337 337 nb_data_by_buffer => nb_data_by_buffer,
338 338 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
339 339 nb_snapshot_param => nb_snapshot_param,
340 340 enable_f0 => enable_f0,
341 341 enable_f1 => enable_f1,
342 342 enable_f2 => enable_f2,
343 343 enable_f3 => enable_f3,
344 344 burst_f0 => burst_f0,
345 345 burst_f1 => burst_f1,
346 346 burst_f2 => burst_f2,
347 347 run => OPEN, --run,
348 348 start_date => start_date,
349 349 -- debug_signal => debug_signal,
350 350 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
351 351 wfp_addr_buffer => wfp_addr_buffer,-- TODO
352 352 wfp_length_buffer => wfp_length_buffer,-- TODO
353 353
354 354 wfp_ready_buffer => wfp_ready_buffer,-- TODO
355 355 wfp_buffer_time => wfp_buffer_time,-- TODO
356 356 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
357 357 -------------------------------------------------------------------------
358 358 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
359 359 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
360 360 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
361 361 sample_f3_valid => sample_f3_val,
362 362 debug_vector => apb_reg_debug_vector
363 363 );
364 364
365 365 -----------------------------------------------------------------------------
366 366 -----------------------------------------------------------------------------
367 367 lpp_waveform_1 : lpp_waveform
368 368 GENERIC MAP (
369 369 tech => inferred,
370 370 data_size => 6*16,
371 371 nb_data_by_buffer_size => nb_data_by_buffer_size,
372 372 nb_snapshot_param_size => nb_snapshot_param_size,
373 373 delta_vector_size => delta_vector_size,
374 374 delta_vector_size_f0_2 => delta_vector_size_f0_2
375 375 )
376 376 PORT MAP (
377 377 clk => clk,
378 378 rstn => rstn,
379 379
380 380 reg_run => '1',--run,
381 381 reg_start_date => start_date,
382 382 reg_delta_snapshot => delta_snapshot,
383 383 reg_delta_f0 => delta_f0,
384 384 reg_delta_f0_2 => delta_f0_2,
385 385 reg_delta_f1 => delta_f1,
386 386 reg_delta_f2 => delta_f2,
387 387
388 388 enable_f0 => enable_f0,
389 389 enable_f1 => enable_f1,
390 390 enable_f2 => enable_f2,
391 391 enable_f3 => enable_f3,
392 392 burst_f0 => burst_f0,
393 393 burst_f1 => burst_f1,
394 394 burst_f2 => burst_f2,
395 395
396 396 nb_data_by_buffer => nb_data_by_buffer,
397 397 nb_snapshot_param => nb_snapshot_param,
398 398 status_new_err => status_new_err,
399 399
400 400 status_buffer_ready => wfp_status_buffer_ready,
401 401 addr_buffer => wfp_addr_buffer,
402 402 length_buffer => wfp_length_buffer,
403 403 ready_buffer => wfp_ready_buffer,
404 404 buffer_time => wfp_buffer_time,
405 405 error_buffer_full => wfp_error_buffer_full,
406 406
407 407 coarse_time => coarse_time,
408 408 -- fine_time => fine_time,
409 409
410 410 --f0
411 411 data_f0_in_valid => sample_f0_val,
412 412 data_f0_in => sample_f0_data,
413 413 data_f0_time => sample_f0_time,
414 414 --f1
415 415 data_f1_in_valid => sample_f1_val,
416 416 data_f1_in => sample_f1_data,
417 417 data_f1_time => sample_f1_time,
418 418 --f2
419 419 data_f2_in_valid => sample_f2_val,
420 420 data_f2_in => sample_f2_data,
421 421 data_f2_time => sample_f2_time,
422 422 --f3
423 423 data_f3_in_valid => sample_f3_val,
424 424 data_f3_in => sample_f3_data,
425 425 data_f3_time => sample_f3_time,
426 426 -- OUTPUT -- DMA interface
427 427
428 428 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
429 429 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
430 430 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
431 431 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
432 432 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
433 433 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
434 434 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
435 435 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
436 436
437 437 );
438 438
439 439 -----------------------------------------------------------------------------
440 440 -- Matrix Spectral
441 441 -----------------------------------------------------------------------------
442 442 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
443 443 NOT(sample_f0_val) & NOT(sample_f0_val);
444 444 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
445 445 NOT(sample_f1_val) & NOT(sample_f1_val);
446 446 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
447 447 NOT(sample_f2_val) & NOT(sample_f2_val);
448 448
449 449 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
450 450 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
451 451 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
452 452
453 453 -------------------------------------------------------------------------------
454 454
455 455 --ms_softandhard_rstn <= rstn AND run_ms AND run;
456 456
457 457 -----------------------------------------------------------------------------
458 458 lpp_lfr_ms_1 : lpp_lfr_ms
459 459 GENERIC MAP (
460 460 Mem_use => Mem_use)
461 461 PORT MAP (
462 462 clk => clk,
463 463 --rstn => ms_softandhard_rstn, --rstn,
464 464 rstn => rstn,
465 465
466 466 run => '1',--run_ms,
467 467
468 468 start_date => start_date,
469 469
470 470 coarse_time => coarse_time,
471 471
472 472 sample_f0_wen => sample_f0_wen,
473 473 sample_f0_wdata => sample_f0_wdata,
474 474 sample_f0_time => sample_f0_time,
475 475 sample_f1_wen => sample_f1_wen,
476 476 sample_f1_wdata => sample_f1_wdata,
477 477 sample_f1_time => sample_f1_time,
478 478 sample_f2_wen => sample_f2_wen,
479 479 sample_f2_wdata => sample_f2_wdata,
480 480 sample_f2_time => sample_f2_time,
481 481
482 482 --DMA
483 483 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
484 484 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
485 485 dma_fifo_ren => dma_fifo_ren(4), -- IN
486 486 dma_buffer_new => dma_buffer_new(4), -- OUT
487 487 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
488 488 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
489 489 dma_buffer_full => dma_buffer_full(4), -- IN
490 490 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
491 491
492 492
493 493
494 494 --REG
495 495 ready_matrix_f0 => ready_matrix_f0,
496 496 ready_matrix_f1 => ready_matrix_f1,
497 497 ready_matrix_f2 => ready_matrix_f2,
498 498 error_buffer_full => error_buffer_full,
499 499 error_input_fifo_write => error_input_fifo_write,
500 500
501 501 status_ready_matrix_f0 => status_ready_matrix_f0,
502 502 status_ready_matrix_f1 => status_ready_matrix_f1,
503 503 status_ready_matrix_f2 => status_ready_matrix_f2,
504 504 addr_matrix_f0 => addr_matrix_f0,
505 505 addr_matrix_f1 => addr_matrix_f1,
506 506 addr_matrix_f2 => addr_matrix_f2,
507 507
508 508 length_matrix_f0 => length_matrix_f0,
509 509 length_matrix_f1 => length_matrix_f1,
510 510 length_matrix_f2 => length_matrix_f2,
511 511
512 512 matrix_time_f0 => matrix_time_f0,
513 513 matrix_time_f1 => matrix_time_f1,
514 514 matrix_time_f2 => matrix_time_f2,
515 515
516 516 debug_vector => debug_vector_ms);
517 517
518 518 -----------------------------------------------------------------------------
519 519 --run_dma <= run_ms OR run;
520 520
521 521 DMA_SubSystem_1 : DMA_SubSystem
522 522 GENERIC MAP (
523 523 hindex => hindex)
524 524 PORT MAP (
525 525 clk => clk,
526 526 rstn => rstn,
527 527 run => '1',--run_dma,
528 528 ahbi => ahbi,
529 529 ahbo => ahbo,
530 530
531 531 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
532 532 fifo_data => dma_fifo_data, --fifo_data,
533 533 fifo_ren => dma_fifo_ren, --fifo_ren,
534 534
535 535 buffer_new => dma_buffer_new, --buffer_new,
536 536 buffer_addr => dma_buffer_addr, --buffer_addr,
537 537 buffer_length => dma_buffer_length, --buffer_length,
538 538 buffer_full => dma_buffer_full, --buffer_full,
539 539 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
540 540 grant_error => dma_grant_error); --grant_error);
541 541
542 END beh; No newline at end of file
542 END beh;
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