diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd --- a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd @@ -64,7 +64,7 @@ ENTITY LFR_EQM IS TAG2 : IN STD_ULOGIC; -- UART1 rx data TAG4 : OUT STD_ULOGIC; -- UART1 tx data -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); nSRAM_MBE : INOUT STD_LOGIC; -- new @@ -217,8 +217,8 @@ BEGIN -- beh NB_AHB_MASTER => NB_AHB_MASTER, NB_AHB_SLAVE => NB_AHB_SLAVE, NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1, + ADDRESS_SIZE => 20, + USES_IAP_MEMCTRLR => 0, BYPASS_EDAC_MEMCTRLR => '0', SRBANKSZ => 8) PORT MAP ( diff --git a/lib/lpp/lpp_dma/DMA_SubSystem.vhd b/lib/lpp/lpp_dma/DMA_SubSystem.vhd --- a/lib/lpp/lpp_dma/DMA_SubSystem.vhd +++ b/lib/lpp/lpp_dma/DMA_SubSystem.vhd @@ -3,6 +3,7 @@ USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY lpp; +USE lpp.apb_devices_list.ALL; USE lpp.lpp_ad_conv.ALL; USE lpp.iir_filter.ALL; USE lpp.FILTERcfg.ALL; @@ -25,27 +26,28 @@ USE GRLIB.DMA2AHB_Package.ALL; ENTITY DMA_SubSystem IS GENERIC ( - hindex : INTEGER := 2); + hindex : INTEGER := 2; + CUSTOM_DMA : INTEGER := 1); PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - run : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; -- AHB - ahbi : IN AHB_Mst_In_Type; - ahbo : OUT AHB_Mst_Out_Type; + ahbi : IN AHB_Mst_In_Type; + ahbo : OUT AHB_Mst_Out_Type; --------------------------------------------------------------------------- - fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); - fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --------------------------------------------------------------------------- - buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); - buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); - buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); + buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --------------------------------------------------------------------------- - grant_error : OUT STD_LOGIC -- + grant_error : OUT STD_LOGIC -- ); @@ -98,7 +100,7 @@ ARCHITECTURE beh OF DMA_SubSystem IS dma_done : IN STD_LOGIC; grant_error : OUT STD_LOGIC); END COMPONENT; - + ----------------------------------------------------------------------------- SIGNAL dma_send : STD_LOGIC; SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) @@ -107,8 +109,8 @@ ARCHITECTURE beh OF DMA_SubSystem IS SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); -- + SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); -- BEGIN -- beh @@ -116,29 +118,52 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- DMA ----------------------------------------------------------------------------- - lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst - GENERIC MAP ( - tech => inferred, - hindex => hindex) - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - run => run, - AHB_Master_In => ahbi, - AHB_Master_Out => ahbo, + GR_DMA : IF CUSTOM_DMA = 0 GENERATE + lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst + GENERIC MAP ( + tech => inferred, + hindex => hindex) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + run => run, + AHB_Master_In => ahbi, + AHB_Master_Out => ahbo, + + send => dma_send, + valid_burst => dma_valid_burst, + done => dma_done, + ren => dma_ren, + address => dma_address, + data => dma_data); + END GENERATE GR_DMA; - send => dma_send, - valid_burst => dma_valid_burst, - done => dma_done, - ren => dma_ren, - address => dma_address, - data => dma_data); + LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE + lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA + GENERIC MAP ( + hindex => hindex, + vendorid => VENDOR_LPP, + deviceid => 10, + version => 0) + PORT MAP ( + clk => clk, + rstn => rstn, + AHB_Master_In => ahbi, + AHB_Master_Out => ahbo, - + ren => dma_ren, + data => dma_data, + send => dma_send, + valid_burst => dma_valid_burst, + done => dma_done, + address => dma_address); + END GENERATE LPP_DMA_IP; + + ----------------------------------------------------------------------------- -- RoundRobin Selection Channel For DMA ----------------------------------------------------------------------------- - DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter + DMA_SubSystem_Arbiter_1 : DMA_SubSystem_Arbiter PORT MAP ( clk => clk, rstn => rstn, @@ -150,28 +175,28 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- Mux between the channel from Waveform Picker and Spectral Matrix ----------------------------------------------------------------------------- - DMA_SubSystem_MUX_1: DMA_SubSystem_MUX + DMA_SubSystem_MUX_1 : DMA_SubSystem_MUX PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - + clk => clk, + rstn => rstn, + run => run, + fifo_grant => fifo_grant, fifo_data => fifo_data, fifo_address => fifo_address, fifo_ren => fifo_ren, fifo_burst_done => burst_send, - + dma_send => dma_send, dma_valid_burst => dma_valid_burst, dma_address => dma_address, dma_data => dma_data, dma_ren => dma_ren, dma_done => dma_done, - - grant_error => grant_error); - - + + grant_error => grant_error); + + ----------------------------------------------------------------------------- -- GEN ADDR ----------------------------------------------------------------------------- diff --git a/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd @@ -0,0 +1,178 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; + +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.general_purpose.ALL; +--USE lpp.lpp_waveform_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_dma_SEND16B_FIFO2DMA IS + GENERIC ( + hindex : INTEGER := 2; + vendorid : IN INTEGER := 0; + deviceid : IN INTEGER := 0; + version : IN INTEGER := 0 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + -- FIFO Interface + ren : OUT STD_LOGIC; + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Controls + send : IN STD_LOGIC; + valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) + done : OUT STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS + + CONSTANT HConfig : AHB_Config_Type := ( + 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0), + OTHERS => (OTHERS => '0')); + + SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL address_counter_reset : STD_LOGIC; + SIGNAL address_counter_add1 : STD_LOGIC; + + SIGNAL REQ_ON_GOING : STD_LOGIC; + SIGNAL DATA_ON_GOING : STD_LOGIC; + SIGNAL DATA_ON_GOING_s : STD_LOGIC; + SIGNAL TRANSACTION_ON_GOING : STD_LOGIC; + SIGNAL internal_send : STD_LOGIC; + +BEGIN + + ----------------------------------------------------------------------------- + AHB_Master_Out.HCONFIG <= HConfig; + AHB_Master_Out.HSIZE <= "010"; --WORDS 32b + AHB_Master_Out.HINDEX <= hindex; + AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS + AHB_Master_Out.HIRQ <= (OTHERS => '0'); + AHB_Master_Out.HBURST <= "001"; -- INCR --"111"; --INCR16 + AHB_Master_Out.HWRITE <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; + + AHB_Master_Out.HBUSREQ <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0'; + AHB_Master_Out.HLOCK <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0'; + ----------------------------------------------------------------------------- + + AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; + AHB_Master_Out.HWDATA <= ahbdrivedata(data); + + + ----------------------------------------------------------------------------- + -- REN GEN + ----------------------------------------------------------------------------- + ren <= NOT (AHB_Master_In.HREADY AND DATA_ON_GOING); + + ----------------------------------------------------------------------------- + -- ADDR GEN + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + address_counter_reg <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF DATA_ON_GOING = '0' THEN + address_counter_reg <= (OTHERS => '0'); + ELSE + address_counter_reg <= address_counter; + END IF; + END IF; + END PROCESS; + + --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN AHB_Master_In.HGRANT(hindex) = '1' AND REQ_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE + -- address_counter_reg; + address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN DATA_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE + address_counter_reg; + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + REQ_ON_GOING <= '0'; + done <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + done <= '0'; + IF send = '1' THEN --send = '1' THEN + REQ_ON_GOING <= '1'; + ELSE + IF address_counter = "1111" AND AHB_Master_In.HREADY = '1' THEN + REQ_ON_GOING <= '0'; + done <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + DATA_ON_GOING <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF REQ_ON_GOING = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + DATA_ON_GOING <= '1'; + ELSE + IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN + DATA_ON_GOING <= '0'; + END IF; +-- DATA_ON_GOING_s <= REQ_ON_GOING ; + END IF; + END IF; + END PROCESS; + --DATA_ON_GOING <= DATA_ON_GOING_s AND REQ_ON_GOING; + + +END Behavioral; diff --git a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd --- a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd @@ -223,7 +223,8 @@ PACKAGE lpp_dma_pkg IS ----------------------------------------------------------------------------- COMPONENT DMA_SubSystem GENERIC ( - hindex : INTEGER); + hindex : INTEGER; + CUSTOM_DMA : INTEGER := 1); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; @@ -285,5 +286,24 @@ PACKAGE lpp_dma_pkg IS dma_done : IN STD_LOGIC; grant_error : OUT STD_LOGIC); END COMPONENT; + + COMPONENT lpp_dma_SEND16B_FIFO2DMA + GENERIC ( + hindex : INTEGER; + vendorid : in Integer; + deviceid : in Integer; + version : in Integer); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + ren : OUT STD_LOGIC; + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + send : IN STD_LOGIC; + valid_burst : IN STD_LOGIC; + done : OUT STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; END; diff --git a/lib/lpp/lpp_dma/vhdlsyn.txt b/lib/lpp/lpp_dma/vhdlsyn.txt --- a/lib/lpp/lpp_dma/vhdlsyn.txt +++ b/lib/lpp/lpp_dma/vhdlsyn.txt @@ -9,3 +9,4 @@ DMA_SubSystem.vhd DMA_SubSystem_GestionBuffer.vhd DMA_SubSystem_Arbiter.vhd DMA_SubSystem_MUX.vhd +lpp_dma_SEND16B_FIFO2DMA.vhd diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -362,15 +362,17 @@ BEGIN errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); dsugen : IF CFG_DSU = 1 GENERATE + dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 0, -- TODO : hindex => 2 + GENERIC MAP (hindex => 2, -- TODO : hindex => 2 haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2),-- TODO :ahbso(2) dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; dsui.break <= '0'; + END GENERATE; END GENERATE; @@ -420,7 +422,7 @@ BEGIN banksz => SRBANKSZ, --512k * 32 rmw => 1, --Aeroflex memory generics: - mbpbusy => BYPASS_EDAC_MEMCTRLR, + mbpedac => BYPASS_EDAC_MEMCTRLR, mprog => 1, -- program memory by default values after reset mpsrate => 15, -- default scrub rate period mpb2s => 14, -- default busy to scrub delay diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -539,4 +539,4 @@ BEGIN buffer_full_err => dma_buffer_full_err, --buffer_full_err, grant_error => dma_grant_error); --grant_error); -END beh; \ No newline at end of file +END beh;