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add custom AHB DMA
pellion -
r575:125577122712 simu_double_DMA
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@@ -0,0 +1,178
1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
33
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.general_purpose.ALL;
40 --USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
43
44
45 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
46 GENERIC (
47 hindex : INTEGER := 2;
48 vendorid : IN INTEGER := 0;
49 deviceid : IN INTEGER := 0;
50 version : IN INTEGER := 0
51 );
52 PORT (
53 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
55
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59
60 -- FIFO Interface
61 ren : OUT STD_LOGIC;
62 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63
64 -- Controls
65 send : IN STD_LOGIC;
66 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
67 done : OUT STD_LOGIC;
68 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
69 );
70 END;
71
72 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
73
74 CONSTANT HConfig : AHB_Config_Type := (
75 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
76 OTHERS => (OTHERS => '0'));
77
78 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
79 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
80
81 SIGNAL address_counter_reset : STD_LOGIC;
82 SIGNAL address_counter_add1 : STD_LOGIC;
83
84 SIGNAL REQ_ON_GOING : STD_LOGIC;
85 SIGNAL DATA_ON_GOING : STD_LOGIC;
86 SIGNAL DATA_ON_GOING_s : STD_LOGIC;
87 SIGNAL TRANSACTION_ON_GOING : STD_LOGIC;
88 SIGNAL internal_send : STD_LOGIC;
89
90 BEGIN
91
92 -----------------------------------------------------------------------------
93 AHB_Master_Out.HCONFIG <= HConfig;
94 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
95 AHB_Master_Out.HINDEX <= hindex;
96 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
97 AHB_Master_Out.HIRQ <= (OTHERS => '0');
98 AHB_Master_Out.HBURST <= "001"; -- INCR --"111"; --INCR16
99 AHB_Master_Out.HWRITE <= '1';
100 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
101
102 AHB_Master_Out.HBUSREQ <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
103 AHB_Master_Out.HLOCK <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
104 -----------------------------------------------------------------------------
105
106 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
107 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
108
109
110 -----------------------------------------------------------------------------
111 -- REN GEN
112 -----------------------------------------------------------------------------
113 ren <= NOT (AHB_Master_In.HREADY AND DATA_ON_GOING);
114
115 -----------------------------------------------------------------------------
116 -- ADDR GEN
117 -----------------------------------------------------------------------------
118 PROCESS (clk, rstn)
119 BEGIN -- PROCESS
120 IF rstn = '0' THEN -- asynchronous reset (active low)
121 address_counter_reg <= (OTHERS => '0');
122 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
123 IF DATA_ON_GOING = '0' THEN
124 address_counter_reg <= (OTHERS => '0');
125 ELSE
126 address_counter_reg <= address_counter;
127 END IF;
128 END IF;
129 END PROCESS;
130
131 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN AHB_Master_In.HGRANT(hindex) = '1' AND REQ_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
132 -- address_counter_reg;
133 address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN DATA_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
134 address_counter_reg;
135
136 -----------------------------------------------------------------------------
137 --
138 -----------------------------------------------------------------------------
139 PROCESS (clk, rstn)
140 BEGIN -- PROCESS
141 IF rstn = '0' THEN -- asynchronous reset (active low)
142 REQ_ON_GOING <= '0';
143 done <= '0';
144 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
145 done <= '0';
146 IF send = '1' THEN --send = '1' THEN
147 REQ_ON_GOING <= '1';
148 ELSE
149 IF address_counter = "1111" AND AHB_Master_In.HREADY = '1' THEN
150 REQ_ON_GOING <= '0';
151 done <= '1';
152 END IF;
153 END IF;
154 END IF;
155 END PROCESS;
156
157 -----------------------------------------------------------------------------
158 --
159 -----------------------------------------------------------------------------
160 PROCESS (clk, rstn)
161 BEGIN -- PROCESS
162 IF rstn = '0' THEN -- asynchronous reset (active low)
163 DATA_ON_GOING <= '0';
164 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
165 IF REQ_ON_GOING = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
166 DATA_ON_GOING <= '1';
167 ELSE
168 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
169 DATA_ON_GOING <= '0';
170 END IF;
171 -- DATA_ON_GOING_s <= REQ_ON_GOING ;
172 END IF;
173 END IF;
174 END PROCESS;
175 --DATA_ON_GOING <= DATA_ON_GOING_s AND REQ_ON_GOING;
176
177
178 END Behavioral;
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@@ -64,7 +64,7 ENTITY LFR_EQM IS
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 -- RAM --------------------------------------------------------------------
66 -- RAM --------------------------------------------------------------------
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
67 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69
69
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
@@ -217,8 +217,8 BEGIN -- beh
217 NB_AHB_MASTER => NB_AHB_MASTER,
217 NB_AHB_MASTER => NB_AHB_MASTER,
218 NB_AHB_SLAVE => NB_AHB_SLAVE,
218 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 NB_APB_SLAVE => NB_APB_SLAVE,
219 NB_APB_SLAVE => NB_APB_SLAVE,
220 ADDRESS_SIZE => 19,
220 ADDRESS_SIZE => 20,
221 USES_IAP_MEMCTRLR => 1,
221 USES_IAP_MEMCTRLR => 0,
222 BYPASS_EDAC_MEMCTRLR => '0',
222 BYPASS_EDAC_MEMCTRLR => '0',
223 SRBANKSZ => 8)
223 SRBANKSZ => 8)
224 PORT MAP (
224 PORT MAP (
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@@ -3,6 +3,7 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.apb_devices_list.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.FILTERcfg.ALL;
@@ -25,27 +26,28 USE GRLIB.DMA2AHB_Package.ALL;
25 ENTITY DMA_SubSystem IS
26 ENTITY DMA_SubSystem IS
26
27
27 GENERIC (
28 GENERIC (
28 hindex : INTEGER := 2);
29 hindex : INTEGER := 2;
30 CUSTOM_DMA : INTEGER := 1);
29
31
30 PORT (
32 PORT (
31 clk : IN STD_LOGIC;
33 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
33 run : IN STD_LOGIC;
35 run : IN STD_LOGIC;
34 -- AHB
36 -- AHB
35 ahbi : IN AHB_Mst_In_Type;
37 ahbi : IN AHB_Mst_In_Type;
36 ahbo : OUT AHB_Mst_Out_Type;
38 ahbo : OUT AHB_Mst_Out_Type;
37 ---------------------------------------------------------------------------
39 ---------------------------------------------------------------------------
38 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
41 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
40 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
42 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
45 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
44 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
46 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
45 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
48 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
48 grant_error : OUT STD_LOGIC --
50 grant_error : OUT STD_LOGIC --
49
51
50 );
52 );
51
53
@@ -98,7 +100,7 ARCHITECTURE beh OF DMA_SubSystem IS
98 dma_done : IN STD_LOGIC;
100 dma_done : IN STD_LOGIC;
99 grant_error : OUT STD_LOGIC);
101 grant_error : OUT STD_LOGIC);
100 END COMPONENT;
102 END COMPONENT;
101
103
102 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
103 SIGNAL dma_send : STD_LOGIC;
105 SIGNAL dma_send : STD_LOGIC;
104 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
106 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
@@ -107,8 +109,8 ARCHITECTURE beh OF DMA_SubSystem IS
107 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
113 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
112
114
113
115
114 BEGIN -- beh
116 BEGIN -- beh
@@ -116,29 +118,52 BEGIN -- beh
116 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
117 -- DMA
119 -- DMA
118 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
119 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
121 GR_DMA : IF CUSTOM_DMA = 0 GENERATE
120 GENERIC MAP (
122 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
121 tech => inferred,
123 GENERIC MAP (
122 hindex => hindex)
124 tech => inferred,
123 PORT MAP (
125 hindex => hindex)
124 HCLK => clk,
126 PORT MAP (
125 HRESETn => rstn,
127 HCLK => clk,
126 run => run,
128 HRESETn => rstn,
127 AHB_Master_In => ahbi,
129 run => run,
128 AHB_Master_Out => ahbo,
130 AHB_Master_In => ahbi,
131 AHB_Master_Out => ahbo,
132
133 send => dma_send,
134 valid_burst => dma_valid_burst,
135 done => dma_done,
136 ren => dma_ren,
137 address => dma_address,
138 data => dma_data);
139 END GENERATE GR_DMA;
129
140
130 send => dma_send,
141 LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
131 valid_burst => dma_valid_burst,
142 lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
132 done => dma_done,
143 GENERIC MAP (
133 ren => dma_ren,
144 hindex => hindex,
134 address => dma_address,
145 vendorid => VENDOR_LPP,
135 data => dma_data);
146 deviceid => 10,
147 version => 0)
148 PORT MAP (
149 clk => clk,
150 rstn => rstn,
151 AHB_Master_In => ahbi,
152 AHB_Master_Out => ahbo,
136
153
137
154 ren => dma_ren,
155 data => dma_data,
156 send => dma_send,
157 valid_burst => dma_valid_burst,
158 done => dma_done,
159 address => dma_address);
160 END GENERATE LPP_DMA_IP;
161
162
138 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
139 -- RoundRobin Selection Channel For DMA
164 -- RoundRobin Selection Channel For DMA
140 -----------------------------------------------------------------------------
165 -----------------------------------------------------------------------------
141 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
166 DMA_SubSystem_Arbiter_1 : DMA_SubSystem_Arbiter
142 PORT MAP (
167 PORT MAP (
143 clk => clk,
168 clk => clk,
144 rstn => rstn,
169 rstn => rstn,
@@ -150,28 +175,28 BEGIN -- beh
150 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
151 -- Mux between the channel from Waveform Picker and Spectral Matrix
176 -- Mux between the channel from Waveform Picker and Spectral Matrix
152 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
153 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
178 DMA_SubSystem_MUX_1 : DMA_SubSystem_MUX
154 PORT MAP (
179 PORT MAP (
155 clk => clk,
180 clk => clk,
156 rstn => rstn,
181 rstn => rstn,
157 run => run,
182 run => run,
158
183
159 fifo_grant => fifo_grant,
184 fifo_grant => fifo_grant,
160 fifo_data => fifo_data,
185 fifo_data => fifo_data,
161 fifo_address => fifo_address,
186 fifo_address => fifo_address,
162 fifo_ren => fifo_ren,
187 fifo_ren => fifo_ren,
163 fifo_burst_done => burst_send,
188 fifo_burst_done => burst_send,
164
189
165 dma_send => dma_send,
190 dma_send => dma_send,
166 dma_valid_burst => dma_valid_burst,
191 dma_valid_burst => dma_valid_burst,
167 dma_address => dma_address,
192 dma_address => dma_address,
168 dma_data => dma_data,
193 dma_data => dma_data,
169 dma_ren => dma_ren,
194 dma_ren => dma_ren,
170 dma_done => dma_done,
195 dma_done => dma_done,
171
196
172 grant_error => grant_error);
197 grant_error => grant_error);
173
198
174
199
175 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
176 -- GEN ADDR
201 -- GEN ADDR
177 -----------------------------------------------------------------------------
202 -----------------------------------------------------------------------------
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@@ -223,7 +223,8 PACKAGE lpp_dma_pkg IS
223 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
224 COMPONENT DMA_SubSystem
224 COMPONENT DMA_SubSystem
225 GENERIC (
225 GENERIC (
226 hindex : INTEGER);
226 hindex : INTEGER;
227 CUSTOM_DMA : INTEGER := 1);
227 PORT (
228 PORT (
228 clk : IN STD_LOGIC;
229 clk : IN STD_LOGIC;
229 rstn : IN STD_LOGIC;
230 rstn : IN STD_LOGIC;
@@ -285,5 +286,24 PACKAGE lpp_dma_pkg IS
285 dma_done : IN STD_LOGIC;
286 dma_done : IN STD_LOGIC;
286 grant_error : OUT STD_LOGIC);
287 grant_error : OUT STD_LOGIC);
287 END COMPONENT;
288 END COMPONENT;
289
290 COMPONENT lpp_dma_SEND16B_FIFO2DMA
291 GENERIC (
292 hindex : INTEGER;
293 vendorid : in Integer;
294 deviceid : in Integer;
295 version : in Integer);
296 PORT (
297 clk : IN STD_LOGIC;
298 rstn : IN STD_LOGIC;
299 AHB_Master_In : IN AHB_Mst_In_Type;
300 AHB_Master_Out : OUT AHB_Mst_Out_Type;
301 ren : OUT STD_LOGIC;
302 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
303 send : IN STD_LOGIC;
304 valid_burst : IN STD_LOGIC;
305 done : OUT STD_LOGIC;
306 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
307 END COMPONENT;
288
308
289 END;
309 END;
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@@ -9,3 +9,4 DMA_SubSystem.vhd
9 DMA_SubSystem_GestionBuffer.vhd
9 DMA_SubSystem_GestionBuffer.vhd
10 DMA_SubSystem_Arbiter.vhd
10 DMA_SubSystem_Arbiter.vhd
11 DMA_SubSystem_MUX.vhd
11 DMA_SubSystem_MUX.vhd
12 lpp_dma_SEND16B_FIFO2DMA.vhd
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@@ -362,15 +362,17 BEGIN
362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
363
363
364 dsugen : IF CFG_DSU = 1 GENERATE
364 dsugen : IF CFG_DSU = 1 GENERATE
365
365 dsu0 : dsu3 -- LEON3 Debug Support Unit
366 dsu0 : dsu3 -- LEON3 Debug Support Unit
366 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
367 GENERIC MAP (hindex => 2, -- TODO : hindex => 2
367 haddr => 16#900#, hmask => 16#F00#,
368 haddr => 16#900#, hmask => 16#F00#,
368 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
369 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
369 irq => 0, kbytes => CFG_ATBSZ)
370 irq => 0, kbytes => CFG_ATBSZ)
370 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
371 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2),-- TODO :ahbso(2)
371 dbgo, dbgi, dsui, dsuo);
372 dbgo, dbgi, dsui, dsuo);
372 dsui.enable <= '1';
373 dsui.enable <= '1';
373 dsui.break <= '0';
374 dsui.break <= '0';
375
374 END GENERATE;
376 END GENERATE;
375 END GENERATE;
377 END GENERATE;
376
378
@@ -420,7 +422,7 BEGIN
420 banksz => SRBANKSZ, --512k * 32
422 banksz => SRBANKSZ, --512k * 32
421 rmw => 1,
423 rmw => 1,
422 --Aeroflex memory generics:
424 --Aeroflex memory generics:
423 mbpbusy => BYPASS_EDAC_MEMCTRLR,
425 mbpedac => BYPASS_EDAC_MEMCTRLR,
424 mprog => 1, -- program memory by default values after reset
426 mprog => 1, -- program memory by default values after reset
425 mpsrate => 15, -- default scrub rate period
427 mpsrate => 15, -- default scrub rate period
426 mpb2s => 14, -- default busy to scrub delay
428 mpb2s => 14, -- default busy to scrub delay
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@@ -539,4 +539,4 BEGIN
539 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
539 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
540 grant_error => dma_grant_error); --grant_error);
540 grant_error => dma_grant_error); --grant_error);
541
541
542 END beh; No newline at end of file
542 END beh;
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