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Modif DMA_SubSystem en cours
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r435:0d4ef716262e JC
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
15
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
18
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
25 ENTITY DMA_SubSystem IS
26
27 GENERIC (
28 hindex : INTEGER := 2);
29
30 PORT (
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 run : IN STD_LOGIC;
34 -- AHB
35 ahbi : IN AHB_Mst_In_Type;
36 ahbo : OUT AHB_Mst_Out_Type;
37 ---------------------------------------------------------------------------
38 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
40 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 ---------------------------------------------------------------------------
42 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
44 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
45 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 ---------------------------------------------------------------------------
48 grant_error : OUT STD_LOGIC --
49
50 );
51
52 END DMA_SubSystem;
53
54
55 ARCHITECTURE beh OF DMA_SubSystem IS
56
57 COMPONENT DMA_SubSystem_GestionBuffer
58 GENERIC (
59 BUFFER_ADDR_SIZE : INTEGER;
60 BUFFER_LENGTH_SIZE : INTEGER);
61 PORT (
62 clk : IN STD_LOGIC;
63 rstn : IN STD_LOGIC;
64 run : IN STD_LOGIC;
65 buffer_new : IN STD_LOGIC;
66 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
67 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
68 buffer_full : OUT STD_LOGIC;
69 buffer_full_err : OUT STD_LOGIC;
70 burst_send : IN STD_LOGIC;
71 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
72 END COMPONENT;
73
74 COMPONENT DMA_SubSystem_Arbiter
75 PORT (
76 clk : IN STD_LOGIC;
77 rstn : IN STD_LOGIC;
78 run : IN STD_LOGIC;
79 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
81 END COMPONENT;
82
83 COMPONENT DMA_SubSystem_MUX
84 PORT (
85 clk : IN STD_LOGIC;
86 rstn : IN STD_LOGIC;
87 run : IN STD_LOGIC;
88 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
89 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
90 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
91 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
92 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
93 dma_send : OUT STD_LOGIC;
94 dma_valid_burst : OUT STD_LOGIC;
95 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 dma_ren : IN STD_LOGIC;
98 dma_done : IN STD_LOGIC;
99 grant_error : OUT STD_LOGIC);
100 END COMPONENT;
101
102 -----------------------------------------------------------------------------
103 SIGNAL dma_send : STD_LOGIC;
104 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
105 SIGNAL dma_done : STD_LOGIC;
106 SIGNAL dma_ren : STD_LOGIC;
107 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
112
113
114 BEGIN -- beh
115
116 -----------------------------------------------------------------------------
117 -- DMA
118 -----------------------------------------------------------------------------
119 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
120 GENERIC MAP (
121 tech => inferred,
122 hindex => hindex)
123 PORT MAP (
124 HCLK => clk,
125 HRESETn => rstn,
126 run => run,
127 AHB_Master_In => ahbi,
128 AHB_Master_Out => ahbo,
129
130 send => dma_send,
131 valid_burst => dma_valid_burst,
132 done => dma_done,
133 ren => dma_ren,
134 address => dma_address,
135 data => dma_data);
136
137
138 -----------------------------------------------------------------------------
139 -- RoundRobin Selection Channel For DMA
140 -----------------------------------------------------------------------------
141 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
142 PORT MAP (
143 clk => clk,
144 rstn => rstn,
145 run => run,
146 data_burst_valid => fifo_burst_valid,
147 data_burst_valid_grant => fifo_grant);
148
149
150 -----------------------------------------------------------------------------
151 -- Mux between the channel from Waveform Picker and Spectral Matrix
152 -----------------------------------------------------------------------------
153 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
154 PORT MAP (
155 clk => clk,
156 rstn => rstn,
157 run => run,
158
159 fifo_grant => fifo_grant,
160 fifo_data => fifo_data,
161 fifo_address => fifo_address,
162 fifo_ren => fifo_ren,
163 fifo_burst_done => burst_send,
164
165 dma_send => dma_send,
166 dma_valid_burst => dma_valid_burst,
167 dma_address => dma_address,
168 dma_data => dma_data,
169 dma_ren => dma_ren,
170 dma_done => dma_done,
171
172 grant_error => grant_error);
173
174
175 -----------------------------------------------------------------------------
176 -- GEN ADDR
177 -----------------------------------------------------------------------------
178 all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
179 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
180 GENERIC MAP (
181 BUFFER_ADDR_SIZE => 32,
182 BUFFER_LENGTH_SIZE => 26)
183 PORT MAP (
184 clk => clk,
185 rstn => rstn,
186 run => run,
187
188 buffer_new => buffer_new(I),
189 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
190 buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
191 buffer_full => buffer_full(I),
192 buffer_full_err => buffer_full_err(I),
193
194 burst_send => burst_send(I),
195 burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
196 );
197 END GENERATE all_buffer;
198
199
200
201 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
15
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
18
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
25 ENTITY DMA_SubSystem_Arbiter IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 run : IN STD_LOGIC;
31 --
32 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
34 );
35
36 END DMA_SubSystem_Arbiter;
37
38
39 ARCHITECTURE beh OF DMA_SubSystem_Arbiter IS
40
41 SIGNAL data_burst_valid_r : STD_LOGIC_VECTOR(4 DOWNTO 0);
42 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
43 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
44 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
45
46 BEGIN -- beh
47 -----------------------------------------------------------------------------
48 -- REG the burst valid signal
49 -----------------------------------------------------------------------------
50 PROCESS (clk, rstn)
51 BEGIN -- PROCESS
52 IF rstn = '0' THEN -- asynchronous reset (active low)
53 data_burst_valid_r <= (OTHERS => '0');
54 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
55 IF run = '1' THEN
56 data_burst_valid_r <= data_burst_valid;
57 ELSE
58 data_burst_valid_r <= (OTHERS => '0');
59 END IF;
60
61 END IF;
62 END PROCESS;
63
64 -----------------------------------------------------------------------------
65 -- ARBITER Between all the "WAVEFORM_PICKER" channel
66 -----------------------------------------------------------------------------
67 RR_Arbiter_4_1 : RR_Arbiter_4
68 PORT MAP (
69 clk => clk,
70 rstn => rstn,
71 in_valid => data_burst_valid_r(3 DOWNTO 0),
72 out_grant => dma_rr_grant_s);
73
74 dma_rr_valid_ms(0) <= data_burst_valid_r(4);--data_ms_valid OR data_ms_valid_burst;
75 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
76 dma_rr_valid_ms(2) <= '0';
77 dma_rr_valid_ms(3) <= '0';
78
79 -----------------------------------------------------------------------------
80 -- ARBITER Between all the "WAVEFORM_PICKER" and "SPECTRAL MATRIX"
81 -----------------------------------------------------------------------------
82
83 RR_Arbiter_4_2 : RR_Arbiter_4
84 PORT MAP (
85 clk => clk,
86 rstn => rstn,
87 in_valid => dma_rr_valid_ms,
88 out_grant => dma_rr_grant_ms);
89
90 data_burst_valid_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
91
92
93
94 END beh;
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5
6 ENTITY DMA_SubSystem_GestionBuffer IS
7 GENERIC (
8 BUFFER_ADDR_SIZE : INTEGER := 32;
9 BUFFER_LENGTH_SIZE : INTEGER := 26);
10 PORT (
11 clk : IN STD_LOGIC;
12 rstn : IN STD_LOGIC;
13 run : IN STD_LOGIC;
14 --
15 buffer_new : IN STD_LOGIC;
16 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
17 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); --in 64B
18 buffer_full : OUT STD_LOGIC;
19 buffer_full_err : OUT STD_LOGIC;
20 --
21 burst_send : IN STD_LOGIC;
22 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0)
23 );
24 END DMA_SubSystem_GestionBuffer;
25
26
27 ARCHITECTURE beh OF DMA_SubSystem_GestionBuffer IS
28
29 TYPE state_DMA_GestionBuffer IS (IDLE, ON_GOING);
30 SIGNAL state : state_DMA_GestionBuffer;
31
32 SIGNAL burst_send_counter : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
33 SIGNAL burst_send_counter_add1 : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
34 SIGNAL addr_shift : STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
35
36 BEGIN
37 addr_shift <= burst_send_counter & "000000";
38 burst_addr <= STD_LOGIC_VECTOR(unsigned(buffer_addr) + unsigned(addr_shift));
39
40 burst_send_counter_add1 <= STD_LOGIC_VECTOR(unsigned(burst_send_counter) + 1);
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 burst_send_counter <= (OTHERS => '0');
46 state <= IDLE;
47 buffer_full <= '0';
48 buffer_full_err <= '0';
49 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
50 CASE state IS
51 WHEN IDLE =>
52 burst_send_counter <= (OTHERS => '0');
53 buffer_full_err <= burst_send;
54 buffer_full <= '0';
55 IF buffer_new = '1' THEN
56 state <= ON_GOING;
57 END IF;
58
59 WHEN ON_GOING =>
60 buffer_full_err <= '0';
61 buffer_full <= '0';
62 IF burst_send = '1' THEN
63 IF burst_send_counter_add1 < buffer_length THEN
64 burst_send_counter <= burst_send_counter_add1;
65 ELSE
66 buffer_full <= '1';
67 state <= IDLE;
68 END IF;
69 END IF;
70
71 WHEN OTHERS => NULL;
72 END CASE;
73 END IF;
74 END PROCESS;
75
76 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
15
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
18
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
25 ENTITY DMA_SubSystem_MUX IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 run : IN STD_LOGIC;
31 --
32 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
34 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
35 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --
36 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 --
38 dma_send : OUT STD_LOGIC;
39 dma_valid_burst : OUT STD_LOGIC; --
40 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
41 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
42 dma_ren : IN STD_LOGIC; --
43 dma_done : IN STD_LOGIC; --
44 --
45 grant_error : OUT STD_LOGIC --
46 );
47
48 END DMA_SubSystem_MUX;
49
50 ARCHITECTURE beh OF DMA_SubSystem_MUX IS
51 SIGNAL channel_ongoing : STD_LOGIC_VECTOR(4 DOWNTO 0);
52 SIGNAL one_grant : STD_LOGIC;
53 SIGNAL more_than_one_grant : STD_LOGIC;
54
55 BEGIN
56
57 one_grant <= '0' WHEN fifo_grant = "00000" ELSE '1';
58 more_than_one_grant <= '0' WHEN fifo_grant = "00000" OR
59 fifo_grant = "00001" OR
60 fifo_grant = "00010" OR
61 fifo_grant = "00100" OR
62 fifo_grant = "01000" OR
63 fifo_grant = "10000" ELSE '1';
64
65 PROCESS (clk, rstn)
66 BEGIN -- PROCESS
67 IF rstn = '0' THEN -- asynchronous reset (active low)
68 channel_ongoing <= (OTHERS => '0');
69 fifo_burst_done <= (OTHERS => '0');
70 dma_send <= '0';
71 dma_valid_burst <= '0';
72 grant_error <= '0';
73 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
74 grant_error <= '0';
75 IF run = '1' THEN
76 IF dma_done = '1' THEN
77 fifo_burst_done <= channel_ongoing;
78 ELSE
79 fifo_burst_done <= (OTHERS => '0');
80 END IF;
81
82 IF channel_ongoing = "00000" OR dma_done = '1' THEN
83 channel_ongoing <= fifo_grant;
84 grant_error <= more_than_one_grant;
85 dma_valid_burst <= one_grant;
86 dma_send <= one_grant;
87 ELSE
88 dma_send <= '0';
89 END IF;
90
91 ELSE
92 channel_ongoing <= (OTHERS => '0');
93 fifo_burst_done <= (OTHERS => '0');
94 dma_send <= '0';
95 dma_valid_burst <= '0';
96 END IF;
97 END IF;
98 END PROCESS;
99
100 -------------------------------------------------------------------------
101
102 all_channel : FOR I IN 4 DOWNTO 0 GENERATE
103 fifo_ren(I) <= dma_ren WHEN channel_ongoing(I) = '1' ELSE '1';
104 END GENERATE all_channel;
105
106 dma_data <= fifo_data(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
107 fifo_data(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
108 fifo_data(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
109 fifo_data(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
110 fifo_data(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE
111
112 dma_address <= fifo_address(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
113 fifo_address(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
114 fifo_address(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
115 fifo_address(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
116 fifo_address(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE
117
118 END beh;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 BEGIN -- beh
179 BEGIN -- beh
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK
182 -- CLK
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184
184
185 PROCESS(clk_50)
185 PROCESS(clk_50)
186 BEGIN
186 BEGIN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 clk_50_s <= NOT clk_50_s;
188 clk_50_s <= NOT clk_50_s;
189 END IF;
189 END IF;
190 END PROCESS;
190 END PROCESS;
191
191
192 PROCESS(clk_50_s)
192 PROCESS(clk_50_s)
193 BEGIN
193 BEGIN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 clk_25 <= NOT clk_25;
195 clk_25 <= NOT clk_25;
196 END IF;
196 END IF;
197 END PROCESS;
197 END PROCESS;
198
198
199 PROCESS(clk_49)
199 PROCESS(clk_49)
200 BEGIN
200 BEGIN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 clk_24 <= NOT clk_24;
202 clk_24 <= NOT clk_24;
203 END IF;
203 END IF;
204 END PROCESS;
204 END PROCESS;
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207
207
208 PROCESS (clk_25, reset)
208 PROCESS (clk_25, reset)
209 BEGIN -- PROCESS
209 BEGIN -- PROCESS
210 IF reset = '0' THEN -- asynchronous reset (active low)
210 IF reset = '0' THEN -- asynchronous reset (active low)
211 LED0 <= '0';
211 LED0 <= '0';
212 LED1 <= '0';
212 LED1 <= '0';
213 LED2 <= '0';
213 LED2 <= '0';
214 --IO1 <= '0';
214 --IO1 <= '0';
215 --IO2 <= '1';
215 --IO2 <= '1';
216 --IO3 <= '0';
216 --IO3 <= '0';
217 --IO4 <= '0';
217 --IO4 <= '0';
218 --IO5 <= '0';
218 --IO5 <= '0';
219 --IO6 <= '0';
219 --IO6 <= '0';
220 --IO7 <= '0';
220 --IO7 <= '0';
221 --IO8 <= '0';
221 --IO8 <= '0';
222 --IO9 <= '0';
222 --IO9 <= '0';
223 --IO10 <= '0';
223 --IO10 <= '0';
224 --IO11 <= '0';
224 --IO11 <= '0';
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 LED0 <= '0';
226 LED0 <= '0';
227 LED1 <= '1';
227 LED1 <= '1';
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 --IO1 <= '1';
229 --IO1 <= '1';
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 --IO3 <= ADC_SDO(0);
231 --IO3 <= ADC_SDO(0);
232 --IO4 <= ADC_SDO(1);
232 --IO4 <= ADC_SDO(1);
233 --IO5 <= ADC_SDO(2);
233 --IO5 <= ADC_SDO(2);
234 --IO6 <= ADC_SDO(3);
234 --IO6 <= ADC_SDO(3);
235 --IO7 <= ADC_SDO(4);
235 --IO7 <= ADC_SDO(4);
236 --IO8 <= ADC_SDO(5);
236 --IO8 <= ADC_SDO(5);
237 --IO9 <= ADC_SDO(6);
237 --IO9 <= ADC_SDO(6);
238 --IO10 <= ADC_SDO(7);
238 --IO10 <= ADC_SDO(7);
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 END IF;
240 END IF;
241 END PROCESS;
241 END PROCESS;
242
242
243 PROCESS (clk_24, reset)
243 PROCESS (clk_24, reset)
244 BEGIN -- PROCESS
244 BEGIN -- PROCESS
245 IF reset = '0' THEN -- asynchronous reset (active low)
245 IF reset = '0' THEN -- asynchronous reset (active low)
246 I00_s <= '0';
246 I00_s <= '0';
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 I00_s <= NOT I00_s ;
248 I00_s <= NOT I00_s ;
249 END IF;
249 END IF;
250 END PROCESS;
250 END PROCESS;
251 -- IO0 <= I00_s;
251 -- IO0 <= I00_s;
252
252
253 --UARTs
253 --UARTs
254 nCTS1 <= '1';
254 nCTS1 <= '1';
255 nCTS2 <= '1';
255 nCTS2 <= '1';
256 nDCD2 <= '1';
256 nDCD2 <= '1';
257
257
258 --EXT CONNECTOR
258 --EXT CONNECTOR
259
259
260 --SPACE WIRE
260 --SPACE WIRE
261
261
262 leon3_soc_1 : leon3_soc
262 leon3_soc_1 : leon3_soc
263 GENERIC MAP (
263 GENERIC MAP (
264 fabtech => apa3e,
264 fabtech => apa3e,
265 memtech => apa3e,
265 memtech => apa3e,
266 padtech => inferred,
266 padtech => inferred,
267 clktech => inferred,
267 clktech => inferred,
268 disas => 0,
268 disas => 0,
269 dbguart => 0,
269 dbguart => 0,
270 pclow => 2,
270 pclow => 2,
271 clk_freq => 25000,
271 clk_freq => 25000,
272 NB_CPU => 1,
272 NB_CPU => 1,
273 ENABLE_FPU => 1,
273 ENABLE_FPU => 1,
274 FPU_NETLIST => 0,
274 FPU_NETLIST => 0,
275 ENABLE_DSU => 1,
275 ENABLE_DSU => 1,
276 ENABLE_AHB_UART => 1,
276 ENABLE_AHB_UART => 1,
277 ENABLE_APB_UART => 1,
277 ENABLE_APB_UART => 1,
278 ENABLE_IRQMP => 1,
278 ENABLE_IRQMP => 1,
279 ENABLE_GPT => 1,
279 ENABLE_GPT => 1,
280 NB_AHB_MASTER => NB_AHB_MASTER,
280 NB_AHB_MASTER => NB_AHB_MASTER,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 NB_APB_SLAVE => NB_APB_SLAVE)
282 NB_APB_SLAVE => NB_APB_SLAVE)
283 PORT MAP (
283 PORT MAP (
284 clk => clk_25,
284 clk => clk_25,
285 reset => reset,
285 reset => reset,
286 errorn => errorn,
286 errorn => errorn,
287 ahbrxd => TXD1,
287 ahbrxd => TXD1,
288 ahbtxd => RXD1,
288 ahbtxd => RXD1,
289 urxd1 => TXD2,
289 urxd1 => TXD2,
290 utxd1 => RXD2,
290 utxd1 => RXD2,
291 address => SRAM_A,
291 address => SRAM_A,
292 data => SRAM_DQ,
292 data => SRAM_DQ,
293 nSRAM_BE0 => SRAM_nBE(0),
293 nSRAM_BE0 => SRAM_nBE(0),
294 nSRAM_BE1 => SRAM_nBE(1),
294 nSRAM_BE1 => SRAM_nBE(1),
295 nSRAM_BE2 => SRAM_nBE(2),
295 nSRAM_BE2 => SRAM_nBE(2),
296 nSRAM_BE3 => SRAM_nBE(3),
296 nSRAM_BE3 => SRAM_nBE(3),
297 nSRAM_WE => SRAM_nWE,
297 nSRAM_WE => SRAM_nWE,
298 nSRAM_CE => SRAM_CE,
298 nSRAM_CE => SRAM_CE,
299 nSRAM_OE => SRAM_nOE,
299 nSRAM_OE => SRAM_nOE,
300
300
301 apbi_ext => apbi_ext,
301 apbi_ext => apbi_ext,
302 apbo_ext => apbo_ext,
302 apbo_ext => apbo_ext,
303 ahbi_s_ext => ahbi_s_ext,
303 ahbi_s_ext => ahbi_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
305 ahbi_m_ext => ahbi_m_ext,
305 ahbi_m_ext => ahbi_m_ext,
306 ahbo_m_ext => ahbo_m_ext);
306 ahbo_m_ext => ahbo_m_ext);
307
307
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 -------------------------------------------------------------------------------
310 -------------------------------------------------------------------------------
311 apb_lfr_time_management_1 : apb_lfr_time_management
311 apb_lfr_time_management_1 : apb_lfr_time_management
312 GENERIC MAP (
312 GENERIC MAP (
313 pindex => 6,
313 pindex => 6,
314 paddr => 6,
314 paddr => 6,
315 pmask => 16#fff#,
315 pmask => 16#fff#,
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 PORT MAP (
318 PORT MAP (
319 clk25MHz => clk_25,
319 clk25MHz => clk_25,
320 clk24_576MHz => clk_24, -- 49.152MHz/2
320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 resetn => reset,
321 resetn => reset,
322 grspw_tick => swno.tickout,
322 grspw_tick => swno.tickout,
323 apbi => apbi_ext,
323 apbi => apbi_ext,
324 apbo => apbo_ext(6),
324 apbo => apbo_ext(6),
325 coarse_time => coarse_time,
325 coarse_time => coarse_time,
326 fine_time => fine_time);
326 fine_time => fine_time);
327
327
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
330 -----------------------------------------------------------------------
330 -----------------------------------------------------------------------
331
331
332 SPW_EN <= '1';
332 SPW_EN <= '1';
333
333
334 spw_clk <= clk_50_s;
334 spw_clk <= clk_50_s;
335 spw_rxtxclk <= spw_clk;
335 spw_rxtxclk <= spw_clk;
336 spw_rxclkn <= NOT spw_rxtxclk;
336 spw_rxclkn <= NOT spw_rxtxclk;
337
337
338 -- PADS for SPW1
338 -- PADS for SPW1
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SIN, stmp(0));
342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 -- PADS FOR SPW2
347 -- PADS FOR SPW2
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_SIN, dtmp(1));
349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 PORT MAP (SPW_RED_DIN, stmp(1));
351 PORT MAP (SPW_RED_DIN, stmp(1));
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356
356
357 -- GRSPW PHY
357 -- GRSPW PHY
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 spw_phy0 : grspw_phy
360 spw_phy0 : grspw_phy
361 GENERIC MAP(
361 GENERIC MAP(
362 tech => apa3e,
362 tech => apa3e,
363 rxclkbuftype => 1,
363 rxclkbuftype => 1,
364 scantest => 0)
364 scantest => 0)
365 PORT MAP(
365 PORT MAP(
366 rxrst => swno.rxrst,
366 rxrst => swno.rxrst,
367 di => dtmp(j),
367 di => dtmp(j),
368 si => stmp(j),
368 si => stmp(j),
369 rxclko => spw_rxclk(j),
369 rxclko => spw_rxclk(j),
370 do => swni.d(j),
370 do => swni.d(j),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 END GENERATE spw_inputloop;
373 END GENERATE spw_inputloop;
374
374
375 -- SPW core
375 -- SPW core
376 sw0 : grspwm GENERIC MAP(
376 sw0 : grspwm GENERIC MAP(
377 tech => apa3e,
377 tech => apa3e,
378 hindex => 1,
378 hindex => 1,
379 pindex => 5,
379 pindex => 5,
380 paddr => 5,
380 paddr => 5,
381 pirq => 11,
381 pirq => 11,
382 sysfreq => 25000, -- CPU_FREQ
382 sysfreq => 25000, -- CPU_FREQ
383 rmap => 1,
383 rmap => 1,
384 rmapcrc => 1,
384 rmapcrc => 1,
385 fifosize1 => 16,
385 fifosize1 => 16,
386 fifosize2 => 16,
386 fifosize2 => 16,
387 rxclkbuftype => 1,
387 rxclkbuftype => 1,
388 rxunaligned => 0,
388 rxunaligned => 0,
389 rmapbufs => 4,
389 rmapbufs => 4,
390 ft => 0,
390 ft => 0,
391 netlist => 0,
391 netlist => 0,
392 ports => 2,
392 ports => 2,
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 memtech => apa3e,
394 memtech => apa3e,
395 destkey => 2,
395 destkey => 2,
396 spwcore => 1
396 spwcore => 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 )
400 )
401 PORT MAP(reset, clk_25, spw_rxclk(0),
401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 swni, swno);
404 swni, swno);
405
405
406 swni.tickin <= '0';
406 swni.tickin <= '0';
407 swni.rmapen <= '1';
407 swni.rmapen <= '1';
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 swni.tickinraw <= '0';
409 swni.tickinraw <= '0';
410 swni.timein <= (OTHERS => '0');
410 swni.timein <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
413
413
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
417 lpp_lfr_1 : lpp_lfr
417 lpp_lfr_1 : lpp_lfr
418 GENERIC MAP (
418 GENERIC MAP (
419 Mem_use => use_RAM,
419 Mem_use => use_RAM,
420 nb_data_by_buffer_size => 32,
420 nb_data_by_buffer_size => 32,
421 nb_word_by_buffer_size => 30,
421 nb_word_by_buffer_size => 30,
422 nb_snapshot_param_size => 32,
422 nb_snapshot_param_size => 32,
423 delta_vector_size => 32,
423 delta_vector_size => 32,
424 delta_vector_size_f0_2 => 7, -- log2(96)
424 delta_vector_size_f0_2 => 7, -- log2(96)
425 pindex => 15,
425 pindex => 15,
426 paddr => 15,
426 paddr => 15,
427 pmask => 16#fff#,
427 pmask => 16#fff#,
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"00011B") -- aa.bb.cc version
431 top_lfr_version => X"00011C") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
435 sample_B => sample_s(2 DOWNTO 0),
435 sample_B => sample_s(2 DOWNTO 0),
436 sample_E => sample_s(7 DOWNTO 3),
436 sample_E => sample_s(7 DOWNTO 3),
437 sample_val => sample_val,
437 sample_val => sample_val,
438 apbi => apbi_ext,
438 apbi => apbi_ext,
439 apbo => apbo_ext(15),
439 apbo => apbo_ext(15),
440 ahbi => ahbi_m_ext,
440 ahbi => ahbi_m_ext,
441 ahbo => ahbo_m_ext(2),
441 ahbo => ahbo_m_ext(2),
442 coarse_time => coarse_time,
442 coarse_time => coarse_time,
443 fine_time => fine_time,
443 fine_time => fine_time,
444 data_shaping_BW => bias_fail_sw_sig,
444 data_shaping_BW => bias_fail_sw_sig,
445 observation_vector_0=> observation_vector_0,
445 observation_vector_0=> observation_vector_0,
446 observation_vector_1 => observation_vector_1,
446 observation_vector_1 => observation_vector_1,
447 observation_reg => observation_reg);
447 observation_reg => observation_reg);
448
448
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
451 END GENERATE all_sample;
451 END GENERATE all_sample;
452
452
453
453
454
454
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
456 GENERIC MAP(
456 GENERIC MAP(
457 ChannelCount => 8,
457 ChannelCount => 8,
458 SampleNbBits => 14,
458 SampleNbBits => 14,
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
461 PORT MAP (
461 PORT MAP (
462 -- CONV
462 -- CONV
463 cnv_clk => clk_24,
463 cnv_clk => clk_24,
464 cnv_rstn => reset,
464 cnv_rstn => reset,
465 cnv => ADC_nCS_sig,
465 cnv => ADC_nCS_sig,
466 -- DATA
466 -- DATA
467 clk => clk_25,
467 clk => clk_25,
468 rstn => reset,
468 rstn => reset,
469 sck => ADC_CLK_sig,
469 sck => ADC_CLK_sig,
470 sdo => ADC_SDO_sig,
470 sdo => ADC_SDO_sig,
471 -- SAMPLE
471 -- SAMPLE
472 sample => sample,
472 sample => sample,
473 sample_val => sample_val);
473 sample_val => sample_val);
474
474
475 --IO10 <= ADC_SDO_sig(5);
475 --IO10 <= ADC_SDO_sig(5);
476 --IO9 <= ADC_SDO_sig(4);
476 --IO9 <= ADC_SDO_sig(4);
477 --IO8 <= ADC_SDO_sig(3);
477 --IO8 <= ADC_SDO_sig(3);
478
478
479 ADC_nCS <= ADC_nCS_sig;
479 ADC_nCS <= ADC_nCS_sig;
480 ADC_CLK <= ADC_CLK_sig;
480 ADC_CLK <= ADC_CLK_sig;
481 ADC_SDO_sig <= ADC_SDO;
481 ADC_SDO_sig <= ADC_SDO;
482
482
483 ----------------------------------------------------------------------
483 ----------------------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
485 ----------------------------------------------------------------------
485 ----------------------------------------------------------------------
486
486
487 grgpio0 : grgpio
487 grgpio0 : grgpio
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
490
490
491 --pio_pad_0 : iopad
491 --pio_pad_0 : iopad
492 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
494 --pio_pad_1 : iopad
494 --pio_pad_1 : iopad
495 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
497 --pio_pad_2 : iopad
497 --pio_pad_2 : iopad
498 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
500 --pio_pad_3 : iopad
500 --pio_pad_3 : iopad
501 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
503 --pio_pad_4 : iopad
503 --pio_pad_4 : iopad
504 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- GENERIC MAP (tech => CFG_PADTECH)
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
506 --pio_pad_5 : iopad
506 --pio_pad_5 : iopad
507 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- GENERIC MAP (tech => CFG_PADTECH)
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
509 --pio_pad_6 : iopad
509 --pio_pad_6 : iopad
510 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- GENERIC MAP (tech => CFG_PADTECH)
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
512 --pio_pad_7 : iopad
512 --pio_pad_7 : iopad
513 -- GENERIC MAP (tech => CFG_PADTECH)
513 -- GENERIC MAP (tech => CFG_PADTECH)
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
515
515
516 PROCESS (clk_25, reset)
516 PROCESS (clk_25, reset)
517 BEGIN -- PROCESS
517 BEGIN -- PROCESS
518 IF reset = '0' THEN -- asynchronous reset (active low)
518 IF reset = '0' THEN -- asynchronous reset (active low)
519 IO0 <= '0';
519 IO0 <= '0';
520 IO1 <= '0';
520 IO1 <= '0';
521 IO2 <= '0';
521 IO2 <= '0';
522 IO3 <= '0';
522 IO3 <= '0';
523 IO4 <= '0';
523 IO4 <= '0';
524 IO5 <= '0';
524 IO5 <= '0';
525 IO6 <= '0';
525 IO6 <= '0';
526 IO7 <= '0';
526 IO7 <= '0';
527 IO8 <= '0';
527 IO8 <= '0';
528 IO9 <= '0';
528 IO9 <= '0';
529 IO10 <= '0';
529 IO10 <= '0';
530 IO11 <= '0';
530 IO11 <= '0';
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
532 CASE gpioo.dout(2 DOWNTO 0) IS
532 CASE gpioo.dout(2 DOWNTO 0) IS
533 WHEN "011" =>
533 WHEN "011" =>
534 IO0 <= observation_reg(0 );
534 IO0 <= observation_reg(0 );
535 IO1 <= observation_reg(1 );
535 IO1 <= observation_reg(1 );
536 IO2 <= observation_reg(2 );
536 IO2 <= observation_reg(2 );
537 IO3 <= observation_reg(3 );
537 IO3 <= observation_reg(3 );
538 IO4 <= observation_reg(4 );
538 IO4 <= observation_reg(4 );
539 IO5 <= observation_reg(5 );
539 IO5 <= observation_reg(5 );
540 IO6 <= observation_reg(6 );
540 IO6 <= observation_reg(6 );
541 IO7 <= observation_reg(7 );
541 IO7 <= observation_reg(7 );
542 IO8 <= observation_reg(8 );
542 IO8 <= observation_reg(8 );
543 IO9 <= observation_reg(9 );
543 IO9 <= observation_reg(9 );
544 IO10 <= observation_reg(10);
544 IO10 <= observation_reg(10);
545 IO11 <= observation_reg(11);
545 IO11 <= observation_reg(11);
546 WHEN "001" =>
546 WHEN "001" =>
547 IO0 <= observation_reg(0 + 12);
547 IO0 <= observation_reg(0 + 12);
548 IO1 <= observation_reg(1 + 12);
548 IO1 <= observation_reg(1 + 12);
549 IO2 <= observation_reg(2 + 12);
549 IO2 <= observation_reg(2 + 12);
550 IO3 <= observation_reg(3 + 12);
550 IO3 <= observation_reg(3 + 12);
551 IO4 <= observation_reg(4 + 12);
551 IO4 <= observation_reg(4 + 12);
552 IO5 <= observation_reg(5 + 12);
552 IO5 <= observation_reg(5 + 12);
553 IO6 <= observation_reg(6 + 12);
553 IO6 <= observation_reg(6 + 12);
554 IO7 <= observation_reg(7 + 12);
554 IO7 <= observation_reg(7 + 12);
555 IO8 <= observation_reg(8 + 12);
555 IO8 <= observation_reg(8 + 12);
556 IO9 <= observation_reg(9 + 12);
556 IO9 <= observation_reg(9 + 12);
557 IO10 <= observation_reg(10 + 12);
557 IO10 <= observation_reg(10 + 12);
558 IO11 <= observation_reg(11 + 12);
558 IO11 <= observation_reg(11 + 12);
559 WHEN "010" =>
559 WHEN "010" =>
560 IO0 <= observation_reg(0 + 12 + 12);
560 IO0 <= observation_reg(0 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
568 IO8 <= '0';
568 IO8 <= '0';
569 IO9 <= '0';
569 IO9 <= '0';
570 IO10 <= '0';
570 IO10 <= '0';
571 IO11 <= '0';
571 IO11 <= '0';
572 WHEN "000" =>
572 WHEN "000" =>
573 IO0 <= observation_vector_0(0 );
573 IO0 <= observation_vector_0(0 );
574 IO1 <= observation_vector_0(1 );
574 IO1 <= observation_vector_0(1 );
575 IO2 <= observation_vector_0(2 );
575 IO2 <= observation_vector_0(2 );
576 IO3 <= observation_vector_0(3 );
576 IO3 <= observation_vector_0(3 );
577 IO4 <= observation_vector_0(4 );
577 IO4 <= observation_vector_0(4 );
578 IO5 <= observation_vector_0(5 );
578 IO5 <= observation_vector_0(5 );
579 IO6 <= observation_vector_0(6 );
579 IO6 <= observation_vector_0(6 );
580 IO7 <= observation_vector_0(7 );
580 IO7 <= observation_vector_0(7 );
581 IO8 <= observation_vector_0(8 );
581 IO8 <= observation_vector_0(8 );
582 IO9 <= observation_vector_0(9 );
582 IO9 <= observation_vector_0(9 );
583 IO10 <= observation_vector_0(10);
583 IO10 <= observation_vector_0(10);
584 IO11 <= observation_vector_0(11);
584 IO11 <= observation_vector_0(11);
585 WHEN "100" =>
585 WHEN "100" =>
586 IO0 <= observation_vector_1(0 );
586 IO0 <= observation_vector_1(0 );
587 IO1 <= observation_vector_1(1 );
587 IO1 <= observation_vector_1(1 );
588 IO2 <= observation_vector_1(2 );
588 IO2 <= observation_vector_1(2 );
589 IO3 <= observation_vector_1(3 );
589 IO3 <= observation_vector_1(3 );
590 IO4 <= observation_vector_1(4 );
590 IO4 <= observation_vector_1(4 );
591 IO5 <= observation_vector_1(5 );
591 IO5 <= observation_vector_1(5 );
592 IO6 <= observation_vector_1(6 );
592 IO6 <= observation_vector_1(6 );
593 IO7 <= observation_vector_1(7 );
593 IO7 <= observation_vector_1(7 );
594 IO8 <= observation_vector_1(8 );
594 IO8 <= observation_vector_1(8 );
595 IO9 <= observation_vector_1(9 );
595 IO9 <= observation_vector_1(9 );
596 IO10 <= observation_vector_1(10);
596 IO10 <= observation_vector_1(10);
597 IO11 <= observation_vector_1(11);
597 IO11 <= observation_vector_1(11);
598 WHEN OTHERS => NULL;
598 WHEN OTHERS => NULL;
599 END CASE;
599 END CASE;
600
600
601 END IF;
601 END IF;
602 END PROCESS;
602 END PROCESS;
603
603
604 END beh;
604 END beh;
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@@ -1,220 +1,289
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE std.textio.ALL;
27 USE std.textio.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34 --LIBRARY lpp;
34 --LIBRARY lpp;
35 --USE lpp.lpp_amba.ALL;
35 --USE lpp.lpp_amba.ALL;
36 --USE lpp.apb_devices_list.ALL;
36 --USE lpp.apb_devices_list.ALL;
37 --USE lpp.lpp_memory.ALL;
37 --USE lpp.lpp_memory.ALL;
38
38
39 PACKAGE lpp_dma_pkg IS
39 PACKAGE lpp_dma_pkg IS
40
40
41 COMPONENT lpp_dma
41 COMPONENT lpp_dma
42 GENERIC (
42 GENERIC (
43 tech : INTEGER;
43 tech : INTEGER;
44 hindex : INTEGER;
44 hindex : INTEGER;
45 pindex : INTEGER;
45 pindex : INTEGER;
46 paddr : INTEGER;
46 paddr : INTEGER;
47 pmask : INTEGER;
47 pmask : INTEGER;
48 pirq : INTEGER);
48 pirq : INTEGER);
49 PORT (
49 PORT (
50 HCLK : IN STD_ULOGIC;
50 HCLK : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
52 apbi : IN apb_slv_in_type;
52 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
53 apbo : OUT apb_slv_out_type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 -- fifo interface
56 -- fifo interface
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 fifo_empty : IN STD_LOGIC;
58 fifo_empty : IN STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
60 -- header
60 -- header
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 header_val : IN STD_LOGIC;
62 header_val : IN STD_LOGIC;
63 header_ack : OUT STD_LOGIC);
63 header_ack : OUT STD_LOGIC);
64 END COMPONENT;
64 END COMPONENT;
65
65
66 COMPONENT fifo_test_dma
66 COMPONENT fifo_test_dma
67 GENERIC (
67 GENERIC (
68 tech : INTEGER;
68 tech : INTEGER;
69 pindex : INTEGER;
69 pindex : INTEGER;
70 paddr : INTEGER;
70 paddr : INTEGER;
71 pmask : INTEGER);
71 pmask : INTEGER);
72 PORT (
72 PORT (
73 HCLK : IN STD_ULOGIC;
73 HCLK : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
75 apbi : IN apb_slv_in_type;
75 apbi : IN apb_slv_in_type;
76 apbo : OUT apb_slv_out_type;
76 apbo : OUT apb_slv_out_type;
77 -- fifo interface
77 -- fifo interface
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fifo_empty : OUT STD_LOGIC;
79 fifo_empty : OUT STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
81 -- header
81 -- header
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 header_val : OUT STD_LOGIC;
83 header_val : OUT STD_LOGIC;
84 header_ack : IN STD_LOGIC
84 header_ack : IN STD_LOGIC
85 );
85 );
86 END COMPONENT;
86 END COMPONENT;
87
87
88 COMPONENT lpp_dma_apbreg
88 COMPONENT lpp_dma_apbreg
89 GENERIC (
89 GENERIC (
90 pindex : INTEGER;
90 pindex : INTEGER;
91 paddr : INTEGER;
91 paddr : INTEGER;
92 pmask : INTEGER;
92 pmask : INTEGER;
93 pirq : INTEGER);
93 pirq : INTEGER);
94 PORT (
94 PORT (
95 HCLK : IN STD_ULOGIC;
95 HCLK : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
97 apbi : IN apb_slv_in_type;
97 apbi : IN apb_slv_in_type;
98 apbo : OUT apb_slv_out_type;
98 apbo : OUT apb_slv_out_type;
99 -- IN
99 -- IN
100 ready_matrix_f0_0 : IN STD_LOGIC;
100 ready_matrix_f0_0 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107
107
108 -- OUT
108 -- OUT
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
115
115
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 );
122 );
123 END COMPONENT;
123 END COMPONENT;
124
124
125 COMPONENT lpp_dma_send_1word
125 COMPONENT lpp_dma_send_1word
126 PORT (
126 PORT (
127 HCLK : IN STD_ULOGIC;
127 HCLK : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
129 DMAIn : OUT DMA_In_Type;
129 DMAIn : OUT DMA_In_Type;
130 DMAOut : IN DMA_OUt_Type;
130 DMAOut : IN DMA_OUt_Type;
131 send : IN STD_LOGIC;
131 send : IN STD_LOGIC;
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 ren : OUT STD_LOGIC;
134 ren : OUT STD_LOGIC;
135 send_ok : OUT STD_LOGIC;
135 send_ok : OUT STD_LOGIC;
136 send_ko : OUT STD_LOGIC);
136 send_ko : OUT STD_LOGIC);
137 END COMPONENT;
137 END COMPONENT;
138
138
139 COMPONENT lpp_dma_send_16word
139 COMPONENT lpp_dma_send_16word
140 PORT (
140 PORT (
141 HCLK : IN STD_ULOGIC;
141 HCLK : IN STD_ULOGIC;
142 HRESETn : IN STD_ULOGIC;
142 HRESETn : IN STD_ULOGIC;
143 DMAIn : OUT DMA_In_Type;
143 DMAIn : OUT DMA_In_Type;
144 DMAOut : IN DMA_OUt_Type;
144 DMAOut : IN DMA_OUt_Type;
145 send : IN STD_LOGIC;
145 send : IN STD_LOGIC;
146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 ren : OUT STD_LOGIC;
148 ren : OUT STD_LOGIC;
149 send_ok : OUT STD_LOGIC;
149 send_ok : OUT STD_LOGIC;
150 send_ko : OUT STD_LOGIC);
150 send_ko : OUT STD_LOGIC);
151 END COMPONENT;
151 END COMPONENT;
152
152
153 COMPONENT fifo_latency_correction
153 COMPONENT fifo_latency_correction
154 PORT (
154 PORT (
155 HCLK : IN STD_ULOGIC;
155 HCLK : IN STD_ULOGIC;
156 HRESETn : IN STD_ULOGIC;
156 HRESETn : IN STD_ULOGIC;
157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
158 fifo_empty : IN STD_LOGIC;
158 fifo_empty : IN STD_LOGIC;
159 fifo_ren : OUT STD_LOGIC;
159 fifo_ren : OUT STD_LOGIC;
160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 dma_empty : OUT STD_LOGIC;
161 dma_empty : OUT STD_LOGIC;
162 dma_ren : IN STD_LOGIC);
162 dma_ren : IN STD_LOGIC);
163 END COMPONENT;
163 END COMPONENT;
164
164
165 COMPONENT lpp_dma_ip
165 COMPONENT lpp_dma_ip
166 GENERIC (
166 GENERIC (
167 tech : INTEGER;
167 tech : INTEGER;
168 hindex : INTEGER);
168 hindex : INTEGER);
169 PORT (
169 PORT (
170 HCLK : IN STD_ULOGIC;
170 HCLK : IN STD_ULOGIC;
171 HRESETn : IN STD_ULOGIC;
171 HRESETn : IN STD_ULOGIC;
172 AHB_Master_In : IN AHB_Mst_In_Type;
172 AHB_Master_In : IN AHB_Mst_In_Type;
173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
175 fifo_empty : IN STD_LOGIC;
175 fifo_empty : IN STD_LOGIC;
176 fifo_ren : OUT STD_LOGIC;
176 fifo_ren : OUT STD_LOGIC;
177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
178 header_val : IN STD_LOGIC;
178 header_val : IN STD_LOGIC;
179 header_ack : OUT STD_LOGIC;
179 header_ack : OUT STD_LOGIC;
180 ready_matrix_f0_0 : OUT STD_LOGIC;
180 ready_matrix_f0_0 : OUT STD_LOGIC;
181 ready_matrix_f0_1 : OUT STD_LOGIC;
181 ready_matrix_f0_1 : OUT STD_LOGIC;
182 ready_matrix_f1 : OUT STD_LOGIC;
182 ready_matrix_f1 : OUT STD_LOGIC;
183 ready_matrix_f2 : OUT STD_LOGIC;
183 ready_matrix_f2 : OUT STD_LOGIC;
184 error_anticipating_empty_fifo : OUT STD_LOGIC;
184 error_anticipating_empty_fifo : OUT STD_LOGIC;
185 error_bad_component_error : OUT STD_LOGIC;
185 error_bad_component_error : OUT STD_LOGIC;
186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 status_ready_matrix_f0_0 : IN STD_LOGIC;
187 status_ready_matrix_f0_0 : IN STD_LOGIC;
188 status_ready_matrix_f0_1 : IN STD_LOGIC;
188 status_ready_matrix_f0_1 : IN STD_LOGIC;
189 status_ready_matrix_f1 : IN STD_LOGIC;
189 status_ready_matrix_f1 : IN STD_LOGIC;
190 status_ready_matrix_f2 : IN STD_LOGIC;
190 status_ready_matrix_f2 : IN STD_LOGIC;
191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
192 status_error_bad_component_error : IN STD_LOGIC;
192 status_error_bad_component_error : IN STD_LOGIC;
193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
194 config_active_interruption_onError : IN STD_LOGIC;
194 config_active_interruption_onError : IN STD_LOGIC;
195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
199 END COMPONENT;
199 END COMPONENT;
200
200
201 COMPONENT lpp_dma_singleOrBurst
201 COMPONENT lpp_dma_singleOrBurst
202 GENERIC (
202 GENERIC (
203 tech : INTEGER;
203 tech : INTEGER;
204 hindex : INTEGER);
204 hindex : INTEGER);
205 PORT (
205 PORT (
206 HCLK : IN STD_ULOGIC;
206 HCLK : IN STD_ULOGIC;
207 HRESETn : IN STD_ULOGIC;
207 HRESETn : IN STD_ULOGIC;
208 run : IN STD_LOGIC;
208 run : IN STD_LOGIC;
209 AHB_Master_In : IN AHB_Mst_In_Type;
209 AHB_Master_In : IN AHB_Mst_In_Type;
210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
211 send : IN STD_LOGIC;
211 send : IN STD_LOGIC;
212 valid_burst : IN STD_LOGIC;
212 valid_burst : IN STD_LOGIC;
213 done : OUT STD_LOGIC;
213 done : OUT STD_LOGIC;
214 ren : OUT STD_LOGIC;
214 ren : OUT STD_LOGIC;
215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 debug_dmaout_okay : OUT STD_LOGIC);
217 debug_dmaout_okay : OUT STD_LOGIC);
218 END COMPONENT;
218 END COMPONENT;
219
220
221 -----------------------------------------------------------------------------
222 -- DMA_SubSystem
223 -----------------------------------------------------------------------------
224 COMPONENT DMA_SubSystem
225 GENERIC (
226 hindex : INTEGER);
227 PORT (
228 clk : IN STD_LOGIC;
229 rstn : IN STD_LOGIC;
230 run : IN STD_LOGIC;
231 ahbi : IN AHB_Mst_In_Type;
232 ahbo : OUT AHB_Mst_Out_Type;
233 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
234 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
235 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
236 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
237 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
238 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
239 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
240 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
241 grant_error : OUT STD_LOGIC);
242 END COMPONENT;
243
244 COMPONENT DMA_SubSystem_GestionBuffer
245 GENERIC (
246 BUFFER_ADDR_SIZE : INTEGER;
247 BUFFER_LENGTH_SIZE : INTEGER);
248 PORT (
249 clk : IN STD_LOGIC;
250 rstn : IN STD_LOGIC;
251 run : IN STD_LOGIC;
252 buffer_new : IN STD_LOGIC;
253 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
254 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
255 buffer_full : OUT STD_LOGIC;
256 buffer_full_err : OUT STD_LOGIC;
257 burst_send : IN STD_LOGIC;
258 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
259 END COMPONENT;
260
261 COMPONENT DMA_SubSystem_Arbiter
262 PORT (
263 clk : IN STD_LOGIC;
264 rstn : IN STD_LOGIC;
265 run : IN STD_LOGIC;
266 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
267 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
268 END COMPONENT;
269
270 COMPONENT DMA_SubSystem_MUX
271 PORT (
272 clk : IN STD_LOGIC;
273 rstn : IN STD_LOGIC;
274 run : IN STD_LOGIC;
275 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
276 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
277 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
278 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
279 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
280 dma_send : OUT STD_LOGIC;
281 dma_valid_burst : OUT STD_LOGIC;
282 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 dma_ren : IN STD_LOGIC;
285 dma_done : IN STD_LOGIC;
286 grant_error : OUT STD_LOGIC);
287 END COMPONENT;
219
288
220 END;
289 END;
Show file before | Show file after | Hide comments
@@ -1,7 +1,11
1 lpp_dma_pkg.vhd
1 lpp_dma_pkg.vhd
2 fifo_latency_correction.vhd
2 fifo_latency_correction.vhd
3 lpp_dma.vhd
3 lpp_dma.vhd
4 lpp_dma_ip.vhd
4 lpp_dma_ip.vhd
5 lpp_dma_send_16word.vhd
5 lpp_dma_send_16word.vhd
6 lpp_dma_send_1word.vhd
6 lpp_dma_send_1word.vhd
7 lpp_dma_singleOrBurst.vhd
7 lpp_dma_singleOrBurst.vhd
8 DMA_SubSystem.vhd
9 DMA_SubSystem_GestionBuffer.vhd
10 DMA_SubSystem_Arbiter.vhd
11 DMA_SubSystem_MUX.vhd
Show file before | Show file after | Hide comments
@@ -1,751 +1,771
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples(2 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC
63 --
63 --
64 --
64 --
65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
65 -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
67
68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
68 -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69
69
70 --debug
70 --debug
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f0_data_valid : OUT STD_LOGIC;
72 --debug_f0_data_valid : OUT STD_LOGIC;
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f1_data_valid : OUT STD_LOGIC;
74 --debug_f1_data_valid : OUT STD_LOGIC;
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76 --debug_f2_data_valid : OUT STD_LOGIC;
76 --debug_f2_data_valid : OUT STD_LOGIC;
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78 --debug_f3_data_valid : OUT STD_LOGIC;
78 --debug_f3_data_valid : OUT STD_LOGIC;
79
79
80 ---- debug FIFO_IN
80 ---- debug FIFO_IN
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89
89
90 ----debug FIFO OUT
90 ----debug FIFO OUT
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99
99
100 ----debug DMA IN
100 ----debug DMA IN
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
109 );
109 );
110 END lpp_lfr;
110 END lpp_lfr;
111
111
112 ARCHITECTURE beh OF lpp_lfr IS
112 ARCHITECTURE beh OF lpp_lfr IS
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
115 --
115 --
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
120 SIGNAL data_shaping_R2 : STD_LOGIC;
120 SIGNAL data_shaping_R2 : STD_LOGIC;
121 --
121 --
122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 --
125 --
126 SIGNAL sample_f0_val : STD_LOGIC;
126 SIGNAL sample_f0_val : STD_LOGIC;
127 SIGNAL sample_f1_val : STD_LOGIC;
127 SIGNAL sample_f1_val : STD_LOGIC;
128 SIGNAL sample_f2_val : STD_LOGIC;
128 SIGNAL sample_f2_val : STD_LOGIC;
129 SIGNAL sample_f3_val : STD_LOGIC;
129 SIGNAL sample_f3_val : STD_LOGIC;
130 --
130 --
131 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
135 --
135 --
136 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
136 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
139
139
140 -- SM
140 -- SM
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
146 SIGNAL error_bad_component_error : STD_LOGIC;
146 -- SIGNAL error_bad_component_error : STD_LOGIC;
147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
154 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
154 --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
155 SIGNAL config_active_interruption_onError : STD_LOGIC;
155 -- SIGNAL config_active_interruption_onError : STD_LOGIC;
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
161 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160
162
161 -- WFP
163 -- WFP
162 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
167 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
170 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
169 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
171 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
170 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
172 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
171
173
172 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
174 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
173 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
175 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
174 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
176 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
175 SIGNAL enable_f0 : STD_LOGIC;
177 SIGNAL enable_f0 : STD_LOGIC;
176 SIGNAL enable_f1 : STD_LOGIC;
178 SIGNAL enable_f1 : STD_LOGIC;
177 SIGNAL enable_f2 : STD_LOGIC;
179 SIGNAL enable_f2 : STD_LOGIC;
178 SIGNAL enable_f3 : STD_LOGIC;
180 SIGNAL enable_f3 : STD_LOGIC;
179 SIGNAL burst_f0 : STD_LOGIC;
181 SIGNAL burst_f0 : STD_LOGIC;
180 SIGNAL burst_f1 : STD_LOGIC;
182 SIGNAL burst_f1 : STD_LOGIC;
181 SIGNAL burst_f2 : STD_LOGIC;
183 SIGNAL burst_f2 : STD_LOGIC;
182 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
186
188
187 SIGNAL run : STD_LOGIC;
189 SIGNAL run : STD_LOGIC;
188 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
190 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
189
191
190 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f0_data_out_valid : STD_LOGIC;
194 SIGNAL data_f0_data_out_valid : STD_LOGIC;
193 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
195 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
194 SIGNAL data_f0_data_out_ren : STD_LOGIC;
196 SIGNAL data_f0_data_out_ren : STD_LOGIC;
195 --f1
197 --f1
196 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f1_data_out_valid : STD_LOGIC;
200 SIGNAL data_f1_data_out_valid : STD_LOGIC;
199 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
200 SIGNAL data_f1_data_out_ren : STD_LOGIC;
202 SIGNAL data_f1_data_out_ren : STD_LOGIC;
201 --f2
203 --f2
202 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f2_data_out_valid : STD_LOGIC;
206 SIGNAL data_f2_data_out_valid : STD_LOGIC;
205 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
207 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
206 SIGNAL data_f2_data_out_ren : STD_LOGIC;
208 SIGNAL data_f2_data_out_ren : STD_LOGIC;
207 --f3
209 --f3
208 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 SIGNAL data_f3_data_out_valid : STD_LOGIC;
212 SIGNAL data_f3_data_out_valid : STD_LOGIC;
211 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
213 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
212 SIGNAL data_f3_data_out_ren : STD_LOGIC;
214 SIGNAL data_f3_data_out_ren : STD_LOGIC;
213
215
214 -----------------------------------------------------------------------------
216 -----------------------------------------------------------------------------
215 --
217 --
216 -----------------------------------------------------------------------------
218 -----------------------------------------------------------------------------
217 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
219 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
218 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
220 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
219 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
221 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
220 --f1
222 --f1
221 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
224 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
223 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
225 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
224 --f2
226 --f2
225 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
227 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
226 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
228 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
227 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
229 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
228 --f3
230 --f3
229 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
231 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
230 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
232 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
231 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
233 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
232
234
233 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
234 -- DMA RR
236 -- DMA RR
235 -----------------------------------------------------------------------------
237 -----------------------------------------------------------------------------
236 SIGNAL dma_sel_valid : STD_LOGIC;
238 SIGNAL dma_sel_valid : STD_LOGIC;
237 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
238 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
240 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
241 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
240 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
242 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
241
243
242 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
244 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
243 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
245 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
244
246
245 -----------------------------------------------------------------------------
247 -----------------------------------------------------------------------------
246 -- DMA_REG
248 -- DMA_REG
247 -----------------------------------------------------------------------------
249 -----------------------------------------------------------------------------
248 SIGNAL ongoing_reg : STD_LOGIC;
250 SIGNAL ongoing_reg : STD_LOGIC;
249 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
251 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
250 SIGNAL dma_send_reg : STD_LOGIC;
252 SIGNAL dma_send_reg : STD_LOGIC;
251 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
253 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
252 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
254
256
255
257
256 -----------------------------------------------------------------------------
258 -----------------------------------------------------------------------------
257 -- DMA
259 -- DMA
258 -----------------------------------------------------------------------------
260 -----------------------------------------------------------------------------
259 SIGNAL dma_send : STD_LOGIC;
261 SIGNAL dma_send : STD_LOGIC;
260 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
262 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
261 SIGNAL dma_done : STD_LOGIC;
263 SIGNAL dma_done : STD_LOGIC;
262 SIGNAL dma_ren : STD_LOGIC;
264 SIGNAL dma_ren : STD_LOGIC;
263 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
265 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
266 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
265 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
266
268
267 -----------------------------------------------------------------------------
269 -----------------------------------------------------------------------------
268 -- MS
270 -- MS
269 -----------------------------------------------------------------------------
271 -----------------------------------------------------------------------------
270
272
271 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL data_ms_valid : STD_LOGIC;
275 SIGNAL data_ms_valid : STD_LOGIC;
274 SIGNAL data_ms_valid_burst : STD_LOGIC;
276 SIGNAL data_ms_valid_burst : STD_LOGIC;
275 SIGNAL data_ms_ren : STD_LOGIC;
277 SIGNAL data_ms_ren : STD_LOGIC;
276 SIGNAL data_ms_done : STD_LOGIC;
278 SIGNAL data_ms_done : STD_LOGIC;
277 SIGNAL dma_ms_ongoing : STD_LOGIC;
279 SIGNAL dma_ms_ongoing : STD_LOGIC;
278
280
279 SIGNAL run_ms : STD_LOGIC;
281 SIGNAL run_ms : STD_LOGIC;
280 SIGNAL ms_softandhard_rstn : STD_LOGIC;
282 SIGNAL ms_softandhard_rstn : STD_LOGIC;
281
283
282 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
284 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
283 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
285 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
284 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
286 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
285 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
287 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
286
288
289
290 SIGNAL error_buffer_full : STD_LOGIC;
291 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
292
293 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
294 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
295
296 -----------------------------------------------------------------------------
297 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
298 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
299 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
300 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
301 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
302 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
303 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
304 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
305 SIGNAL dma_grant_error : STD_LOGIC;
287
306
288 SIGNAL error_buffer_full : STD_LOGIC;
289 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
290
291 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
292 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
293
294 BEGIN
307 BEGIN
295
308
296 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
309 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
297 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
310 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
298
311
299 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
312 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
300 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
313 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
301 --END GENERATE all_channel;
314 --END GENERATE all_channel;
302
315
303 -----------------------------------------------------------------------------
316 -----------------------------------------------------------------------------
304 lpp_lfr_filter_1 : lpp_lfr_filter
317 lpp_lfr_filter_1 : lpp_lfr_filter
305 GENERIC MAP (
318 GENERIC MAP (
306 Mem_use => Mem_use)
319 Mem_use => Mem_use)
307 PORT MAP (
320 PORT MAP (
308 sample => sample_s,
321 sample => sample_s,
309 sample_val => sample_val,
322 sample_val => sample_val,
310 clk => clk,
323 clk => clk,
311 rstn => rstn,
324 rstn => rstn,
312 data_shaping_SP0 => data_shaping_SP0,
325 data_shaping_SP0 => data_shaping_SP0,
313 data_shaping_SP1 => data_shaping_SP1,
326 data_shaping_SP1 => data_shaping_SP1,
314 data_shaping_R0 => data_shaping_R0,
327 data_shaping_R0 => data_shaping_R0,
315 data_shaping_R1 => data_shaping_R1,
328 data_shaping_R1 => data_shaping_R1,
316 data_shaping_R2 => data_shaping_R2,
329 data_shaping_R2 => data_shaping_R2,
317 sample_f0_val => sample_f0_val,
330 sample_f0_val => sample_f0_val,
318 sample_f1_val => sample_f1_val,
331 sample_f1_val => sample_f1_val,
319 sample_f2_val => sample_f2_val,
332 sample_f2_val => sample_f2_val,
320 sample_f3_val => sample_f3_val,
333 sample_f3_val => sample_f3_val,
321 sample_f0_wdata => sample_f0_data,
334 sample_f0_wdata => sample_f0_data,
322 sample_f1_wdata => sample_f1_data,
335 sample_f1_wdata => sample_f1_data,
323 sample_f2_wdata => sample_f2_data,
336 sample_f2_wdata => sample_f2_data,
324 sample_f3_wdata => sample_f3_data);
337 sample_f3_wdata => sample_f3_data);
325
338
326 -----------------------------------------------------------------------------
339 -----------------------------------------------------------------------------
327 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
340 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
328 GENERIC MAP (
341 GENERIC MAP (
329 nb_data_by_buffer_size => nb_data_by_buffer_size,
342 nb_data_by_buffer_size => nb_data_by_buffer_size,
330 nb_word_by_buffer_size => nb_word_by_buffer_size,
343 nb_word_by_buffer_size => nb_word_by_buffer_size,
331 nb_snapshot_param_size => nb_snapshot_param_size,
344 nb_snapshot_param_size => nb_snapshot_param_size,
332 delta_vector_size => delta_vector_size,
345 delta_vector_size => delta_vector_size,
333 delta_vector_size_f0_2 => delta_vector_size_f0_2,
346 delta_vector_size_f0_2 => delta_vector_size_f0_2,
334 pindex => pindex,
347 pindex => pindex,
335 paddr => paddr,
348 paddr => paddr,
336 pmask => pmask,
349 pmask => pmask,
337 pirq_ms => pirq_ms,
350 pirq_ms => pirq_ms,
338 pirq_wfp => pirq_wfp,
351 pirq_wfp => pirq_wfp,
339 top_lfr_version => top_lfr_version)
352 top_lfr_version => top_lfr_version)
340 PORT MAP (
353 PORT MAP (
341 HCLK => clk,
354 HCLK => clk,
342 HRESETn => rstn,
355 HRESETn => rstn,
343 apbi => apbi,
356 apbi => apbi,
344 apbo => apbo,
357 apbo => apbo,
345
358
346 run_ms => run_ms,
359 run_ms => run_ms,
347
360
348 ready_matrix_f0 => ready_matrix_f0,
361 ready_matrix_f0 => ready_matrix_f0,
349 -- ready_matrix_f0_1 => ready_matrix_f0_1,
362 ready_matrix_f1 => ready_matrix_f1,
350 ready_matrix_f1 => ready_matrix_f1,
363 ready_matrix_f2 => ready_matrix_f2,
351 ready_matrix_f2 => ready_matrix_f2,
364 error_buffer_full => error_buffer_full, -- TODO
352 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
365 error_input_fifo_write => error_input_fifo_write, -- TODO
353 error_bad_component_error => error_bad_component_error,
366 status_ready_matrix_f0 => status_ready_matrix_f0,
354 error_buffer_full => error_buffer_full, -- TODO
367 status_ready_matrix_f1 => status_ready_matrix_f1,
355 error_input_fifo_write => error_input_fifo_write, -- TODO
368 status_ready_matrix_f2 => status_ready_matrix_f2,
356 -- debug_reg => debug_reg,
357 status_ready_matrix_f0 => status_ready_matrix_f0,
358 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
359 status_ready_matrix_f1 => status_ready_matrix_f1,
360 status_ready_matrix_f2 => status_ready_matrix_f2,
361 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
362 -- status_error_bad_component_error => status_error_bad_component_error,
363 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
364 config_active_interruption_onError => config_active_interruption_onError,
365
369
366 matrix_time_f0 => matrix_time_f0,
370 matrix_time_f0 => matrix_time_f0,
367 -- matrix_time_f0_1 => matrix_time_f0_1,
371 matrix_time_f1 => matrix_time_f1,
368 matrix_time_f1 => matrix_time_f1,
372 matrix_time_f2 => matrix_time_f2,
369 matrix_time_f2 => matrix_time_f2,
370
373
371 addr_matrix_f0 => addr_matrix_f0,
374 addr_matrix_f0 => addr_matrix_f0,
372 -- addr_matrix_f0_1 => addr_matrix_f0_1,
375 addr_matrix_f1 => addr_matrix_f1,
373 addr_matrix_f1 => addr_matrix_f1,
376 addr_matrix_f2 => addr_matrix_f2,
374 addr_matrix_f2 => addr_matrix_f2,
377
378 length_matrix_f0 => length_matrix_f0,
379 length_matrix_f1 => length_matrix_f1,
380 length_matrix_f2 => length_matrix_f2,
375 -------------------------------------------------------------------------
381 -------------------------------------------------------------------------
376 status_full => status_full,
382 status_full => status_full,
377 status_full_ack => status_full_ack,
383 status_full_ack => status_full_ack,
378 status_full_err => status_full_err,
384 status_full_err => status_full_err,
379 status_new_err => status_new_err,
385 status_new_err => status_new_err,
380 data_shaping_BW => data_shaping_BW,
386 data_shaping_BW => data_shaping_BW,
381 data_shaping_SP0 => data_shaping_SP0,
387 data_shaping_SP0 => data_shaping_SP0,
382 data_shaping_SP1 => data_shaping_SP1,
388 data_shaping_SP1 => data_shaping_SP1,
383 data_shaping_R0 => data_shaping_R0,
389 data_shaping_R0 => data_shaping_R0,
384 data_shaping_R1 => data_shaping_R1,
390 data_shaping_R1 => data_shaping_R1,
385 data_shaping_R2 => data_shaping_R2,
391 data_shaping_R2 => data_shaping_R2,
386 delta_snapshot => delta_snapshot,
392 delta_snapshot => delta_snapshot,
387 delta_f0 => delta_f0,
393 delta_f0 => delta_f0,
388 delta_f0_2 => delta_f0_2,
394 delta_f0_2 => delta_f0_2,
389 delta_f1 => delta_f1,
395 delta_f1 => delta_f1,
390 delta_f2 => delta_f2,
396 delta_f2 => delta_f2,
391 nb_data_by_buffer => nb_data_by_buffer,
397 nb_data_by_buffer => nb_data_by_buffer,
392 nb_word_by_buffer => nb_word_by_buffer,
398 nb_word_by_buffer => nb_word_by_buffer,
393 nb_snapshot_param => nb_snapshot_param,
399 nb_snapshot_param => nb_snapshot_param,
394 enable_f0 => enable_f0,
400 enable_f0 => enable_f0,
395 enable_f1 => enable_f1,
401 enable_f1 => enable_f1,
396 enable_f2 => enable_f2,
402 enable_f2 => enable_f2,
397 enable_f3 => enable_f3,
403 enable_f3 => enable_f3,
398 burst_f0 => burst_f0,
404 burst_f0 => burst_f0,
399 burst_f1 => burst_f1,
405 burst_f1 => burst_f1,
400 burst_f2 => burst_f2,
406 burst_f2 => burst_f2,
401 run => run,
407 run => run,
402 addr_data_f0 => addr_data_f0,
408 addr_data_f0 => addr_data_f0,
403 addr_data_f1 => addr_data_f1,
409 addr_data_f1 => addr_data_f1,
404 addr_data_f2 => addr_data_f2,
410 addr_data_f2 => addr_data_f2,
405 addr_data_f3 => addr_data_f3,
411 addr_data_f3 => addr_data_f3,
406 start_date => start_date,
412 start_date => start_date,
407 debug_signal => debug_signal);
413 debug_signal => debug_signal);
408
414
409 -----------------------------------------------------------------------------
415 -----------------------------------------------------------------------------
410 -----------------------------------------------------------------------------
416 -----------------------------------------------------------------------------
411 lpp_waveform_1 : lpp_waveform
417 lpp_waveform_1 : lpp_waveform
412 GENERIC MAP (
418 GENERIC MAP (
413 tech => inferred,
419 tech => inferred,
414 data_size => 6*16,
420 data_size => 6*16,
415 nb_data_by_buffer_size => nb_data_by_buffer_size,
421 nb_data_by_buffer_size => nb_data_by_buffer_size,
416 nb_word_by_buffer_size => nb_word_by_buffer_size,
422 nb_word_by_buffer_size => nb_word_by_buffer_size,
417 nb_snapshot_param_size => nb_snapshot_param_size,
423 nb_snapshot_param_size => nb_snapshot_param_size,
418 delta_vector_size => delta_vector_size,
424 delta_vector_size => delta_vector_size,
419 delta_vector_size_f0_2 => delta_vector_size_f0_2
425 delta_vector_size_f0_2 => delta_vector_size_f0_2
420 )
426 )
421 PORT MAP (
427 PORT MAP (
422 clk => clk,
428 clk => clk,
423 rstn => rstn,
429 rstn => rstn,
424
430
425 reg_run => run,
431 reg_run => run,
426 reg_start_date => start_date,
432 reg_start_date => start_date,
427 reg_delta_snapshot => delta_snapshot,
433 reg_delta_snapshot => delta_snapshot,
428 reg_delta_f0 => delta_f0,
434 reg_delta_f0 => delta_f0,
429 reg_delta_f0_2 => delta_f0_2,
435 reg_delta_f0_2 => delta_f0_2,
430 reg_delta_f1 => delta_f1,
436 reg_delta_f1 => delta_f1,
431 reg_delta_f2 => delta_f2,
437 reg_delta_f2 => delta_f2,
432
438
433 enable_f0 => enable_f0,
439 enable_f0 => enable_f0,
434 enable_f1 => enable_f1,
440 enable_f1 => enable_f1,
435 enable_f2 => enable_f2,
441 enable_f2 => enable_f2,
436 enable_f3 => enable_f3,
442 enable_f3 => enable_f3,
437 burst_f0 => burst_f0,
443 burst_f0 => burst_f0,
438 burst_f1 => burst_f1,
444 burst_f1 => burst_f1,
439 burst_f2 => burst_f2,
445 burst_f2 => burst_f2,
440
446
441 nb_data_by_buffer => nb_data_by_buffer,
447 nb_data_by_buffer => nb_data_by_buffer,
442 nb_word_by_buffer => nb_word_by_buffer,
448 nb_word_by_buffer => nb_word_by_buffer,
443 nb_snapshot_param => nb_snapshot_param,
449 nb_snapshot_param => nb_snapshot_param,
444 status_full => status_full,
450 status_full => status_full,
445 status_full_ack => status_full_ack,
451 status_full_ack => status_full_ack,
446 status_full_err => status_full_err,
452 status_full_err => status_full_err,
447 status_new_err => status_new_err,
453 status_new_err => status_new_err,
448
454
449 coarse_time => coarse_time,
455 coarse_time => coarse_time,
450 fine_time => fine_time,
456 fine_time => fine_time,
451
457
452 --f0
458 --f0
453 addr_data_f0 => addr_data_f0,
459 addr_data_f0 => addr_data_f0,
454 data_f0_in_valid => sample_f0_val,
460 data_f0_in_valid => sample_f0_val,
455 data_f0_in => sample_f0_data,
461 data_f0_in => sample_f0_data,
456 --f1
462 --f1
457 addr_data_f1 => addr_data_f1,
463 addr_data_f1 => addr_data_f1,
458 data_f1_in_valid => sample_f1_val,
464 data_f1_in_valid => sample_f1_val,
459 data_f1_in => sample_f1_data,
465 data_f1_in => sample_f1_data,
460 --f2
466 --f2
461 addr_data_f2 => addr_data_f2,
467 addr_data_f2 => addr_data_f2,
462 data_f2_in_valid => sample_f2_val,
468 data_f2_in_valid => sample_f2_val,
463 data_f2_in => sample_f2_data,
469 data_f2_in => sample_f2_data,
464 --f3
470 --f3
465 addr_data_f3 => addr_data_f3,
471 addr_data_f3 => addr_data_f3,
466 data_f3_in_valid => sample_f3_val,
472 data_f3_in_valid => sample_f3_val,
467 data_f3_in => sample_f3_data,
473 data_f3_in => sample_f3_data,
468 -- OUTPUT -- DMA interface
474 -- OUTPUT -- DMA interface
469 --f0
475 --f0
470 data_f0_addr_out => data_f0_addr_out_s,
476 data_f0_addr_out => data_f0_addr_out_s,
471 data_f0_data_out => data_f0_data_out,
477 data_f0_data_out => data_f0_data_out,
472 data_f0_data_out_valid => data_f0_data_out_valid_s,
478 data_f0_data_out_valid => data_f0_data_out_valid_s,
473 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
479 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
474 data_f0_data_out_ren => data_f0_data_out_ren,
480 data_f0_data_out_ren => data_f0_data_out_ren,
475 --f1
481 --f1
476 data_f1_addr_out => data_f1_addr_out_s,
482 data_f1_addr_out => data_f1_addr_out_s,
477 data_f1_data_out => data_f1_data_out,
483 data_f1_data_out => data_f1_data_out,
478 data_f1_data_out_valid => data_f1_data_out_valid_s,
484 data_f1_data_out_valid => data_f1_data_out_valid_s,
479 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
485 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
480 data_f1_data_out_ren => data_f1_data_out_ren,
486 data_f1_data_out_ren => data_f1_data_out_ren,
481 --f2
487 --f2
482 data_f2_addr_out => data_f2_addr_out_s,
488 data_f2_addr_out => data_f2_addr_out_s,
483 data_f2_data_out => data_f2_data_out,
489 data_f2_data_out => data_f2_data_out,
484 data_f2_data_out_valid => data_f2_data_out_valid_s,
490 data_f2_data_out_valid => data_f2_data_out_valid_s,
485 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
491 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
486 data_f2_data_out_ren => data_f2_data_out_ren,
492 data_f2_data_out_ren => data_f2_data_out_ren,
487 --f3
493 --f3
488 data_f3_addr_out => data_f3_addr_out_s,
494 data_f3_addr_out => data_f3_addr_out_s,
489 data_f3_data_out => data_f3_data_out,
495 data_f3_data_out => data_f3_data_out,
490 data_f3_data_out_valid => data_f3_data_out_valid_s,
496 data_f3_data_out_valid => data_f3_data_out_valid_s,
491 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
497 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
492 data_f3_data_out_ren => data_f3_data_out_ren ,
498 data_f3_data_out_ren => data_f3_data_out_ren ,
493
499
494 -------------------------------------------------------------------------
500 -------------------------------------------------------------------------
495 observation_reg => OPEN
501 observation_reg => OPEN
496
502
497 );
503 );
498
504
499
505
500 -----------------------------------------------------------------------------
506 -----------------------------------------------------------------------------
501 -- TEMP
507 -- TEMP
502 -----------------------------------------------------------------------------
508 -----------------------------------------------------------------------------
503
509
504 PROCESS (clk, rstn)
510 PROCESS (clk, rstn)
505 BEGIN -- PROCESS
511 BEGIN -- PROCESS
506 IF rstn = '0' THEN -- asynchronous reset (active low)
512 IF rstn = '0' THEN -- asynchronous reset (active low)
507 data_f0_data_out_valid <= '0';
513 data_f0_data_out_valid <= '0';
508 data_f0_data_out_valid_burst <= '0';
514 data_f0_data_out_valid_burst <= '0';
509 data_f1_data_out_valid <= '0';
515 data_f1_data_out_valid <= '0';
510 data_f1_data_out_valid_burst <= '0';
516 data_f1_data_out_valid_burst <= '0';
511 data_f2_data_out_valid <= '0';
517 data_f2_data_out_valid <= '0';
512 data_f2_data_out_valid_burst <= '0';
518 data_f2_data_out_valid_burst <= '0';
513 data_f3_data_out_valid <= '0';
519 data_f3_data_out_valid <= '0';
514 data_f3_data_out_valid_burst <= '0';
520 data_f3_data_out_valid_burst <= '0';
515 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
521 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
516 data_f0_data_out_valid <= data_f0_data_out_valid_s;
522 data_f0_data_out_valid <= data_f0_data_out_valid_s;
517 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
523 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
518 data_f1_data_out_valid <= data_f1_data_out_valid_s;
524 data_f1_data_out_valid <= data_f1_data_out_valid_s;
519 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
525 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
520 data_f2_data_out_valid <= data_f2_data_out_valid_s;
526 data_f2_data_out_valid <= data_f2_data_out_valid_s;
521 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
527 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
522 data_f3_data_out_valid <= data_f3_data_out_valid_s;
528 data_f3_data_out_valid <= data_f3_data_out_valid_s;
523 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
529 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
524 END IF;
530 END IF;
525 END PROCESS;
531 END PROCESS;
526
532
527 data_f0_addr_out <= data_f0_addr_out_s;
533 data_f0_addr_out <= data_f0_addr_out_s;
528 data_f1_addr_out <= data_f1_addr_out_s;
534 data_f1_addr_out <= data_f1_addr_out_s;
529 data_f2_addr_out <= data_f2_addr_out_s;
535 data_f2_addr_out <= data_f2_addr_out_s;
530 data_f3_addr_out <= data_f3_addr_out_s;
536 data_f3_addr_out <= data_f3_addr_out_s;
531
537
532 -----------------------------------------------------------------------------
538 -----------------------------------------------------------------------------
533 -- RoundRobin Selection For DMA
539 -- RoundRobin Selection For DMA
534 -----------------------------------------------------------------------------
540 -----------------------------------------------------------------------------
535
541
536 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
542 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
537 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
543 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
538 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
544 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
539 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
545 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
540
546
541 RR_Arbiter_4_1 : RR_Arbiter_4
547 RR_Arbiter_4_1 : RR_Arbiter_4
542 PORT MAP (
548 PORT MAP (
543 clk => clk,
549 clk => clk,
544 rstn => rstn,
550 rstn => rstn,
545 in_valid => dma_rr_valid,
551 in_valid => dma_rr_valid,
546 out_grant => dma_rr_grant_s);
552 out_grant => dma_rr_grant_s);
547
553
548 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
554 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
549 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
555 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
550 dma_rr_valid_ms(2) <= '0';
556 dma_rr_valid_ms(2) <= '0';
551 dma_rr_valid_ms(3) <= '0';
557 dma_rr_valid_ms(3) <= '0';
552
558
553 RR_Arbiter_4_2 : RR_Arbiter_4
559 RR_Arbiter_4_2 : RR_Arbiter_4
554 PORT MAP (
560 PORT MAP (
555 clk => clk,
561 clk => clk,
556 rstn => rstn,
562 rstn => rstn,
557 in_valid => dma_rr_valid_ms,
563 in_valid => dma_rr_valid_ms,
558 out_grant => dma_rr_grant_ms);
564 out_grant => dma_rr_grant_ms);
559
565
560 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
566 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
561
567
562
568
563 -----------------------------------------------------------------------------
569 -----------------------------------------------------------------------------
564 -- in : dma_rr_grant
570 -- in : dma_rr_grant
565 -- send
571 -- send
566 -- out : dma_sel
572 -- out : dma_sel
567 -- dma_valid_burst
573 -- dma_valid_burst
568 -- dma_sel_valid
574 -- dma_sel_valid
569 -----------------------------------------------------------------------------
575 -----------------------------------------------------------------------------
570 PROCESS (clk, rstn)
576 PROCESS (clk, rstn)
571 BEGIN -- PROCESS
577 BEGIN -- PROCESS
572 IF rstn = '0' THEN -- asynchronous reset (active low)
578 IF rstn = '0' THEN -- asynchronous reset (active low)
573 dma_sel <= (OTHERS => '0');
579 dma_sel <= (OTHERS => '0');
574 dma_send <= '0';
580 dma_send <= '0';
575 dma_valid_burst <= '0';
581 dma_valid_burst <= '0';
576 data_ms_done <= '0';
582 data_ms_done <= '0';
577 dma_ms_ongoing <= '0';
583 dma_ms_ongoing <= '0';
578 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
584 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
579 IF run = '1' THEN
585 IF run = '1' THEN
580 data_ms_done <= '0';
586 data_ms_done <= '0';
581 IF dma_sel = "00000" OR dma_done = '1' THEN
587 IF dma_sel = "00000" OR dma_done = '1' THEN
582 dma_sel <= dma_rr_grant;
588 dma_sel <= dma_rr_grant;
583 IF dma_rr_grant(0) = '1' THEN
589 IF dma_rr_grant(0) = '1' THEN
584 dma_ms_ongoing <= '0';
590 dma_ms_ongoing <= '0';
585 dma_send <= '1';
591 dma_send <= '1';
586 dma_valid_burst <= data_f0_data_out_valid_burst;
592 dma_valid_burst <= data_f0_data_out_valid_burst;
587 dma_sel_valid <= data_f0_data_out_valid;
593 dma_sel_valid <= data_f0_data_out_valid;
588 ELSIF dma_rr_grant(1) = '1' THEN
594 ELSIF dma_rr_grant(1) = '1' THEN
589 dma_ms_ongoing <= '0';
595 dma_ms_ongoing <= '0';
590 dma_send <= '1';
596 dma_send <= '1';
591 dma_valid_burst <= data_f1_data_out_valid_burst;
597 dma_valid_burst <= data_f1_data_out_valid_burst;
592 dma_sel_valid <= data_f1_data_out_valid;
598 dma_sel_valid <= data_f1_data_out_valid;
593 ELSIF dma_rr_grant(2) = '1' THEN
599 ELSIF dma_rr_grant(2) = '1' THEN
594 dma_ms_ongoing <= '0';
600 dma_ms_ongoing <= '0';
595 dma_send <= '1';
601 dma_send <= '1';
596 dma_valid_burst <= data_f2_data_out_valid_burst;
602 dma_valid_burst <= data_f2_data_out_valid_burst;
597 dma_sel_valid <= data_f2_data_out_valid;
603 dma_sel_valid <= data_f2_data_out_valid;
598 ELSIF dma_rr_grant(3) = '1' THEN
604 ELSIF dma_rr_grant(3) = '1' THEN
599 dma_ms_ongoing <= '0';
605 dma_ms_ongoing <= '0';
600 dma_send <= '1';
606 dma_send <= '1';
601 dma_valid_burst <= data_f3_data_out_valid_burst;
607 dma_valid_burst <= data_f3_data_out_valid_burst;
602 dma_sel_valid <= data_f3_data_out_valid;
608 dma_sel_valid <= data_f3_data_out_valid;
603 ELSIF dma_rr_grant(4) = '1' THEN
609 ELSIF dma_rr_grant(4) = '1' THEN
604 dma_ms_ongoing <= '1';
610 dma_ms_ongoing <= '1';
605 dma_send <= '1';
611 dma_send <= '1';
606 dma_valid_burst <= data_ms_valid_burst;
612 dma_valid_burst <= data_ms_valid_burst;
607 dma_sel_valid <= data_ms_valid;
613 dma_sel_valid <= data_ms_valid;
608 --ELSE
614 --ELSE
609 --dma_ms_ongoing <= '0';
615 --dma_ms_ongoing <= '0';
610 END IF;
616 END IF;
611
617
612 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
618 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
613 data_ms_done <= '1';
619 data_ms_done <= '1';
614 END IF;
620 END IF;
615 ELSE
621 ELSE
616 dma_sel <= dma_sel;
622 dma_sel <= dma_sel;
617 dma_send <= '0';
623 dma_send <= '0';
618 END IF;
624 END IF;
619 ELSE
625 ELSE
620 data_ms_done <= '0';
626 data_ms_done <= '0';
621 dma_sel <= (OTHERS => '0');
627 dma_sel <= (OTHERS => '0');
622 dma_send <= '0';
628 dma_send <= '0';
623 dma_valid_burst <= '0';
629 dma_valid_burst <= '0';
624 END IF;
630 END IF;
625 END IF;
631 END IF;
626 END PROCESS;
632 END PROCESS;
627
633
628
634
629 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
635 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
630 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
636 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
631 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
637 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
632 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
638 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
633 data_ms_addr;
639 data_ms_addr;
634
640
635 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
641 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
636 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
642 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
637 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
643 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
638 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
644 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
639 data_ms_data;
645 data_ms_data;
640
646
641 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
647 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
642 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
648 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
643 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
649 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
644 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
650 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
645 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
651 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
646
652
647 dma_data_2 <= dma_data;
653 dma_data_2 <= dma_data;
648
654
649
655
650 -----------------------------------------------------------------------------
656 -----------------------------------------------------------------------------
651 -- DMA
657 -- DMA
652 -----------------------------------------------------------------------------
658 -----------------------------------------------------------------------------
653 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
659 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
654 GENERIC MAP (
660 GENERIC MAP (
655 tech => inferred,
661 tech => inferred,
656 hindex => hindex)
662 hindex => hindex)
657 PORT MAP (
663 PORT MAP (
658 HCLK => clk,
664 HCLK => clk,
659 HRESETn => rstn,
665 HRESETn => rstn,
660 run => run,
666 run => run,
661 AHB_Master_In => ahbi,
667 AHB_Master_In => OPEN,
662 AHB_Master_Out => ahbo,
668 AHB_Master_Out => OPEN,
663
669
664 send => dma_send,
670 send => dma_send,
665 valid_burst => dma_valid_burst,
671 valid_burst => dma_valid_burst,
666 done => dma_done,
672 done => dma_done,
667 ren => dma_ren,
673 ren => dma_ren,
668 address => dma_address,
674 address => dma_address,
669 data => dma_data_2);
675 data => dma_data_2);
670
676
671 -----------------------------------------------------------------------------
677 -----------------------------------------------------------------------------
672 -- Matrix Spectral
678 -- Matrix Spectral
673 -----------------------------------------------------------------------------
679 -----------------------------------------------------------------------------
674 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
680 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
675 NOT(sample_f0_val) & NOT(sample_f0_val);
681 NOT(sample_f0_val) & NOT(sample_f0_val);
676 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
682 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
677 NOT(sample_f1_val) & NOT(sample_f1_val);
683 NOT(sample_f1_val) & NOT(sample_f1_val);
678 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
684 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
679 NOT(sample_f2_val) & NOT(sample_f2_val);
685 NOT(sample_f2_val) & NOT(sample_f2_val);
680
686
681 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
687 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
682 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
688 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
683 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
689 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
684
690
685 -------------------------------------------------------------------------------
691 -------------------------------------------------------------------------------
686
692
687 ms_softandhard_rstn <= rstn AND run_ms AND run;
693 ms_softandhard_rstn <= rstn AND run_ms AND run;
688
694
689 -----------------------------------------------------------------------------
695 -----------------------------------------------------------------------------
690 lpp_lfr_ms_1 : lpp_lfr_ms
696 lpp_lfr_ms_1 : lpp_lfr_ms
691 GENERIC MAP (
697 GENERIC MAP (
692 Mem_use => Mem_use)
698 Mem_use => Mem_use)
693 PORT MAP (
699 PORT MAP (
694 clk => clk,
700 clk => clk,
695 rstn => ms_softandhard_rstn, --rstn,
701 rstn => ms_softandhard_rstn, --rstn,
702 run => run_ms,
696
703
697 coarse_time => coarse_time,
704 coarse_time => coarse_time,
698 fine_time => fine_time,
705 fine_time => fine_time,
699
706
700 sample_f0_wen => sample_f0_wen,
707 sample_f0_wen => sample_f0_wen,
701 sample_f0_wdata => sample_f0_wdata,
708 sample_f0_wdata => sample_f0_wdata,
702 sample_f1_wen => sample_f1_wen,
709 sample_f1_wen => sample_f1_wen,
703 sample_f1_wdata => sample_f1_wdata,
710 sample_f1_wdata => sample_f1_wdata,
704 sample_f2_wen => sample_f2_wen, -- TODO
711 sample_f2_wen => sample_f2_wen,
705 sample_f2_wdata => sample_f2_wdata,-- TODO
712 sample_f2_wdata => sample_f2_wdata,
706
713
707 dma_addr => data_ms_addr, --
714 --DMA
708 dma_data => data_ms_data, --
715 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
709 dma_valid => data_ms_valid, --
716 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
710 dma_valid_burst => data_ms_valid_burst, --
717 dma_fifo_ren => dma_fifo_ren(4), -- IN
711 dma_ren => data_ms_ren, --
718 dma_buffer_new => dma_buffer_new(4), -- OUT
712 dma_done => data_ms_done, --
719 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
720 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
721 dma_buffer_full => dma_buffer_full(4), -- IN
722 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
723
724
713
725
714 ready_matrix_f0 => ready_matrix_f0,
726 --REG
715 ready_matrix_f1 => ready_matrix_f1,
727 ready_matrix_f0 => ready_matrix_f0,
716 ready_matrix_f2 => ready_matrix_f2,
728 ready_matrix_f1 => ready_matrix_f1,
717 error_bad_component_error => error_bad_component_error,
729 ready_matrix_f2 => ready_matrix_f2,
718 error_buffer_full => error_buffer_full,
730 error_buffer_full => error_buffer_full,
719 error_input_fifo_write => error_input_fifo_write,
731 error_input_fifo_write => error_input_fifo_write,
720
721 debug_reg => debug_ms,--observation_reg,
722 observation_vector_0 => observation_vector_0,
723 observation_vector_1 => observation_vector_1,
724
725 status_ready_matrix_f0 => status_ready_matrix_f0,
726 status_ready_matrix_f1 => status_ready_matrix_f1,
727 status_ready_matrix_f2 => status_ready_matrix_f2,
728 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
729 config_active_interruption_onError => config_active_interruption_onError,
730 addr_matrix_f0 => addr_matrix_f0,
731 addr_matrix_f1 => addr_matrix_f1,
732 addr_matrix_f2 => addr_matrix_f2,
733
732
734 matrix_time_f0 => matrix_time_f0,
733 status_ready_matrix_f0 => status_ready_matrix_f0,
735 matrix_time_f1 => matrix_time_f1,
734 status_ready_matrix_f1 => status_ready_matrix_f1,
736 matrix_time_f2 => matrix_time_f2);
735 status_ready_matrix_f2 => status_ready_matrix_f2,
736 addr_matrix_f0 => addr_matrix_f0,
737 addr_matrix_f1 => addr_matrix_f1,
738 addr_matrix_f2 => addr_matrix_f2,
739
740 length_matrix_f0 => length_matrix_f0,
741 length_matrix_f1 => length_matrix_f1,
742 length_matrix_f2 => length_matrix_f2,
743
744 matrix_time_f0 => matrix_time_f0,
745 matrix_time_f1 => matrix_time_f1,
746 matrix_time_f2 => matrix_time_f2);
737
747
738 -----------------------------------------------------------------------------
748 -----------------------------------------------------------------------------
739
749
740
750 DMA_SubSystem_1 : DMA_SubSystem
741 observation_reg(31 DOWNTO 0) <=
751 GENERIC MAP (
742 dma_sel(4) & -- 31
752 hindex => hindex)
743 dma_ms_ongoing & -- 30
753 PORT MAP (
744 data_ms_done & -- 29
754 clk => clk,
745 dma_done & -- 28
755 rstn => rstn,
746 ms_softandhard_rstn & --27
756 run => run_ms,
747 debug_ms(14 DOWNTO 12) & -- 26 .. 24
757 ahbi => ahbi,
748 debug_ms(11 DOWNTO 0) & -- 23 .. 12
758 ahbo => ahbo,
749 debug_signal(11 DOWNTO 0); -- 11 .. 0
759
750
760 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
761 fifo_data => dma_fifo_data, --fifo_data,
762 fifo_ren => dma_fifo_ren, --fifo_ren,
763
764 buffer_new => dma_buffer_new, --buffer_new,
765 buffer_addr => dma_buffer_addr, --buffer_addr,
766 buffer_length => dma_buffer_length, --buffer_length,
767 buffer_full => dma_buffer_full, --buffer_full,
768 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
769 grant_error => dma_grant_error); --grant_error);
770
751 END beh;
771 END beh;
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@@ -1,703 +1,721
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
36 USE techmap.gencomp.ALL;
37
37
38 ENTITY lpp_lfr_apbreg IS
38 ENTITY lpp_lfr_apbreg IS
39 GENERIC (
39 GENERIC (
40 nb_data_by_buffer_size : INTEGER := 11;
40 nb_data_by_buffer_size : INTEGER := 11;
41 nb_word_by_buffer_size : INTEGER := 11;
41 nb_word_by_buffer_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
43 delta_vector_size : INTEGER := 20;
43 delta_vector_size : INTEGER := 20;
44 delta_vector_size_f0_2 : INTEGER := 3;
44 delta_vector_size_f0_2 : INTEGER := 3;
45
45
46 pindex : INTEGER := 4;
46 pindex : INTEGER := 4;
47 paddr : INTEGER := 4;
47 paddr : INTEGER := 4;
48 pmask : INTEGER := 16#fff#;
48 pmask : INTEGER := 16#fff#;
49 pirq_ms : INTEGER := 0;
49 pirq_ms : INTEGER := 0;
50 pirq_wfp : INTEGER := 1;
50 pirq_wfp : INTEGER := 1;
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56
56
57 -- AMBA APB Slave Interface
57 -- AMBA APB Slave Interface
58 apbi : IN apb_slv_in_type;
58 apbi : IN apb_slv_in_type;
59 apbo : OUT apb_slv_out_type;
59 apbo : OUT apb_slv_out_type;
60
60
61 ---------------------------------------------------------------------------
61 ---------------------------------------------------------------------------
62 -- Spectral Matrix Reg
62 -- Spectral Matrix Reg
63 run_ms : OUT STD_LOGIC;
63 run_ms : OUT STD_LOGIC;
64 -- IN
64 -- IN
65 ready_matrix_f0 : IN STD_LOGIC;
65 ready_matrix_f0 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
68
68
69 error_bad_component_error : IN STD_LOGIC;
69 -- error_bad_component_error : IN STD_LOGIC;
70 error_buffer_full : IN STD_LOGIC; -- TODO
70 error_buffer_full : IN STD_LOGIC; -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72
72
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 -- OUT
75 -- OUT
76 status_ready_matrix_f0 : OUT STD_LOGIC;
76 status_ready_matrix_f0 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 config_active_interruption_onError : OUT STD_LOGIC;
81 --config_active_interruption_onError : OUT STD_LOGIC;
82
82
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90
87 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90
94
91 ---------------------------------------------------------------------------
95 ---------------------------------------------------------------------------
92 ---------------------------------------------------------------------------
96 ---------------------------------------------------------------------------
93 -- WaveForm picker Reg
97 -- WaveForm picker Reg
94 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
95 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
99 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
96 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
97 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98
102
99 -- OUT
103 -- OUT
100 data_shaping_BW : OUT STD_LOGIC;
104 data_shaping_BW : OUT STD_LOGIC;
101 data_shaping_SP0 : OUT STD_LOGIC;
105 data_shaping_SP0 : OUT STD_LOGIC;
102 data_shaping_SP1 : OUT STD_LOGIC;
106 data_shaping_SP1 : OUT STD_LOGIC;
103 data_shaping_R0 : OUT STD_LOGIC;
107 data_shaping_R0 : OUT STD_LOGIC;
104 data_shaping_R1 : OUT STD_LOGIC;
108 data_shaping_R1 : OUT STD_LOGIC;
105 data_shaping_R2 : OUT STD_LOGIC;
109 data_shaping_R2 : OUT STD_LOGIC;
106
110
107 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
108 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
109 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
113 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
110 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
116 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
113 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
117 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
114 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
118 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
115
119
116 enable_f0 : OUT STD_LOGIC;
120 enable_f0 : OUT STD_LOGIC;
117 enable_f1 : OUT STD_LOGIC;
121 enable_f1 : OUT STD_LOGIC;
118 enable_f2 : OUT STD_LOGIC;
122 enable_f2 : OUT STD_LOGIC;
119 enable_f3 : OUT STD_LOGIC;
123 enable_f3 : OUT STD_LOGIC;
120
124
121 burst_f0 : OUT STD_LOGIC;
125 burst_f0 : OUT STD_LOGIC;
122 burst_f1 : OUT STD_LOGIC;
126 burst_f1 : OUT STD_LOGIC;
123 burst_f2 : OUT STD_LOGIC;
127 burst_f2 : OUT STD_LOGIC;
124
128
125 run : OUT STD_LOGIC;
129 run : OUT STD_LOGIC;
126
130
127 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
131 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
133 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
134 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
131 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
135 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
132 ---------------------------------------------------------------------------
136 ---------------------------------------------------------------------------
133 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
137 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
134 ---------------------------------------------------------------------------
138 ---------------------------------------------------------------------------
135 );
139 );
136
140
137 END lpp_lfr_apbreg;
141 END lpp_lfr_apbreg;
138
142
139 ARCHITECTURE beh OF lpp_lfr_apbreg IS
143 ARCHITECTURE beh OF lpp_lfr_apbreg IS
140
144
141 CONSTANT REVISION : INTEGER := 1;
145 CONSTANT REVISION : INTEGER := 1;
142
146
143 CONSTANT pconfig : apb_config_type := (
147 CONSTANT pconfig : apb_config_type := (
144 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
148 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
145 1 => apb_iobar(paddr, pmask));
149 1 => apb_iobar(paddr, pmask));
146
150
147 TYPE lpp_SpectralMatrix_regs IS RECORD
151 TYPE lpp_SpectralMatrix_regs IS RECORD
148 config_active_interruption_onNewMatrix : STD_LOGIC;
152 config_active_interruption_onNewMatrix : STD_LOGIC;
149 config_active_interruption_onError : STD_LOGIC;
153 config_active_interruption_onError : STD_LOGIC;
150 config_ms_run : STD_LOGIC;
154 config_ms_run : STD_LOGIC;
151 status_ready_matrix_f0_0 : STD_LOGIC;
155 status_ready_matrix_f0_0 : STD_LOGIC;
152 status_ready_matrix_f1_0 : STD_LOGIC;
156 status_ready_matrix_f1_0 : STD_LOGIC;
153 status_ready_matrix_f2_0 : STD_LOGIC;
157 status_ready_matrix_f2_0 : STD_LOGIC;
154 status_ready_matrix_f0_1 : STD_LOGIC;
158 status_ready_matrix_f0_1 : STD_LOGIC;
155 status_ready_matrix_f1_1 : STD_LOGIC;
159 status_ready_matrix_f1_1 : STD_LOGIC;
156 status_ready_matrix_f2_1 : STD_LOGIC;
160 status_ready_matrix_f2_1 : STD_LOGIC;
157 status_error_bad_component_error : STD_LOGIC;
161 -- status_error_bad_component_error : STD_LOGIC;
158 status_error_buffer_full : STD_LOGIC;
162 status_error_buffer_full : STD_LOGIC;
159 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
163 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
160
164
161 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167
171
172 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
173
168 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
174 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
169 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
172 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
173 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
174 END RECORD;
180 END RECORD;
175 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
181 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
176
182
177 TYPE lpp_WaveformPicker_regs IS RECORD
183 TYPE lpp_WaveformPicker_regs IS RECORD
178 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 data_shaping_BW : STD_LOGIC;
187 data_shaping_BW : STD_LOGIC;
182 data_shaping_SP0 : STD_LOGIC;
188 data_shaping_SP0 : STD_LOGIC;
183 data_shaping_SP1 : STD_LOGIC;
189 data_shaping_SP1 : STD_LOGIC;
184 data_shaping_R0 : STD_LOGIC;
190 data_shaping_R0 : STD_LOGIC;
185 data_shaping_R1 : STD_LOGIC;
191 data_shaping_R1 : STD_LOGIC;
186 data_shaping_R2 : STD_LOGIC;
192 data_shaping_R2 : STD_LOGIC;
187 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
193 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
188 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
189 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
195 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
190 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
191 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
192 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
198 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
193 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
199 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
194 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
200 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
195 enable_f0 : STD_LOGIC;
201 enable_f0 : STD_LOGIC;
196 enable_f1 : STD_LOGIC;
202 enable_f1 : STD_LOGIC;
197 enable_f2 : STD_LOGIC;
203 enable_f2 : STD_LOGIC;
198 enable_f3 : STD_LOGIC;
204 enable_f3 : STD_LOGIC;
199 burst_f0 : STD_LOGIC;
205 burst_f0 : STD_LOGIC;
200 burst_f1 : STD_LOGIC;
206 burst_f1 : STD_LOGIC;
201 burst_f2 : STD_LOGIC;
207 burst_f2 : STD_LOGIC;
202 run : STD_LOGIC;
208 run : STD_LOGIC;
203 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
213 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
208 END RECORD;
214 END RECORD;
209 SIGNAL reg_wp : lpp_WaveformPicker_regs;
215 SIGNAL reg_wp : lpp_WaveformPicker_regs;
210
216
211 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
212
218
213 -----------------------------------------------------------------------------
219 -----------------------------------------------------------------------------
214 -- IRQ
220 -- IRQ
215 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
216 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
222 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
217 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
223 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
218 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
224 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
219 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
225 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
220 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
221 SIGNAL ored_irq_wfp : STD_LOGIC;
227 SIGNAL ored_irq_wfp : STD_LOGIC;
222
228
223 -----------------------------------------------------------------------------
229 -----------------------------------------------------------------------------
224 --
230 --
225 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
226 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
232 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
227 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
233 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
229
235
230 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
236 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
231 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
237 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
238 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
233
239
234 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
240 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
235 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
242 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
237
243
238 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
244 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
239 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
245 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
246 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241
247
242 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
248 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
243 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
249 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
250 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
245
251
246 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
252 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
247 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
254 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249 SIGNAL apbo_irq_ms : STD_LOGIC;
255 SIGNAL apbo_irq_ms : STD_LOGIC;
250 SIGNAL apbo_irq_wfp : STD_LOGIC;
256 SIGNAL apbo_irq_wfp : STD_LOGIC;
251
257
252 BEGIN -- beh
258 BEGIN -- beh
253
259
254 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
260 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
255 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
261 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
256 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
262 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
257
263
258 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
264 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
259 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
265 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
260
266
261
267
262 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
268 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
263 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
269 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
264 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
270 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
265
271
266
272
267 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
273 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
268 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
274 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
269 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
275 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
270 data_shaping_R0 <= reg_wp.data_shaping_R0;
276 data_shaping_R0 <= reg_wp.data_shaping_R0;
271 data_shaping_R1 <= reg_wp.data_shaping_R1;
277 data_shaping_R1 <= reg_wp.data_shaping_R1;
272 data_shaping_R2 <= reg_wp.data_shaping_R2;
278 data_shaping_R2 <= reg_wp.data_shaping_R2;
273
279
274 delta_snapshot <= reg_wp.delta_snapshot;
280 delta_snapshot <= reg_wp.delta_snapshot;
275 delta_f0 <= reg_wp.delta_f0;
281 delta_f0 <= reg_wp.delta_f0;
276 delta_f0_2 <= reg_wp.delta_f0_2;
282 delta_f0_2 <= reg_wp.delta_f0_2;
277 delta_f1 <= reg_wp.delta_f1;
283 delta_f1 <= reg_wp.delta_f1;
278 delta_f2 <= reg_wp.delta_f2;
284 delta_f2 <= reg_wp.delta_f2;
279 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
285 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
280 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
286 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
281 nb_snapshot_param <= reg_wp.nb_snapshot_param;
287 nb_snapshot_param <= reg_wp.nb_snapshot_param;
282
288
283 enable_f0 <= reg_wp.enable_f0;
289 enable_f0 <= reg_wp.enable_f0;
284 enable_f1 <= reg_wp.enable_f1;
290 enable_f1 <= reg_wp.enable_f1;
285 enable_f2 <= reg_wp.enable_f2;
291 enable_f2 <= reg_wp.enable_f2;
286 enable_f3 <= reg_wp.enable_f3;
292 enable_f3 <= reg_wp.enable_f3;
287
293
288 burst_f0 <= reg_wp.burst_f0;
294 burst_f0 <= reg_wp.burst_f0;
289 burst_f1 <= reg_wp.burst_f1;
295 burst_f1 <= reg_wp.burst_f1;
290 burst_f2 <= reg_wp.burst_f2;
296 burst_f2 <= reg_wp.burst_f2;
291
297
292 run <= reg_wp.run;
298 run <= reg_wp.run;
293
299
294 addr_data_f0 <= reg_wp.addr_data_f0;
300 addr_data_f0 <= reg_wp.addr_data_f0;
295 addr_data_f1 <= reg_wp.addr_data_f1;
301 addr_data_f1 <= reg_wp.addr_data_f1;
296 addr_data_f2 <= reg_wp.addr_data_f2;
302 addr_data_f2 <= reg_wp.addr_data_f2;
297 addr_data_f3 <= reg_wp.addr_data_f3;
303 addr_data_f3 <= reg_wp.addr_data_f3;
298
304
299 start_date <= reg_wp.start_date;
305 start_date <= reg_wp.start_date;
300
306
307 length_matrix_f0 <= reg_sp.length_matrix;
308 length_matrix_f1 <= reg_sp.length_matrix;
309 length_matrix_f2 <= reg_sp.length_matrix;
310
311
301 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
312 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
302 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
313 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
303 BEGIN -- PROCESS lpp_dma_top
314 BEGIN -- PROCESS lpp_dma_top
304 IF HRESETn = '0' THEN -- asynchronous reset (active low)
315 IF HRESETn = '0' THEN -- asynchronous reset (active low)
305 reg_sp.config_active_interruption_onNewMatrix <= '0';
316 reg_sp.config_active_interruption_onNewMatrix <= '0';
306 reg_sp.config_active_interruption_onError <= '0';
317 reg_sp.config_active_interruption_onError <= '0';
307 reg_sp.config_ms_run <= '1';
318 reg_sp.config_ms_run <= '1';
308 reg_sp.status_ready_matrix_f0_0 <= '0';
319 reg_sp.status_ready_matrix_f0_0 <= '0';
309 reg_sp.status_ready_matrix_f1_0 <= '0';
320 reg_sp.status_ready_matrix_f1_0 <= '0';
310 reg_sp.status_ready_matrix_f2_0 <= '0';
321 reg_sp.status_ready_matrix_f2_0 <= '0';
311 reg_sp.status_ready_matrix_f0_1 <= '0';
322 reg_sp.status_ready_matrix_f0_1 <= '0';
312 reg_sp.status_ready_matrix_f1_1 <= '0';
323 reg_sp.status_ready_matrix_f1_1 <= '0';
313 reg_sp.status_ready_matrix_f2_1 <= '0';
324 reg_sp.status_ready_matrix_f2_1 <= '0';
314 reg_sp.status_error_bad_component_error <= '0';
325 -- reg_sp.status_error_bad_component_error <= '0';
315 reg_sp.status_error_buffer_full <= '0';
326 reg_sp.status_error_buffer_full <= '0';
316 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
327 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
317
328
318 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
329 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
319 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
330 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
320 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
331 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
321
332
322 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
333 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
323 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
334 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
324 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
335 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
325
336
337 reg_sp.length_matrix <= (OTHERS => '0');
338
326 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
339 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
327 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
340 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
328 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
341 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
329
342
330 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
343 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
331 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
344 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
332 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
345 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
333
346
334 prdata <= (OTHERS => '0');
347 prdata <= (OTHERS => '0');
335
348
336
349
337 apbo_irq_ms <= '0';
350 apbo_irq_ms <= '0';
338 apbo_irq_wfp <= '0';
351 apbo_irq_wfp <= '0';
339
352
340
353
341 status_full_ack <= (OTHERS => '0');
354 status_full_ack <= (OTHERS => '0');
342
355
343 reg_wp.data_shaping_BW <= '0';
356 reg_wp.data_shaping_BW <= '0';
344 reg_wp.data_shaping_SP0 <= '0';
357 reg_wp.data_shaping_SP0 <= '0';
345 reg_wp.data_shaping_SP1 <= '0';
358 reg_wp.data_shaping_SP1 <= '0';
346 reg_wp.data_shaping_R0 <= '0';
359 reg_wp.data_shaping_R0 <= '0';
347 reg_wp.data_shaping_R1 <= '0';
360 reg_wp.data_shaping_R1 <= '0';
348 reg_wp.data_shaping_R2 <= '0';
361 reg_wp.data_shaping_R2 <= '0';
349 reg_wp.enable_f0 <= '0';
362 reg_wp.enable_f0 <= '0';
350 reg_wp.enable_f1 <= '0';
363 reg_wp.enable_f1 <= '0';
351 reg_wp.enable_f2 <= '0';
364 reg_wp.enable_f2 <= '0';
352 reg_wp.enable_f3 <= '0';
365 reg_wp.enable_f3 <= '0';
353 reg_wp.burst_f0 <= '0';
366 reg_wp.burst_f0 <= '0';
354 reg_wp.burst_f1 <= '0';
367 reg_wp.burst_f1 <= '0';
355 reg_wp.burst_f2 <= '0';
368 reg_wp.burst_f2 <= '0';
356 reg_wp.run <= '0';
369 reg_wp.run <= '0';
357 reg_wp.addr_data_f0 <= (OTHERS => '0');
370 reg_wp.addr_data_f0 <= (OTHERS => '0');
358 reg_wp.addr_data_f1 <= (OTHERS => '0');
371 reg_wp.addr_data_f1 <= (OTHERS => '0');
359 reg_wp.addr_data_f2 <= (OTHERS => '0');
372 reg_wp.addr_data_f2 <= (OTHERS => '0');
360 reg_wp.addr_data_f3 <= (OTHERS => '0');
373 reg_wp.addr_data_f3 <= (OTHERS => '0');
361 reg_wp.status_full <= (OTHERS => '0');
374 reg_wp.status_full <= (OTHERS => '0');
362 reg_wp.status_full_err <= (OTHERS => '0');
375 reg_wp.status_full_err <= (OTHERS => '0');
363 reg_wp.status_new_err <= (OTHERS => '0');
376 reg_wp.status_new_err <= (OTHERS => '0');
364 reg_wp.delta_snapshot <= (OTHERS => '0');
377 reg_wp.delta_snapshot <= (OTHERS => '0');
365 reg_wp.delta_f0 <= (OTHERS => '0');
378 reg_wp.delta_f0 <= (OTHERS => '0');
366 reg_wp.delta_f0_2 <= (OTHERS => '0');
379 reg_wp.delta_f0_2 <= (OTHERS => '0');
367 reg_wp.delta_f1 <= (OTHERS => '0');
380 reg_wp.delta_f1 <= (OTHERS => '0');
368 reg_wp.delta_f2 <= (OTHERS => '0');
381 reg_wp.delta_f2 <= (OTHERS => '0');
369 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
382 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
370 reg_wp.nb_snapshot_param <= (OTHERS => '0');
383 reg_wp.nb_snapshot_param <= (OTHERS => '0');
371 reg_wp.start_date <= (OTHERS => '0');
384 reg_wp.start_date <= (OTHERS => '0');
372
385
373 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
386 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
374
387
375 status_full_ack <= (OTHERS => '0');
388 status_full_ack <= (OTHERS => '0');
376
389
377 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
390 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
378 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
391 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
379 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
392 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
380
393
381 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
394 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
382 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
395 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
383 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
396 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
384
397
385 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
398 -- reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
386
399
387 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
400 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
388 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
401 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
389 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
402 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
390 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
403 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
391
404
392
405
393
406
394 all_status : FOR I IN 3 DOWNTO 0 LOOP
407 all_status : FOR I IN 3 DOWNTO 0 LOOP
395 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
408 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
396 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
409 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
397 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
410 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
398 END LOOP all_status;
411 END LOOP all_status;
399
412
400 paddr := "000000";
413 paddr := "000000";
401 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
414 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
402 prdata <= (OTHERS => '0');
415 prdata <= (OTHERS => '0');
403 IF apbi.psel(pindex) = '1' THEN
416 IF apbi.psel(pindex) = '1' THEN
404 -- APB DMA READ --
417 -- APB DMA READ --
405 CASE paddr(7 DOWNTO 2) IS
418 CASE paddr(7 DOWNTO 2) IS
406 --0
419 --0
407 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
420 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
408 prdata(1) <= reg_sp.config_active_interruption_onError;
421 prdata(1) <= reg_sp.config_active_interruption_onError;
409 prdata(2) <= reg_sp.config_ms_run;
422 prdata(2) <= reg_sp.config_ms_run;
410 --1
423 --1
411 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
424 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
412 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
425 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
413 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
426 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
414 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
427 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
415 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
428 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
416 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
429 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
417 prdata(6) <= reg_sp.status_error_bad_component_error;
430 -- prdata(6) <= reg_sp.status_error_bad_component_error;
418 prdata(7) <= reg_sp.status_error_buffer_full;
431 prdata(7) <= reg_sp.status_error_buffer_full;
419 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
432 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
420 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
433 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
421 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
434 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
422 --2
435 --2
423 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
436 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
424 --3
437 --3
425 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
438 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
426 --4
439 --4
427 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
440 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
428 --5
441 --5
429 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
442 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
430 --6
443 --6
431 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
444 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
432 --7
445 --7
433 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
446 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
434 --8
447 --8
435 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
448 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
436 --9
449 --9
437 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
450 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
438 --10
451 --10
439 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
452 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
440 --11
453 --11
441 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
454 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
442 --12
455 --12
443 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
456 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
444 --13
457 --13
445 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
458 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
446 --14
459 --14
447 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
460 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
448 --15
461 --15
449 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
462 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
450 --16
463 --16
451 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
464 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
452 --17
465 --17
453 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
466 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
454 --18
467 --18
455 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
468 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
456 --19
469 --19
457 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
470 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
471 --20
472 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
458 ---------------------------------------------------------------------
473 ---------------------------------------------------------------------
459 --20
474 --20
460 WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
475 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
461 prdata(1) <= reg_wp.data_shaping_SP0;
476 prdata(1) <= reg_wp.data_shaping_SP0;
462 prdata(2) <= reg_wp.data_shaping_SP1;
477 prdata(2) <= reg_wp.data_shaping_SP1;
463 prdata(3) <= reg_wp.data_shaping_R0;
478 prdata(3) <= reg_wp.data_shaping_R0;
464 prdata(4) <= reg_wp.data_shaping_R1;
479 prdata(4) <= reg_wp.data_shaping_R1;
465 prdata(5) <= reg_wp.data_shaping_R2;
480 prdata(5) <= reg_wp.data_shaping_R2;
466 --21
481 --21
467 WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
482 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
468 prdata(1) <= reg_wp.enable_f1;
483 prdata(1) <= reg_wp.enable_f1;
469 prdata(2) <= reg_wp.enable_f2;
484 prdata(2) <= reg_wp.enable_f2;
470 prdata(3) <= reg_wp.enable_f3;
485 prdata(3) <= reg_wp.enable_f3;
471 prdata(4) <= reg_wp.burst_f0;
486 prdata(4) <= reg_wp.burst_f0;
472 prdata(5) <= reg_wp.burst_f1;
487 prdata(5) <= reg_wp.burst_f1;
473 prdata(6) <= reg_wp.burst_f2;
488 prdata(6) <= reg_wp.burst_f2;
474 prdata(7) <= reg_wp.run;
489 prdata(7) <= reg_wp.run;
475 --22
490 --22
476 WHEN "010110" => prdata <= reg_wp.addr_data_f0;
491 WHEN "010111" => prdata <= reg_wp.addr_data_f0;
477 --23
492 --23
478 WHEN "010111" => prdata <= reg_wp.addr_data_f1;
493 WHEN "011000" => prdata <= reg_wp.addr_data_f1;
479 --24
494 --24
480 WHEN "011000" => prdata <= reg_wp.addr_data_f2;
495 WHEN "011001" => prdata <= reg_wp.addr_data_f2;
481 --25
496 --25
482 WHEN "011001" => prdata <= reg_wp.addr_data_f3;
497 WHEN "011010" => prdata <= reg_wp.addr_data_f3;
483 --26
498 --26
484 WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
499 WHEN "011011" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
485 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
500 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
486 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
501 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
487 --27
502 --27
488 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
503 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
489 --28
504 --28
490 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
505 WHEN "011101" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
491 --29
506 --29
492 WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
507 WHEN "011110" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
493 --30
508 --30
494 WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
509 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
495 --31
510 --31
496 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
497 --32
512 --32
498 WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
513 WHEN "100001" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
499 --33
514 --33
500 WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
515 WHEN "100010" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
501 --34
516 --34
502 WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
517 WHEN "100011" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
503 --35
518 --35
504 WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
519 WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
505 ----------------------------------------------------
520 ----------------------------------------------------
506 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
521 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
507 WHEN OTHERS => NULL;
522 WHEN OTHERS => NULL;
508
523
509 END CASE;
524 END CASE;
510 IF (apbi.pwrite AND apbi.penable) = '1' THEN
525 IF (apbi.pwrite AND apbi.penable) = '1' THEN
511 -- APB DMA WRITE --
526 -- APB DMA WRITE --
512 CASE paddr(7 DOWNTO 2) IS
527 CASE paddr(7 DOWNTO 2) IS
513 --
528 --
514 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
529 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
515 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
530 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
516 reg_sp.config_ms_run <= apbi.pwdata(2);
531 reg_sp.config_ms_run <= apbi.pwdata(2);
517
532
518 WHEN "000001" =>
533 WHEN "000001" =>
519 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
534 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
520 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
535 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
521 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
536 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
522 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
537 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
523 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
538 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
524 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
539 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
525 reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error;
526 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
540 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
527 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
541 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
528 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
542 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
529 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
543 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
530 --2
544 --2
531 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
545 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
532 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
546 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
533 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
547 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
534 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
548 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
535 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
549 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
536 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
550 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
537 --8 to 19
551 --8 to 19
538 --20
552 --20
539 WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
553 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
554 --20
555 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
540 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
556 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
541 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
557 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
542 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
558 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
543 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
559 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
544 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
560 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
545 WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
561 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
546 reg_wp.enable_f1 <= apbi.pwdata(1);
562 reg_wp.enable_f1 <= apbi.pwdata(1);
547 reg_wp.enable_f2 <= apbi.pwdata(2);
563 reg_wp.enable_f2 <= apbi.pwdata(2);
548 reg_wp.enable_f3 <= apbi.pwdata(3);
564 reg_wp.enable_f3 <= apbi.pwdata(3);
549 reg_wp.burst_f0 <= apbi.pwdata(4);
565 reg_wp.burst_f0 <= apbi.pwdata(4);
550 reg_wp.burst_f1 <= apbi.pwdata(5);
566 reg_wp.burst_f1 <= apbi.pwdata(5);
551 reg_wp.burst_f2 <= apbi.pwdata(6);
567 reg_wp.burst_f2 <= apbi.pwdata(6);
552 reg_wp.run <= apbi.pwdata(7);
568 reg_wp.run <= apbi.pwdata(7);
553 --22
569 --22
554 WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata;
570 WHEN "010111" => reg_wp.addr_data_f0 <= apbi.pwdata;
555 WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata;
571 WHEN "011000" => reg_wp.addr_data_f1 <= apbi.pwdata;
556 WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata;
572 WHEN "011001" => reg_wp.addr_data_f2 <= apbi.pwdata;
557 WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata;
573 WHEN "011010" => reg_wp.addr_data_f3 <= apbi.pwdata;
558 --26
574 --26
559 WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
575 WHEN "011011" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
560 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
576 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
561 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
577 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
562 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
578 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
563 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
579 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
564 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
580 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
565 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
581 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
566 WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
582 WHEN "011100" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
567 WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
583 WHEN "011101" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
568 WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
584 WHEN "011110" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
569 WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
585 WHEN "011111" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
570 WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
586 WHEN "100000" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
571 WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
587 WHEN "100001" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
572 WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
588 WHEN "100010" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
573 WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
589 WHEN "100011" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
574 WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
590 WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
575 --
591 --
576 WHEN OTHERS => NULL;
592 WHEN OTHERS => NULL;
577 END CASE;
593 END CASE;
578 END IF;
594 END IF;
579 END IF;
595 END IF;
580 --apbo.pirq(pirq_ms) <=
596 --apbo.pirq(pirq_ms) <=
581 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
597 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
582 ready_matrix_f1 OR
598 ready_matrix_f1 OR
583 ready_matrix_f2)
599 ready_matrix_f2)
584 )
600 )
585 OR
601 OR
586 (reg_sp.config_active_interruption_onError AND (
602 (reg_sp.config_active_interruption_onError AND (
587 error_bad_component_error
603 -- error_bad_component_error OR
588 OR error_buffer_full
604 error_buffer_full
589 OR error_input_fifo_write(0)
605 OR error_input_fifo_write(0)
590 OR error_input_fifo_write(1)
606 OR error_input_fifo_write(1)
591 OR error_input_fifo_write(2))
607 OR error_input_fifo_write(2))
592 ));
608 ));
593 -- apbo.pirq(pirq_wfp)
609 -- apbo.pirq(pirq_wfp)
594 apbo_irq_wfp<= ored_irq_wfp;
610 apbo_irq_wfp<= ored_irq_wfp;
595
611
596 END IF;
612 END IF;
597 END PROCESS lpp_lfr_apbreg;
613 END PROCESS lpp_lfr_apbreg;
598
614
599 apbo.pirq(pirq_ms) <= apbo_irq_ms;
615 apbo.pirq(pirq_ms) <= apbo_irq_ms;
600 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
616 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
601
617
602 apbo.pindex <= pindex;
618 apbo.pindex <= pindex;
603 apbo.pconfig <= pconfig;
619 apbo.pconfig <= pconfig;
604 apbo.prdata <= prdata;
620 apbo.prdata <= prdata;
605
621
606 -----------------------------------------------------------------------------
622 -----------------------------------------------------------------------------
607 -- IRQ
623 -- IRQ
608 -----------------------------------------------------------------------------
624 -----------------------------------------------------------------------------
609 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
625 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
610
626
611 PROCESS (HCLK, HRESETn)
627 PROCESS (HCLK, HRESETn)
612 BEGIN -- PROCESS
628 BEGIN -- PROCESS
613 IF HRESETn = '0' THEN -- asynchronous reset (active low)
629 IF HRESETn = '0' THEN -- asynchronous reset (active low)
614 irq_wfp_reg <= (OTHERS => '0');
630 irq_wfp_reg <= (OTHERS => '0');
615 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
631 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
616 irq_wfp_reg <= irq_wfp_reg_s;
632 irq_wfp_reg <= irq_wfp_reg_s;
617 END IF;
633 END IF;
618 END PROCESS;
634 END PROCESS;
619
635
620 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
636 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
621 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
637 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
622 END GENERATE all_irq_wfp;
638 END GENERATE all_irq_wfp;
623
639
624 irq_wfp_ZERO <= (OTHERS => '0');
640 irq_wfp_ZERO <= (OTHERS => '0');
625 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
641 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
626
642
627 run_ms <= reg_sp.config_ms_run;
643 run_ms <= reg_sp.config_ms_run;
628
644
629 -----------------------------------------------------------------------------
645 -----------------------------------------------------------------------------
630 --
646 --
631 -----------------------------------------------------------------------------
647 -----------------------------------------------------------------------------
632 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
648 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
633 PORT MAP (
649 PORT MAP (
634 clk => HCLK,
650 clk => HCLK,
635 rstn => HRESETn,
651 rstn => HRESETn,
636
652
637 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
653 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
638 reg0_ready_matrix => reg0_ready_matrix_f0,
654 reg0_ready_matrix => reg0_ready_matrix_f0,
639 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
655 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
640 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
656 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
641
657
642 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
658 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
643 reg1_ready_matrix => reg1_ready_matrix_f0,
659 reg1_ready_matrix => reg1_ready_matrix_f0,
644 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
660 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
645 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
661 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
646
662
647 ready_matrix => ready_matrix_f0,
663 ready_matrix => ready_matrix_f0,
648 status_ready_matrix => status_ready_matrix_f0,
664 status_ready_matrix => status_ready_matrix_f0,
649 addr_matrix => addr_matrix_f0,
665 addr_matrix => addr_matrix_f0,
650 matrix_time => matrix_time_f0);
666 matrix_time => matrix_time_f0);
651
667
652 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
668 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
653 PORT MAP (
669 PORT MAP (
654 clk => HCLK,
670 clk => HCLK,
655 rstn => HRESETn,
671 rstn => HRESETn,
656
672
657 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
673 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
658 reg0_ready_matrix => reg0_ready_matrix_f1,
674 reg0_ready_matrix => reg0_ready_matrix_f1,
659 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
675 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
660 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
676 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
661
677
662 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
678 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
663 reg1_ready_matrix => reg1_ready_matrix_f1,
679 reg1_ready_matrix => reg1_ready_matrix_f1,
664 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
680 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
665 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
681 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
666
682
667 ready_matrix => ready_matrix_f1,
683 ready_matrix => ready_matrix_f1,
668 status_ready_matrix => status_ready_matrix_f1,
684 status_ready_matrix => status_ready_matrix_f1,
669 addr_matrix => addr_matrix_f1,
685 addr_matrix => addr_matrix_f1,
670 matrix_time => matrix_time_f1);
686 matrix_time => matrix_time_f1);
671
687
672 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
688 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
673 PORT MAP (
689 PORT MAP (
674 clk => HCLK,
690 clk => HCLK,
675 rstn => HRESETn,
691 rstn => HRESETn,
676
692
677 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
693 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
678 reg0_ready_matrix => reg0_ready_matrix_f2,
694 reg0_ready_matrix => reg0_ready_matrix_f2,
679 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
695 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
680 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
696 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
681
697
682 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
698 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
683 reg1_ready_matrix => reg1_ready_matrix_f2,
699 reg1_ready_matrix => reg1_ready_matrix_f2,
684 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
700 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
685 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
701 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
686
702
687 ready_matrix => ready_matrix_f2,
703 ready_matrix => ready_matrix_f2,
688 status_ready_matrix => status_ready_matrix_f2,
704 status_ready_matrix => status_ready_matrix_f2,
689 addr_matrix => addr_matrix_f2,
705 addr_matrix => addr_matrix_f2,
690 matrix_time => matrix_time_f2);
706 matrix_time => matrix_time_f2);
691
707
692 -----------------------------------------------------------------------------
708 -----------------------------------------------------------------------------
693 debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
709 debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
694 debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11
710 debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11
695 reg_sp.status_error_input_fifo_write(2) &--10
711 reg_sp.status_error_input_fifo_write(2) &--10
696 reg_sp.status_error_input_fifo_write(1) &--9
712 reg_sp.status_error_input_fifo_write(1) &--9
697 reg_sp.status_error_input_fifo_write(0) &--8
713 reg_sp.status_error_input_fifo_write(0) &--8
698 reg_sp.status_error_buffer_full & reg_sp.status_error_bad_component_error & --7 6
714 reg_sp.status_error_buffer_full &
715 '0' &
716 -- reg_sp.status_error_bad_component_error & --7 6
699 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
717 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
700 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
718 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
701 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
719 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
702
720
703 END beh;
721 END beh;
Show file before | Show file after | Hide comments
@@ -1,1042 +1,1144
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
15 USE lpp.fft_components.ALL;
16
16
17 ENTITY lpp_lfr_ms IS
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
19 Mem_use : INTEGER := use_RAM
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 run : IN STD_LOGIC;
24
25
25 ---------------------------------------------------------------------------
26 ---------------------------------------------------------------------------
26 -- DATA INPUT
27 -- DATA INPUT
27 ---------------------------------------------------------------------------
28 ---------------------------------------------------------------------------
28 -- TIME
29 -- TIME
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 --
32 --
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
35 --
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
38 --
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40
41
41 ---------------------------------------------------------------------------
42 ---------------------------------------------------------------------------
42 -- DMA
43 -- DMA
43 ---------------------------------------------------------------------------
44 ---------------------------------------------------------------------------
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
46 dma_valid : OUT STD_LOGIC;
47 dma_fifo_ren : IN STD_LOGIC; --TODO
47 dma_valid_burst : OUT STD_LOGIC;
48 dma_buffer_new : OUT STD_LOGIC; --TODO
48 dma_ren : IN STD_LOGIC;
49 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
49 dma_done : IN STD_LOGIC;
50 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
51 dma_buffer_full : IN STD_LOGIC; --TODO
52 dma_buffer_full_err : IN STD_LOGIC; --TODO
50
53
51 -- Reg out
54 -- Reg out
52 ready_matrix_f0 : OUT STD_LOGIC;
55 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
53 ready_matrix_f1 : OUT STD_LOGIC;
56 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
54 ready_matrix_f2 : OUT STD_LOGIC;
57 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
55 error_bad_component_error : OUT STD_LOGIC;
58 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
56 error_buffer_full : OUT STD_LOGIC;
59 error_buffer_full : OUT STD_LOGIC; -- TODO
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
60 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58
61
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 --
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63
64 -- Reg In
62 -- Reg In
65 status_ready_matrix_f0 : IN STD_LOGIC;
63 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
66 status_ready_matrix_f1 : IN STD_LOGIC;
64 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
67 status_ready_matrix_f2 : IN STD_LOGIC;
65 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
68
66
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
67 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
70 config_active_interruption_onError : IN STD_LOGIC;
68 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
72 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
73 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
74
74
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
78
78
79 );
79 );
80 END;
80 END;
81
81
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83
83
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89
89
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95
95
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100
100
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102
102
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107
107
108 SIGNAL error_wen_f0 : STD_LOGIC;
108 SIGNAL error_wen_f0 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
111
111
112 SIGNAL one_sample_f1_full : STD_LOGIC;
112 SIGNAL one_sample_f1_full : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
116
116
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 -- FSM / SWITCH SELECT CHANNEL
118 -- FSM / SWITCH SELECT CHANNEL
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123
123
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128
128
129 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 -- FSM LOAD FFT
130 -- FSM LOAD FFT
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135
135
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 SIGNAL sample_load : STD_LOGIC;
137 SIGNAL sample_load : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141
141
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- FFT
144 -- FFT
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 SIGNAL fft_read : STD_LOGIC;
146 SIGNAL fft_read : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_valid : STD_LOGIC;
150 SIGNAL fft_data_valid : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 SIGNAL current_fifo_empty : STD_LOGIC;
158 SIGNAL current_fifo_empty : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162
162
163 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176
176
177 SIGNAL SM_correlation_start : STD_LOGIC;
177 SIGNAL SM_correlation_start : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
184
184
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188
188
189 SIGNAL current_matrix_write : STD_LOGIC;
189 SIGNAL current_matrix_write : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 SIGNAL fifo_0_ready : STD_LOGIC;
192 SIGNAL fifo_0_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
195
195
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
207 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
208 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
207
209
208 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
209 -- TIME REG & INFOs
211 -- TIME REG & INFOs
210 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
213 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212
214
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
217 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
218 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
217
219
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
223 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222
224
223 --SIGNAL time_update_f0_A : STD_LOGIC;
225 --SIGNAL time_update_f0_A : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
226 --SIGNAL time_update_f0_B : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
227 --SIGNAL time_update_f1 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
228 --SIGNAL time_update_f2 : STD_LOGIC;
227 --
229 --
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
231 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
232 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
231
233
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
235 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
236 SIGNAL status_component_fifo_0_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
237 SIGNAL status_component_fifo_1_end : STD_LOGIC;
236 -----------------------------------------------------------------------------
238 -----------------------------------------------------------------------------
237 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
239 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
238
240
239 SIGNAL fft_ready_reg : STD_LOGIC;
241 SIGNAL fft_ready_reg : STD_LOGIC;
240 SIGNAL fft_ready_rising_down : STD_LOGIC;
242 SIGNAL fft_ready_rising_down : STD_LOGIC;
241
243
242 SIGNAL sample_load_reg : STD_LOGIC;
244 SIGNAL sample_load_reg : STD_LOGIC;
243 SIGNAL sample_load_rising_down : STD_LOGIC;
245 SIGNAL sample_load_rising_down : STD_LOGIC;
244
246
245 -----------------------------------------------------------------------------
247 -----------------------------------------------------------------------------
246 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
248 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
247 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
249 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
248 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
250 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
249 SIGNAL sample_f1_full_head_in : STD_LOGIC;
251 SIGNAL sample_f1_full_head_in : STD_LOGIC;
250 SIGNAL sample_f1_full_head_out : STD_LOGIC;
252 SIGNAL sample_f1_full_head_out : STD_LOGIC;
251 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
253 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
252
254
253 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
255 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
254
256
255 BEGIN
257 BEGIN
256
258
257
259
258 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
260 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
259
261
260
262
261 switch_f0_inst : spectral_matrix_switch_f0
263 switch_f0_inst : spectral_matrix_switch_f0
262 PORT MAP (
264 PORT MAP (
263 clk => clk,
265 clk => clk,
264 rstn => rstn,
266 rstn => rstn,
265
267
266 sample_wen => sample_f0_wen,
268 sample_wen => sample_f0_wen,
267
269
268 fifo_A_empty => sample_f0_A_empty,
270 fifo_A_empty => sample_f0_A_empty,
269 fifo_A_full => sample_f0_A_full,
271 fifo_A_full => sample_f0_A_full,
270 fifo_A_wen => sample_f0_A_wen,
272 fifo_A_wen => sample_f0_A_wen,
271
273
272 fifo_B_empty => sample_f0_B_empty,
274 fifo_B_empty => sample_f0_B_empty,
273 fifo_B_full => sample_f0_B_full,
275 fifo_B_full => sample_f0_B_full,
274 fifo_B_wen => sample_f0_B_wen,
276 fifo_B_wen => sample_f0_B_wen,
275
277
276 error_wen => error_wen_f0); -- TODO
278 error_wen => error_wen_f0); -- TODO
277
279
278 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
279 -- FIFO IN
281 -- FIFO IN
280 -----------------------------------------------------------------------------
282 -----------------------------------------------------------------------------
281 lppFIFOxN_f0_a : lppFIFOxN
283 lppFIFOxN_f0_a : lppFIFOxN
282 GENERIC MAP (
284 GENERIC MAP (
283 tech => 0,
285 tech => 0,
284 Mem_use => Mem_use,
286 Mem_use => Mem_use,
285 Data_sz => 16,
287 Data_sz => 16,
286 Addr_sz => 8,
288 Addr_sz => 8,
287 FifoCnt => 5)
289 FifoCnt => 5)
288 PORT MAP (
290 PORT MAP (
289 clk => clk,
291 clk => clk,
290 rstn => rstn,
292 rstn => rstn,
291
293
292 ReUse => (OTHERS => '0'),
294 ReUse => (OTHERS => '0'),
293
295
294 run => (OTHERS => '1'),
296 run => (OTHERS => '1'),
295
297
296 wen => sample_f0_A_wen,
298 wen => sample_f0_A_wen,
297 wdata => sample_f0_wdata,
299 wdata => sample_f0_wdata,
298
300
299 ren => sample_f0_A_ren,
301 ren => sample_f0_A_ren,
300 rdata => sample_f0_A_rdata,
302 rdata => sample_f0_A_rdata,
301
303
302 empty => sample_f0_A_empty,
304 empty => sample_f0_A_empty,
303 full => sample_f0_A_full,
305 full => sample_f0_A_full,
304 almost_full => OPEN);
306 almost_full => OPEN);
305
307
306 lppFIFOxN_f0_b : lppFIFOxN
308 lppFIFOxN_f0_b : lppFIFOxN
307 GENERIC MAP (
309 GENERIC MAP (
308 tech => 0,
310 tech => 0,
309 Mem_use => Mem_use,
311 Mem_use => Mem_use,
310 Data_sz => 16,
312 Data_sz => 16,
311 Addr_sz => 8,
313 Addr_sz => 8,
312 FifoCnt => 5)
314 FifoCnt => 5)
313 PORT MAP (
315 PORT MAP (
314 clk => clk,
316 clk => clk,
315 rstn => rstn,
317 rstn => rstn,
316
318
317 ReUse => (OTHERS => '0'),
319 ReUse => (OTHERS => '0'),
318 run => (OTHERS => '1'),
320 run => (OTHERS => '1'),
319
321
320 wen => sample_f0_B_wen,
322 wen => sample_f0_B_wen,
321 wdata => sample_f0_wdata,
323 wdata => sample_f0_wdata,
322 ren => sample_f0_B_ren,
324 ren => sample_f0_B_ren,
323 rdata => sample_f0_B_rdata,
325 rdata => sample_f0_B_rdata,
324 empty => sample_f0_B_empty,
326 empty => sample_f0_B_empty,
325 full => sample_f0_B_full,
327 full => sample_f0_B_full,
326 almost_full => OPEN);
328 almost_full => OPEN);
327
329
328 -----------------------------------------------------------------------------
330 -----------------------------------------------------------------------------
329 -- sample_f1_wen in
331 -- sample_f1_wen in
330 -- sample_f1_wdata in
332 -- sample_f1_wdata in
331 -- sample_f1_full OUT
333 -- sample_f1_full OUT
332
334
333 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
335 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
334 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
336 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
335 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
337 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
336
338
337 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
339 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
338 PORT MAP (
340 PORT MAP (
339 clk => clk,
341 clk => clk,
340 rstn => rstn,
342 rstn => rstn,
341 in_wen => sample_f1_wen_head_in,
343 in_wen => sample_f1_wen_head_in,
342 in_data => sample_f1_wdata,
344 in_data => sample_f1_wdata,
343 in_full => sample_f1_full_head_in,
345 in_full => sample_f1_full_head_in,
344 in_empty => sample_f1_empty_head_in,
346 in_empty => sample_f1_empty_head_in,
345 out_wen => sample_f1_wen_head_out,
347 out_wen => sample_f1_wen_head_out,
346 out_data => sample_f1_wdata_head,
348 out_data => sample_f1_wdata_head,
347 out_full => sample_f1_full_head_out);
349 out_full => sample_f1_full_head_out);
348
350
349 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
351 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
350
352
351
353
352 lppFIFOxN_f1 : lppFIFOxN
354 lppFIFOxN_f1 : lppFIFOxN
353 GENERIC MAP (
355 GENERIC MAP (
354 tech => 0,
356 tech => 0,
355 Mem_use => Mem_use,
357 Mem_use => Mem_use,
356 Data_sz => 16,
358 Data_sz => 16,
357 Addr_sz => 8,
359 Addr_sz => 8,
358 FifoCnt => 5)
360 FifoCnt => 5)
359 PORT MAP (
361 PORT MAP (
360 clk => clk,
362 clk => clk,
361 rstn => rstn,
363 rstn => rstn,
362
364
363 ReUse => (OTHERS => '0'),
365 ReUse => (OTHERS => '0'),
364 run => (OTHERS => '1'),
366 run => (OTHERS => '1'),
365
367
366 wen => sample_f1_wen_head,
368 wen => sample_f1_wen_head,
367 wdata => sample_f1_wdata_head,
369 wdata => sample_f1_wdata_head,
368 ren => sample_f1_ren,
370 ren => sample_f1_ren,
369 rdata => sample_f1_rdata,
371 rdata => sample_f1_rdata,
370 empty => sample_f1_empty,
372 empty => sample_f1_empty,
371 full => sample_f1_full,
373 full => sample_f1_full,
372 almost_full => sample_f1_almost_full);
374 almost_full => sample_f1_almost_full);
373
375
374
376
375 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
377 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
376
378
377 PROCESS (clk, rstn)
379 PROCESS (clk, rstn)
378 BEGIN -- PROCESS
380 BEGIN -- PROCESS
379 IF rstn = '0' THEN -- asynchronous reset (active low)
381 IF rstn = '0' THEN -- asynchronous reset (active low)
380 one_sample_f1_full <= '0';
382 one_sample_f1_full <= '0';
381 error_wen_f1 <= '0';
383 error_wen_f1 <= '0';
382 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
383 IF sample_f1_full_head_out = '0' THEN
385 IF sample_f1_full_head_out = '0' THEN
384 one_sample_f1_full <= '0';
386 one_sample_f1_full <= '0';
385 ELSE
387 ELSE
386 one_sample_f1_full <= '1';
388 one_sample_f1_full <= '1';
387 END IF;
389 END IF;
388 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
390 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
389 END IF;
391 END IF;
390 END PROCESS;
392 END PROCESS;
391
393
392 -----------------------------------------------------------------------------
394 -----------------------------------------------------------------------------
393
395
394
396
395 lppFIFOxN_f2 : lppFIFOxN
397 lppFIFOxN_f2 : lppFIFOxN
396 GENERIC MAP (
398 GENERIC MAP (
397 tech => 0,
399 tech => 0,
398 Mem_use => Mem_use,
400 Mem_use => Mem_use,
399 Data_sz => 16,
401 Data_sz => 16,
400 Addr_sz => 8,
402 Addr_sz => 8,
401 FifoCnt => 5)
403 FifoCnt => 5)
402 PORT MAP (
404 PORT MAP (
403 clk => clk,
405 clk => clk,
404 rstn => rstn,
406 rstn => rstn,
405
407
406 ReUse => (OTHERS => '0'),
408 ReUse => (OTHERS => '0'),
407 run => (OTHERS => '1'),
409 run => (OTHERS => '1'),
408
410
409 wen => sample_f2_wen,
411 wen => sample_f2_wen,
410 wdata => sample_f2_wdata,
412 wdata => sample_f2_wdata,
411 ren => sample_f2_ren,
413 ren => sample_f2_ren,
412 rdata => sample_f2_rdata,
414 rdata => sample_f2_rdata,
413 empty => sample_f2_empty,
415 empty => sample_f2_empty,
414 full => sample_f2_full,
416 full => sample_f2_full,
415 almost_full => OPEN);
417 almost_full => OPEN);
416
418
417
419
418 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
420 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
419
421
420 PROCESS (clk, rstn)
422 PROCESS (clk, rstn)
421 BEGIN -- PROCESS
423 BEGIN -- PROCESS
422 IF rstn = '0' THEN -- asynchronous reset (active low)
424 IF rstn = '0' THEN -- asynchronous reset (active low)
423 one_sample_f2_full <= '0';
425 one_sample_f2_full <= '0';
424 error_wen_f2 <= '0';
426 error_wen_f2 <= '0';
425 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
427 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
426 IF sample_f2_full = "00000" THEN
428 IF sample_f2_full = "00000" THEN
427 one_sample_f2_full <= '0';
429 one_sample_f2_full <= '0';
428 ELSE
430 ELSE
429 one_sample_f2_full <= '1';
431 one_sample_f2_full <= '1';
430 END IF;
432 END IF;
431 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
433 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
432 END IF;
434 END IF;
433 END PROCESS;
435 END PROCESS;
434
436
435 -----------------------------------------------------------------------------
437 -----------------------------------------------------------------------------
436 -- FSM SELECT CHANNEL
438 -- FSM SELECT CHANNEL
437 -----------------------------------------------------------------------------
439 -----------------------------------------------------------------------------
438 PROCESS (clk, rstn)
440 PROCESS (clk, rstn)
439 BEGIN
441 BEGIN
440 IF rstn = '0' THEN
442 IF rstn = '0' THEN
441 state_fsm_select_channel <= IDLE;
443 state_fsm_select_channel <= IDLE;
442 ELSIF clk'EVENT AND clk = '1' THEN
444 ELSIF clk'EVENT AND clk = '1' THEN
443 CASE state_fsm_select_channel IS
445 CASE state_fsm_select_channel IS
444 WHEN IDLE =>
446 WHEN IDLE =>
445 IF sample_f1_full = "11111" THEN
447 IF sample_f1_full = "11111" THEN
446 state_fsm_select_channel <= SWITCH_F1;
448 state_fsm_select_channel <= SWITCH_F1;
447 ELSIF sample_f1_almost_full = "00000" THEN
449 ELSIF sample_f1_almost_full = "00000" THEN
448 IF sample_f0_A_full = "11111" THEN
450 IF sample_f0_A_full = "11111" THEN
449 state_fsm_select_channel <= SWITCH_F0_A;
451 state_fsm_select_channel <= SWITCH_F0_A;
450 ELSIF sample_f0_B_full = "11111" THEN
452 ELSIF sample_f0_B_full = "11111" THEN
451 state_fsm_select_channel <= SWITCH_F0_B;
453 state_fsm_select_channel <= SWITCH_F0_B;
452 ELSIF sample_f2_full = "11111" THEN
454 ELSIF sample_f2_full = "11111" THEN
453 state_fsm_select_channel <= SWITCH_F2;
455 state_fsm_select_channel <= SWITCH_F2;
454 END IF;
456 END IF;
455 END IF;
457 END IF;
456
458
457 WHEN SWITCH_F0_A =>
459 WHEN SWITCH_F0_A =>
458 IF sample_f0_A_empty = "11111" THEN
460 IF sample_f0_A_empty = "11111" THEN
459 state_fsm_select_channel <= IDLE;
461 state_fsm_select_channel <= IDLE;
460 END IF;
462 END IF;
461 WHEN SWITCH_F0_B =>
463 WHEN SWITCH_F0_B =>
462 IF sample_f0_B_empty = "11111" THEN
464 IF sample_f0_B_empty = "11111" THEN
463 state_fsm_select_channel <= IDLE;
465 state_fsm_select_channel <= IDLE;
464 END IF;
466 END IF;
465 WHEN SWITCH_F1 =>
467 WHEN SWITCH_F1 =>
466 IF sample_f1_empty = "11111" THEN
468 IF sample_f1_empty = "11111" THEN
467 state_fsm_select_channel <= IDLE;
469 state_fsm_select_channel <= IDLE;
468 END IF;
470 END IF;
469 WHEN SWITCH_F2 =>
471 WHEN SWITCH_F2 =>
470 IF sample_f2_empty = "11111" THEN
472 IF sample_f2_empty = "11111" THEN
471 state_fsm_select_channel <= IDLE;
473 state_fsm_select_channel <= IDLE;
472 END IF;
474 END IF;
473 WHEN OTHERS => NULL;
475 WHEN OTHERS => NULL;
474 END CASE;
476 END CASE;
475
477
476 END IF;
478 END IF;
477 END PROCESS;
479 END PROCESS;
478
480
479 PROCESS (clk, rstn)
481 PROCESS (clk, rstn)
480 BEGIN
482 BEGIN
481 IF rstn = '0' THEN
483 IF rstn = '0' THEN
482 pre_state_fsm_select_channel <= IDLE;
484 pre_state_fsm_select_channel <= IDLE;
483 ELSIF clk'EVENT AND clk = '1' THEN
485 ELSIF clk'EVENT AND clk = '1' THEN
484 pre_state_fsm_select_channel <= state_fsm_select_channel;
486 pre_state_fsm_select_channel <= state_fsm_select_channel;
485 END IF;
487 END IF;
486 END PROCESS;
488 END PROCESS;
487
489
488
490
489 -----------------------------------------------------------------------------
491 -----------------------------------------------------------------------------
490 -- SWITCH SELECT CHANNEL
492 -- SWITCH SELECT CHANNEL
491 -----------------------------------------------------------------------------
493 -----------------------------------------------------------------------------
492 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
494 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
493 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
495 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
494 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
496 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
495 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
497 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
496 (OTHERS => '1');
498 (OTHERS => '1');
497
499
498 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
500 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
499 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
501 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
500 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
502 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
501 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
503 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
502 (OTHERS => '0');
504 (OTHERS => '0');
503
505
504 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
506 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
505 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
507 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
506 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
508 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
507 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
509 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
508
510
509
511
510 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
512 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
511 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
513 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
512 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
514 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
513 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
515 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
514
516
515
517
516 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
518 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
517 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
519 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
518 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
520 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
519 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
521 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
520
522
521 -----------------------------------------------------------------------------
523 -----------------------------------------------------------------------------
522 -- FSM LOAD FFT
524 -- FSM LOAD FFT
523 -----------------------------------------------------------------------------
525 -----------------------------------------------------------------------------
524
526
525 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
527 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
526 sample_ren_s WHEN sample_load = '1' ELSE
528 sample_ren_s WHEN sample_load = '1' ELSE
527 (OTHERS => '1');
529 (OTHERS => '1');
528
530
529 PROCESS (clk, rstn)
531 PROCESS (clk, rstn)
530 BEGIN
532 BEGIN
531 IF rstn = '0' THEN
533 IF rstn = '0' THEN
532 sample_ren_s <= (OTHERS => '1');
534 sample_ren_s <= (OTHERS => '1');
533 state_fsm_load_FFT <= IDLE;
535 state_fsm_load_FFT <= IDLE;
534 status_MS_input <= (OTHERS => '0');
536 status_MS_input <= (OTHERS => '0');
535 --next_state_fsm_load_FFT <= IDLE;
537 --next_state_fsm_load_FFT <= IDLE;
536 --sample_valid <= '0';
538 --sample_valid <= '0';
537 ELSIF clk'EVENT AND clk = '1' THEN
539 ELSIF clk'EVENT AND clk = '1' THEN
538 CASE state_fsm_load_FFT IS
540 CASE state_fsm_load_FFT IS
539 WHEN IDLE =>
541 WHEN IDLE =>
540 --sample_valid <= '0';
542 --sample_valid <= '0';
541 sample_ren_s <= (OTHERS => '1');
543 sample_ren_s <= (OTHERS => '1');
542 IF sample_full = "11111" AND sample_load = '1' THEN
544 IF sample_full = "11111" AND sample_load = '1' THEN
543 state_fsm_load_FFT <= FIFO_1;
545 state_fsm_load_FFT <= FIFO_1;
544 status_MS_input <= status_channel;
546 status_MS_input <= status_channel;
545 END IF;
547 END IF;
546
548
547 WHEN FIFO_1 =>
549 WHEN FIFO_1 =>
548 sample_ren_s <= "1111" & NOT(sample_load);
550 sample_ren_s <= "1111" & NOT(sample_load);
549 IF sample_empty(0) = '1' THEN
551 IF sample_empty(0) = '1' THEN
550 sample_ren_s <= (OTHERS => '1');
552 sample_ren_s <= (OTHERS => '1');
551 state_fsm_load_FFT <= FIFO_2;
553 state_fsm_load_FFT <= FIFO_2;
552 END IF;
554 END IF;
553
555
554 WHEN FIFO_2 =>
556 WHEN FIFO_2 =>
555 sample_ren_s <= "111" & NOT(sample_load) & '1';
557 sample_ren_s <= "111" & NOT(sample_load) & '1';
556 IF sample_empty(1) = '1' THEN
558 IF sample_empty(1) = '1' THEN
557 sample_ren_s <= (OTHERS => '1');
559 sample_ren_s <= (OTHERS => '1');
558 state_fsm_load_FFT <= FIFO_3;
560 state_fsm_load_FFT <= FIFO_3;
559 END IF;
561 END IF;
560
562
561 WHEN FIFO_3 =>
563 WHEN FIFO_3 =>
562 sample_ren_s <= "11" & NOT(sample_load) & "11";
564 sample_ren_s <= "11" & NOT(sample_load) & "11";
563 IF sample_empty(2) = '1' THEN
565 IF sample_empty(2) = '1' THEN
564 sample_ren_s <= (OTHERS => '1');
566 sample_ren_s <= (OTHERS => '1');
565 state_fsm_load_FFT <= FIFO_4;
567 state_fsm_load_FFT <= FIFO_4;
566 END IF;
568 END IF;
567
569
568 WHEN FIFO_4 =>
570 WHEN FIFO_4 =>
569 sample_ren_s <= '1' & NOT(sample_load) & "111";
571 sample_ren_s <= '1' & NOT(sample_load) & "111";
570 IF sample_empty(3) = '1' THEN
572 IF sample_empty(3) = '1' THEN
571 sample_ren_s <= (OTHERS => '1');
573 sample_ren_s <= (OTHERS => '1');
572 state_fsm_load_FFT <= FIFO_5;
574 state_fsm_load_FFT <= FIFO_5;
573 END IF;
575 END IF;
574
576
575 WHEN FIFO_5 =>
577 WHEN FIFO_5 =>
576 sample_ren_s <= NOT(sample_load) & "1111";
578 sample_ren_s <= NOT(sample_load) & "1111";
577 IF sample_empty(4) = '1' THEN
579 IF sample_empty(4) = '1' THEN
578 sample_ren_s <= (OTHERS => '1');
580 sample_ren_s <= (OTHERS => '1');
579 state_fsm_load_FFT <= IDLE;
581 state_fsm_load_FFT <= IDLE;
580 END IF;
582 END IF;
581 WHEN OTHERS => NULL;
583 WHEN OTHERS => NULL;
582 END CASE;
584 END CASE;
583 END IF;
585 END IF;
584 END PROCESS;
586 END PROCESS;
585
587
586 PROCESS (clk, rstn)
588 PROCESS (clk, rstn)
587 BEGIN
589 BEGIN
588 IF rstn = '0' THEN
590 IF rstn = '0' THEN
589 sample_valid_r <= '0';
591 sample_valid_r <= '0';
590 next_state_fsm_load_FFT <= IDLE;
592 next_state_fsm_load_FFT <= IDLE;
591 ELSIF clk'EVENT AND clk = '1' THEN
593 ELSIF clk'EVENT AND clk = '1' THEN
592 next_state_fsm_load_FFT <= state_fsm_load_FFT;
594 next_state_fsm_load_FFT <= state_fsm_load_FFT;
593 IF sample_ren_s = "11111" THEN
595 IF sample_ren_s = "11111" THEN
594 sample_valid_r <= '0';
596 sample_valid_r <= '0';
595 ELSE
597 ELSE
596 sample_valid_r <= '1';
598 sample_valid_r <= '1';
597 END IF;
599 END IF;
598 END IF;
600 END IF;
599 END PROCESS;
601 END PROCESS;
600
602
601 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
603 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
602
604
603 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
605 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
604 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
606 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
605 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
607 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
606 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
608 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
607 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
609 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
608
610
609 -----------------------------------------------------------------------------
611 -----------------------------------------------------------------------------
610 -- FFT
612 -- FFT
611 -----------------------------------------------------------------------------
613 -----------------------------------------------------------------------------
612 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
614 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
613 PORT MAP (
615 PORT MAP (
614 clk => clk,
616 clk => clk,
615 rstn => rstn,
617 rstn => rstn,
616 sample_valid => sample_valid,
618 sample_valid => sample_valid,
617 fft_read => fft_read,
619 fft_read => fft_read,
618 sample_data => sample_data,
620 sample_data => sample_data,
619 sample_load => sample_load,
621 sample_load => sample_load,
620 fft_pong => fft_pong,
622 fft_pong => fft_pong,
621 fft_data_im => fft_data_im,
623 fft_data_im => fft_data_im,
622 fft_data_re => fft_data_re,
624 fft_data_re => fft_data_re,
623 fft_data_valid => fft_data_valid,
625 fft_data_valid => fft_data_valid,
624 fft_ready => fft_ready);
626 fft_ready => fft_ready);
625
627
626 observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
627 fft_ongoing_counter & --9 8
628 sample_load_rising_down & --7
629 fft_ready_rising_down & --6
630 fft_ready & --5
631 fft_data_valid & --4
632 fft_pong & --3
633 sample_load & --2
634 fft_read & --1
635 sample_valid; --0
636
637 -----------------------------------------------------------------------------
628 -----------------------------------------------------------------------------
638 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
629 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
639 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
630 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
640
631
641 PROCESS (clk, rstn)
632 PROCESS (clk, rstn)
642 BEGIN
633 BEGIN
643 IF rstn = '0' THEN
634 IF rstn = '0' THEN
644 fft_ready_reg <= '0';
635 fft_ready_reg <= '0';
645 sample_load_reg <= '0';
636 sample_load_reg <= '0';
646
637
647 fft_ongoing_counter <= '0';
638 fft_ongoing_counter <= '0';
648 ELSIF clk'event AND clk = '1' THEN
639 ELSIF clk'event AND clk = '1' THEN
649 fft_ready_reg <= fft_ready;
640 fft_ready_reg <= fft_ready;
650 sample_load_reg <= sample_load;
641 sample_load_reg <= sample_load;
651
642
652 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
643 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
653 fft_ongoing_counter <= '0';
644 fft_ongoing_counter <= '0';
654
645
655 -- CASE fft_ongoing_counter IS
646 -- CASE fft_ongoing_counter IS
656 -- WHEN "01" => fft_ongoing_counter <= "00";
647 -- WHEN "01" => fft_ongoing_counter <= "00";
657 ---- WHEN "10" => fft_ongoing_counter <= "01";
648 ---- WHEN "10" => fft_ongoing_counter <= "01";
658 -- WHEN OTHERS => NULL;
649 -- WHEN OTHERS => NULL;
659 -- END CASE;
650 -- END CASE;
660 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
651 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
661 fft_ongoing_counter <= '1';
652 fft_ongoing_counter <= '1';
662 -- CASE fft_ongoing_counter IS
653 -- CASE fft_ongoing_counter IS
663 -- WHEN "00" => fft_ongoing_counter <= "01";
654 -- WHEN "00" => fft_ongoing_counter <= "01";
664 ---- WHEN "01" => fft_ongoing_counter <= "10";
655 ---- WHEN "01" => fft_ongoing_counter <= "10";
665 -- WHEN OTHERS => NULL;
656 -- WHEN OTHERS => NULL;
666 -- END CASE;
657 -- END CASE;
667 END IF;
658 END IF;
668
659
669 END IF;
660 END IF;
670 END PROCESS;
661 END PROCESS;
671
662
672 -----------------------------------------------------------------------------
663 -----------------------------------------------------------------------------
673 PROCESS (clk, rstn)
664 PROCESS (clk, rstn)
674 BEGIN
665 BEGIN
675 IF rstn = '0' THEN
666 IF rstn = '0' THEN
676 state_fsm_load_MS_memory <= IDLE;
667 state_fsm_load_MS_memory <= IDLE;
677 current_fifo_load <= "00001";
668 current_fifo_load <= "00001";
678 ELSIF clk'EVENT AND clk = '1' THEN
669 ELSIF clk'EVENT AND clk = '1' THEN
679 CASE state_fsm_load_MS_memory IS
670 CASE state_fsm_load_MS_memory IS
680 WHEN IDLE =>
671 WHEN IDLE =>
681 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
672 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
682 state_fsm_load_MS_memory <= LOAD_FIFO;
673 state_fsm_load_MS_memory <= LOAD_FIFO;
683 END IF;
674 END IF;
684 WHEN LOAD_FIFO =>
675 WHEN LOAD_FIFO =>
685 IF current_fifo_full = '1' THEN
676 IF current_fifo_full = '1' THEN
686 state_fsm_load_MS_memory <= TRASH_FFT;
677 state_fsm_load_MS_memory <= TRASH_FFT;
687 END IF;
678 END IF;
688 WHEN TRASH_FFT =>
679 WHEN TRASH_FFT =>
689 IF fft_ready = '0' THEN
680 IF fft_ready = '0' THEN
690 state_fsm_load_MS_memory <= IDLE;
681 state_fsm_load_MS_memory <= IDLE;
691 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
682 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
692 END IF;
683 END IF;
693 WHEN OTHERS => NULL;
684 WHEN OTHERS => NULL;
694 END CASE;
685 END CASE;
695
686
696 END IF;
687 END IF;
697 END PROCESS;
688 END PROCESS;
698
689
699 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
690 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
700 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
691 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
701 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
692 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
702 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
693 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
703 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
694 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
704
695
705 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
696 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
706 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
697 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
707 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
698 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
708 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
699 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
709 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
700 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
710
701
711 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
702 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
712 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
703 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
713 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
704 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
714 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
705 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
715 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
706 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
716
707
717 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
708 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
718
709
719 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
710 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
720 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
711 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
721 AND state_fsm_load_MS_memory = LOAD_FIFO
712 AND state_fsm_load_MS_memory = LOAD_FIFO
722 AND current_fifo_load(I) = '1'
713 AND current_fifo_load(I) = '1'
723 ELSE '1';
714 ELSE '1';
724 END GENERATE all_fifo;
715 END GENERATE all_fifo;
725
716
726 PROCESS (clk, rstn)
717 PROCESS (clk, rstn)
727 BEGIN
718 BEGIN
728 IF rstn = '0' THEN
719 IF rstn = '0' THEN
729 MEM_IN_SM_wen <= (OTHERS => '1');
720 MEM_IN_SM_wen <= (OTHERS => '1');
730 ELSIF clk'EVENT AND clk = '1' THEN
721 ELSIF clk'EVENT AND clk = '1' THEN
731 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
722 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
732 END IF;
723 END IF;
733 END PROCESS;
724 END PROCESS;
734
725
735 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
726 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
736 (fft_data_im & fft_data_re) &
727 (fft_data_im & fft_data_re) &
737 (fft_data_im & fft_data_re) &
728 (fft_data_im & fft_data_re) &
738 (fft_data_im & fft_data_re) &
729 (fft_data_im & fft_data_re) &
739 (fft_data_im & fft_data_re);
730 (fft_data_im & fft_data_re);
740 -----------------------------------------------------------------------------
731 -----------------------------------------------------------------------------
741
732
742
733
743 -----------------------------------------------------------------------------
734 -----------------------------------------------------------------------------
744 Mem_In_SpectralMatrix : lppFIFOxN
735 Mem_In_SpectralMatrix : lppFIFOxN
745 GENERIC MAP (
736 GENERIC MAP (
746 tech => 0,
737 tech => 0,
747 Mem_use => Mem_use,
738 Mem_use => Mem_use,
748 Data_sz => 32, --16,
739 Data_sz => 32, --16,
749 Addr_sz => 7, --8
740 Addr_sz => 7, --8
750 FifoCnt => 5)
741 FifoCnt => 5)
751 PORT MAP (
742 PORT MAP (
752 clk => clk,
743 clk => clk,
753 rstn => rstn,
744 rstn => rstn,
754
745
755 ReUse => MEM_IN_SM_ReUse,
746 ReUse => MEM_IN_SM_ReUse,
756 run => (OTHERS => '1'),
747 run => (OTHERS => '1'),
757
748
758 wen => MEM_IN_SM_wen,
749 wen => MEM_IN_SM_wen,
759 wdata => MEM_IN_SM_wData,
750 wdata => MEM_IN_SM_wData,
760
751
761 ren => MEM_IN_SM_ren,
752 ren => MEM_IN_SM_ren,
762 rdata => MEM_IN_SM_rData,
753 rdata => MEM_IN_SM_rData,
763 full => MEM_IN_SM_Full,
754 full => MEM_IN_SM_Full,
764 empty => MEM_IN_SM_Empty,
755 empty => MEM_IN_SM_Empty,
765 almost_full => OPEN);
756 almost_full => OPEN);
766
757
767 -----------------------------------------------------------------------------
768
769 observation_vector_1(11 DOWNTO 0) <= '0' &
770 SM_correlation_done & --4
771 SM_correlation_auto & --3
772 SM_correlation_start &
773 SM_correlation_start & --7
774 status_MS_input(1 DOWNTO 0)& --6..5
775 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
776
758
777 -----------------------------------------------------------------------------
759 -----------------------------------------------------------------------------
778 MS_control_1 : MS_control
760 MS_control_1 : MS_control
779 PORT MAP (
761 PORT MAP (
780 clk => clk,
762 clk => clk,
781 rstn => rstn,
763 rstn => rstn,
782
764
783 current_status_ms => status_MS_input,
765 current_status_ms => status_MS_input,
784
766
785 fifo_in_lock => MEM_IN_SM_locked,
767 fifo_in_lock => MEM_IN_SM_locked,
786 fifo_in_data => MEM_IN_SM_rdata,
768 fifo_in_data => MEM_IN_SM_rdata,
787 fifo_in_full => MEM_IN_SM_Full,
769 fifo_in_full => MEM_IN_SM_Full,
788 fifo_in_empty => MEM_IN_SM_Empty,
770 fifo_in_empty => MEM_IN_SM_Empty,
789 fifo_in_ren => MEM_IN_SM_ren,
771 fifo_in_ren => MEM_IN_SM_ren,
790 fifo_in_reuse => MEM_IN_SM_ReUse,
772 fifo_in_reuse => MEM_IN_SM_ReUse,
791
773
792 fifo_out_data => SM_in_data,
774 fifo_out_data => SM_in_data,
793 fifo_out_ren => SM_in_ren,
775 fifo_out_ren => SM_in_ren,
794 fifo_out_empty => SM_in_empty,
776 fifo_out_empty => SM_in_empty,
795
777
796 current_status_component => status_component,
778 current_status_component => status_component,
797
779
798 correlation_start => SM_correlation_start,
780 correlation_start => SM_correlation_start,
799 correlation_auto => SM_correlation_auto,
781 correlation_auto => SM_correlation_auto,
800 correlation_done => SM_correlation_done);
782 correlation_done => SM_correlation_done);
801
783
802
784
803 MS_calculation_1 : MS_calculation
785 MS_calculation_1 : MS_calculation
804 PORT MAP (
786 PORT MAP (
805 clk => clk,
787 clk => clk,
806 rstn => rstn,
788 rstn => rstn,
807
789
808 fifo_in_data => SM_in_data,
790 fifo_in_data => SM_in_data,
809 fifo_in_ren => SM_in_ren,
791 fifo_in_ren => SM_in_ren,
810 fifo_in_empty => SM_in_empty,
792 fifo_in_empty => SM_in_empty,
811
793
812 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
794 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
813 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
795 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
814 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
796 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
815
797
816 correlation_start => SM_correlation_start,
798 correlation_start => SM_correlation_start,
817 correlation_auto => SM_correlation_auto,
799 correlation_auto => SM_correlation_auto,
818 correlation_begin => SM_correlation_begin,
800 correlation_begin => SM_correlation_begin,
819 correlation_done => SM_correlation_done);
801 correlation_done => SM_correlation_done);
820
802
821 -----------------------------------------------------------------------------
803 -----------------------------------------------------------------------------
822 PROCESS (clk, rstn)
804 PROCESS (clk, rstn)
823 BEGIN -- PROCESS
805 BEGIN -- PROCESS
824 IF rstn = '0' THEN -- asynchronous reset (active low)
806 IF rstn = '0' THEN -- asynchronous reset (active low)
825 current_matrix_write <= '0';
807 current_matrix_write <= '0';
826 current_matrix_wait_empty <= '1';
808 current_matrix_wait_empty <= '1';
827 status_component_fifo_0 <= (OTHERS => '0');
809 status_component_fifo_0 <= (OTHERS => '0');
828 status_component_fifo_1 <= (OTHERS => '0');
810 status_component_fifo_1 <= (OTHERS => '0');
829 status_component_fifo_0_end <= '0';
811 status_component_fifo_0_end <= '0';
830 status_component_fifo_1_end <= '0';
812 status_component_fifo_1_end <= '0';
831 SM_correlation_done_reg1 <= '0';
813 SM_correlation_done_reg1 <= '0';
832 SM_correlation_done_reg2 <= '0';
814 SM_correlation_done_reg2 <= '0';
833 SM_correlation_done_reg3 <= '0';
815 SM_correlation_done_reg3 <= '0';
834
816
835 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
817 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
836 SM_correlation_done_reg1 <= SM_correlation_done;
818 SM_correlation_done_reg1 <= SM_correlation_done;
837 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
819 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
838 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
820 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
839 status_component_fifo_0_end <= '0';
821 status_component_fifo_0_end <= '0';
840 status_component_fifo_1_end <= '0';
822 status_component_fifo_1_end <= '0';
841 IF SM_correlation_begin = '1' THEN
823 IF SM_correlation_begin = '1' THEN
842 IF current_matrix_write = '0' THEN
824 IF current_matrix_write = '0' THEN
843 status_component_fifo_0 <= status_component;
825 status_component_fifo_0 <= status_component;
844 ELSE
826 ELSE
845 status_component_fifo_1 <= status_component;
827 status_component_fifo_1 <= status_component;
846 END IF;
828 END IF;
847 END IF;
829 END IF;
848
830
849 IF SM_correlation_done_reg3 = '1' THEN
831 IF SM_correlation_done_reg3 = '1' THEN
850 IF current_matrix_write = '0' THEN
832 IF current_matrix_write = '0' THEN
851 status_component_fifo_0_end <= '1';
833 status_component_fifo_0_end <= '1';
852 ELSE
834 ELSE
853 status_component_fifo_1_end <= '1';
835 status_component_fifo_1_end <= '1';
854 END IF;
836 END IF;
855 current_matrix_wait_empty <= '1';
837 current_matrix_wait_empty <= '1';
856 current_matrix_write <= NOT current_matrix_write;
838 current_matrix_write <= NOT current_matrix_write;
857 END IF;
839 END IF;
858
840
859 IF current_matrix_wait_empty <= '1' THEN
841 IF current_matrix_wait_empty <= '1' THEN
860 IF current_matrix_write = '0' THEN
842 IF current_matrix_write = '0' THEN
861 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
843 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
862 ELSE
844 ELSE
863 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
845 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
864 END IF;
846 END IF;
865 END IF;
847 END IF;
866
848
867 END IF;
849 END IF;
868 END PROCESS;
850 END PROCESS;
869
851
870 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
852 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
871 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
853 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
872 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
854 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
873 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
855 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
874 '1' WHEN current_matrix_wait_empty = '1' ELSE
856 '1' WHEN current_matrix_wait_empty = '1' ELSE
875 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
857 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
876 MEM_OUT_SM_Full(1);
858 MEM_OUT_SM_Full(1);
877
859
878 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
860 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
879 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
861 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
880
862
881 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
863 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
882 -----------------------------------------------------------------------------
864 -----------------------------------------------------------------------------
883
865
884 Mem_Out_SpectralMatrix : lppFIFOxN
866 --Mem_Out_SpectralMatrix : lppFIFOxN
885 GENERIC MAP (
867 -- GENERIC MAP (
886 tech => 0,
868 -- tech => 0,
887 Mem_use => Mem_use,
869 -- Mem_use => Mem_use,
888 Data_sz => 32,
870 -- Data_sz => 32,
889 Addr_sz => 8,
871 -- Addr_sz => 8,
890 FifoCnt => 2)
872 -- FifoCnt => 2)
891 PORT MAP (
873 -- PORT MAP (
892 clk => clk,
874 -- clk => clk,
893 rstn => rstn,
875 -- rstn => rstn,
876
877 -- ReUse => (OTHERS => '0'),
878 -- run => (OTHERS => '1'),
879
880 -- wen => MEM_OUT_SM_Write,
881 -- wdata => MEM_OUT_SM_Data_in,
882
883 -- ren => MEM_OUT_SM_Read,
884 -- rdata => MEM_OUT_SM_Data_out,
885
886 -- full => MEM_OUT_SM_Full,
887 -- empty => MEM_OUT_SM_Empty,
888 -- almost_full => OPEN);
894
889
895 ReUse => (OTHERS => '0'),
890
896 run => (OTHERS => '1'),
891 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
897
892 Mem_Out_SpectralMatrix_I: lpp_fifo
898 wen => MEM_OUT_SM_Write,
893 GENERIC MAP (
899 wdata => MEM_OUT_SM_Data_in,
894 tech => 0,
895 Mem_use => Mem_use,
896 EMPTY_THRESHOLD_LIMIT => 15,
897 FULL_THRESHOLD_LIMIT => 1,
898 DataSz => 32,
899 AddrSz => 8)
900 PORT MAP (
901 clk => clk,
902 rstn => rstn,
903 reUse => '0',
904 run => run,
900
905
901 ren => MEM_OUT_SM_Read,
906 ren => MEM_OUT_SM_Read(I),
902 rdata => MEM_OUT_SM_Data_out,
907 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
903
908
904 full => MEM_OUT_SM_Full,
909 wen => MEM_OUT_SM_Write(I),
905 empty => MEM_OUT_SM_Empty,
910 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
906 almost_full => OPEN);
911
912 empty => MEM_OUT_SM_Empty(I),
913 full => MEM_OUT_SM_Full(I),
914 full_almost => OPEN,
915 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
916
917 full_threshold => OPEN);
918
919 END GENERATE all_Mem_Out_SpectralMatrix;
907
920
908 -----------------------------------------------------------------------------
921 -----------------------------------------------------------------------------
909 -- MEM_OUT_SM_Read <= "00";
922 -- MEM_OUT_SM_Read <= "00";
910 PROCESS (clk, rstn)
923 PROCESS (clk, rstn)
911 BEGIN
924 BEGIN
912 IF rstn = '0' THEN
925 IF rstn = '0' THEN
913 fifo_0_ready <= '0';
926 fifo_0_ready <= '0';
914 fifo_1_ready <= '0';
927 fifo_1_ready <= '0';
915 fifo_ongoing <= '0';
928 fifo_ongoing <= '0';
916 ELSIF clk'EVENT AND clk = '1' THEN
929 ELSIF clk'EVENT AND clk = '1' THEN
917 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
930 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
918 fifo_ongoing <= '1';
931 fifo_ongoing <= '1';
919 fifo_0_ready <= '0';
932 fifo_0_ready <= '0';
920 ELSIF status_component_fifo_0_end = '1' THEN
933 ELSIF status_component_fifo_0_end = '1' THEN
921 fifo_0_ready <= '1';
934 fifo_0_ready <= '1';
922 END IF;
935 END IF;
923
936
924 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
937 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
925 fifo_ongoing <= '0';
938 fifo_ongoing <= '0';
926 fifo_1_ready <= '0';
939 fifo_1_ready <= '0';
927 ELSIF status_component_fifo_1_end = '1' THEN
940 ELSIF status_component_fifo_1_end = '1' THEN
928 fifo_1_ready <= '1';
941 fifo_1_ready <= '1';
929 END IF;
942 END IF;
930
943
931 END IF;
944 END IF;
932 END PROCESS;
945 END PROCESS;
933
946
934 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
947 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
935 '1' WHEN fifo_0_ready = '0' ELSE
948 '1' WHEN fifo_0_ready = '0' ELSE
936 FSM_DMA_fifo_ren;
949 FSM_DMA_fifo_ren;
937
950
938 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
951 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
939 '1' WHEN fifo_1_ready = '0' ELSE
952 '1' WHEN fifo_1_ready = '0' ELSE
940 FSM_DMA_fifo_ren;
953 FSM_DMA_fifo_ren;
941
954
942 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
955 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
943 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
956 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
944 '1';
957 '1';
945
958
946 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
959 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
947 status_component_fifo_1;
960 status_component_fifo_1;
948
961
949 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
962 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
950 MEM_OUT_SM_Data_out(63 DOWNTO 32);
963 MEM_OUT_SM_Data_out(63 DOWNTO 32);
951
964
965
966 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
967 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
968 '0';
969
952 -----------------------------------------------------------------------------
970 -----------------------------------------------------------------------------
953 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
971 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
954 PORT MAP (
972 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
955 HCLK => clk,
973 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
956 HRESETn => rstn,
974 -- fifo_data => FSM_DMA_fifo_data, --IN
957
975 -- fifo_empty => FSM_DMA_fifo_empty, --IN
958 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
976 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
959 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
977 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
960 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
978
961 fifo_data => FSM_DMA_fifo_data,
962 fifo_empty => FSM_DMA_fifo_empty,
963 fifo_ren => FSM_DMA_fifo_ren,
964
979
965 dma_addr => dma_addr,
980 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
966 dma_data => dma_data,
981 PORT MAP (
967 dma_valid => dma_valid,
982 clk => clk,
968 dma_valid_burst => dma_valid_burst,
983 rstn => rstn,
969 dma_ren => dma_ren,
984 run => run,
970 dma_done => dma_done,
985
971
986 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
972 ready_matrix_f0 => ready_matrix_f0,
987 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
973 ready_matrix_f1 => ready_matrix_f1,
988 fifo_data => FSM_DMA_fifo_data,
974 ready_matrix_f2 => ready_matrix_f2,
989 fifo_empty => FSM_DMA_fifo_empty,
975
990 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
976 error_bad_component_error => error_bad_component_error,
991 fifo_ren => FSM_DMA_fifo_ren,
977 error_buffer_full => error_buffer_full,
992
978
993 dma_fifo_valid_burst => dma_fifo_burst_valid,
979 debug_reg => debug_reg,
994 dma_fifo_data => dma_fifo_data,
995 dma_fifo_ren => dma_fifo_ren,
996 dma_buffer_new => dma_buffer_new,
997 dma_buffer_addr => dma_buffer_addr,
998 dma_buffer_length => dma_buffer_length,
999 dma_buffer_full => dma_buffer_full,
1000 dma_buffer_full_err => dma_buffer_full_err,
1001
980 status_ready_matrix_f0 => status_ready_matrix_f0,
1002 status_ready_matrix_f0 => status_ready_matrix_f0,
981 status_ready_matrix_f1 => status_ready_matrix_f1,
1003 status_ready_matrix_f1 => status_ready_matrix_f1,
982 status_ready_matrix_f2 => status_ready_matrix_f2,
1004 status_ready_matrix_f2 => status_ready_matrix_f2,
1005 addr_matrix_f0 => addr_matrix_f0,
1006 addr_matrix_f1 => addr_matrix_f1,
1007 addr_matrix_f2 => addr_matrix_f2,
1008 length_matrix_f0 => length_matrix_f0,
1009 length_matrix_f1 => length_matrix_f1,
1010 length_matrix_f2 => length_matrix_f2,
1011 ready_matrix_f0 => ready_matrix_f0,
1012 ready_matrix_f1 => ready_matrix_f1,
1013 ready_matrix_f2 => ready_matrix_f2,
1014 matrix_time_f0 => matrix_time_f0,
1015 matrix_time_f1 => matrix_time_f1,
1016 matrix_time_f2 => matrix_time_f2,
1017 error_buffer_full => error_buffer_full);
1018
983
1019
984 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1020
985 config_active_interruption_onError => config_active_interruption_onError,
1021
1022
1023 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1024 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1025 --dma_fifo_ren : IN STD_LOGIC; --TODO
1026 --dma_buffer_new : OUT STD_LOGIC; --TODO
1027 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1028 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1029 --dma_buffer_full : IN STD_LOGIC; --TODO
1030 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1031
1032 ---- Reg out
1033 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1034 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1035 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1036 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1037 --error_buffer_full : OUT STD_LOGIC; -- TODO
1038
1039 ---- Reg In
1040 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1041 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1042 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1043
1044 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1045 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1046 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
986
1047
987 addr_matrix_f0 => addr_matrix_f0,
1048 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
988 addr_matrix_f1 => addr_matrix_f1,
1049 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
989 addr_matrix_f2 => addr_matrix_f2,
1050 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1051 -----------------------------------------------------------------------------
1052
1053 -----------------------------------------------------------------------------
1054 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1055 -- PORT MAP (
1056 -- HCLK => clk,
1057 -- HRESETn => rstn,
1058
1059 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1060 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1061 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1062 -- fifo_data => FSM_DMA_fifo_data,
1063 -- fifo_empty => FSM_DMA_fifo_empty,
1064 -- fifo_ren => FSM_DMA_fifo_ren,
990
1065
991 matrix_time_f0 => matrix_time_f0,
1066 -- dma_addr => dma_addr,
992 matrix_time_f1 => matrix_time_f1,
1067 -- dma_data => dma_data,
993 matrix_time_f2 => matrix_time_f2
1068 -- dma_valid => dma_valid,
994 );
1069 -- dma_valid_burst => dma_valid_burst,
1070 -- dma_ren => dma_ren,
1071 -- dma_done => dma_done,
1072
1073 -- ready_matrix_f0 => ready_matrix_f0,
1074 -- ready_matrix_f1 => ready_matrix_f1,
1075 -- ready_matrix_f2 => ready_matrix_f2,
1076
1077 -- error_bad_component_error => error_bad_component_error,
1078 -- error_buffer_full => error_buffer_full,
1079
1080 -- debug_reg => debug_reg,
1081 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1082 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1083 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1084
1085 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1086 -- config_active_interruption_onError => config_active_interruption_onError,
1087
1088 -- addr_matrix_f0 => addr_matrix_f0,
1089 -- addr_matrix_f1 => addr_matrix_f1,
1090 -- addr_matrix_f2 => addr_matrix_f2,
1091
1092 -- matrix_time_f0 => matrix_time_f0,
1093 -- matrix_time_f1 => matrix_time_f1,
1094 -- matrix_time_f2 => matrix_time_f2
1095 -- );
995 -----------------------------------------------------------------------------
1096 -----------------------------------------------------------------------------
996
1097
1098
997
1099
998
1100
999
1101
1000
1102
1001 -----------------------------------------------------------------------------
1103 -----------------------------------------------------------------------------
1002 -- TIME MANAGMENT
1104 -- TIME MANAGMENT
1003 -----------------------------------------------------------------------------
1105 -----------------------------------------------------------------------------
1004 all_time <= coarse_time & fine_time;
1106 all_time <= coarse_time & fine_time;
1005 --
1107 --
1006 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1108 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1007 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1109 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1008 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1110 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1009 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1111 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1010
1112
1011 all_time_reg: FOR I IN 0 TO 3 GENERATE
1113 all_time_reg: FOR I IN 0 TO 3 GENERATE
1012
1114
1013 PROCESS (clk, rstn)
1115 PROCESS (clk, rstn)
1014 BEGIN
1116 BEGIN
1015 IF rstn = '0' THEN
1117 IF rstn = '0' THEN
1016 f_empty_reg(I) <= '1';
1118 f_empty_reg(I) <= '1';
1017 ELSIF clk'event AND clk = '1' THEN
1119 ELSIF clk'event AND clk = '1' THEN
1018 f_empty_reg(I) <= f_empty(I);
1120 f_empty_reg(I) <= f_empty(I);
1019 END IF;
1121 END IF;
1020 END PROCESS;
1122 END PROCESS;
1021
1123
1022 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1124 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1023
1125
1024 s_m_t_m_f0_A : spectral_matrix_time_managment
1126 s_m_t_m_f0_A : spectral_matrix_time_managment
1025 PORT MAP (
1127 PORT MAP (
1026 clk => clk,
1128 clk => clk,
1027 rstn => rstn,
1129 rstn => rstn,
1028 time_in => all_time,
1130 time_in => all_time,
1029 update_1 => time_update_f(I),
1131 update_1 => time_update_f(I),
1030 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1132 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1031 );
1133 );
1032
1134
1033 END GENERATE all_time_reg;
1135 END GENERATE all_time_reg;
1034
1136
1035 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1137 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1036 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1138 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1037 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1139 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1038 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1140 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1039
1141
1040 -----------------------------------------------------------------------------
1142 -----------------------------------------------------------------------------
1041
1143
1042 END Behavioral;
1144 END Behavioral; No newline at end of file
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@@ -1,299 +1,187
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
26 USE ieee.numeric_std.ALL;
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
33 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
37 LIBRARY techmap;
37 LIBRARY techmap;
38 USE techmap.gencomp.ALL;
38 USE techmap.gencomp.ALL;
39
39
40
40
41 ENTITY lpp_lfr_ms_fsmdma IS
41 ENTITY lpp_lfr_ms_fsmdma IS
42 PORT (
42 PORT (
43 -- AMBA AHB system signals
43 -- AMBA AHB system signals
44 HCLK : IN STD_ULOGIC;
44 clk : IN STD_ULOGIC;
45 HRESETn : IN STD_ULOGIC;
45 rstn : IN STD_ULOGIC;
46 run : IN STD_LOGIC;
46
47
47 ---------------------------------------------------------------------------
48 ---------------------------------------------------------------------------
48 -- FIFO - IN
49 -- FIFO - IN
49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_empty : IN STD_LOGIC;
53 fifo_empty : IN STD_LOGIC;
54 fifo_empty_threshold : IN STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
55
56
56 ---------------------------------------------------------------------------
57 ---------------------------------------------------------------------------
57 -- DMA - OUT
58 -- DMA - OUT
58 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 dma_fifo_valid_burst : OUT STD_LOGIC;
59 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 dma_valid : OUT STD_LOGIC;
61 dma_fifo_ren : IN STD_LOGIC;
61 dma_valid_burst : OUT STD_LOGIC;
62
62 dma_ren : IN STD_LOGIC;
63 dma_buffer_new : OUT STD_LOGIC;
63 dma_done : IN STD_LOGIC;
64 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
66 dma_buffer_full : IN STD_LOGIC;
67 dma_buffer_full_err : IN STD_LOGIC;
64
68
65 ---------------------------------------------------------------------------
69 ---------------------------------------------------------------------------
66 -- Reg out
70 -- Reg In
67 ready_matrix_f0 : OUT STD_LOGIC;
71 status_ready_matrix_f0 : IN STD_LOGIC;
68 ready_matrix_f1 : OUT STD_LOGIC;
72 status_ready_matrix_f1 : IN STD_LOGIC;
69 ready_matrix_f2 : OUT STD_LOGIC;
73 status_ready_matrix_f2 : IN STD_LOGIC;
70
74
71 error_bad_component_error : OUT STD_LOGIC;
75 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 error_buffer_full : OUT STD_LOGIC;
76 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
78
75 -- Reg In
79 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
76 status_ready_matrix_f0 : IN STD_LOGIC;
80 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
77 status_ready_matrix_f1 : IN STD_LOGIC;
81 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
78 status_ready_matrix_f2 : IN STD_LOGIC;
79
82
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
83 -- Reg Out
81 config_active_interruption_onError : IN STD_LOGIC;
84 ready_matrix_f0 : OUT STD_LOGIC;
82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 ready_matrix_f1 : OUT STD_LOGIC;
83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 ready_matrix_f2 : OUT STD_LOGIC;
84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85
87
86 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
90 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
89
91 error_buffer_full : OUT STD_LOGIC
90 );
92 );
91 END;
93 END;
92
94
93 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
95 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
94 -----------------------------------------------------------------------------
95 TYPE state_DMAWriteBurst IS (IDLE,
96 CHECK_COMPONENT_TYPE,
97 WRITE_COARSE_TIME,
98 WRITE_FINE_TIME,
99 TRASH_FIFO,
100 SEND_DATA,
101 WAIT_DATA_ACK
102 );
103 SIGNAL state : state_DMAWriteBurst;
104
105 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
106 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SIGNAL header_check_ok : STD_LOGIC;
109 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113
96
114 SIGNAL component_send : STD_LOGIC;
97 TYPE FSM_DMA_STATE IS (IDLE, ONGOING);
115 SIGNAL component_send_ok : STD_LOGIC;
98 SIGNAL state : FSM_DMA_STATE;
116 -----------------------------------------------------------------------------
99 SIGNAL burst_valid_s : STD_LOGIC;
117 SIGNAL fifo_ren_trash : STD_LOGIC;
118
119 -----------------------------------------------------------------------------
120 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 -----------------------------------------------------------------------------
122 SIGNAL log_empty_fifo : STD_LOGIC;
123 -----------------------------------------------------------------------------
124
100
125 SIGNAL matrix_buffer_ready : STD_LOGIC;
101 SIGNAL current_matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 BEGIN
127
128 debug_reg <= debug_reg_s;
129
130
131 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
132 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
133 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
134 '0';
135
102
136 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
103 BEGIN
137 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
104 burst_valid_s <= NOT fifo_empty_threshold;
138 '1' WHEN component_type = component_type_pre + "0001" ELSE
139 '0';
140
141 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
142 addr_matrix_f1 WHEN matrix_type = "01" ELSE
143 addr_matrix_f2 WHEN matrix_type = "10" ELSE
144 (OTHERS => '0');
145
105
146 debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
106 error_buffer_full <= dma_buffer_full_err;
147 -----------------------------------------------------------------------------
148 -- DMA control
149 -----------------------------------------------------------------------------
150 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
151 BEGIN
152 IF HRESETn = '0' THEN
153 matrix_type <= (OTHERS => '0');
154 component_type <= (OTHERS => '0');
155 state <= IDLE;
156 ready_matrix_f0 <= '0';
157 ready_matrix_f1 <= '0';
158 ready_matrix_f2 <= '0';
159 error_bad_component_error <= '0';
160 error_buffer_full <= '0'; -- TODO
161 component_type_pre <= "0000";
162 fifo_ren_trash <= '1';
163 component_send <= '0';
164 address <= (OTHERS => '0');
165
107
166 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
108 fifo_ren <= dma_fifo_ren WHEN state = ONGOING ELSE '1';
167 debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0');
109 dma_fifo_data <= fifo_data;
168 debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0');
110 dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE '1';
169 debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0');
170 debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0');
171
172 log_empty_fifo <= '0';
173
174 matrix_time_f0 <= (OTHERS => '0');
175 matrix_time_f1 <= (OTHERS => '0');
176 matrix_time_f2 <= (OTHERS => '0');
177
111
178 ELSIF HCLK'EVENT AND HCLK = '1' THEN
112 PROCESS (clk, rstn)
179 --
113 BEGIN -- PROCESS
180 debug_reg_s(3) <= status_ready_matrix_f0;
114 IF rstn = '0' THEN -- asynchronous reset (active low)
181 debug_reg_s(4) <= status_ready_matrix_f1;
115 state <= IDLE;
182 debug_reg_s(5) <= status_ready_matrix_f2;
116 current_matrix_type <= "00";
183 debug_reg_s(6) <= '0';
117 matrix_time_f0 <= (OTHERS => '0');
184 debug_reg_s(7) <= '0';
118 matrix_time_f1 <= (OTHERS => '0');
185 debug_reg_s(8) <= '0';
119 matrix_time_f2 <= (OTHERS => '0');
186 debug_reg_s(10 DOWNTO 9) <= matrix_type;
120 dma_buffer_addr <= (OTHERS => '0');
187 debug_reg_s(14 DOWNTO 11) <= component_type;
121 dma_buffer_length <= (OTHERS => '0');
188
122 dma_buffer_new <= '0';
189 --
123 ready_matrix_f0 <= '0';
190
124 ready_matrix_f1 <= '0';
191
125 ready_matrix_f2 <= '0';
192
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
193 ready_matrix_f0 <= '0';
127 ready_matrix_f0 <= '0';
194 ready_matrix_f1 <= '0';
128 ready_matrix_f1 <= '0';
195 ready_matrix_f2 <= '0';
129 ready_matrix_f2 <= '0';
196 error_bad_component_error <= '0';
130 IF run = '1' THEN
197 error_buffer_full <= '0';
131 CASE state IS
198
132 WHEN IDLE =>
199 CASE state IS
133 IF fifo_empty = '0' THEN
200 WHEN IDLE =>
134 current_matrix_type <= fifo_matrix_type;
201 debug_reg_s(2 DOWNTO 0) <= "000";
135 CASE fifo_matrix_type IS
202 IF fifo_empty = '0' THEN
136 WHEN "00" =>
203 state <= CHECK_COMPONENT_TYPE;
137 IF status_ready_matrix_f0 = '0' THEN
204 matrix_type <= fifo_matrix_type;
138 state <= ONGOING;
205 component_type <= fifo_matrix_component;
139 matrix_time_f0 <= fifo_matrix_time;
206 component_type_pre <= component_type;
140 dma_buffer_addr <= addr_matrix_f0;
207 END IF;
141 dma_buffer_length <= length_matrix_f0;
208
142 dma_buffer_new <= '1';
209 log_empty_fifo <= '0';
143 END IF;
210
144 WHEN "01" =>
211 WHEN CHECK_COMPONENT_TYPE =>
145 IF status_ready_matrix_f1 = '0' THEN
212 debug_reg_s(2 DOWNTO 0) <= "001";
146 state <= ONGOING;
213
147 matrix_time_f1 <= fifo_matrix_time;
214 IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN
148 dma_buffer_addr <= addr_matrix_f1;
215 IF component_type = "0000" THEN
149 dma_buffer_length <= length_matrix_f1;
216 address <= address_matrix;
150 dma_buffer_new <= '1';
217 CASE matrix_type IS
151 END IF;
218 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
152 WHEN "10" =>
219 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
153 IF status_ready_matrix_f2 = '0' THEN
220 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
154 state <= ONGOING;
221 WHEN OTHERS => NULL;
155 matrix_time_f2 <= fifo_matrix_time;
222 END CASE;
156 dma_buffer_addr <= addr_matrix_f2;
223 component_send <= '1';
157 dma_buffer_length <= length_matrix_f2;
224 END IF;
158 dma_buffer_new <= '1';
225 state <= SEND_DATA;
159 END IF;
226 --
227 ELSE
228 error_bad_component_error <= NOT header_check_ok;
229 error_buffer_full <= NOT matrix_buffer_ready; -- TODO
230 component_type_pre <= "0000";
231 state <= TRASH_FIFO;
232 END IF;
233
234 WHEN TRASH_FIFO =>
235 debug_reg_s(2 DOWNTO 0) <= "100";
236
237 error_buffer_full <= '0';
238 error_bad_component_error <= '0';
239 IF fifo_empty = '1' THEN
240 state <= IDLE;
241 fifo_ren_trash <= '1';
242 ELSE
243 fifo_ren_trash <= '0';
244 END IF;
245
246 WHEN SEND_DATA =>
247 debug_reg_s(2 DOWNTO 0) <= "010";
248
249 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
250 state <= IDLE;
251 IF component_type = "1110" THEN
252 CASE matrix_type IS
253 WHEN "00" =>
254 ready_matrix_f0 <= '1';
255 debug_reg_s(6) <= '1';
256 WHEN "01" =>
257 ready_matrix_f1 <= '1';
258 debug_reg_s(7) <= '1';
259 WHEN "10" =>
260 ready_matrix_f2 <= '1';
261 debug_reg_s(8) <= '1';
262 WHEN OTHERS => NULL;
160 WHEN OTHERS => NULL;
263 END CASE;
161 END CASE;
264 END IF;
162 END IF;
265 ELSE
163 WHEN ONGOING =>
266 component_send <= '1';
164 IF dma_buffer_full = '1' THEN
267 address <= address;
165 CASE current_matrix_type IS
268 state <= WAIT_DATA_ACK;
166 WHEN "00" => ready_matrix_f0 <= '1'; state <= IDLE;
269 END IF;
167 WHEN "01" => ready_matrix_f1 <= '1'; state <= IDLE;
270
168 WHEN "10" => ready_matrix_f2 <= '1'; state <= IDLE;
271 WHEN WAIT_DATA_ACK =>
169 WHEN OTHERS => NULL;
272 log_empty_fifo <= fifo_empty OR log_empty_fifo;
170 END CASE;
273
171 END IF;
274 debug_reg_s(2 DOWNTO 0) <= "011";
172 WHEN OTHERS => NULL;
275
173 END CASE;
276 IF dma_ren = '0' THEN
174 ELSE
277 component_send <= '0';
175 state <= IDLE;
278 END IF;
176 current_matrix_type <= "00";
279
177 matrix_time_f0 <= (OTHERS => '0');
280 IF component_send_ok = '1' THEN
178 matrix_time_f1 <= (OTHERS => '0');
281 address <= address + 64;
179 matrix_time_f2 <= (OTHERS => '0');
282 state <= SEND_DATA;
180 dma_buffer_addr <= (OTHERS => '0');
283 END IF;
181 dma_buffer_length <= (OTHERS => '0');
284
182 dma_buffer_new <= '0';
285 WHEN OTHERS => NULL;
183 END IF;
286 END CASE;
287
288 END IF;
184 END IF;
289 END PROCESS DMAWriteFSM_p;
185 END PROCESS;
290
291 dma_valid_burst <= component_send;
292 dma_valid <= '0';
293 dma_data <= fifo_data;
294 dma_addr <= address;
295 fifo_ren <= dma_ren AND fifo_ren_trash;
296
297 component_send_ok <= dma_done;
298
186
299 END Behavioral;
187 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,431 +1,393
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
16 -----------------------------------------------------------------------------
17 -- TEMP
17 -- TEMP
18 -----------------------------------------------------------------------------
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
20 GENERIC (
21 Mem_use : INTEGER);
21 Mem_use : INTEGER);
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
25
26 -- TIME
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
38
39
39
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
43
44 --
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
51
52 -- IN
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
54
55 -----------------------------------------------------------------------------
55 -----------------------------------------------------------------------------
56
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
61
62 SM_correlation_start : OUT STD_LOGIC;
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
64 SM_correlation_done : IN STD_LOGIC
65 );
65 );
66 END COMPONENT;
66 END COMPONENT;
67
67
68
68
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
71 GENERIC (
71 GENERIC (
72 Mem_use : INTEGER
72 Mem_use : INTEGER);
73 );
74 PORT (
73 PORT (
75 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
77
76 run : IN STD_LOGIC;
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
77 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
78 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
80
79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83
82 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86
85 dma_fifo_burst_valid : OUT STD_LOGIC;
87 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
86 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 dma_fifo_ren : IN STD_LOGIC;
89
88 dma_buffer_new : OUT STD_LOGIC;
90 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92 dma_valid : OUT STD_LOGIC;
91 dma_buffer_full : IN STD_LOGIC;
93 dma_valid_burst : OUT STD_LOGIC;
92 dma_buffer_full_err : IN STD_LOGIC;
94 dma_ren : IN STD_LOGIC;
93 ready_matrix_f0 : OUT STD_LOGIC;
95 dma_done : IN STD_LOGIC;
94 ready_matrix_f1 : OUT STD_LOGIC;
96
95 ready_matrix_f2 : OUT STD_LOGIC;
97 ready_matrix_f0 : OUT STD_LOGIC;
96 error_buffer_full : OUT STD_LOGIC;
98 -- ready_matrix_f0_1 : OUT STD_LOGIC;
97 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
99 ready_matrix_f1 : OUT STD_LOGIC;
98 status_ready_matrix_f0 : IN STD_LOGIC;
100 ready_matrix_f2 : OUT STD_LOGIC;
99 status_ready_matrix_f1 : IN STD_LOGIC;
101 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
100 status_ready_matrix_f2 : IN STD_LOGIC;
102 error_bad_component_error : OUT STD_LOGIC;
101 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 error_buffer_full : OUT STD_LOGIC;
102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 --
105 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
106 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
107 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 -------------------------------------------------------------------------
108 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
110 status_ready_matrix_f0 : IN STD_LOGIC;
109 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
111 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
112 status_ready_matrix_f1 : IN STD_LOGIC;
113 status_ready_matrix_f2 : IN STD_LOGIC;
114 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
115 -- status_error_bad_component_error : IN STD_LOGIC;
116 config_active_interruption_onNewMatrix : IN STD_LOGIC;
117 config_active_interruption_onError : IN STD_LOGIC;
118 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
119 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
122
123 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
124 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
125 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
126 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
127 END COMPONENT;
110 END COMPONENT;
128
111
129 COMPONENT lpp_lfr_ms_fsmdma
112 COMPONENT lpp_lfr_ms_fsmdma
130 PORT (
113 PORT (
131 HCLK : IN STD_ULOGIC;
114 clk : IN STD_ULOGIC;
132 HRESETn : IN STD_ULOGIC;
115 rstn : IN STD_ULOGIC;
133 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
116 run : IN STD_LOGIC;
134 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
117 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
135 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
118 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
136 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
119 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 fifo_empty : IN STD_LOGIC;
120 fifo_empty : IN STD_LOGIC;
138 fifo_ren : OUT STD_LOGIC;
121 fifo_empty_threshold : IN STD_LOGIC;
139 --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
122 fifo_ren : OUT STD_LOGIC;
140 --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
123 dma_fifo_valid_burst : OUT STD_LOGIC;
141 --fifo_empty : IN STD_LOGIC;
124 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 --fifo_ren : OUT STD_LOGIC;
125 dma_fifo_ren : IN STD_LOGIC;
143 --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
126 dma_buffer_new : OUT STD_LOGIC;
144 --header_val : IN STD_LOGIC;
127 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
145 --header_ack : OUT STD_LOGIC;
128 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
146 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 dma_buffer_full : IN STD_LOGIC;
147 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 dma_buffer_full_err : IN STD_LOGIC;
148 dma_valid : OUT STD_LOGIC;
131 status_ready_matrix_f0 : IN STD_LOGIC;
149 dma_valid_burst : OUT STD_LOGIC;
132 status_ready_matrix_f1 : IN STD_LOGIC;
150 dma_ren : IN STD_LOGIC;
133 status_ready_matrix_f2 : IN STD_LOGIC;
151 dma_done : IN STD_LOGIC;
134 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
152 ready_matrix_f0 : OUT STD_LOGIC;
135 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
153 -- ready_matrix_f0_1 : OUT STD_LOGIC;
136 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
154 ready_matrix_f1 : OUT STD_LOGIC;
137 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
155 ready_matrix_f2 : OUT STD_LOGIC;
138 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
156 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
139 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
157 error_bad_component_error : OUT STD_LOGIC;
140 ready_matrix_f0 : OUT STD_LOGIC;
158 error_buffer_full : OUT STD_LOGIC;
141 ready_matrix_f1 : OUT STD_LOGIC;
159 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 ready_matrix_f2 : OUT STD_LOGIC;
160 status_ready_matrix_f0 : IN STD_LOGIC;
143 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
161 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
144 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
162 status_ready_matrix_f1 : IN STD_LOGIC;
145 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
163 status_ready_matrix_f2 : IN STD_LOGIC;
146 error_buffer_full : OUT STD_LOGIC);
164 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
165 -- status_error_bad_component_error : IN STD_LOGIC;
166 config_active_interruption_onNewMatrix : IN STD_LOGIC;
167 config_active_interruption_onError : IN STD_LOGIC;
168 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
169 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
172
173 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
174 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
175 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
176 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
177 );
178 END COMPONENT;
147 END COMPONENT;
179
148
180 COMPONENT lpp_lfr_ms_FFT
149 COMPONENT lpp_lfr_ms_FFT
181 PORT (
150 PORT (
182 clk : IN STD_LOGIC;
151 clk : IN STD_LOGIC;
183 rstn : IN STD_LOGIC;
152 rstn : IN STD_LOGIC;
184 sample_valid : IN STD_LOGIC;
153 sample_valid : IN STD_LOGIC;
185 fft_read : IN STD_LOGIC;
154 fft_read : IN STD_LOGIC;
186 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
155 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
187 sample_load : OUT STD_LOGIC;
156 sample_load : OUT STD_LOGIC;
188 fft_pong : OUT STD_LOGIC;
157 fft_pong : OUT STD_LOGIC;
189 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
158 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
190 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
159 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
191 fft_data_valid : OUT STD_LOGIC;
160 fft_data_valid : OUT STD_LOGIC;
192 fft_ready : OUT STD_LOGIC);
161 fft_ready : OUT STD_LOGIC);
193 END COMPONENT;
162 END COMPONENT;
194
163
195 COMPONENT lpp_lfr_filter
164 COMPONENT lpp_lfr_filter
196 GENERIC (
165 GENERIC (
197 Mem_use : INTEGER);
166 Mem_use : INTEGER);
198 PORT (
167 PORT (
199 sample : IN Samples(7 DOWNTO 0);
168 sample : IN Samples(7 DOWNTO 0);
200 sample_val : IN STD_LOGIC;
169 sample_val : IN STD_LOGIC;
201 clk : IN STD_LOGIC;
170 clk : IN STD_LOGIC;
202 rstn : IN STD_LOGIC;
171 rstn : IN STD_LOGIC;
203 data_shaping_SP0 : IN STD_LOGIC;
172 data_shaping_SP0 : IN STD_LOGIC;
204 data_shaping_SP1 : IN STD_LOGIC;
173 data_shaping_SP1 : IN STD_LOGIC;
205 data_shaping_R0 : IN STD_LOGIC;
174 data_shaping_R0 : IN STD_LOGIC;
206 data_shaping_R1 : IN STD_LOGIC;
175 data_shaping_R1 : IN STD_LOGIC;
207 data_shaping_R2 : IN STD_LOGIC;
176 data_shaping_R2 : IN STD_LOGIC;
208 sample_f0_val : OUT STD_LOGIC;
177 sample_f0_val : OUT STD_LOGIC;
209 sample_f1_val : OUT STD_LOGIC;
178 sample_f1_val : OUT STD_LOGIC;
210 sample_f2_val : OUT STD_LOGIC;
179 sample_f2_val : OUT STD_LOGIC;
211 sample_f3_val : OUT STD_LOGIC;
180 sample_f3_val : OUT STD_LOGIC;
212 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
181 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
213 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
182 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
214 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
215 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
184 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
216 END COMPONENT;
185 END COMPONENT;
217
186
218 COMPONENT lpp_lfr
187 COMPONENT lpp_lfr
219 GENERIC (
188 GENERIC (
220 Mem_use : INTEGER;
189 Mem_use : INTEGER;
221 nb_data_by_buffer_size : INTEGER;
190 nb_data_by_buffer_size : INTEGER;
222 nb_word_by_buffer_size : INTEGER;
191 nb_word_by_buffer_size : INTEGER;
223 nb_snapshot_param_size : INTEGER;
192 nb_snapshot_param_size : INTEGER;
224 delta_vector_size : INTEGER;
193 delta_vector_size : INTEGER;
225 delta_vector_size_f0_2 : INTEGER;
194 delta_vector_size_f0_2 : INTEGER;
226 pindex : INTEGER;
195 pindex : INTEGER;
227 paddr : INTEGER;
196 paddr : INTEGER;
228 pmask : INTEGER;
197 pmask : INTEGER;
229 pirq_ms : INTEGER;
198 pirq_ms : INTEGER;
230 pirq_wfp : INTEGER;
199 pirq_wfp : INTEGER;
231 hindex : INTEGER;
200 hindex : INTEGER;
232 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
201 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
233 );
202 );
234 PORT (
203 PORT (
235 clk : IN STD_LOGIC;
204 clk : IN STD_LOGIC;
236 rstn : IN STD_LOGIC;
205 rstn : IN STD_LOGIC;
237 sample_B : IN Samples(2 DOWNTO 0);
206 sample_B : IN Samples(2 DOWNTO 0);
238 sample_E : IN Samples(4 DOWNTO 0);
207 sample_E : IN Samples(4 DOWNTO 0);
239 sample_val : IN STD_LOGIC;
208 sample_val : IN STD_LOGIC;
240 apbi : IN apb_slv_in_type;
209 apbi : IN apb_slv_in_type;
241 apbo : OUT apb_slv_out_type;
210 apbo : OUT apb_slv_out_type;
242 ahbi : IN AHB_Mst_In_Type;
211 ahbi : IN AHB_Mst_In_Type;
243 ahbo : OUT AHB_Mst_Out_Type;
212 ahbo : OUT AHB_Mst_Out_Type;
244 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
213 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
245 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
214 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
246 data_shaping_BW : OUT STD_LOGIC;
215 data_shaping_BW : OUT STD_LOGIC;
247 --
216 --
248 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
217 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
249 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
218 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
250 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
219 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
251 );
220 );
252 END COMPONENT;
221 END COMPONENT;
253
222
254 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
255 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
224 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
256 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
257 COMPONENT lpp_lfr_WFP_nMS
226 COMPONENT lpp_lfr_WFP_nMS
258 GENERIC (
227 GENERIC (
259 Mem_use : INTEGER;
228 Mem_use : INTEGER;
260 nb_data_by_buffer_size : INTEGER;
229 nb_data_by_buffer_size : INTEGER;
261 nb_word_by_buffer_size : INTEGER;
230 nb_word_by_buffer_size : INTEGER;
262 nb_snapshot_param_size : INTEGER;
231 nb_snapshot_param_size : INTEGER;
263 delta_vector_size : INTEGER;
232 delta_vector_size : INTEGER;
264 delta_vector_size_f0_2 : INTEGER;
233 delta_vector_size_f0_2 : INTEGER;
265 pindex : INTEGER;
234 pindex : INTEGER;
266 paddr : INTEGER;
235 paddr : INTEGER;
267 pmask : INTEGER;
236 pmask : INTEGER;
268 pirq_ms : INTEGER;
237 pirq_ms : INTEGER;
269 pirq_wfp : INTEGER;
238 pirq_wfp : INTEGER;
270 hindex : INTEGER;
239 hindex : INTEGER;
271 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
240 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
272 PORT (
241 PORT (
273 clk : IN STD_LOGIC;
242 clk : IN STD_LOGIC;
274 rstn : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
275 sample_B : IN Samples(2 DOWNTO 0);
244 sample_B : IN Samples(2 DOWNTO 0);
276 sample_E : IN Samples(4 DOWNTO 0);
245 sample_E : IN Samples(4 DOWNTO 0);
277 sample_val : IN STD_LOGIC;
246 sample_val : IN STD_LOGIC;
278 apbi : IN apb_slv_in_type;
247 apbi : IN apb_slv_in_type;
279 apbo : OUT apb_slv_out_type;
248 apbo : OUT apb_slv_out_type;
280 ahbi : IN AHB_Mst_In_Type;
249 ahbi : IN AHB_Mst_In_Type;
281 ahbo : OUT AHB_Mst_Out_Type;
250 ahbo : OUT AHB_Mst_Out_Type;
282 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
251 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
283 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
252 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
284 data_shaping_BW : OUT STD_LOGIC;
253 data_shaping_BW : OUT STD_LOGIC;
285 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
286 END COMPONENT;
255 END COMPONENT;
287 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
257
288 COMPONENT lpp_lfr_apbreg
258 COMPONENT lpp_lfr_apbreg
289 GENERIC (
259 GENERIC (
290 nb_data_by_buffer_size : INTEGER;
260 nb_data_by_buffer_size : INTEGER;
291 nb_word_by_buffer_size : INTEGER;
261 nb_word_by_buffer_size : INTEGER;
292 nb_snapshot_param_size : INTEGER;
262 nb_snapshot_param_size : INTEGER;
293 delta_vector_size : INTEGER;
263 delta_vector_size : INTEGER;
294 delta_vector_size_f0_2 : INTEGER;
264 delta_vector_size_f0_2 : INTEGER;
295 pindex : INTEGER;
265 pindex : INTEGER;
296 paddr : INTEGER;
266 paddr : INTEGER;
297 pmask : INTEGER;
267 pmask : INTEGER;
298 pirq_ms : INTEGER;
268 pirq_ms : INTEGER;
299 pirq_wfp : INTEGER;
269 pirq_wfp : INTEGER;
300 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
270 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
301 PORT (
271 PORT (
302 HCLK : IN STD_ULOGIC;
272 HCLK : IN STD_ULOGIC;
303 HRESETn : IN STD_ULOGIC;
273 HRESETn : IN STD_ULOGIC;
304 apbi : IN apb_slv_in_type;
274 apbi : IN apb_slv_in_type;
305 apbo : OUT apb_slv_out_type;
275 apbo : OUT apb_slv_out_type;
306 run_ms : OUT STD_LOGIC;
276 run_ms : OUT STD_LOGIC;
307 ready_matrix_f0 : IN STD_LOGIC;
277 ready_matrix_f0 : IN STD_LOGIC;
308 ready_matrix_f1 : IN STD_LOGIC;
278 ready_matrix_f1 : IN STD_LOGIC;
309 ready_matrix_f2 : IN STD_LOGIC;
279 ready_matrix_f2 : IN STD_LOGIC;
310 error_bad_component_error : IN STD_LOGIC;
280 error_buffer_full : IN STD_LOGIC;
311 error_buffer_full : in STD_LOGIC;
281 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
312 error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0);
282 status_ready_matrix_f0 : OUT STD_LOGIC;
313 --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
283 status_ready_matrix_f1 : OUT STD_LOGIC;
314 status_ready_matrix_f0 : OUT STD_LOGIC;
284 status_ready_matrix_f2 : OUT STD_LOGIC;
315 status_ready_matrix_f1 : OUT STD_LOGIC;
285 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
316 status_ready_matrix_f2 : OUT STD_LOGIC;
286 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
317 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
287 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
318 config_active_interruption_onError : OUT STD_LOGIC;
288 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
319 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
289 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
320 -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
290 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
321 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
291 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
322 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
292 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
323 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
293 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
324 -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
294 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
325 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
295 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
326 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
296 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
327 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
297 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
328 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
298 data_shaping_BW : OUT STD_LOGIC;
329 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
299 data_shaping_SP0 : OUT STD_LOGIC;
330 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
300 data_shaping_SP1 : OUT STD_LOGIC;
331 data_shaping_BW : OUT STD_LOGIC;
301 data_shaping_R0 : OUT STD_LOGIC;
332 data_shaping_SP0 : OUT STD_LOGIC;
302 data_shaping_R1 : OUT STD_LOGIC;
333 data_shaping_SP1 : OUT STD_LOGIC;
303 data_shaping_R2 : OUT STD_LOGIC;
334 data_shaping_R0 : OUT STD_LOGIC;
304 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
335 data_shaping_R1 : OUT STD_LOGIC;
305 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
336 data_shaping_R2 : OUT STD_LOGIC;
306 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
337 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
307 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
338 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
308 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
339 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
309 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
340 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
310 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
341 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
311 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
342 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
312 enable_f0 : OUT STD_LOGIC;
343 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
313 enable_f1 : OUT STD_LOGIC;
344 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
314 enable_f2 : OUT STD_LOGIC;
345 enable_f0 : OUT STD_LOGIC;
315 enable_f3 : OUT STD_LOGIC;
346 enable_f1 : OUT STD_LOGIC;
316 burst_f0 : OUT STD_LOGIC;
347 enable_f2 : OUT STD_LOGIC;
317 burst_f1 : OUT STD_LOGIC;
348 enable_f3 : OUT STD_LOGIC;
318 burst_f2 : OUT STD_LOGIC;
349 burst_f0 : OUT STD_LOGIC;
319 run : OUT STD_LOGIC;
350 burst_f1 : OUT STD_LOGIC;
320 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
351 burst_f2 : OUT STD_LOGIC;
321 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
352 run : OUT STD_LOGIC;
322 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
323 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
324 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
355 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
325 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
356 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
357 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
358
359 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
360
361 );
362 END COMPONENT;
326 END COMPONENT;
363
327
364
365
366 COMPONENT lpp_top_ms
328 COMPONENT lpp_top_ms
367 GENERIC (
329 GENERIC (
368 Mem_use : INTEGER;
330 Mem_use : INTEGER;
369 nb_burst_available_size : INTEGER;
331 nb_burst_available_size : INTEGER;
370 nb_snapshot_param_size : INTEGER;
332 nb_snapshot_param_size : INTEGER;
371 delta_snapshot_size : INTEGER;
333 delta_snapshot_size : INTEGER;
372 delta_f2_f0_size : INTEGER;
334 delta_f2_f0_size : INTEGER;
373 delta_f2_f1_size : INTEGER;
335 delta_f2_f1_size : INTEGER;
374 pindex : INTEGER;
336 pindex : INTEGER;
375 paddr : INTEGER;
337 paddr : INTEGER;
376 pmask : INTEGER;
338 pmask : INTEGER;
377 pirq_ms : INTEGER;
339 pirq_ms : INTEGER;
378 pirq_wfp : INTEGER;
340 pirq_wfp : INTEGER;
379 hindex_wfp : INTEGER;
341 hindex_wfp : INTEGER;
380 hindex_ms : INTEGER);
342 hindex_ms : INTEGER);
381 PORT (
343 PORT (
382 clk : IN STD_LOGIC;
344 clk : IN STD_LOGIC;
383 rstn : IN STD_LOGIC;
345 rstn : IN STD_LOGIC;
384 sample_B : IN Samples14v(2 DOWNTO 0);
346 sample_B : IN Samples14v(2 DOWNTO 0);
385 sample_E : IN Samples14v(4 DOWNTO 0);
347 sample_E : IN Samples14v(4 DOWNTO 0);
386 sample_val : IN STD_LOGIC;
348 sample_val : IN STD_LOGIC;
387 apbi : IN apb_slv_in_type;
349 apbi : IN apb_slv_in_type;
388 apbo : OUT apb_slv_out_type;
350 apbo : OUT apb_slv_out_type;
389 ahbi_ms : IN AHB_Mst_In_Type;
351 ahbi_ms : IN AHB_Mst_In_Type;
390 ahbo_ms : OUT AHB_Mst_Out_Type;
352 ahbo_ms : OUT AHB_Mst_Out_Type;
391 data_shaping_BW : OUT STD_LOGIC;
353 data_shaping_BW : OUT STD_LOGIC;
392 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
354 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
393 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
355 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
394 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
356 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
395 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
357 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
396
358
397 );
359 );
398 END COMPONENT;
360 END COMPONENT;
399
361
400 COMPONENT lpp_apbreg_ms_pointer
362 COMPONENT lpp_apbreg_ms_pointer
401 PORT (
363 PORT (
402 clk : IN STD_LOGIC;
364 clk : IN STD_LOGIC;
403 rstn : IN STD_LOGIC;
365 rstn : IN STD_LOGIC;
404 reg0_status_ready_matrix : IN STD_LOGIC;
366 reg0_status_ready_matrix : IN STD_LOGIC;
405 reg0_ready_matrix : OUT STD_LOGIC;
367 reg0_ready_matrix : OUT STD_LOGIC;
406 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
368 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
407 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
369 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
408 reg1_status_ready_matrix : IN STD_LOGIC;
370 reg1_status_ready_matrix : IN STD_LOGIC;
409 reg1_ready_matrix : OUT STD_LOGIC;
371 reg1_ready_matrix : OUT STD_LOGIC;
410 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
372 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
411 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
373 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
412 ready_matrix : IN STD_LOGIC;
374 ready_matrix : IN STD_LOGIC;
413 status_ready_matrix : OUT STD_LOGIC;
375 status_ready_matrix : OUT STD_LOGIC;
414 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
376 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
415 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
377 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
416 END COMPONENT;
378 END COMPONENT;
417
379
418 COMPONENT lpp_lfr_ms_reg_head
380 COMPONENT lpp_lfr_ms_reg_head
419 PORT (
381 PORT (
420 clk : IN STD_LOGIC;
382 clk : IN STD_LOGIC;
421 rstn : IN STD_LOGIC;
383 rstn : IN STD_LOGIC;
422 in_wen : IN STD_LOGIC;
384 in_wen : IN STD_LOGIC;
423 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
385 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
424 in_full : IN STD_LOGIC;
386 in_full : IN STD_LOGIC;
425 in_empty : IN STD_LOGIC;
387 in_empty : IN STD_LOGIC;
426 out_wen : OUT STD_LOGIC;
388 out_wen : OUT STD_LOGIC;
427 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
389 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
428 out_full : OUT STD_LOGIC);
390 out_full : OUT STD_LOGIC);
429 END COMPONENT;
391 END COMPONENT;
430
392
431 END lpp_lfr_pkg;
393 END lpp_lfr_pkg;
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@@ -1,597 +1,576
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35 USE lpp.iir_filter.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37
37
38 LIBRARY techmap;
38 LIBRARY techmap;
39 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_waveform IS
41 ENTITY lpp_waveform IS
42
42
43 GENERIC (
43 GENERIC (
44 tech : INTEGER := inferred;
44 tech : INTEGER := inferred;
45 data_size : INTEGER := 96; --16*6
45 data_size : INTEGER := 96; --16*6
46 nb_data_by_buffer_size : INTEGER := 11;
46 nb_data_by_buffer_size : INTEGER := 11;
47 nb_word_by_buffer_size : INTEGER := 11;
47 nb_word_by_buffer_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
49 delta_vector_size : INTEGER := 20;
49 delta_vector_size : INTEGER := 20;
50 delta_vector_size_f0_2 : INTEGER := 3);
50 delta_vector_size_f0_2 : INTEGER := 3);
51
51
52 PORT (
52 PORT (
53 clk : IN STD_LOGIC;
53 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
55
55
56 ---- AMBA AHB Master Interface
56 ---- AMBA AHB Master Interface
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59
59
60 --config
60 --config
61 reg_run : IN STD_LOGIC;
61 reg_run : IN STD_LOGIC;
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68
68
69 enable_f0 : IN STD_LOGIC;
69 enable_f0 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
73
73
74 burst_f0 : IN STD_LOGIC;
74 burst_f0 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
77
77
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
79 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
83 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
83 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
84 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
84 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 -- INPUT
86 -- INPUT
87 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
87 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
88 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
89
89
90 --f0
90 --f0
91 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 data_f0_in_valid : IN STD_LOGIC;
92 data_f0_in_valid : IN STD_LOGIC;
93 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
93 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
94 --f1
94 --f1
95 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
95 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 data_f1_in_valid : IN STD_LOGIC;
96 data_f1_in_valid : IN STD_LOGIC;
97 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
97 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
98 --f2
98 --f2
99 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
99 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 data_f2_in_valid : IN STD_LOGIC;
100 data_f2_in_valid : IN STD_LOGIC;
101 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
101 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 --f3
102 --f3
103 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 data_f3_in_valid : IN STD_LOGIC;
104 data_f3_in_valid : IN STD_LOGIC;
105 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106
106
107 ---------------------------------------------------------------------------
107 ---------------------------------------------------------------------------
108 -- OUTPUT
108 -- DMA --------------------------------------------------------------------
109 --f0
110 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
111 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
112 data_f0_data_out_valid : OUT STD_LOGIC;
113 data_f0_data_out_valid_burst : OUT STD_LOGIC;
114 data_f0_data_out_ren : IN STD_LOGIC;
115 --f1
116 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 data_f1_data_out_valid : OUT STD_LOGIC;
119 data_f1_data_out_valid_burst : OUT STD_LOGIC;
120 data_f1_data_out_ren : IN STD_LOGIC;
121 --f2
122 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 data_f2_data_out_valid : OUT STD_LOGIC;
125 data_f2_data_out_valid_burst : OUT STD_LOGIC;
126 data_f2_data_out_ren : IN STD_LOGIC;
127 --f3
128 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 data_f3_data_out_valid : OUT STD_LOGIC;
131 data_f3_data_out_valid_burst : OUT STD_LOGIC;
132 data_f3_data_out_ren : IN STD_LOGIC;
133
134 ---------------------------------------------------------------------------
135 --
136 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
137
109
138
110 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
139 ----debug SNAPSHOT OUT
111 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
140 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
112 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 --debug_f0_data_valid : OUT STD_LOGIC;
113 dma_buffer_new : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
142 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
114 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
143 --debug_f1_data_valid : OUT STD_LOGIC;
115 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
144 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
116 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
145 --debug_f2_data_valid : OUT STD_LOGIC;
117 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
146 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 --debug_f3_data_valid : OUT STD_LOGIC;
148
149 ----debug FIFO IN
150 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
152 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
153 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
154 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
156 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
157 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
158
118
159 );
119 );
160
120
161 END lpp_waveform;
121 END lpp_waveform;
162
122
163 ARCHITECTURE beh OF lpp_waveform IS
123 ARCHITECTURE beh OF lpp_waveform IS
164 SIGNAL start_snapshot_f0 : STD_LOGIC;
124 SIGNAL start_snapshot_f0 : STD_LOGIC;
165 SIGNAL start_snapshot_f1 : STD_LOGIC;
125 SIGNAL start_snapshot_f1 : STD_LOGIC;
166 SIGNAL start_snapshot_f2 : STD_LOGIC;
126 SIGNAL start_snapshot_f2 : STD_LOGIC;
167
127
168 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
128 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
169 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
129 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
170 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
130 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
171 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
131 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
172
132
173 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
133 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
176 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
177
137
178 SIGNAL data_f0_out_valid : STD_LOGIC;
138 SIGNAL data_f0_out_valid : STD_LOGIC;
179 SIGNAL data_f1_out_valid : STD_LOGIC;
139 SIGNAL data_f1_out_valid : STD_LOGIC;
180 SIGNAL data_f2_out_valid : STD_LOGIC;
140 SIGNAL data_f2_out_valid : STD_LOGIC;
181 SIGNAL data_f3_out_valid : STD_LOGIC;
141 SIGNAL data_f3_out_valid : STD_LOGIC;
182 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
142 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
183 --
143 --
184 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
144 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
145 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
146 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
147 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
148 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
190 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
191 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
195 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
196 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
197 --
157 --
198 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
202 --
162 --
203 SIGNAL run : STD_LOGIC;
163 SIGNAL run : STD_LOGIC;
204 --
164 --
205 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
165 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
206 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
166 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
207 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
167 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
208 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
168 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
209 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
169 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
210 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
211 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 --
172 --
213
173
214 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
174 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
215 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
217 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
218 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
178 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
219
179
220 --
180 --
221
181
222 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
224
183
225
184
226 BEGIN -- beh
185 BEGIN -- beh
227
186
228
229 -----------------------------------------------------------------------------
230 -- DEBUG
231 -----------------------------------------------------------------------------
232 PROCESS (clk, rstn)
233 BEGIN -- PROCESS
234 IF rstn = '0' THEN -- asynchronous reset (active low)
235 observation_reg <= (OTHERS => '0');
236 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
237 observation_reg <= observation_reg_s;
238 END IF;
239 END PROCESS;
240 observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0;
241 observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
242 observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ;
243 observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0);
244 observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0);
245 observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
246 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
247
188
248 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
189 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
249 GENERIC MAP (
190 GENERIC MAP (
250 delta_vector_size => delta_vector_size,
191 delta_vector_size => delta_vector_size,
251 delta_vector_size_f0_2 => delta_vector_size_f0_2
192 delta_vector_size_f0_2 => delta_vector_size_f0_2
252 )
193 )
253 PORT MAP (
194 PORT MAP (
254 clk => clk,
195 clk => clk,
255 rstn => rstn,
196 rstn => rstn,
256 reg_run => reg_run,
197 reg_run => reg_run,
257 reg_start_date => reg_start_date,
198 reg_start_date => reg_start_date,
258 reg_delta_snapshot => reg_delta_snapshot,
199 reg_delta_snapshot => reg_delta_snapshot,
259 reg_delta_f0 => reg_delta_f0,
200 reg_delta_f0 => reg_delta_f0,
260 reg_delta_f0_2 => reg_delta_f0_2,
201 reg_delta_f0_2 => reg_delta_f0_2,
261 reg_delta_f1 => reg_delta_f1,
202 reg_delta_f1 => reg_delta_f1,
262 reg_delta_f2 => reg_delta_f2,
203 reg_delta_f2 => reg_delta_f2,
263 coarse_time => coarse_time(30 DOWNTO 0),
204 coarse_time => coarse_time(30 DOWNTO 0),
264 data_f0_valid => data_f0_in_valid,
205 data_f0_valid => data_f0_in_valid,
265 data_f2_valid => data_f2_in_valid,
206 data_f2_valid => data_f2_in_valid,
266 start_snapshot_f0 => start_snapshot_f0,
207 start_snapshot_f0 => start_snapshot_f0,
267 start_snapshot_f1 => start_snapshot_f1,
208 start_snapshot_f1 => start_snapshot_f1,
268 start_snapshot_f2 => start_snapshot_f2,
209 start_snapshot_f2 => start_snapshot_f2,
269 wfp_on => run);
210 wfp_on => run);
270
211
271 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
212 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
272 GENERIC MAP (
213 GENERIC MAP (
273 data_size => data_size,
214 data_size => data_size,
274 nb_snapshot_param_size => nb_snapshot_param_size)
215 nb_snapshot_param_size => nb_snapshot_param_size)
275 PORT MAP (
216 PORT MAP (
276 clk => clk,
217 clk => clk,
277 rstn => rstn,
218 rstn => rstn,
278 run => run,
219 run => run,
279 enable => enable_f0,
220 enable => enable_f0,
280 burst_enable => burst_f0,
221 burst_enable => burst_f0,
281 nb_snapshot_param => nb_snapshot_param,
222 nb_snapshot_param => nb_snapshot_param,
282 start_snapshot => start_snapshot_f0,
223 start_snapshot => start_snapshot_f0,
283 data_in => data_f0_in,
224 data_in => data_f0_in,
284 data_in_valid => data_f0_in_valid,
225 data_in_valid => data_f0_in_valid,
285 data_out => data_f0_out,
226 data_out => data_f0_out,
286 data_out_valid => data_f0_out_valid);
227 data_out_valid => data_f0_out_valid);
287
228
288 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
229 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
289
230
290 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
231 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
291 GENERIC MAP (
232 GENERIC MAP (
292 data_size => data_size,
233 data_size => data_size,
293 nb_snapshot_param_size => nb_snapshot_param_size+1)
234 nb_snapshot_param_size => nb_snapshot_param_size+1)
294 PORT MAP (
235 PORT MAP (
295 clk => clk,
236 clk => clk,
296 rstn => rstn,
237 rstn => rstn,
297 run => run,
238 run => run,
298 enable => enable_f1,
239 enable => enable_f1,
299 burst_enable => burst_f1,
240 burst_enable => burst_f1,
300 nb_snapshot_param => nb_snapshot_param_more_one,
241 nb_snapshot_param => nb_snapshot_param_more_one,
301 start_snapshot => start_snapshot_f1,
242 start_snapshot => start_snapshot_f1,
302 data_in => data_f1_in,
243 data_in => data_f1_in,
303 data_in_valid => data_f1_in_valid,
244 data_in_valid => data_f1_in_valid,
304 data_out => data_f1_out,
245 data_out => data_f1_out,
305 data_out_valid => data_f1_out_valid);
246 data_out_valid => data_f1_out_valid);
306
247
307 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
248 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
308 GENERIC MAP (
249 GENERIC MAP (
309 data_size => data_size,
250 data_size => data_size,
310 nb_snapshot_param_size => nb_snapshot_param_size+1)
251 nb_snapshot_param_size => nb_snapshot_param_size+1)
311 PORT MAP (
252 PORT MAP (
312 clk => clk,
253 clk => clk,
313 rstn => rstn,
254 rstn => rstn,
314 run => run,
255 run => run,
315 enable => enable_f2,
256 enable => enable_f2,
316 burst_enable => burst_f2,
257 burst_enable => burst_f2,
317 nb_snapshot_param => nb_snapshot_param_more_one,
258 nb_snapshot_param => nb_snapshot_param_more_one,
318 start_snapshot => start_snapshot_f2,
259 start_snapshot => start_snapshot_f2,
319 data_in => data_f2_in,
260 data_in => data_f2_in,
320 data_in_valid => data_f2_in_valid,
261 data_in_valid => data_f2_in_valid,
321 data_out => data_f2_out,
262 data_out => data_f2_out,
322 data_out_valid => data_f2_out_valid);
263 data_out_valid => data_f2_out_valid);
323
264
324 lpp_waveform_burst_f3 : lpp_waveform_burst
265 lpp_waveform_burst_f3 : lpp_waveform_burst
325 GENERIC MAP (
266 GENERIC MAP (
326 data_size => data_size)
267 data_size => data_size)
327 PORT MAP (
268 PORT MAP (
328 clk => clk,
269 clk => clk,
329 rstn => rstn,
270 rstn => rstn,
330 run => run,
271 run => run,
331 enable => enable_f3,
272 enable => enable_f3,
332 data_in => data_f3_in,
273 data_in => data_f3_in,
333 data_in_valid => data_f3_in_valid,
274 data_in_valid => data_f3_in_valid,
334 data_out => data_f3_out,
275 data_out => data_f3_out,
335 data_out_valid => data_f3_out_valid);
276 data_out_valid => data_f3_out_valid);
336
277
337 -----------------------------------------------------------------------------
278 -----------------------------------------------------------------------------
338 -- DEBUG -- SNAPSHOT OUT
279 -- DEBUG -- SNAPSHOT OUT
339 --debug_f0_data_valid <= data_f0_out_valid;
280 --debug_f0_data_valid <= data_f0_out_valid;
340 --debug_f0_data <= data_f0_out;
281 --debug_f0_data <= data_f0_out;
341 --debug_f1_data_valid <= data_f1_out_valid;
282 --debug_f1_data_valid <= data_f1_out_valid;
342 --debug_f1_data <= data_f1_out;
283 --debug_f1_data <= data_f1_out;
343 --debug_f2_data_valid <= data_f2_out_valid;
284 --debug_f2_data_valid <= data_f2_out_valid;
344 --debug_f2_data <= data_f2_out;
285 --debug_f2_data <= data_f2_out;
345 --debug_f3_data_valid <= data_f3_out_valid;
286 --debug_f3_data_valid <= data_f3_out_valid;
346 --debug_f3_data <= data_f3_out;
287 --debug_f3_data <= data_f3_out;
347 -----------------------------------------------------------------------------
288 -----------------------------------------------------------------------------
348
289
349 PROCESS (clk, rstn)
290 PROCESS (clk, rstn)
350 BEGIN -- PROCESS
291 BEGIN -- PROCESS
351 IF rstn = '0' THEN -- asynchronous reset (active low)
292 IF rstn = '0' THEN -- asynchronous reset (active low)
352 time_reg1 <= (OTHERS => '0');
293 time_reg1 <= (OTHERS => '0');
353 time_reg2 <= (OTHERS => '0');
294 time_reg2 <= (OTHERS => '0');
354 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
295 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
355 time_reg1 <= fine_time & coarse_time;
296 time_reg1 <= fine_time & coarse_time;
356 time_reg2 <= time_reg1;
297 time_reg2 <= time_reg1;
357 END IF;
298 END IF;
358 END PROCESS;
299 END PROCESS;
359
300
360 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
301 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
361 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
302 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
362 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
303 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
363 PORT MAP (
304 PORT MAP (
364 HCLK => clk,
305 HCLK => clk,
365 HRESETn => rstn,
306 HRESETn => rstn,
366 run => run,
307 run => run,
367 valid_in => valid_in(I),
308 valid_in => valid_in(I),
368 ack_in => valid_ack(I),
309 ack_in => valid_ack(I),
369 time_in => time_reg2, -- Todo
310 time_in => time_reg2, -- Todo
370 valid_out => valid_out(I),
311 valid_out => valid_out(I),
371 time_out => time_out(I), -- Todo
312 time_out => time_out(I), -- Todo
372 error => status_new_err(I));
313 error => status_new_err(I));
373 END GENERATE all_input_valid;
314 END GENERATE all_input_valid;
374
315
375 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
316 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
376 data_f0_out((16*6)-1 DOWNTO 16*5) &
317 data_f0_out((16*6)-1 DOWNTO 16*5) &
377 data_f0_out((16*3)-1 DOWNTO 16*2) &
318 data_f0_out((16*3)-1 DOWNTO 16*2) &
378 data_f0_out((16*4)-1 DOWNTO 16*3) &
319 data_f0_out((16*4)-1 DOWNTO 16*3) &
379 data_f0_out((16*1)-1 DOWNTO 16*0) &
320 data_f0_out((16*1)-1 DOWNTO 16*0) &
380 data_f0_out((16*2)-1 DOWNTO 16*1) ;
321 data_f0_out((16*2)-1 DOWNTO 16*1) ;
381
322
382 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
323 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
383 data_f1_out((16*6)-1 DOWNTO 16*5) &
324 data_f1_out((16*6)-1 DOWNTO 16*5) &
384 data_f1_out((16*3)-1 DOWNTO 16*2) &
325 data_f1_out((16*3)-1 DOWNTO 16*2) &
385 data_f1_out((16*4)-1 DOWNTO 16*3) &
326 data_f1_out((16*4)-1 DOWNTO 16*3) &
386 data_f1_out((16*1)-1 DOWNTO 16*0) &
327 data_f1_out((16*1)-1 DOWNTO 16*0) &
387 data_f1_out((16*2)-1 DOWNTO 16*1) ;
328 data_f1_out((16*2)-1 DOWNTO 16*1) ;
388
329
389 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
330 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
390 data_f2_out((16*6)-1 DOWNTO 16*5) &
331 data_f2_out((16*6)-1 DOWNTO 16*5) &
391 data_f2_out((16*3)-1 DOWNTO 16*2) &
332 data_f2_out((16*3)-1 DOWNTO 16*2) &
392 data_f2_out((16*4)-1 DOWNTO 16*3) &
333 data_f2_out((16*4)-1 DOWNTO 16*3) &
393 data_f2_out((16*1)-1 DOWNTO 16*0) &
334 data_f2_out((16*1)-1 DOWNTO 16*0) &
394 data_f2_out((16*2)-1 DOWNTO 16*1) ;
335 data_f2_out((16*2)-1 DOWNTO 16*1) ;
395
336
396 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
337 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
397 data_f3_out((16*6)-1 DOWNTO 16*5) &
338 data_f3_out((16*6)-1 DOWNTO 16*5) &
398 data_f3_out((16*3)-1 DOWNTO 16*2) &
339 data_f3_out((16*3)-1 DOWNTO 16*2) &
399 data_f3_out((16*4)-1 DOWNTO 16*3) &
340 data_f3_out((16*4)-1 DOWNTO 16*3) &
400 data_f3_out((16*1)-1 DOWNTO 16*0) &
341 data_f3_out((16*1)-1 DOWNTO 16*0) &
401 data_f3_out((16*2)-1 DOWNTO 16*1) ;
342 data_f3_out((16*2)-1 DOWNTO 16*1) ;
402
343
403 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
344 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
404 data_out(0, I) <= data_f0_out_swap(I);
345 data_out(0, I) <= data_f0_out_swap(I);
405 data_out(1, I) <= data_f1_out_swap(I);
346 data_out(1, I) <= data_f1_out_swap(I);
406 data_out(2, I) <= data_f2_out_swap(I);
347 data_out(2, I) <= data_f2_out_swap(I);
407 data_out(3, I) <= data_f3_out_swap(I);
348 data_out(3, I) <= data_f3_out_swap(I);
408 END GENERATE all_bit_of_data_out;
349 END GENERATE all_bit_of_data_out;
409
350
410 -----------------------------------------------------------------------------
351 -----------------------------------------------------------------------------
411 -- TODO : debug
352 -- TODO : debug
412 -----------------------------------------------------------------------------
353 -----------------------------------------------------------------------------
413 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
354 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
414 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
355 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
415 time_out_2(J, I) <= time_out(J)(I);
356 time_out_2(J, I) <= time_out(J)(I);
416 END GENERATE all_sample_of_time_out;
357 END GENERATE all_sample_of_time_out;
417 END GENERATE all_bit_of_time_out;
358 END GENERATE all_bit_of_time_out;
418
359
419 -- DEBUG --
360 -- DEBUG --
420 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
361 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
421 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
362 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
422 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
363 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
423 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
364 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
424
365
425 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
366 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
426 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
367 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
427 -- time_out_2(J, I) <= time_out_debug(J)(I);
368 -- time_out_2(J, I) <= time_out_debug(J)(I);
428 -- END GENERATE all_sample_of_time_out;
369 -- END GENERATE all_sample_of_time_out;
429 --END GENERATE all_bit_of_time_out;
370 --END GENERATE all_bit_of_time_out;
430 -- DEBUG --
371 -- DEBUG --
431
372
432 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
373 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
433 GENERIC MAP (tech => tech,
374 GENERIC MAP (tech => tech,
434 nb_data_by_buffer_size => nb_data_by_buffer_size)
375 nb_data_by_buffer_size => nb_data_by_buffer_size)
435 PORT MAP (
376 PORT MAP (
436 clk => clk,
377 clk => clk,
437 rstn => rstn,
378 rstn => rstn,
438 run => run,
379 run => run,
439 nb_data_by_buffer => nb_data_by_buffer,
380 nb_data_by_buffer => nb_data_by_buffer,
440 data_in_valid => valid_out,
381 data_in_valid => valid_out,
441 data_in_ack => valid_ack,
382 data_in_ack => valid_ack,
442 data_in => data_out,
383 data_in => data_out,
443 time_in => time_out_2,
384 time_in => time_out_2,
444
385
445 data_out => wdata,
386 data_out => wdata,
446 data_out_wen => data_wen,
387 data_out_wen => data_wen,
447 full_almost => full_almost,
388 full_almost => full_almost,
448 full => full);
389 full => full);
449
390
450 -----------------------------------------------------------------------------
391 -----------------------------------------------------------------------------
451 -- DEBUG -- SNAPSHOT IN
392 -- DEBUG -- SNAPSHOT IN
452 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
393 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
453 --debug_f0_data_fifo_in <= wdata;
394 --debug_f0_data_fifo_in <= wdata;
454 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
395 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
455 --debug_f1_data_fifo_in <= wdata;
396 --debug_f1_data_fifo_in <= wdata;
456 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
397 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
457 --debug_f2_data_fifo_in <= wdata;
398 --debug_f2_data_fifo_in <= wdata;
458 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
399 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
459 --debug_f3_data_fifo_in <= wdata;s
400 --debug_f3_data_fifo_in <= wdata;s
460 -----------------------------------------------------------------------------
401 -----------------------------------------------------------------------------
461
402
462
403
463 -- lpp_fifo_4_shared_1: lpp_fifo_4_shared
404 -- lpp_fifo_4_shared_1: lpp_fifo_4_shared
464 -- GENERIC MAP (
405 -- GENERIC MAP (
465 -- tech => tech,
406 -- tech => tech,
466 -- Mem_use => use_RAM,
407 -- Mem_use => use_RAM,
467 -- EMPTY_ALMOST_LIMIT => 16,
408 -- EMPTY_ALMOST_LIMIT => 16,
468 -- FULL_ALMOST_LIMIT => 5,
409 -- FULL_ALMOST_LIMIT => 5,
469 -- DataSz => 32,
410 -- DataSz => 32,
470 -- AddrSz => 7
411 -- AddrSz => 7
471 -- )
412 -- )
472 -- PORT MAP (
413 -- PORT MAP (
473 -- clk => clk,
414 -- clk => clk,
474 -- rstn => rstn,
415 -- rstn => rstn,
475 -- run => run,
416 -- run => run,
476 -- empty_almost => s_empty_almost,
417 -- empty_almost => s_empty_almost,
477 -- empty => s_empty,
418 -- empty => s_empty,
478 -- r_en => s_data_ren,
419 -- r_en => s_data_ren,
479 -- r_data => s_rdata,
420 -- r_data => s_rdata,
480 -- full_almost => full_almost,
421 -- full_almost => full_almost,
481 -- full => full,
422 -- full => full,
482 -- w_en => data_wen,
423 -- w_en => data_wen,
483 -- w_data => wdata);
424 -- w_data => wdata);
484
425
485 --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1
426 --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1
486 -- PORT MAP (
427 -- PORT MAP (
487 -- clk => clk,
428 -- clk => clk,
488 -- rstn => rstn,
429 -- rstn => rstn,
489 -- run => run,
430 -- run => run,
490 -- o_empty_almost => empty_almost,
431 -- o_empty_almost => empty_almost,
491 -- o_empty => empty,
432 -- o_empty => empty,
492
433
493 -- o_data_ren => data_ren,
434 -- o_data_ren => data_ren,
494 -- o_rdata_0 => data_f0_data_out,
435 -- o_rdata_0 => data_f0_data_out,
495 -- o_rdata_1 => data_f1_data_out,
436 -- o_rdata_1 => data_f1_data_out,
496 -- o_rdata_2 => data_f2_data_out,
437 -- o_rdata_2 => data_f2_data_out,
497 -- o_rdata_3 => data_f3_data_out,
438 -- o_rdata_3 => data_f3_data_out,
498
439
499 -- i_empty_almost => s_empty_almost,
440 -- i_empty_almost => s_empty_almost,
500 -- i_empty => s_empty,
441 -- i_empty => s_empty,
501 -- i_data_ren => s_data_ren,
442 -- i_data_ren => s_data_ren,
502 -- i_rdata => s_rdata);
443 -- i_rdata => s_rdata);
503
444
504 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
445 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
505 lpp_fifo_1: lpp_fifo
446 lpp_fifo_1: lpp_fifo
506 GENERIC MAP (
447 GENERIC MAP (
507 tech => tech,
448 tech => tech,
508 Mem_use => use_RAM,
449 Mem_use => use_RAM,
509 EMPTY_THRESHOLD_LIMIT => 16,
450 EMPTY_THRESHOLD_LIMIT => 15,
510 FULL_THRESHOLD_LIMIT => 5,
451 FULL_THRESHOLD_LIMIT => 3,
511 DataSz => 32,
452 DataSz => 32,
512 AddrSz => 7)
453 AddrSz => 7)
513 PORT MAP (
454 PORT MAP (
514 clk => clk,
455 clk => clk,
515 rstn => rstn,
456 rstn => rstn,
516 reUse => '0',
457 reUse => '0',
517 run => run,
458 run => run,
518 ren => data_ren(I),
459 ren => data_ren(I),
519 rdata => s_rdata_v((I+1)*32-1 downto I*32),
460 rdata => s_rdata_v((I+1)*32-1 downto I*32),
520 wen => data_wen(I),
461 wen => data_wen(I),
521 wdata => wdata,
462 wdata => wdata,
522 empty => empty(I),
463 empty => empty(I),
523 full => full(I),
464 full => full(I),
524 full_almost => OPEN,
465 full_almost => OPEN,
525 empty_threshold => empty_almost(I),
466 empty_threshold => empty_almost(I),
526 full_threshold => full_almost(I) );
467 full_threshold => full_almost(I) );
527
468
528 END GENERATE generate_all_fifo;
469 END GENERATE generate_all_fifo;
529
470
530
471
531 --empty <= s_empty;
472 ----empty <= s_empty;
532 --empty_almost <= s_empty_almost;
473 ----empty_almost <= s_empty_almost;
533 --s_data_ren <= data_ren;
474 ----s_data_ren <= data_ren;
534
475
535 data_f0_data_out <= s_rdata_v(31 downto 0);
476 --data_f0_data_out <= s_rdata_v(31 downto 0);
536 data_f1_data_out <= s_rdata_v(31+32 downto 0+32);
477 --data_f1_data_out <= s_rdata_v(31+32 downto 0+32);
537 data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2);
478 --data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2);
538 data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3);
479 --data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3);
480
481 --data_ren <= data_f3_data_out_ren &
482 -- data_f2_data_out_ren &
483 -- data_f1_data_out_ren &
484 -- data_f0_data_out_ren;
485
486 --lpp_waveform_gen_address_1 : lpp_waveform_genaddress
487 -- GENERIC MAP (
488 -- nb_data_by_buffer_size => nb_word_by_buffer_size)
489 -- PORT MAP (
490 -- clk => clk,
491 -- rstn => rstn,
492 -- run => run,
539
493
540 data_ren <= data_f3_data_out_ren &
494 -- -------------------------------------------------------------------------
541 data_f2_data_out_ren &
495 -- -- CONFIG
542 data_f1_data_out_ren &
496 -- -------------------------------------------------------------------------
543 data_f0_data_out_ren;
497 -- nb_data_by_buffer => nb_word_by_buffer,
544
545 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
546 GENERIC MAP (
547 nb_data_by_buffer_size => nb_word_by_buffer_size)
548 PORT MAP (
549 clk => clk,
550 rstn => rstn,
551 run => run,
552
498
553 -------------------------------------------------------------------------
499 -- addr_data_f0 => addr_data_f0,
554 -- CONFIG
500 -- addr_data_f1 => addr_data_f1,
555 -------------------------------------------------------------------------
501 -- addr_data_f2 => addr_data_f2,
556 nb_data_by_buffer => nb_word_by_buffer,
502 -- addr_data_f3 => addr_data_f3,
503 -- -------------------------------------------------------------------------
504 -- -- CTRL
505 -- -------------------------------------------------------------------------
506 -- -- IN
507 -- empty => empty,
508 -- empty_almost => empty_almost,
509 -- data_ren => data_ren,
510
511 -- -------------------------------------------------------------------------
512 -- -- STATUS
513 -- -------------------------------------------------------------------------
514 -- status_full => status_full_s,
515 -- status_full_ack => status_full_ack,
516 -- status_full_err => status_full_err,
557
517
558 addr_data_f0 => addr_data_f0,
518 -- -------------------------------------------------------------------------
559 addr_data_f1 => addr_data_f1,
519 -- -- ADDR DATA OUT
560 addr_data_f2 => addr_data_f2,
520 -- -------------------------------------------------------------------------
561 addr_data_f3 => addr_data_f3,
521 -- data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
562 -------------------------------------------------------------------------
522 -- data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
563 -- CTRL
523 -- data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
564 -------------------------------------------------------------------------
524 -- data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
565 -- IN
566 empty => empty,
567 empty_almost => empty_almost,
568 data_ren => data_ren,
569
525
570 -------------------------------------------------------------------------
526 -- data_f0_data_out_valid => data_f0_data_out_valid,
571 -- STATUS
527 -- data_f1_data_out_valid => data_f1_data_out_valid,
572 -------------------------------------------------------------------------
528 -- data_f2_data_out_valid => data_f2_data_out_valid,
573 status_full => status_full_s,
529 -- data_f3_data_out_valid => data_f3_data_out_valid,
574 status_full_ack => status_full_ack,
530
575 status_full_err => status_full_err,
531 -- data_f0_addr_out => data_f0_addr_out,
532 -- data_f1_addr_out => data_f1_addr_out,
533 -- data_f2_addr_out => data_f2_addr_out,
534 -- data_f3_addr_out => data_f3_addr_out
535 -- );
536 --status_full <= status_full_s;
537
576
538
577 -------------------------------------------------------------------------
539 -----------------------------------------------------------------------------
578 -- ADDR DATA OUT
540 --
579 -------------------------------------------------------------------------
541 -----------------------------------------------------------------------------
580 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
542
581 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
543 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
582 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
544 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
583 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
545 PORT MAP (
546 clk => clk,
547 rstn => rstn,
548 run => run,
549
550 fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
551
552 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
553 fifo_empty => empty(I),
554 fifo_empty_threshold => empty_almost(I),
555 fifo_ren => data_ren(I),
556
557 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
558 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
559 dma_fifo_ren => dma_fifo_ren(I),
560 dma_buffer_new => dma_buffer_new(I),
561 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
562 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
563 dma_buffer_full => dma_buffer_full(I),
564 dma_buffer_full_err => dma_buffer_full_err(I),
565
566 status_buffer_ready => status_buffer_ready(I), -- TODO
567 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
568 length_buffer => length_buffer(26*(I+1)-1 DOWNTO 26*I), -- TODO
569 ready_buffer => ready_buffer(I), -- TODO
570 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
571 error_buffer_full => error_buffer_full(I)); -- TODO
572
573 END GENERATE all_channel;
584
574
585 data_f0_data_out_valid => data_f0_data_out_valid,
586 data_f1_data_out_valid => data_f1_data_out_valid,
587 data_f2_data_out_valid => data_f2_data_out_valid,
588 data_f3_data_out_valid => data_f3_data_out_valid,
589
590 data_f0_addr_out => data_f0_addr_out,
591 data_f1_addr_out => data_f1_addr_out,
592 data_f2_addr_out => data_f2_addr_out,
593 data_f3_addr_out => data_f3_addr_out
594 );
595 status_full <= status_full_s;
596
575
597 END beh;
576 END beh;
Show file before | Show file after | Hide comments
@@ -1,376 +1,402
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25
25
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
31
31
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34
34
35 PACKAGE lpp_waveform_pkg IS
35 PACKAGE lpp_waveform_pkg IS
36
36
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
38
38
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
40
40
41 -----------------------------------------------------------------------------
41 -----------------------------------------------------------------------------
42 -- SNAPSHOT
42 -- SNAPSHOT
43 -----------------------------------------------------------------------------
43 -----------------------------------------------------------------------------
44
44
45 COMPONENT lpp_waveform_snapshot
45 COMPONENT lpp_waveform_snapshot
46 GENERIC (
46 GENERIC (
47 data_size : INTEGER;
47 data_size : INTEGER;
48 nb_snapshot_param_size : INTEGER);
48 nb_snapshot_param_size : INTEGER);
49 PORT (
49 PORT (
50 clk : IN STD_LOGIC;
50 clk : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
52 run : IN STD_LOGIC;
52 run : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 start_snapshot : IN STD_LOGIC;
56 start_snapshot : IN STD_LOGIC;
57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
58 data_in_valid : IN STD_LOGIC;
58 data_in_valid : IN STD_LOGIC;
59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
60 data_out_valid : OUT STD_LOGIC);
60 data_out_valid : OUT STD_LOGIC);
61 END COMPONENT;
61 END COMPONENT;
62
62
63 COMPONENT lpp_waveform_burst
63 COMPONENT lpp_waveform_burst
64 GENERIC (
64 GENERIC (
65 data_size : INTEGER);
65 data_size : INTEGER);
66 PORT (
66 PORT (
67 clk : IN STD_LOGIC;
67 clk : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
69 run : IN STD_LOGIC;
69 run : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
72 data_in_valid : IN STD_LOGIC;
72 data_in_valid : IN STD_LOGIC;
73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
74 data_out_valid : OUT STD_LOGIC);
74 data_out_valid : OUT STD_LOGIC);
75 END COMPONENT;
75 END COMPONENT;
76
76
77 COMPONENT lpp_waveform_snapshot_controler
77 COMPONENT lpp_waveform_snapshot_controler
78 GENERIC (
78 GENERIC (
79 delta_vector_size : INTEGER;
79 delta_vector_size : INTEGER;
80 delta_vector_size_f0_2 : INTEGER);
80 delta_vector_size_f0_2 : INTEGER);
81 PORT (
81 PORT (
82 clk : IN STD_LOGIC;
82 clk : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
84 reg_run : IN STD_LOGIC;
84 reg_run : IN STD_LOGIC;
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
92 data_f0_valid : IN STD_LOGIC;
92 data_f0_valid : IN STD_LOGIC;
93 data_f2_valid : IN STD_LOGIC;
93 data_f2_valid : IN STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
97 wfp_on : OUT STD_LOGIC);
97 wfp_on : OUT STD_LOGIC);
98 END COMPONENT;
98 END COMPONENT;
99
99
100 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
101 --
101 --
102 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
103 COMPONENT lpp_waveform
103 COMPONENT lpp_waveform
104 GENERIC (
104 GENERIC (
105 tech : INTEGER;
105 tech : INTEGER;
106 data_size : INTEGER;
106 data_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
109 nb_snapshot_param_size : INTEGER;
109 nb_snapshot_param_size : INTEGER;
110 delta_vector_size : INTEGER;
110 delta_vector_size : INTEGER;
111 delta_vector_size_f0_2 : INTEGER);
111 delta_vector_size_f0_2 : INTEGER);
112 PORT (
112 PORT (
113 clk : IN STD_LOGIC;
113 clk : IN STD_LOGIC;
114 rstn : IN STD_LOGIC;
114 rstn : IN STD_LOGIC;
115 reg_run : IN STD_LOGIC;
115 reg_run : IN STD_LOGIC;
116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 enable_f0 : IN STD_LOGIC;
122 enable_f0 : IN STD_LOGIC;
123 enable_f1 : IN STD_LOGIC;
123 enable_f1 : IN STD_LOGIC;
124 enable_f2 : IN STD_LOGIC;
124 enable_f2 : IN STD_LOGIC;
125 enable_f3 : IN STD_LOGIC;
125 enable_f3 : IN STD_LOGIC;
126 burst_f0 : IN STD_LOGIC;
126 burst_f0 : IN STD_LOGIC;
127 burst_f1 : IN STD_LOGIC;
127 burst_f1 : IN STD_LOGIC;
128 burst_f2 : IN STD_LOGIC;
128 burst_f2 : IN STD_LOGIC;
129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 data_f0_in_valid : IN STD_LOGIC;
139 data_f0_in_valid : IN STD_LOGIC;
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
142 data_f1_in_valid : IN STD_LOGIC;
142 data_f1_in_valid : IN STD_LOGIC;
143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 data_f2_in_valid : IN STD_LOGIC;
145 data_f2_in_valid : IN STD_LOGIC;
146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 data_f3_in_valid : IN STD_LOGIC;
148 data_f3_in_valid : IN STD_LOGIC;
149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 data_f0_data_out_valid : OUT STD_LOGIC;
152 data_f0_data_out_valid : OUT STD_LOGIC;
153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
154 data_f0_data_out_ren : IN STD_LOGIC;
154 data_f0_data_out_ren : IN STD_LOGIC;
155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
157 data_f1_data_out_valid : OUT STD_LOGIC;
157 data_f1_data_out_valid : OUT STD_LOGIC;
158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
159 data_f1_data_out_ren : IN STD_LOGIC;
159 data_f1_data_out_ren : IN STD_LOGIC;
160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 data_f2_data_out_valid : OUT STD_LOGIC;
162 data_f2_data_out_valid : OUT STD_LOGIC;
163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
164 data_f2_data_out_ren : IN STD_LOGIC;
164 data_f2_data_out_ren : IN STD_LOGIC;
165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
167 data_f3_data_out_valid : OUT STD_LOGIC;
167 data_f3_data_out_valid : OUT STD_LOGIC;
168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
169 data_f3_data_out_ren : IN STD_LOGIC;
169 data_f3_data_out_ren : IN STD_LOGIC;
170
170
171 --debug
171 --debug
172 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
172 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
173 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 --debug_f0_data_valid : OUT STD_LOGIC;
174 --debug_f0_data_valid : OUT STD_LOGIC;
175 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
176 --debug_f1_data_valid : OUT STD_LOGIC;
176 --debug_f1_data_valid : OUT STD_LOGIC;
177 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
177 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
178 --debug_f2_data_valid : OUT STD_LOGIC;
178 --debug_f2_data_valid : OUT STD_LOGIC;
179 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
179 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
180 --debug_f3_data_valid : OUT STD_LOGIC;
180 --debug_f3_data_valid : OUT STD_LOGIC;
181
181
182 ----debug FIFO IN
182 ----debug FIFO IN
183 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
183 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
184 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
184 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
185 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
186 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
187 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
188 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
188 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
189 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
190 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
191 );
191 );
192 END COMPONENT;
192 END COMPONENT;
193
193
194 COMPONENT lpp_waveform_dma_genvalid
194 COMPONENT lpp_waveform_dma_genvalid
195 PORT (
195 PORT (
196 HCLK : IN STD_LOGIC;
196 HCLK : IN STD_LOGIC;
197 HRESETn : IN STD_LOGIC;
197 HRESETn : IN STD_LOGIC;
198 run : IN STD_LOGIC;
198 run : IN STD_LOGIC;
199 valid_in : IN STD_LOGIC;
199 valid_in : IN STD_LOGIC;
200 ack_in : IN STD_LOGIC;
200 ack_in : IN STD_LOGIC;
201 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
201 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
202 valid_out : OUT STD_LOGIC;
202 valid_out : OUT STD_LOGIC;
203 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
203 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
204 error : OUT STD_LOGIC);
204 error : OUT STD_LOGIC);
205 END COMPONENT;
205 END COMPONENT;
206
206
207 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
208 -- FIFO
208 -- FIFO
209 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
210 COMPONENT lpp_waveform_fifo_ctrl
210 COMPONENT lpp_waveform_fifo_ctrl
211 GENERIC (
211 GENERIC (
212 offset : INTEGER;
212 offset : INTEGER;
213 length : INTEGER);
213 length : INTEGER);
214 PORT (
214 PORT (
215 clk : IN STD_LOGIC;
215 clk : IN STD_LOGIC;
216 rstn : IN STD_LOGIC;
216 rstn : IN STD_LOGIC;
217 run : IN STD_LOGIC;
217 run : IN STD_LOGIC;
218 ren : IN STD_LOGIC;
218 ren : IN STD_LOGIC;
219 wen : IN STD_LOGIC;
219 wen : IN STD_LOGIC;
220 mem_re : OUT STD_LOGIC;
220 mem_re : OUT STD_LOGIC;
221 mem_we : OUT STD_LOGIC;
221 mem_we : OUT STD_LOGIC;
222 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
222 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
223 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
223 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
224 empty_almost : OUT STD_LOGIC;
224 empty_almost : OUT STD_LOGIC;
225 empty : OUT STD_LOGIC;
225 empty : OUT STD_LOGIC;
226 full_almost : OUT STD_LOGIC;
226 full_almost : OUT STD_LOGIC;
227 full : OUT STD_LOGIC);
227 full : OUT STD_LOGIC);
228 END COMPONENT;
228 END COMPONENT;
229
229
230 COMPONENT lpp_waveform_fifo_arbiter
230 COMPONENT lpp_waveform_fifo_arbiter
231 GENERIC (
231 GENERIC (
232 tech : INTEGER;
232 tech : INTEGER;
233 nb_data_by_buffer_size : INTEGER);
233 nb_data_by_buffer_size : INTEGER);
234 PORT (
234 PORT (
235 clk : IN STD_LOGIC;
235 clk : IN STD_LOGIC;
236 rstn : IN STD_LOGIC;
236 rstn : IN STD_LOGIC;
237 run : IN STD_LOGIC;
237 run : IN STD_LOGIC;
238 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
238 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
239 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
239 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
240 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
240 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
241 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
241 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
242 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
242 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
243 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
243 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
244 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
244 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
245 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
245 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
246 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
246 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
247 END COMPONENT;
247 END COMPONENT;
248
248
249 COMPONENT lpp_waveform_fifo
249 COMPONENT lpp_waveform_fifo
250 GENERIC (
250 GENERIC (
251 tech : INTEGER);
251 tech : INTEGER);
252 PORT (
252 PORT (
253 clk : IN STD_LOGIC;
253 clk : IN STD_LOGIC;
254 rstn : IN STD_LOGIC;
254 rstn : IN STD_LOGIC;
255 run : IN STD_LOGIC;
255 run : IN STD_LOGIC;
256 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
256 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
257 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
257 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
258 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
258 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
259 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
259 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
260 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
260 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
261 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
261 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
262 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
262 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
263 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
263 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
264 END COMPONENT;
264 END COMPONENT;
265
265
266 COMPONENT lpp_waveform_fifo_headreg
266 COMPONENT lpp_waveform_fifo_headreg
267 GENERIC (
267 GENERIC (
268 tech : INTEGER);
268 tech : INTEGER);
269 PORT (
269 PORT (
270 clk : IN STD_LOGIC;
270 clk : IN STD_LOGIC;
271 rstn : IN STD_LOGIC;
271 rstn : IN STD_LOGIC;
272 run : IN STD_LOGIC;
272 run : IN STD_LOGIC;
273 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
273 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
274 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
274 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
275 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
275 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
276 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
276 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
277 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
277 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
278 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
278 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
279 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
279 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
280 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
280 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
281 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
281 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
282 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
282 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
283 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
283 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
284 END COMPONENT;
284 END COMPONENT;
285
285
286 COMPONENT lpp_waveform_fifo_latencyCorrection
286 COMPONENT lpp_waveform_fifo_latencyCorrection
287 GENERIC (
287 GENERIC (
288 tech : INTEGER);
288 tech : INTEGER);
289 PORT (
289 PORT (
290 clk : IN STD_LOGIC;
290 clk : IN STD_LOGIC;
291 rstn : IN STD_LOGIC;
291 rstn : IN STD_LOGIC;
292 run : IN STD_LOGIC;
292 run : IN STD_LOGIC;
293 empty_almost : OUT STD_LOGIC;
293 empty_almost : OUT STD_LOGIC;
294 empty : OUT STD_LOGIC;
294 empty : OUT STD_LOGIC;
295 data_ren : IN STD_LOGIC;
295 data_ren : IN STD_LOGIC;
296 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
296 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
297 empty_almost_fifo : IN STD_LOGIC;
297 empty_almost_fifo : IN STD_LOGIC;
298 empty_fifo : IN STD_LOGIC;
298 empty_fifo : IN STD_LOGIC;
299 data_ren_fifo : OUT STD_LOGIC;
299 data_ren_fifo : OUT STD_LOGIC;
300 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
300 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
301 END COMPONENT;
301 END COMPONENT;
302
302
303 COMPONENT lpp_waveform_fifo_withoutLatency
303 COMPONENT lpp_waveform_fifo_withoutLatency
304 GENERIC (
304 GENERIC (
305 tech : INTEGER);
305 tech : INTEGER);
306 PORT (
306 PORT (
307 clk : IN STD_LOGIC;
307 clk : IN STD_LOGIC;
308 rstn : IN STD_LOGIC;
308 rstn : IN STD_LOGIC;
309 run : IN STD_LOGIC;
309 run : IN STD_LOGIC;
310 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
310 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
311 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
311 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
312 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
312 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
313 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
313 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
314 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
314 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
315 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
315 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
316 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
316 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
317 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
317 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
318 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
318 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
319 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
319 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
320 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
320 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
321 END COMPONENT;
321 END COMPONENT;
322
322
323 -----------------------------------------------------------------------------
323 -----------------------------------------------------------------------------
324 -- GEN ADDRESS
324 -- GEN ADDRESS
325 -----------------------------------------------------------------------------
325 -----------------------------------------------------------------------------
326 COMPONENT lpp_waveform_genaddress
326 COMPONENT lpp_waveform_genaddress
327 GENERIC (
327 GENERIC (
328 nb_data_by_buffer_size : INTEGER);
328 nb_data_by_buffer_size : INTEGER);
329 PORT (
329 PORT (
330 clk : IN STD_LOGIC;
330 clk : IN STD_LOGIC;
331 rstn : IN STD_LOGIC;
331 rstn : IN STD_LOGIC;
332 run : IN STD_LOGIC;
332 run : IN STD_LOGIC;
333 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
333 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
334 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
334 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
335 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
335 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
336 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
336 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
337 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
337 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
338 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
338 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
339 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
339 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
340 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
340 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
341 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
341 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
342 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
342 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
343 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
343 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
344 data_f0_data_out_valid_burst : OUT STD_LOGIC;
344 data_f0_data_out_valid_burst : OUT STD_LOGIC;
345 data_f1_data_out_valid_burst : OUT STD_LOGIC;
345 data_f1_data_out_valid_burst : OUT STD_LOGIC;
346 data_f2_data_out_valid_burst : OUT STD_LOGIC;
346 data_f2_data_out_valid_burst : OUT STD_LOGIC;
347 data_f3_data_out_valid_burst : OUT STD_LOGIC;
347 data_f3_data_out_valid_burst : OUT STD_LOGIC;
348 data_f0_data_out_valid : OUT STD_LOGIC;
348 data_f0_data_out_valid : OUT STD_LOGIC;
349 data_f1_data_out_valid : OUT STD_LOGIC;
349 data_f1_data_out_valid : OUT STD_LOGIC;
350 data_f2_data_out_valid : OUT STD_LOGIC;
350 data_f2_data_out_valid : OUT STD_LOGIC;
351 data_f3_data_out_valid : OUT STD_LOGIC;
351 data_f3_data_out_valid : OUT STD_LOGIC;
352 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
352 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
355 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
355 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
356 END COMPONENT;
356 END COMPONENT;
357
357
358 -----------------------------------------------------------------------------
358 -----------------------------------------------------------------------------
359 -- lpp_waveform_fifo_arbiter_reg
359 -- lpp_waveform_fifo_arbiter_reg
360 -----------------------------------------------------------------------------
360 -----------------------------------------------------------------------------
361 COMPONENT lpp_waveform_fifo_arbiter_reg
361 COMPONENT lpp_waveform_fifo_arbiter_reg
362 GENERIC (
362 GENERIC (
363 data_size : INTEGER;
363 data_size : INTEGER;
364 data_nb : INTEGER);
364 data_nb : INTEGER);
365 PORT (
365 PORT (
366 clk : IN STD_LOGIC;
366 clk : IN STD_LOGIC;
367 rstn : IN STD_LOGIC;
367 rstn : IN STD_LOGIC;
368 run : IN STD_LOGIC;
368 run : IN STD_LOGIC;
369 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
369 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
370 enable : IN STD_LOGIC;
370 enable : IN STD_LOGIC;
371 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
371 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
372 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
372 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
373 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
373 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
374 END COMPONENT;
374 END COMPONENT;
375
376 COMPONENT lpp_waveform_fsmdma
377 PORT (
378 clk : IN STD_ULOGIC;
379 rstn : IN STD_ULOGIC;
380 run : IN STD_LOGIC;
381 fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
382 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
383 fifo_empty : IN STD_LOGIC;
384 fifo_empty_threshold : IN STD_LOGIC;
385 fifo_ren : OUT STD_LOGIC;
386 dma_fifo_valid_burst : OUT STD_LOGIC;
387 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
388 dma_fifo_ren : IN STD_LOGIC;
389 dma_buffer_new : OUT STD_LOGIC;
390 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
391 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
392 dma_buffer_full : IN STD_LOGIC;
393 dma_buffer_full_err : IN STD_LOGIC;
394 status_buffer_ready : IN STD_LOGIC;
395 addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
396 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
397 ready_buffer : OUT STD_LOGIC;
398 buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
399 error_buffer_full : OUT STD_LOGIC);
400 END COMPONENT;
375
401
376 END lpp_waveform_pkg;
402 END lpp_waveform_pkg;
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