diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -428,7 +428,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00011B") -- aa.bb.cc version + top_lfr_version => X"00011C") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, diff --git a/lib/lpp/lpp_dma/DMA_SubSystem.vhd b/lib/lpp/lpp_dma/DMA_SubSystem.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_dma/DMA_SubSystem.vhd @@ -0,0 +1,201 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.general_purpose.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY DMA_SubSystem IS + + GENERIC ( + hindex : INTEGER := 2); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + -- AHB + ahbi : IN AHB_Mst_In_Type; + ahbo : OUT AHB_Mst_Out_Type; + --------------------------------------------------------------------------- + fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + --------------------------------------------------------------------------- + buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); + buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + --------------------------------------------------------------------------- + grant_error : OUT STD_LOGIC -- + + ); + +END DMA_SubSystem; + + +ARCHITECTURE beh OF DMA_SubSystem IS + + COMPONENT DMA_SubSystem_GestionBuffer + GENERIC ( + BUFFER_ADDR_SIZE : INTEGER; + BUFFER_LENGTH_SIZE : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + buffer_new : IN STD_LOGIC; + buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); + buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); + buffer_full : OUT STD_LOGIC; + buffer_full_err : OUT STD_LOGIC; + burst_send : IN STD_LOGIC; + burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT DMA_SubSystem_Arbiter + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); + END COMPONENT; + + COMPONENT DMA_SubSystem_MUX + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + dma_send : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; + grant_error : OUT STD_LOGIC); + END COMPONENT; + + ----------------------------------------------------------------------------- + SIGNAL dma_send : STD_LOGIC; + SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) + SIGNAL dma_done : STD_LOGIC; + SIGNAL dma_ren : STD_LOGIC; + SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); -- + + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- DMA + ----------------------------------------------------------------------------- + lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst + GENERIC MAP ( + tech => inferred, + hindex => hindex) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + run => run, + AHB_Master_In => ahbi, + AHB_Master_Out => ahbo, + + send => dma_send, + valid_burst => dma_valid_burst, + done => dma_done, + ren => dma_ren, + address => dma_address, + data => dma_data); + + + ----------------------------------------------------------------------------- + -- RoundRobin Selection Channel For DMA + ----------------------------------------------------------------------------- + DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + data_burst_valid => fifo_burst_valid, + data_burst_valid_grant => fifo_grant); + + + ----------------------------------------------------------------------------- + -- Mux between the channel from Waveform Picker and Spectral Matrix + ----------------------------------------------------------------------------- + DMA_SubSystem_MUX_1: DMA_SubSystem_MUX + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + fifo_grant => fifo_grant, + fifo_data => fifo_data, + fifo_address => fifo_address, + fifo_ren => fifo_ren, + fifo_burst_done => burst_send, + + dma_send => dma_send, + dma_valid_burst => dma_valid_burst, + dma_address => dma_address, + dma_data => dma_data, + dma_ren => dma_ren, + dma_done => dma_done, + + grant_error => grant_error); + + + ----------------------------------------------------------------------------- + -- GEN ADDR + ----------------------------------------------------------------------------- + all_buffer : FOR I IN 4 DOWNTO 0 GENERATE + DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer + GENERIC MAP ( + BUFFER_ADDR_SIZE => 32, + BUFFER_LENGTH_SIZE => 26) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + buffer_new => buffer_new(I), + buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32), + buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26), + buffer_full => buffer_full(I), + buffer_full_err => buffer_full_err(I), + + burst_send => burst_send(I), + burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I) + ); + END GENERATE all_buffer; + + + +END beh; diff --git a/lib/lpp/lpp_dma/DMA_SubSystem_Arbiter.vhd b/lib/lpp/lpp_dma/DMA_SubSystem_Arbiter.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_dma/DMA_SubSystem_Arbiter.vhd @@ -0,0 +1,94 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.general_purpose.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY DMA_SubSystem_Arbiter IS + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + -- + data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) + ); + +END DMA_SubSystem_Arbiter; + + +ARCHITECTURE beh OF DMA_SubSystem_Arbiter IS + + SIGNAL data_burst_valid_r : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); + +BEGIN -- beh + ----------------------------------------------------------------------------- + -- REG the burst valid signal + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_burst_valid_r <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF run = '1' THEN + data_burst_valid_r <= data_burst_valid; + ELSE + data_burst_valid_r <= (OTHERS => '0'); + END IF; + + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- ARBITER Between all the "WAVEFORM_PICKER" channel + ----------------------------------------------------------------------------- + RR_Arbiter_4_1 : RR_Arbiter_4 + PORT MAP ( + clk => clk, + rstn => rstn, + in_valid => data_burst_valid_r(3 DOWNTO 0), + out_grant => dma_rr_grant_s); + + dma_rr_valid_ms(0) <= data_burst_valid_r(4);--data_ms_valid OR data_ms_valid_burst; + dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; + dma_rr_valid_ms(2) <= '0'; + dma_rr_valid_ms(3) <= '0'; + + ----------------------------------------------------------------------------- + -- ARBITER Between all the "WAVEFORM_PICKER" and "SPECTRAL MATRIX" + ----------------------------------------------------------------------------- + + RR_Arbiter_4_2 : RR_Arbiter_4 + PORT MAP ( + clk => clk, + rstn => rstn, + in_valid => dma_rr_valid_ms, + out_grant => dma_rr_grant_ms); + + data_burst_valid_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; + + + +END beh; diff --git a/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd b/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd @@ -0,0 +1,76 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY DMA_SubSystem_GestionBuffer IS + GENERIC ( + BUFFER_ADDR_SIZE : INTEGER := 32; + BUFFER_LENGTH_SIZE : INTEGER := 26); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + -- + buffer_new : IN STD_LOGIC; + buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); + buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); --in 64B + buffer_full : OUT STD_LOGIC; + buffer_full_err : OUT STD_LOGIC; + -- + burst_send : IN STD_LOGIC; + burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0) + ); +END DMA_SubSystem_GestionBuffer; + + +ARCHITECTURE beh OF DMA_SubSystem_GestionBuffer IS + + TYPE state_DMA_GestionBuffer IS (IDLE, ON_GOING); + SIGNAL state : state_DMA_GestionBuffer; + + SIGNAL burst_send_counter : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); + SIGNAL burst_send_counter_add1 : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); + SIGNAL addr_shift : STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); + +BEGIN + addr_shift <= burst_send_counter & "000000"; + burst_addr <= STD_LOGIC_VECTOR(unsigned(buffer_addr) + unsigned(addr_shift)); + + burst_send_counter_add1 <= STD_LOGIC_VECTOR(unsigned(burst_send_counter) + 1); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + burst_send_counter <= (OTHERS => '0'); + state <= IDLE; + buffer_full <= '0'; + buffer_full_err <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + CASE state IS + WHEN IDLE => + burst_send_counter <= (OTHERS => '0'); + buffer_full_err <= burst_send; + buffer_full <= '0'; + IF buffer_new = '1' THEN + state <= ON_GOING; + END IF; + + WHEN ON_GOING => + buffer_full_err <= '0'; + buffer_full <= '0'; + IF burst_send = '1' THEN + IF burst_send_counter_add1 < buffer_length THEN + burst_send_counter <= burst_send_counter_add1; + ELSE + buffer_full <= '1'; + state <= IDLE; + END IF; + END IF; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_dma/DMA_SubSystem_MUX.vhd b/lib/lpp/lpp_dma/DMA_SubSystem_MUX.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_dma/DMA_SubSystem_MUX.vhd @@ -0,0 +1,118 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.general_purpose.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY DMA_SubSystem_MUX IS + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + -- + fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); -- + fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); -- + fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- + fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + -- + dma_send : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; -- + dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + dma_ren : IN STD_LOGIC; -- + dma_done : IN STD_LOGIC; -- + -- + grant_error : OUT STD_LOGIC -- + ); + +END DMA_SubSystem_MUX; + +ARCHITECTURE beh OF DMA_SubSystem_MUX IS + SIGNAL channel_ongoing : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL one_grant : STD_LOGIC; + SIGNAL more_than_one_grant : STD_LOGIC; + +BEGIN + + one_grant <= '0' WHEN fifo_grant = "00000" ELSE '1'; + more_than_one_grant <= '0' WHEN fifo_grant = "00000" OR + fifo_grant = "00001" OR + fifo_grant = "00010" OR + fifo_grant = "00100" OR + fifo_grant = "01000" OR + fifo_grant = "10000" ELSE '1'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + channel_ongoing <= (OTHERS => '0'); + fifo_burst_done <= (OTHERS => '0'); + dma_send <= '0'; + dma_valid_burst <= '0'; + grant_error <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + grant_error <= '0'; + IF run = '1' THEN + IF dma_done = '1' THEN + fifo_burst_done <= channel_ongoing; + ELSE + fifo_burst_done <= (OTHERS => '0'); + END IF; + + IF channel_ongoing = "00000" OR dma_done = '1' THEN + channel_ongoing <= fifo_grant; + grant_error <= more_than_one_grant; + dma_valid_burst <= one_grant; + dma_send <= one_grant; + ELSE + dma_send <= '0'; + END IF; + + ELSE + channel_ongoing <= (OTHERS => '0'); + fifo_burst_done <= (OTHERS => '0'); + dma_send <= '0'; + dma_valid_burst <= '0'; + END IF; + END IF; + END PROCESS; + + ------------------------------------------------------------------------- + + all_channel : FOR I IN 4 DOWNTO 0 GENERATE + fifo_ren(I) <= dma_ren WHEN channel_ongoing(I) = '1' ELSE '1'; + END GENERATE all_channel; + + dma_data <= fifo_data(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE + fifo_data(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE + fifo_data(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE + fifo_data(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE + fifo_data(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE + + dma_address <= fifo_address(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE + fifo_address(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE + fifo_address(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE + fifo_address(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE + fifo_address(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE + +END beh; diff --git a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd --- a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd @@ -216,5 +216,74 @@ PACKAGE lpp_dma_pkg IS data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); debug_dmaout_okay : OUT STD_LOGIC); END COMPONENT; + + + ----------------------------------------------------------------------------- + -- DMA_SubSystem + ----------------------------------------------------------------------------- + COMPONENT DMA_SubSystem + GENERIC ( + hindex : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + ahbi : IN AHB_Mst_In_Type; + ahbo : OUT AHB_Mst_Out_Type; + fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); + buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + grant_error : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT DMA_SubSystem_GestionBuffer + GENERIC ( + BUFFER_ADDR_SIZE : INTEGER; + BUFFER_LENGTH_SIZE : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + buffer_new : IN STD_LOGIC; + buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); + buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); + buffer_full : OUT STD_LOGIC; + buffer_full_err : OUT STD_LOGIC; + burst_send : IN STD_LOGIC; + burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT DMA_SubSystem_Arbiter + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); + END COMPONENT; + + COMPONENT DMA_SubSystem_MUX + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + dma_send : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; + grant_error : OUT STD_LOGIC); + END COMPONENT; END; diff --git a/lib/lpp/lpp_dma/vhdlsyn.txt b/lib/lpp/lpp_dma/vhdlsyn.txt --- a/lib/lpp/lpp_dma/vhdlsyn.txt +++ b/lib/lpp/lpp_dma/vhdlsyn.txt @@ -5,3 +5,7 @@ lpp_dma_ip.vhd lpp_dma_send_16word.vhd lpp_dma_send_1word.vhd lpp_dma_singleOrBurst.vhd +DMA_SubSystem.vhd +DMA_SubSystem_GestionBuffer.vhd +DMA_SubSystem_Arbiter.vhd +DMA_SubSystem_MUX.vhd diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -59,13 +59,13 @@ ENTITY lpp_lfr IS coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo -- - data_shaping_BW : OUT STD_LOGIC; + data_shaping_BW : OUT STD_LOGIC -- -- - observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - - observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) +-- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); +-- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + +-- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --debug --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); @@ -138,25 +138,27 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- SM - SIGNAL ready_matrix_f0 : STD_LOGIC; - SIGNAL ready_matrix_f0_1 : STD_LOGIC; - SIGNAL ready_matrix_f1 : STD_LOGIC; - SIGNAL ready_matrix_f2 : STD_LOGIC; + SIGNAL ready_matrix_f0 : STD_LOGIC; + SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; - SIGNAL error_bad_component_error : STD_LOGIC; +-- SIGNAL error_bad_component_error : STD_LOGIC; -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL status_ready_matrix_f0 : STD_LOGIC; - SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; - SIGNAL status_ready_matrix_f1 : STD_LOGIC; - SIGNAL status_ready_matrix_f2 : STD_LOGIC; + SIGNAL status_ready_matrix_f0 : STD_LOGIC; + SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; -- SIGNAL status_error_bad_component_error : STD_LOGIC; - SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; - SIGNAL config_active_interruption_onError : STD_LOGIC; - SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; +-- SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); + SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); + SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- WFP SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -278,19 +280,30 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL run_ms : STD_LOGIC; SIGNAL ms_softandhard_rstn : STD_LOGIC; - - SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); + + SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); - + SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + + + SIGNAL error_buffer_full : STD_LOGIC; + SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); + +-- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); + SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dma_grant_error : STD_LOGIC; - SIGNAL error_buffer_full : STD_LOGIC; - SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); - - SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); - BEGIN sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); @@ -345,33 +358,26 @@ BEGIN run_ms => run_ms, - ready_matrix_f0 => ready_matrix_f0, --- ready_matrix_f0_1 => ready_matrix_f0_1, - ready_matrix_f1 => ready_matrix_f1, - ready_matrix_f2 => ready_matrix_f2, --- error_anticipating_empty_fifo => error_anticipating_empty_fifo, - error_bad_component_error => error_bad_component_error, - error_buffer_full => error_buffer_full, -- TODO - error_input_fifo_write => error_input_fifo_write, -- TODO --- debug_reg => debug_reg, - status_ready_matrix_f0 => status_ready_matrix_f0, --- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, - status_ready_matrix_f1 => status_ready_matrix_f1, - status_ready_matrix_f2 => status_ready_matrix_f2, --- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, --- status_error_bad_component_error => status_error_bad_component_error, - config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, - config_active_interruption_onError => config_active_interruption_onError, + ready_matrix_f0 => ready_matrix_f0, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_buffer_full => error_buffer_full, -- TODO + error_input_fifo_write => error_input_fifo_write, -- TODO + status_ready_matrix_f0 => status_ready_matrix_f0, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, matrix_time_f0 => matrix_time_f0, --- matrix_time_f0_1 => matrix_time_f0_1, - matrix_time_f1 => matrix_time_f1, - matrix_time_f2 => matrix_time_f2, + matrix_time_f1 => matrix_time_f1, + matrix_time_f2 => matrix_time_f2, - addr_matrix_f0 => addr_matrix_f0, --- addr_matrix_f0_1 => addr_matrix_f0_1, - addr_matrix_f1 => addr_matrix_f1, - addr_matrix_f2 => addr_matrix_f2, + addr_matrix_f0 => addr_matrix_f0, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + + length_matrix_f0 => length_matrix_f0, + length_matrix_f1 => length_matrix_f1, + length_matrix_f2 => length_matrix_f2, ------------------------------------------------------------------------- status_full => status_full, status_full_ack => status_full_ack, @@ -452,19 +458,19 @@ BEGIN --f0 addr_data_f0 => addr_data_f0, data_f0_in_valid => sample_f0_val, - data_f0_in => sample_f0_data, + data_f0_in => sample_f0_data, --f1 addr_data_f1 => addr_data_f1, data_f1_in_valid => sample_f1_val, - data_f1_in => sample_f1_data, + data_f1_in => sample_f1_data, --f2 addr_data_f2 => addr_data_f2, data_f2_in_valid => sample_f2_val, - data_f2_in => sample_f2_data, + data_f2_in => sample_f2_data, --f3 addr_data_f3 => addr_data_f3, data_f3_in_valid => sample_f3_val, - data_f3_in => sample_f3_data, + data_f3_in => sample_f3_data, -- OUTPUT -- DMA interface --f0 data_f0_addr_out => data_f0_addr_out_s, @@ -492,7 +498,7 @@ BEGIN data_f3_data_out_ren => data_f3_data_out_ren , ------------------------------------------------------------------------- - observation_reg => OPEN + observation_reg => OPEN ); @@ -605,8 +611,8 @@ BEGIN dma_send <= '1'; dma_valid_burst <= data_ms_valid_burst; dma_sel_valid <= data_ms_valid; - --ELSE - --dma_ms_ongoing <= '0'; + --ELSE + --dma_ms_ongoing <= '0'; END IF; IF dma_ms_ongoing = '1' AND dma_done = '1' THEN @@ -658,8 +664,8 @@ BEGIN HCLK => clk, HRESETn => rstn, run => run, - AHB_Master_In => ahbi, - AHB_Master_Out => ahbo, + AHB_Master_In => OPEN, + AHB_Master_Out => OPEN, send => dma_send, valid_burst => dma_valid_burst, @@ -693,6 +699,7 @@ BEGIN PORT MAP ( clk => clk, rstn => ms_softandhard_rstn, --rstn, + run => run_ms, coarse_time => coarse_time, fine_time => fine_time, @@ -701,51 +708,64 @@ BEGIN sample_f0_wdata => sample_f0_wdata, sample_f1_wen => sample_f1_wen, sample_f1_wdata => sample_f1_wdata, - sample_f2_wen => sample_f2_wen, -- TODO - sample_f2_wdata => sample_f2_wdata,-- TODO + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, - dma_addr => data_ms_addr, -- - dma_data => data_ms_data, -- - dma_valid => data_ms_valid, -- - dma_valid_burst => data_ms_valid_burst, -- - dma_ren => data_ms_ren, -- - dma_done => data_ms_done, -- + --DMA + dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT + dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT + dma_fifo_ren => dma_fifo_ren(4), -- IN + dma_buffer_new => dma_buffer_new(4), -- OUT + dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT + dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT + dma_buffer_full => dma_buffer_full(4), -- IN + dma_buffer_full_err => dma_buffer_full_err(4), -- IN + + - ready_matrix_f0 => ready_matrix_f0, - ready_matrix_f1 => ready_matrix_f1, - ready_matrix_f2 => ready_matrix_f2, - error_bad_component_error => error_bad_component_error, - error_buffer_full => error_buffer_full, - error_input_fifo_write => error_input_fifo_write, - - debug_reg => debug_ms,--observation_reg, - observation_vector_0 => observation_vector_0, - observation_vector_1 => observation_vector_1, - - status_ready_matrix_f0 => status_ready_matrix_f0, - status_ready_matrix_f1 => status_ready_matrix_f1, - status_ready_matrix_f2 => status_ready_matrix_f2, - config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, - config_active_interruption_onError => config_active_interruption_onError, - addr_matrix_f0 => addr_matrix_f0, - addr_matrix_f1 => addr_matrix_f1, - addr_matrix_f2 => addr_matrix_f2, + --REG + ready_matrix_f0 => ready_matrix_f0, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_buffer_full => error_buffer_full, + error_input_fifo_write => error_input_fifo_write, - matrix_time_f0 => matrix_time_f0, - matrix_time_f1 => matrix_time_f1, - matrix_time_f2 => matrix_time_f2); + status_ready_matrix_f0 => status_ready_matrix_f0, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + addr_matrix_f0 => addr_matrix_f0, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + + length_matrix_f0 => length_matrix_f0, + length_matrix_f1 => length_matrix_f1, + length_matrix_f2 => length_matrix_f2, + + matrix_time_f0 => matrix_time_f0, + matrix_time_f1 => matrix_time_f1, + matrix_time_f2 => matrix_time_f2); ----------------------------------------------------------------------------- - - observation_reg(31 DOWNTO 0) <= - dma_sel(4) & -- 31 - dma_ms_ongoing & -- 30 - data_ms_done & -- 29 - dma_done & -- 28 - ms_softandhard_rstn & --27 - debug_ms(14 DOWNTO 12) & -- 26 .. 24 - debug_ms(11 DOWNTO 0) & -- 23 .. 12 - debug_signal(11 DOWNTO 0); -- 11 .. 0 - + DMA_SubSystem_1 : DMA_SubSystem + GENERIC MAP ( + hindex => hindex) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run_ms, + ahbi => ahbi, + ahbo => ahbo, + + fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid, + fifo_data => dma_fifo_data, --fifo_data, + fifo_ren => dma_fifo_ren, --fifo_ren, + + buffer_new => dma_buffer_new, --buffer_new, + buffer_addr => dma_buffer_addr, --buffer_addr, + buffer_length => dma_buffer_length, --buffer_length, + buffer_full => dma_buffer_full, --buffer_full, + buffer_full_err => dma_buffer_full_err, --buffer_full_err, + grant_error => dma_grant_error); --grant_error); + END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -66,7 +66,7 @@ ENTITY lpp_lfr_apbreg IS ready_matrix_f1 : IN STD_LOGIC; ready_matrix_f2 : IN STD_LOGIC; - error_bad_component_error : IN STD_LOGIC; +-- error_bad_component_error : IN STD_LOGIC; error_buffer_full : IN STD_LOGIC; -- TODO error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO @@ -77,13 +77,17 @@ ENTITY lpp_lfr_apbreg IS status_ready_matrix_f1 : OUT STD_LOGIC; status_ready_matrix_f2 : OUT STD_LOGIC; - config_active_interruption_onNewMatrix : OUT STD_LOGIC; - config_active_interruption_onError : OUT STD_LOGIC; + --config_active_interruption_onNewMatrix : OUT STD_LOGIC; + --config_active_interruption_onError : OUT STD_LOGIC; addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); @@ -154,7 +158,7 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS status_ready_matrix_f0_1 : STD_LOGIC; status_ready_matrix_f1_1 : STD_LOGIC; status_ready_matrix_f2_1 : STD_LOGIC; - status_error_bad_component_error : STD_LOGIC; +-- status_error_bad_component_error : STD_LOGIC; status_error_buffer_full : STD_LOGIC; status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); @@ -165,6 +169,8 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0); + time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); @@ -255,8 +261,8 @@ BEGIN -- beh -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; - config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; - config_active_interruption_onError <= reg_sp.config_active_interruption_onError; +-- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; +-- config_active_interruption_onError <= reg_sp.config_active_interruption_onError; -- addr_matrix_f0 <= reg_sp.addr_matrix_f0; @@ -298,6 +304,11 @@ BEGIN -- beh start_date <= reg_wp.start_date; + length_matrix_f0 <= reg_sp.length_matrix; + length_matrix_f1 <= reg_sp.length_matrix; + length_matrix_f2 <= reg_sp.length_matrix; + + lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); BEGIN -- PROCESS lpp_dma_top @@ -311,7 +322,7 @@ BEGIN -- beh reg_sp.status_ready_matrix_f0_1 <= '0'; reg_sp.status_ready_matrix_f1_1 <= '0'; reg_sp.status_ready_matrix_f2_1 <= '0'; - reg_sp.status_error_bad_component_error <= '0'; +-- reg_sp.status_error_bad_component_error <= '0'; reg_sp.status_error_buffer_full <= '0'; reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); @@ -323,6 +334,8 @@ BEGIN -- beh reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); + reg_sp.length_matrix <= (OTHERS => '0'); + -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok @@ -382,7 +395,7 @@ BEGIN -- beh reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; - reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; +-- reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); @@ -414,7 +427,7 @@ BEGIN -- beh prdata(3) <= reg_sp.status_ready_matrix_f1_1; prdata(4) <= reg_sp.status_ready_matrix_f2_0; prdata(5) <= reg_sp.status_ready_matrix_f2_1; - prdata(6) <= reg_sp.status_error_bad_component_error; +-- prdata(6) <= reg_sp.status_error_bad_component_error; prdata(7) <= reg_sp.status_error_buffer_full; prdata(8) <= reg_sp.status_error_input_fifo_write(0); prdata(9) <= reg_sp.status_error_input_fifo_write(1); @@ -455,16 +468,18 @@ BEGIN -- beh WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); --19 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); + --20 + WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix; --------------------------------------------------------------------- --20 - WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW; + WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW; prdata(1) <= reg_wp.data_shaping_SP0; prdata(2) <= reg_wp.data_shaping_SP1; prdata(3) <= reg_wp.data_shaping_R0; prdata(4) <= reg_wp.data_shaping_R1; prdata(5) <= reg_wp.data_shaping_R2; --21 - WHEN "010101" => prdata(0) <= reg_wp.enable_f0; + WHEN "010110" => prdata(0) <= reg_wp.enable_f0; prdata(1) <= reg_wp.enable_f1; prdata(2) <= reg_wp.enable_f2; prdata(3) <= reg_wp.enable_f3; @@ -473,35 +488,35 @@ BEGIN -- beh prdata(6) <= reg_wp.burst_f2; prdata(7) <= reg_wp.run; --22 - WHEN "010110" => prdata <= reg_wp.addr_data_f0; + WHEN "010111" => prdata <= reg_wp.addr_data_f0; --23 - WHEN "010111" => prdata <= reg_wp.addr_data_f1; + WHEN "011000" => prdata <= reg_wp.addr_data_f1; --24 - WHEN "011000" => prdata <= reg_wp.addr_data_f2; + WHEN "011001" => prdata <= reg_wp.addr_data_f2; --25 - WHEN "011001" => prdata <= reg_wp.addr_data_f3; + WHEN "011010" => prdata <= reg_wp.addr_data_f3; --26 - WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full; + WHEN "011011" => prdata(3 DOWNTO 0) <= reg_wp.status_full; prdata(7 DOWNTO 4) <= reg_wp.status_full_err; prdata(11 DOWNTO 8) <= reg_wp.status_new_err; --27 - WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; + WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; --28 - WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; + WHEN "011101" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; --29 - WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; + WHEN "011110" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; --30 - WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; + WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; --31 - WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; + WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; --32 - WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; + WHEN "100001" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; --33 - WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; + WHEN "100010" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; --34 - WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date; + WHEN "100011" => prdata(30 DOWNTO 0) <= reg_wp.start_date; --35 - WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; + WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; ---------------------------------------------------- WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); WHEN OTHERS => NULL; @@ -522,7 +537,6 @@ BEGIN -- beh reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1; reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2; reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2; - reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error; reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full; reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0); reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1); @@ -536,13 +550,15 @@ BEGIN -- beh WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; --8 to 19 --20 - WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0); + WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0); + --20 + WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0); reg_wp.data_shaping_SP0 <= apbi.pwdata(1); reg_wp.data_shaping_SP1 <= apbi.pwdata(2); reg_wp.data_shaping_R0 <= apbi.pwdata(3); reg_wp.data_shaping_R1 <= apbi.pwdata(4); reg_wp.data_shaping_R2 <= apbi.pwdata(5); - WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0); + WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0); reg_wp.enable_f1 <= apbi.pwdata(1); reg_wp.enable_f2 <= apbi.pwdata(2); reg_wp.enable_f3 <= apbi.pwdata(3); @@ -551,27 +567,27 @@ BEGIN -- beh reg_wp.burst_f2 <= apbi.pwdata(6); reg_wp.run <= apbi.pwdata(7); --22 - WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata; - WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata; - WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata; - WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata; + WHEN "010111" => reg_wp.addr_data_f0 <= apbi.pwdata; + WHEN "011000" => reg_wp.addr_data_f1 <= apbi.pwdata; + WHEN "011001" => reg_wp.addr_data_f2 <= apbi.pwdata; + WHEN "011010" => reg_wp.addr_data_f3 <= apbi.pwdata; --26 - WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); + WHEN "011011" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); - WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); - WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); - WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); - WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); - WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); + WHEN "011100" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "011101" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "011110" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); + WHEN "011111" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "100000" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "100001" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); + WHEN "100010" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); + WHEN "100011" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); + WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); -- WHEN OTHERS => NULL; END CASE; @@ -584,8 +600,8 @@ BEGIN -- beh ) OR (reg_sp.config_active_interruption_onError AND ( - error_bad_component_error - OR error_buffer_full +-- error_bad_component_error OR + error_buffer_full OR error_input_fifo_write(0) OR error_input_fifo_write(1) OR error_input_fifo_write(2)) @@ -695,7 +711,9 @@ BEGIN -- beh reg_sp.status_error_input_fifo_write(2) &--10 reg_sp.status_error_input_fifo_write(1) &--9 reg_sp.status_error_input_fifo_write(0) &--8 - reg_sp.status_error_buffer_full & reg_sp.status_error_bad_component_error & --7 6 + reg_sp.status_error_buffer_full & + '0' & +-- reg_sp.status_error_bad_component_error & --7 6 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0 diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -21,6 +21,7 @@ ENTITY lpp_lfr_ms IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; + run : IN STD_LOGIC; --------------------------------------------------------------------------- -- DATA INPUT @@ -41,40 +42,39 @@ ENTITY lpp_lfr_ms IS --------------------------------------------------------------------------- -- DMA --------------------------------------------------------------------------- - dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_valid : OUT STD_LOGIC; - dma_valid_burst : OUT STD_LOGIC; - dma_ren : IN STD_LOGIC; - dma_done : IN STD_LOGIC; + dma_fifo_burst_valid: OUT STD_LOGIC; --TODO + dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO + dma_fifo_ren : IN STD_LOGIC; --TODO + dma_buffer_new : OUT STD_LOGIC; --TODO + dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO + dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO + dma_buffer_full : IN STD_LOGIC; --TODO + dma_buffer_full_err : IN STD_LOGIC; --TODO -- Reg out - ready_matrix_f0 : OUT STD_LOGIC; - ready_matrix_f1 : OUT STD_LOGIC; - ready_matrix_f2 : OUT STD_LOGIC; - error_bad_component_error : OUT STD_LOGIC; - error_buffer_full : OUT STD_LOGIC; + ready_matrix_f0 : OUT STD_LOGIC; -- TODO + ready_matrix_f1 : OUT STD_LOGIC; -- TODO + ready_matrix_f2 : OUT STD_LOGIC; -- TODO +-- error_bad_component_error : OUT STD_LOGIC; -- TODO + error_buffer_full : OUT STD_LOGIC; -- TODO error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - -- - observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - -- Reg In - status_ready_matrix_f0 : IN STD_LOGIC; - status_ready_matrix_f1 : IN STD_LOGIC; - status_ready_matrix_f2 : IN STD_LOGIC; + status_ready_matrix_f0 : IN STD_LOGIC; -- TODO + status_ready_matrix_f1 : IN STD_LOGIC; -- TODO + status_ready_matrix_f2 : IN STD_LOGIC; -- TODO - config_active_interruption_onNewMatrix : IN STD_LOGIC; - config_active_interruption_onError : IN STD_LOGIC; - addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO + + length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO + length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO + length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO - matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO ); END; @@ -195,6 +195,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; + SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC; SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); ----------------------------------------------------------------------------- @@ -204,6 +205,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0); ----------------------------------------------------------------------------- -- TIME REG & INFOs @@ -623,17 +625,6 @@ BEGIN fft_data_valid => fft_data_valid, fft_ready => fft_ready); - observation_vector_0(11 DOWNTO 0) <= "000" & --11 10 - fft_ongoing_counter & --9 8 - sample_load_rising_down & --7 - fft_ready_rising_down & --6 - fft_ready & --5 - fft_data_valid & --4 - fft_pong & --3 - sample_load & --2 - fft_read & --1 - sample_valid; --0 - ----------------------------------------------------------------------------- fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; sample_load_rising_down <= sample_load_reg AND NOT sample_load; @@ -764,15 +755,6 @@ BEGIN empty => MEM_IN_SM_Empty, almost_full => OPEN); - ----------------------------------------------------------------------------- - - observation_vector_1(11 DOWNTO 0) <= '0' & - SM_correlation_done & --4 - SM_correlation_auto & --3 - SM_correlation_start & - SM_correlation_start & --7 - status_MS_input(1 DOWNTO 0)& --6..5 - MEM_IN_SM_locked(4 DOWNTO 0); --4..0 ----------------------------------------------------------------------------- MS_control_1 : MS_control @@ -881,29 +863,60 @@ BEGIN MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; ----------------------------------------------------------------------------- - Mem_Out_SpectralMatrix : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 32, - Addr_sz => 8, - FifoCnt => 2) - PORT MAP ( - clk => clk, - rstn => rstn, + --Mem_Out_SpectralMatrix : lppFIFOxN + -- GENERIC MAP ( + -- tech => 0, + -- Mem_use => Mem_use, + -- Data_sz => 32, + -- Addr_sz => 8, + -- FifoCnt => 2) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + + -- ReUse => (OTHERS => '0'), + -- run => (OTHERS => '1'), + + -- wen => MEM_OUT_SM_Write, + -- wdata => MEM_OUT_SM_Data_in, + + -- ren => MEM_OUT_SM_Read, + -- rdata => MEM_OUT_SM_Data_out, + + -- full => MEM_OUT_SM_Full, + -- empty => MEM_OUT_SM_Empty, + -- almost_full => OPEN); - ReUse => (OTHERS => '0'), - run => (OTHERS => '1'), - - wen => MEM_OUT_SM_Write, - wdata => MEM_OUT_SM_Data_in, + + all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE + Mem_Out_SpectralMatrix_I: lpp_fifo + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + EMPTY_THRESHOLD_LIMIT => 15, + FULL_THRESHOLD_LIMIT => 1, + DataSz => 32, + AddrSz => 8) + PORT MAP ( + clk => clk, + rstn => rstn, + reUse => '0', + run => run, - ren => MEM_OUT_SM_Read, - rdata => MEM_OUT_SM_Data_out, - - full => MEM_OUT_SM_Full, - empty => MEM_OUT_SM_Empty, - almost_full => OPEN); + ren => MEM_OUT_SM_Read(I), + rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i), + + wen => MEM_OUT_SM_Write(I), + wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i), + + empty => MEM_OUT_SM_Empty(I), + full => MEM_OUT_SM_Full(I), + full_almost => OPEN, + empty_threshold => MEM_OUT_SM_Empty_Threshold(I), + + full_threshold => OPEN); + + END GENERATE all_Mem_Out_SpectralMatrix; ----------------------------------------------------------------------------- -- MEM_OUT_SM_Read <= "00"; @@ -949,51 +962,140 @@ BEGIN FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE MEM_OUT_SM_Data_out(63 DOWNTO 32); + + FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE + MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE + '0'; + ----------------------------------------------------------------------------- - lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - - fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), - fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), - fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), - fifo_data => FSM_DMA_fifo_data, - fifo_empty => FSM_DMA_fifo_empty, - fifo_ren => FSM_DMA_fifo_ren, + -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN + -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN + -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN + -- fifo_data => FSM_DMA_fifo_data, --IN + -- fifo_empty => FSM_DMA_fifo_empty, --IN + -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN + -- fifo_ren => FSM_DMA_fifo_ren, --OUT + - dma_addr => dma_addr, - dma_data => dma_data, - dma_valid => dma_valid, - dma_valid_burst => dma_valid_burst, - dma_ren => dma_ren, - dma_done => dma_done, - - ready_matrix_f0 => ready_matrix_f0, - ready_matrix_f1 => ready_matrix_f1, - ready_matrix_f2 => ready_matrix_f2, - - error_bad_component_error => error_bad_component_error, - error_buffer_full => error_buffer_full, - - debug_reg => debug_reg, + lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), + fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), + fifo_data => FSM_DMA_fifo_data, + fifo_empty => FSM_DMA_fifo_empty, + fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, + fifo_ren => FSM_DMA_fifo_ren, + + dma_fifo_valid_burst => dma_fifo_burst_valid, + dma_fifo_data => dma_fifo_data, + dma_fifo_ren => dma_fifo_ren, + dma_buffer_new => dma_buffer_new, + dma_buffer_addr => dma_buffer_addr, + dma_buffer_length => dma_buffer_length, + dma_buffer_full => dma_buffer_full, + dma_buffer_full_err => dma_buffer_full_err, + status_ready_matrix_f0 => status_ready_matrix_f0, status_ready_matrix_f1 => status_ready_matrix_f1, status_ready_matrix_f2 => status_ready_matrix_f2, + addr_matrix_f0 => addr_matrix_f0, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + length_matrix_f0 => length_matrix_f0, + length_matrix_f1 => length_matrix_f1, + length_matrix_f2 => length_matrix_f2, + ready_matrix_f0 => ready_matrix_f0, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + matrix_time_f0 => matrix_time_f0, + matrix_time_f1 => matrix_time_f1, + matrix_time_f2 => matrix_time_f2, + error_buffer_full => error_buffer_full); + - config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, - config_active_interruption_onError => config_active_interruption_onError, + + + + --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO + --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO + --dma_fifo_ren : IN STD_LOGIC; --TODO + --dma_buffer_new : OUT STD_LOGIC; --TODO + --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO + --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO + --dma_buffer_full : IN STD_LOGIC; --TODO + --dma_buffer_full_err : IN STD_LOGIC; --TODO + + ---- Reg out + --ready_matrix_f0 : OUT STD_LOGIC; -- TODO + --ready_matrix_f1 : OUT STD_LOGIC; -- TODO + --ready_matrix_f2 : OUT STD_LOGIC; -- TODO + --error_bad_component_error : OUT STD_LOGIC; -- TODO + --error_buffer_full : OUT STD_LOGIC; -- TODO + + ---- Reg In + --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO + --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO + --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO + + --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO + --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO + --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO - addr_matrix_f0 => addr_matrix_f0, - addr_matrix_f1 => addr_matrix_f1, - addr_matrix_f2 => addr_matrix_f2, + --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO + --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO + --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma + -- PORT MAP ( + -- HCLK => clk, + -- HRESETn => rstn, + + -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), + -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), + -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), + -- fifo_data => FSM_DMA_fifo_data, + -- fifo_empty => FSM_DMA_fifo_empty, + -- fifo_ren => FSM_DMA_fifo_ren, - matrix_time_f0 => matrix_time_f0, - matrix_time_f1 => matrix_time_f1, - matrix_time_f2 => matrix_time_f2 - ); + -- dma_addr => dma_addr, + -- dma_data => dma_data, + -- dma_valid => dma_valid, + -- dma_valid_burst => dma_valid_burst, + -- dma_ren => dma_ren, + -- dma_done => dma_done, + + -- ready_matrix_f0 => ready_matrix_f0, + -- ready_matrix_f1 => ready_matrix_f1, + -- ready_matrix_f2 => ready_matrix_f2, + + -- error_bad_component_error => error_bad_component_error, + -- error_buffer_full => error_buffer_full, + + -- debug_reg => debug_reg, + -- status_ready_matrix_f0 => status_ready_matrix_f0, + -- status_ready_matrix_f1 => status_ready_matrix_f1, + -- status_ready_matrix_f2 => status_ready_matrix_f2, + + -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + -- config_active_interruption_onError => config_active_interruption_onError, + + -- addr_matrix_f0 => addr_matrix_f0, + -- addr_matrix_f1 => addr_matrix_f1, + -- addr_matrix_f2 => addr_matrix_f2, + + -- matrix_time_f0 => matrix_time_f0, + -- matrix_time_f1 => matrix_time_f1, + -- matrix_time_f2 => matrix_time_f2 + -- ); ----------------------------------------------------------------------------- + @@ -1039,4 +1141,4 @@ BEGIN ----------------------------------------------------------------------------- -END Behavioral; +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd @@ -41,259 +41,147 @@ USE techmap.gencomp.ALL; ENTITY lpp_lfr_ms_fsmdma IS PORT ( -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; + clk : IN STD_ULOGIC; + rstn : IN STD_ULOGIC; + run : IN STD_LOGIC; --------------------------------------------------------------------------- -- FIFO - IN - fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fifo_empty : IN STD_LOGIC; - fifo_ren : OUT STD_LOGIC; + fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fifo_empty : IN STD_LOGIC; + fifo_empty_threshold : IN STD_LOGIC; + fifo_ren : OUT STD_LOGIC; --------------------------------------------------------------------------- -- DMA - OUT - dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_valid : OUT STD_LOGIC; - dma_valid_burst : OUT STD_LOGIC; - dma_ren : IN STD_LOGIC; - dma_done : IN STD_LOGIC; + dma_fifo_valid_burst : OUT STD_LOGIC; + dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC; + + dma_buffer_new : OUT STD_LOGIC; + dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC; + dma_buffer_full_err : IN STD_LOGIC; --------------------------------------------------------------------------- - -- Reg out - ready_matrix_f0 : OUT STD_LOGIC; - ready_matrix_f1 : OUT STD_LOGIC; - ready_matrix_f2 : OUT STD_LOGIC; - - error_bad_component_error : OUT STD_LOGIC; - error_buffer_full : OUT STD_LOGIC; - debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + -- Reg In + status_ready_matrix_f0 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + + addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- Reg In - status_ready_matrix_f0 : IN STD_LOGIC; - status_ready_matrix_f1 : IN STD_LOGIC; - status_ready_matrix_f2 : IN STD_LOGIC; + length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); - config_active_interruption_onNewMatrix : IN STD_LOGIC; - config_active_interruption_onError : IN STD_LOGIC; - addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + -- Reg Out + ready_matrix_f0 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; - matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) - + matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + error_buffer_full : OUT STD_LOGIC ); END; ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS - ----------------------------------------------------------------------------- - TYPE state_DMAWriteBurst IS (IDLE, - CHECK_COMPONENT_TYPE, - WRITE_COARSE_TIME, - WRITE_FINE_TIME, - TRASH_FIFO, - SEND_DATA, - WAIT_DATA_ACK - ); - SIGNAL state : state_DMAWriteBurst; - - SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL header_check_ok : STD_LOGIC; - SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); - ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- - SIGNAL component_send : STD_LOGIC; - SIGNAL component_send_ok : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL fifo_ren_trash : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL log_empty_fifo : STD_LOGIC; - ----------------------------------------------------------------------------- + TYPE FSM_DMA_STATE IS (IDLE, ONGOING); + SIGNAL state : FSM_DMA_STATE; + SIGNAL burst_valid_s : STD_LOGIC; - SIGNAL matrix_buffer_ready : STD_LOGIC; -BEGIN - - debug_reg <= debug_reg_s; - - - matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE - '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE - '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE - '0'; + SIGNAL current_matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); - header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" - '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE - '1' WHEN component_type = component_type_pre + "0001" ELSE - '0'; - - address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE - addr_matrix_f1 WHEN matrix_type = "01" ELSE - addr_matrix_f2 WHEN matrix_type = "10" ELSE - (OTHERS => '0'); +BEGIN + burst_valid_s <= NOT fifo_empty_threshold; - debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); - ----------------------------------------------------------------------------- - -- DMA control - ----------------------------------------------------------------------------- - DMAWriteFSM_p : PROCESS (HCLK, HRESETn) - BEGIN - IF HRESETn = '0' THEN - matrix_type <= (OTHERS => '0'); - component_type <= (OTHERS => '0'); - state <= IDLE; - ready_matrix_f0 <= '0'; - ready_matrix_f1 <= '0'; - ready_matrix_f2 <= '0'; - error_bad_component_error <= '0'; - error_buffer_full <= '0'; -- TODO - component_type_pre <= "0000"; - fifo_ren_trash <= '1'; - component_send <= '0'; - address <= (OTHERS => '0'); + error_buffer_full <= dma_buffer_full_err; - debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); - debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0'); - debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0'); - debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0'); - debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0'); - - log_empty_fifo <= '0'; - - matrix_time_f0 <= (OTHERS => '0'); - matrix_time_f1 <= (OTHERS => '0'); - matrix_time_f2 <= (OTHERS => '0'); + fifo_ren <= dma_fifo_ren WHEN state = ONGOING ELSE '1'; + dma_fifo_data <= fifo_data; + dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE '1'; - ELSIF HCLK'EVENT AND HCLK = '1' THEN - -- - debug_reg_s(3) <= status_ready_matrix_f0; - debug_reg_s(4) <= status_ready_matrix_f1; - debug_reg_s(5) <= status_ready_matrix_f2; - debug_reg_s(6) <= '0'; - debug_reg_s(7) <= '0'; - debug_reg_s(8) <= '0'; - debug_reg_s(10 DOWNTO 9) <= matrix_type; - debug_reg_s(14 DOWNTO 11) <= component_type; - - -- - - - - ready_matrix_f0 <= '0'; - ready_matrix_f1 <= '0'; - ready_matrix_f2 <= '0'; - error_bad_component_error <= '0'; - error_buffer_full <= '0'; - - CASE state IS - WHEN IDLE => - debug_reg_s(2 DOWNTO 0) <= "000"; - IF fifo_empty = '0' THEN - state <= CHECK_COMPONENT_TYPE; - matrix_type <= fifo_matrix_type; - component_type <= fifo_matrix_component; - component_type_pre <= component_type; - END IF; - - log_empty_fifo <= '0'; - - WHEN CHECK_COMPONENT_TYPE => - debug_reg_s(2 DOWNTO 0) <= "001"; - - IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN - IF component_type = "0000" THEN - address <= address_matrix; - CASE matrix_type IS - WHEN "00" => matrix_time_f0 <= fifo_matrix_time; - WHEN "01" => matrix_time_f1 <= fifo_matrix_time; - WHEN "10" => matrix_time_f2 <= fifo_matrix_time; - WHEN OTHERS => NULL; - END CASE; - component_send <= '1'; - END IF; - state <= SEND_DATA; - -- - ELSE - error_bad_component_error <= NOT header_check_ok; - error_buffer_full <= NOT matrix_buffer_ready; -- TODO - component_type_pre <= "0000"; - state <= TRASH_FIFO; - END IF; - - WHEN TRASH_FIFO => - debug_reg_s(2 DOWNTO 0) <= "100"; - - error_buffer_full <= '0'; - error_bad_component_error <= '0'; - IF fifo_empty = '1' THEN - state <= IDLE; - fifo_ren_trash <= '1'; - ELSE - fifo_ren_trash <= '0'; - END IF; - - WHEN SEND_DATA => - debug_reg_s(2 DOWNTO 0) <= "010"; - - IF fifo_empty = '1' OR log_empty_fifo = '1' THEN - state <= IDLE; - IF component_type = "1110" THEN - CASE matrix_type IS - WHEN "00" => - ready_matrix_f0 <= '1'; - debug_reg_s(6) <= '1'; - WHEN "01" => - ready_matrix_f1 <= '1'; - debug_reg_s(7) <= '1'; - WHEN "10" => - ready_matrix_f2 <= '1'; - debug_reg_s(8) <= '1'; + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + current_matrix_type <= "00"; + matrix_time_f0 <= (OTHERS => '0'); + matrix_time_f1 <= (OTHERS => '0'); + matrix_time_f2 <= (OTHERS => '0'); + dma_buffer_addr <= (OTHERS => '0'); + dma_buffer_length <= (OTHERS => '0'); + dma_buffer_new <= '0'; + ready_matrix_f0 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + ready_matrix_f0 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; + IF run = '1' THEN + CASE state IS + WHEN IDLE => + IF fifo_empty = '0' THEN + current_matrix_type <= fifo_matrix_type; + CASE fifo_matrix_type IS + WHEN "00" => + IF status_ready_matrix_f0 = '0' THEN + state <= ONGOING; + matrix_time_f0 <= fifo_matrix_time; + dma_buffer_addr <= addr_matrix_f0; + dma_buffer_length <= length_matrix_f0; + dma_buffer_new <= '1'; + END IF; + WHEN "01" => + IF status_ready_matrix_f1 = '0' THEN + state <= ONGOING; + matrix_time_f1 <= fifo_matrix_time; + dma_buffer_addr <= addr_matrix_f1; + dma_buffer_length <= length_matrix_f1; + dma_buffer_new <= '1'; + END IF; + WHEN "10" => + IF status_ready_matrix_f2 = '0' THEN + state <= ONGOING; + matrix_time_f2 <= fifo_matrix_time; + dma_buffer_addr <= addr_matrix_f2; + dma_buffer_length <= length_matrix_f2; + dma_buffer_new <= '1'; + END IF; WHEN OTHERS => NULL; END CASE; END IF; - ELSE - component_send <= '1'; - address <= address; - state <= WAIT_DATA_ACK; - END IF; - - WHEN WAIT_DATA_ACK => - log_empty_fifo <= fifo_empty OR log_empty_fifo; - - debug_reg_s(2 DOWNTO 0) <= "011"; - - IF dma_ren = '0' THEN - component_send <= '0'; - END IF; - - IF component_send_ok = '1' THEN - address <= address + 64; - state <= SEND_DATA; - END IF; - - WHEN OTHERS => NULL; - END CASE; - + WHEN ONGOING => + IF dma_buffer_full = '1' THEN + CASE current_matrix_type IS + WHEN "00" => ready_matrix_f0 <= '1'; state <= IDLE; + WHEN "01" => ready_matrix_f1 <= '1'; state <= IDLE; + WHEN "10" => ready_matrix_f2 <= '1'; state <= IDLE; + WHEN OTHERS => NULL; + END CASE; + END IF; + WHEN OTHERS => NULL; + END CASE; + ELSE + state <= IDLE; + current_matrix_type <= "00"; + matrix_time_f0 <= (OTHERS => '0'); + matrix_time_f1 <= (OTHERS => '0'); + matrix_time_f2 <= (OTHERS => '0'); + dma_buffer_addr <= (OTHERS => '0'); + dma_buffer_length <= (OTHERS => '0'); + dma_buffer_new <= '0'; + END IF; END IF; - END PROCESS DMAWriteFSM_p; - - dma_valid_burst <= component_send; - dma_valid <= '0'; - dma_data <= fifo_data; - dma_addr <= address; - fifo_ren <= dma_ren AND fifo_ren_trash; - - component_send_ok <= dma_done; + END PROCESS; END Behavioral; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -69,114 +69,83 @@ PACKAGE lpp_lfr_pkg IS ----------------------------------------------------------------------------- COMPONENT lpp_lfr_ms GENERIC ( - Mem_use : INTEGER - ); + Mem_use : INTEGER); PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo - - sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_valid : OUT STD_LOGIC; - dma_valid_burst : OUT STD_LOGIC; - dma_ren : IN STD_LOGIC; - dma_done : IN STD_LOGIC; - - ready_matrix_f0 : OUT STD_LOGIC; --- ready_matrix_f0_1 : OUT STD_LOGIC; - ready_matrix_f1 : OUT STD_LOGIC; - ready_matrix_f2 : OUT STD_LOGIC; --- error_anticipating_empty_fifo : OUT STD_LOGIC; - error_bad_component_error : OUT STD_LOGIC; - error_buffer_full : OUT STD_LOGIC; - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - -- - observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - ------------------------------------------------------------------------- - status_ready_matrix_f0 : IN STD_LOGIC; --- status_ready_matrix_f0_1 : IN STD_LOGIC; - status_ready_matrix_f1 : IN STD_LOGIC; - status_ready_matrix_f2 : IN STD_LOGIC; --- status_error_anticipating_empty_fifo : IN STD_LOGIC; --- status_error_bad_component_error : IN STD_LOGIC; - config_active_interruption_onNewMatrix : IN STD_LOGIC; - config_active_interruption_onError : IN STD_LOGIC; - addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - - matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); --- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + dma_fifo_burst_valid : OUT STD_LOGIC; + dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC; + dma_buffer_new : OUT STD_LOGIC; + dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC; + dma_buffer_full_err : IN STD_LOGIC; + ready_matrix_f0 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_buffer_full : OUT STD_LOGIC; + error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + status_ready_matrix_f0 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); END COMPONENT; COMPONENT lpp_lfr_ms_fsmdma PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fifo_empty : IN STD_LOGIC; - fifo_ren : OUT STD_LOGIC; - --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - --fifo_empty : IN STD_LOGIC; - --fifo_ren : OUT STD_LOGIC; - --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - --header_val : IN STD_LOGIC; - --header_ack : OUT STD_LOGIC; - dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_valid : OUT STD_LOGIC; - dma_valid_burst : OUT STD_LOGIC; - dma_ren : IN STD_LOGIC; - dma_done : IN STD_LOGIC; - ready_matrix_f0 : OUT STD_LOGIC; --- ready_matrix_f0_1 : OUT STD_LOGIC; - ready_matrix_f1 : OUT STD_LOGIC; - ready_matrix_f2 : OUT STD_LOGIC; --- error_anticipating_empty_fifo : OUT STD_LOGIC; - error_bad_component_error : OUT STD_LOGIC; - error_buffer_full : OUT STD_LOGIC; - debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - status_ready_matrix_f0 : IN STD_LOGIC; --- status_ready_matrix_f0_1 : IN STD_LOGIC; - status_ready_matrix_f1 : IN STD_LOGIC; - status_ready_matrix_f2 : IN STD_LOGIC; --- status_error_anticipating_empty_fifo : IN STD_LOGIC; --- status_error_bad_component_error : IN STD_LOGIC; - config_active_interruption_onNewMatrix : IN STD_LOGIC; - config_active_interruption_onError : IN STD_LOGIC; - addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - - matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); --- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) - ); + clk : IN STD_ULOGIC; + rstn : IN STD_ULOGIC; + run : IN STD_LOGIC; + fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fifo_empty : IN STD_LOGIC; + fifo_empty_threshold : IN STD_LOGIC; + fifo_ren : OUT STD_LOGIC; + dma_fifo_valid_burst : OUT STD_LOGIC; + dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC; + dma_buffer_new : OUT STD_LOGIC; + dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC; + dma_buffer_full_err : IN STD_LOGIC; + status_ready_matrix_f0 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + ready_matrix_f0 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + error_buffer_full : OUT STD_LOGIC); END COMPONENT; - + COMPONENT lpp_lfr_ms_FFT PORT ( clk : IN STD_LOGIC; @@ -285,6 +254,7 @@ PACKAGE lpp_lfr_pkg IS observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; ----------------------------------------------------------------------------- + COMPONENT lpp_lfr_apbreg GENERIC ( nb_data_by_buffer_size : INTEGER; @@ -299,70 +269,62 @@ PACKAGE lpp_lfr_pkg IS pirq_wfp : INTEGER; top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - run_ms : OUT STD_LOGIC; - ready_matrix_f0 : IN STD_LOGIC; - ready_matrix_f1 : IN STD_LOGIC; - ready_matrix_f2 : IN STD_LOGIC; - error_bad_component_error : IN STD_LOGIC; - error_buffer_full : in STD_LOGIC; - error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); ---x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - status_ready_matrix_f0 : OUT STD_LOGIC; - status_ready_matrix_f1 : OUT STD_LOGIC; - status_ready_matrix_f2 : OUT STD_LOGIC; - config_active_interruption_onNewMatrix : OUT STD_LOGIC; - config_active_interruption_onError : OUT STD_LOGIC; - addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); --- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - data_shaping_BW : OUT STD_LOGIC; - data_shaping_SP0 : OUT STD_LOGIC; - data_shaping_SP1 : OUT STD_LOGIC; - data_shaping_R0 : OUT STD_LOGIC; - data_shaping_R1 : OUT STD_LOGIC; - data_shaping_R2 : OUT STD_LOGIC; - delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); - delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); - nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - enable_f0 : OUT STD_LOGIC; - enable_f1 : OUT STD_LOGIC; - enable_f2 : OUT STD_LOGIC; - enable_f3 : OUT STD_LOGIC; - burst_f0 : OUT STD_LOGIC; - burst_f1 : OUT STD_LOGIC; - burst_f2 : OUT STD_LOGIC; - run : OUT STD_LOGIC; - addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); - - debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - - ); + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + run_ms : OUT STD_LOGIC; + ready_matrix_f0 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_buffer_full : IN STD_LOGIC; + error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + status_ready_matrix_f0 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + data_shaping_R2 : OUT STD_LOGIC; + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + run : OUT STD_LOGIC; + addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); + debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; - - COMPONENT lpp_top_ms GENERIC ( Mem_use : INTEGER; diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -103,58 +103,18 @@ ENTITY lpp_waveform IS addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_f3_in_valid : IN STD_LOGIC; data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - + --------------------------------------------------------------------------- - -- OUTPUT - --f0 - data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f0_data_out_valid : OUT STD_LOGIC; - data_f0_data_out_valid_burst : OUT STD_LOGIC; - data_f0_data_out_ren : IN STD_LOGIC; - --f1 - data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f1_data_out_valid : OUT STD_LOGIC; - data_f1_data_out_valid_burst : OUT STD_LOGIC; - data_f1_data_out_ren : IN STD_LOGIC; - --f2 - data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f2_data_out_valid : OUT STD_LOGIC; - data_f2_data_out_valid_burst : OUT STD_LOGIC; - data_f2_data_out_ren : IN STD_LOGIC; - --f3 - data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f3_data_out_valid : OUT STD_LOGIC; - data_f3_data_out_valid_burst : OUT STD_LOGIC; - data_f3_data_out_ren : IN STD_LOGIC; - - --------------------------------------------------------------------------- - -- - observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + -- DMA -------------------------------------------------------------------- - - ----debug SNAPSHOT OUT - --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f0_data_valid : OUT STD_LOGIC; - --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f1_data_valid : OUT STD_LOGIC; - --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f2_data_valid : OUT STD_LOGIC; - --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f3_data_valid : OUT STD_LOGIC; - - ----debug FIFO IN - --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f3_data_fifo_in_valid : OUT STD_LOGIC + dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_new : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ); @@ -219,30 +179,11 @@ ARCHITECTURE beh OF lpp_waveform IS -- - SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN -- beh - - ----------------------------------------------------------------------------- - -- DEBUG - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - observation_reg <= (OTHERS => '0'); - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - observation_reg <= observation_reg_s; - END IF; - END PROCESS; - observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0; - observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; - observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ; - observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0); - observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0); - observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); ----------------------------------------------------------------------------- lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler @@ -506,8 +447,8 @@ BEGIN -- beh GENERIC MAP ( tech => tech, Mem_use => use_RAM, - EMPTY_THRESHOLD_LIMIT => 16, - FULL_THRESHOLD_LIMIT => 5, + EMPTY_THRESHOLD_LIMIT => 15, + FULL_THRESHOLD_LIMIT => 3, DataSz => 32, AddrSz => 7) PORT MAP ( @@ -528,70 +469,108 @@ BEGIN -- beh END GENERATE generate_all_fifo; - --empty <= s_empty; - --empty_almost <= s_empty_almost; - --s_data_ren <= data_ren; + ----empty <= s_empty; + ----empty_almost <= s_empty_almost; + ----s_data_ren <= data_ren; - data_f0_data_out <= s_rdata_v(31 downto 0); - data_f1_data_out <= s_rdata_v(31+32 downto 0+32); - data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2); - data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3); + --data_f0_data_out <= s_rdata_v(31 downto 0); + --data_f1_data_out <= s_rdata_v(31+32 downto 0+32); + --data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2); + --data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3); + + --data_ren <= data_f3_data_out_ren & + -- data_f2_data_out_ren & + -- data_f1_data_out_ren & + -- data_f0_data_out_ren; + + --lpp_waveform_gen_address_1 : lpp_waveform_genaddress + -- GENERIC MAP ( + -- nb_data_by_buffer_size => nb_word_by_buffer_size) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, - data_ren <= data_f3_data_out_ren & - data_f2_data_out_ren & - data_f1_data_out_ren & - data_f0_data_out_ren; - - lpp_waveform_gen_address_1 : lpp_waveform_genaddress - GENERIC MAP ( - nb_data_by_buffer_size => nb_word_by_buffer_size) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, + -- ------------------------------------------------------------------------- + -- -- CONFIG + -- ------------------------------------------------------------------------- + -- nb_data_by_buffer => nb_word_by_buffer, - ------------------------------------------------------------------------- - -- CONFIG - ------------------------------------------------------------------------- - nb_data_by_buffer => nb_word_by_buffer, + -- addr_data_f0 => addr_data_f0, + -- addr_data_f1 => addr_data_f1, + -- addr_data_f2 => addr_data_f2, + -- addr_data_f3 => addr_data_f3, + -- ------------------------------------------------------------------------- + -- -- CTRL + -- ------------------------------------------------------------------------- + -- -- IN + -- empty => empty, + -- empty_almost => empty_almost, + -- data_ren => data_ren, + + -- ------------------------------------------------------------------------- + -- -- STATUS + -- ------------------------------------------------------------------------- + -- status_full => status_full_s, + -- status_full_ack => status_full_ack, + -- status_full_err => status_full_err, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3, - ------------------------------------------------------------------------- - -- CTRL - ------------------------------------------------------------------------- - -- IN - empty => empty, - empty_almost => empty_almost, - data_ren => data_ren, + -- ------------------------------------------------------------------------- + -- -- ADDR DATA OUT + -- ------------------------------------------------------------------------- + -- data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, + -- data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, + -- data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, + -- data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, - ------------------------------------------------------------------------- - -- STATUS - ------------------------------------------------------------------------- - status_full => status_full_s, - status_full_ack => status_full_ack, - status_full_err => status_full_err, + -- data_f0_data_out_valid => data_f0_data_out_valid, + -- data_f1_data_out_valid => data_f1_data_out_valid, + -- data_f2_data_out_valid => data_f2_data_out_valid, + -- data_f3_data_out_valid => data_f3_data_out_valid, + + -- data_f0_addr_out => data_f0_addr_out, + -- data_f1_addr_out => data_f1_addr_out, + -- data_f2_addr_out => data_f2_addr_out, + -- data_f3_addr_out => data_f3_addr_out + -- ); + --status_full <= status_full_s; + - ------------------------------------------------------------------------- - -- ADDR DATA OUT - ------------------------------------------------------------------------- - data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, - data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, - data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, - data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + + all_channel: FOR I IN 3 DOWNTO 0 GENERATE + lpp_waveform_fsmdma_I: lpp_waveform_fsmdma + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO + + fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I), + fifo_empty => empty(I), + fifo_empty_threshold => empty_almost(I), + fifo_ren => data_ren(I), + + dma_fifo_valid_burst => dma_fifo_valid_burst(I), + dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I), + dma_fifo_ren => dma_fifo_ren(I), + dma_buffer_new => dma_buffer_new(I), + dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I), + dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I), + dma_buffer_full => dma_buffer_full(I), + dma_buffer_full_err => dma_buffer_full_err(I), + + status_buffer_ready => status_buffer_ready(I), -- TODO + addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO + length_buffer => length_buffer(26*(I+1)-1 DOWNTO 26*I), -- TODO + ready_buffer => ready_buffer(I), -- TODO + buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO + error_buffer_full => error_buffer_full(I)); -- TODO + + END GENERATE all_channel; - data_f0_data_out_valid => data_f0_data_out_valid, - data_f1_data_out_valid => data_f1_data_out_valid, - data_f2_data_out_valid => data_f2_data_out_valid, - data_f3_data_out_valid => data_f3_data_out_valid, - - data_f0_addr_out => data_f0_addr_out, - data_f1_addr_out => data_f1_addr_out, - data_f2_addr_out => data_f2_addr_out, - data_f3_addr_out => data_f3_addr_out - ); - status_full <= status_full_s; END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -372,5 +372,31 @@ PACKAGE lpp_waveform_pkg IS data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)); END COMPONENT; + + COMPONENT lpp_waveform_fsmdma + PORT ( + clk : IN STD_ULOGIC; + rstn : IN STD_ULOGIC; + run : IN STD_LOGIC; + fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fifo_empty : IN STD_LOGIC; + fifo_empty_threshold : IN STD_LOGIC; + fifo_ren : OUT STD_LOGIC; + dma_fifo_valid_burst : OUT STD_LOGIC; + dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC; + dma_buffer_new : OUT STD_LOGIC; + dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC; + dma_buffer_full_err : IN STD_LOGIC; + status_buffer_ready : IN STD_LOGIC; + addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + ready_buffer : OUT STD_LOGIC; + buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + error_buffer_full : OUT STD_LOGIC); + END COMPONENT; END lpp_waveform_pkg;