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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
5 ENTITY fine_time_max_value_gen IS
6
7 PORT (
8 clk : IN STD_LOGIC;
9 rstn : IN STD_LOGIC;
10 tick : IN STD_LOGIC;
11 fine_time_add : IN STD_LOGIC;
12 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
13 );
14
15 END fine_time_max_value_gen;
16
17 ARCHITECTURE beh OF fine_time_max_value_gen IS
18
19 SIGNAL count_even : STD_LOGIC;
20 SIGNAL count_first : STD_LOGIC;
21 SIGNAL count_modulo_33 : STD_LOGIC;
22
23
24 SIGNAL count_33 : INTEGER range 0 TO 32;
25
26 BEGIN -- beh
27
28 fine_time_max_value <= STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_first = '1' ELSE
29 STD_LOGIC_VECTOR(to_unsigned(380,9)) WHEN count_even = count_modulo_33 ELSE
30 STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_even = '1' ELSE
31 STD_LOGIC_VECTOR(to_unsigned(379,9)) WHEN count_modulo_33 = '1' ELSE
32 STD_LOGIC_VECTOR(to_unsigned(380,9));
33
34
35
36 PROCESS (clk, rstn)
37 BEGIN -- PROCESS
38 IF rstn = '0' THEN -- asynchronous reset (active low)
39 count_first <= '1';
40 count_even <= '0';
41 count_modulo_33 <= '0';
42 count_33 <= 0;
43 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
44 IF tick = '1' THEN
45 count_even <= '0';
46 count_first <= '1';
47 count_modulo_33 <= '0';
48 count_33 <= 0;
49 ELSE
50 IF fine_time_add = '1' THEN
51 count_first <= '0';
52 IF count_even = '1' THEN
53 count_even <= '0';
54 ELSE
55 count_even <= '1';
56 END IF;
57 IF count_33 = 31 THEN
58 count_modulo_33 <= '1';
59 ELSE
60 count_modulo_33 <= '0';
61 END IF;
62
63 IF count_33 = 32 THEN
64 count_33 <= 0;
65 ELSE
66 count_33 <= count_33 + 1;
67 END IF;
68 END IF;
69 END IF;
70 END IF;
71 END PROCESS;
72
73 END beh;
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1 1 # use glob syntax.
2 2 syntax: glob
3 3
4 4 *.tex
5 5 *.html
6 6 *log*
7 7 *.png
8 8 *.dot
9 9 *.css
10 10 *.md5
11 11 *.eps
12 12 *.pdf
13 13 *.toc
14 14 *.map
15 15 *.sty
16 16 *.3
17 17 *.js
18 18 *.aux
19 19 *.idx
20 20 *doc*
21 21 *Doc*
22 22 *vhdlsyn.txt
23 23 *dirs.txt
24 24 *.orig
25 25 *.o
26 26 *.a
27 27 *.bin
28 28 *~
29 29 apb_devices_list.h
30 30 apb_devices_list.vhd
31 31 twiddle.vhd
32 32 primitives.vhd
33 33 fftSm.vhd
34 34 fftDp.vhd
35 35 fft_components.vhd
36 36 CoreFFT.vhd
37 37 actram.vhd
38 actar.vhd No newline at end of file
38 actar.vhd
39 *.bak
40 *.pdc.ce
41 *.zip
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@@ -1,124 +1,124
1 1 #set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout
4 4
5 5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
6 6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
7 7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
8 8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
9 9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
10 10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
11 11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
12 12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
14 14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
15 15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
16 16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
17 17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
18 18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
19 19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
20 20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
21 21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
22 22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
23 23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
24 24
25 25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
26 26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
27 27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
28 28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
29 29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
30 30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
31 31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
32 32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
33 33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
34 34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
35 35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
36 36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
37 37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
38 38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
39 39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
40 40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
41 41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
42 42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
44 44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
45 45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
46 46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
47 47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
48 48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
49 49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
50 50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
51 51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
52 52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
53 53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
54 54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
55 55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
56 56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
57 57
58 58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
59 59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
60 60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
61 61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
62 62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
63 63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
64 64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
65 65
66 66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
67 67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
68 68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
69 69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71 71
72 72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
73 73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
74 74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
75 75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
76 76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
77 77
78 78 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
79 79 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
80 80 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
81 81 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
82 82 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
83 set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
84 set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
85 85 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
86 86 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
87 87
88 88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
89 89
90 90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
91 91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
92 92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
93 93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
94 94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
95 95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
96 96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
97 97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
98 98
99 99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
100 100
101 101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
102 102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
103 103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
104 104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
105 105
106 106 #set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
107 107 #set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
108 108 #set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
109 109 #set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
110 110 #set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
111 111 #set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
112 112 #set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
113 113 #set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
114 114 #set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
115 115 #set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
116 116 #set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
117 117 #set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
118 118 #set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
119 119 #set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
120 120
121 121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
122 122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
123 123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
124 124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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@@ -1,39 +1,40
1 1 # Top Level Design Parameters
2 2
3 3 # Clocks
4 4
5 5 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
6 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25
6 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
7
7 8
9
10 #create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25
8 11 #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q}
9
10 #create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
11 12 #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
12 13 #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
13 14
14 15
15 16 # False Paths Between Clocks
16 17
17 18
18 19 # False Path Constraints
19 20
20 21
21 22 # Maximum Delay Constraints
22 23
23 24 # Multicycle Constraints
24 25
25 26
26 27 # Virtual Clocks
27 28 # Output Load Constraints
28 29 # Driving Cell Constraints
29 30 # Wire Loads
30 31 # set_wire_load_mode top
31 32
32 33 # Other Constraints
33 34
34 35
35 36 ## GRSPW constraints
36 37 create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}
37 38 create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}
38 39 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y]
39 40 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y]
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@@ -1,465 +1,468
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 library proasic3l;
49 49 use proasic3l.all;
50 50
51 51 ENTITY LFR_EQM IS
52 GENERIC (
53 Mem_use : INTEGER := use_RAM);
52 54
53 55 PORT (
54 56 clk50MHz : IN STD_ULOGIC;
55 57 clk49_152MHz : IN STD_ULOGIC;
56 58 reset : IN STD_ULOGIC;
57 59
58 60 -- TAG --------------------------------------------------------------------
59 61 TAG1 : IN STD_ULOGIC; -- DSU rx data
60 62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
61 63 -- UART APB ---------------------------------------------------------------
62 64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
63 65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
64 66 -- RAM --------------------------------------------------------------------
65 67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
66 68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67 69
68 70 nSRAM_MBE : INOUT STD_LOGIC; -- new
69 71 nSRAM_E1 : OUT STD_LOGIC; -- new
70 72 nSRAM_E2 : OUT STD_LOGIC; -- new
71 73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
72 74 nSRAM_W : OUT STD_LOGIC; -- new
73 75 nSRAM_G : OUT STD_LOGIC; -- new
74 76 nSRAM_BUSY : IN STD_LOGIC; -- new
75 77 -- SPW --------------------------------------------------------------------
76 78 spw1_en : OUT STD_LOGIC; -- new
77 79 spw1_din : IN STD_LOGIC;
78 80 spw1_sin : IN STD_LOGIC;
79 81 spw1_dout : OUT STD_LOGIC;
80 82 spw1_sout : OUT STD_LOGIC;
81 83 spw2_en : OUT STD_LOGIC; -- new
82 84 spw2_din : IN STD_LOGIC;
83 85 spw2_sin : IN STD_LOGIC;
84 86 spw2_dout : OUT STD_LOGIC;
85 87 spw2_sout : OUT STD_LOGIC;
86 88 -- ADC --------------------------------------------------------------------
87 89 bias_fail_sw : OUT STD_LOGIC;
88 90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
89 91 ADC_smpclk : OUT STD_LOGIC;
90 92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
91 93 -- DAC --------------------------------------------------------------------
92 94 DAC_SDO : OUT STD_LOGIC;
93 95 DAC_SCK : OUT STD_LOGIC;
94 96 DAC_SYNC : OUT STD_LOGIC;
95 97 DAC_CAL_EN : OUT STD_LOGIC;
96 98 -- HK ---------------------------------------------------------------------
97 99 HK_smpclk : OUT STD_LOGIC;
98 100 ADC_OEB_bar_HK : OUT STD_LOGIC;
99 101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
100 102 ---------------------------------------------------------------------------
101 103 TAG8 : OUT STD_LOGIC
102 104 );
103 105
104 106 END LFR_EQM;
105 107
106 108
107 109 ARCHITECTURE beh OF LFR_EQM IS
108 110
109 111 SIGNAL clk_25 : STD_LOGIC := '0';
110 112 SIGNAL clk_24 : STD_LOGIC := '0';
111 113 -----------------------------------------------------------------------------
112 114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
114 116
115 117 -- CONSTANTS
116 118 CONSTANT CFG_PADTECH : INTEGER := inferred;
117 119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
118 120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
119 121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
120 122
121 123 SIGNAL apbi_ext : apb_slv_in_type;
122 124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
123 125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
124 126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
125 127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
126 128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
127 129
128 130 -- Spacewire signals
129 131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
131 133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 134 SIGNAL spw_rxtxclk : STD_ULOGIC;
133 135 SIGNAL spw_rxclkn : STD_ULOGIC;
134 136 SIGNAL spw_clk : STD_LOGIC;
135 137 SIGNAL swni : grspw_in_type;
136 138 SIGNAL swno : grspw_out_type;
137 139
138 140 --GPIO
139 141 SIGNAL gpioi : gpio_in_type;
140 142 SIGNAL gpioo : gpio_out_type;
141 143
142 144 -- AD Converter ADS7886
143 145 SIGNAL sample : Samples14v(8 DOWNTO 0);
144 146 SIGNAL sample_s : Samples(8 DOWNTO 0);
145 147 SIGNAL sample_val : STD_LOGIC;
146 148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
147 149
148 150 -----------------------------------------------------------------------------
149 151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 152
151 153 -----------------------------------------------------------------------------
152 154 SIGNAL rstn_25 : STD_LOGIC;
153 155 SIGNAL rstn_24 : STD_LOGIC;
154 156
155 157 SIGNAL LFR_soft_rstn : STD_LOGIC;
156 158 SIGNAL LFR_rstn : STD_LOGIC;
157 159
158 160 SIGNAL ADC_smpclk_s : STD_LOGIC;
159 161
160 162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
161 163
162 164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
163 165 SIGNAL clk_25_int : STD_LOGIC := '0';
164 166
165 167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
166 168
167 169 BEGIN -- beh
168 170
169 171 -----------------------------------------------------------------------------
170 172 -- CLK
171 173 -----------------------------------------------------------------------------
172 174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
173 175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
174 176
175 177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
176 178 clk50MHz_int <= clk50MHz;
177 179
178 180 PROCESS(clk50MHz_int)
179 181 BEGIN
180 182 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
181 183 --clk_25_int <= NOT clk_25_int;
182 184 clk_25 <= NOT clk_25;
183 185 END IF;
184 186 END PROCESS;
185 187 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
186 188
187 189 PROCESS(clk49_152MHz)
188 190 BEGIN
189 191 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
190 192 clk_24 <= NOT clk_24;
191 193 END IF;
192 194 END PROCESS;
193 195
194 196 -----------------------------------------------------------------------------
195 197 --
196 198 leon3_soc_1 : leon3_soc
197 199 GENERIC MAP (
198 200 fabtech => apa3e,
199 201 memtech => apa3e,
200 202 padtech => inferred,
201 203 clktech => inferred,
202 204 disas => 0,
203 205 dbguart => 0,
204 206 pclow => 2,
205 207 clk_freq => 25000,
206 208 IS_RADHARD => 0,
207 209 NB_CPU => 1,
208 210 ENABLE_FPU => 1,
209 211 FPU_NETLIST => 0,
210 212 ENABLE_DSU => 1,
211 213 ENABLE_AHB_UART => 1,
212 214 ENABLE_APB_UART => 1,
213 215 ENABLE_IRQMP => 1,
214 216 ENABLE_GPT => 1,
215 217 NB_AHB_MASTER => NB_AHB_MASTER,
216 218 NB_AHB_SLAVE => NB_AHB_SLAVE,
217 219 NB_APB_SLAVE => NB_APB_SLAVE,
218 220 ADDRESS_SIZE => 19,
219 USES_IAP_MEMCTRLR => 1)
221 USES_IAP_MEMCTRLR => 1,
222 BYPASS_EDAC_MEMCTRLR => '1')
220 223 PORT MAP (
221 224 clk => clk_25,
222 225 reset => rstn_25,
223 226 errorn => OPEN,
224 227
225 228 ahbrxd => TAG1,
226 229 ahbtxd => TAG3,
227 230 urxd1 => TAG2,
228 231 utxd1 => TAG4,
229 232
230 233 address => address,
231 234 data => data,
232 235 nSRAM_BE0 => OPEN,
233 236 nSRAM_BE1 => OPEN,
234 237 nSRAM_BE2 => OPEN,
235 238 nSRAM_BE3 => OPEN,
236 239 nSRAM_WE => nSRAM_W,
237 240 nSRAM_CE => nSRAM_CE,
238 241 nSRAM_OE => nSRAM_G,
239 242 nSRAM_READY => nSRAM_BUSY,
240 243 SRAM_MBE => nSRAM_MBE,
241 244
242 245 apbi_ext => apbi_ext,
243 246 apbo_ext => apbo_ext,
244 247 ahbi_s_ext => ahbi_s_ext,
245 248 ahbo_s_ext => ahbo_s_ext,
246 249 ahbi_m_ext => ahbi_m_ext,
247 250 ahbo_m_ext => ahbo_m_ext);
248 251
249 252
250 253 nSRAM_E1 <= nSRAM_CE(0);
251 254 nSRAM_E2 <= nSRAM_CE(1);
252 255
253 256 -------------------------------------------------------------------------------
254 257 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
255 258 -------------------------------------------------------------------------------
256 259 apb_lfr_management_1 : apb_lfr_management
257 260 GENERIC MAP (
258 261 tech => apa3e,
259 262 pindex => 6,
260 263 paddr => 6,
261 264 pmask => 16#fff#,
262 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
265 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
263 266 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
264 267 PORT MAP (
265 268 clk25MHz => clk_25,
266 269 resetn_25MHz => rstn_25, -- TODO
267 clk24_576MHz => clk_24, -- 49.152MHz/2
268 resetn_24_576MHz => rstn_24, -- TODO
270 --clk24_576MHz => clk_24, -- 49.152MHz/2
271 --resetn_24_576MHz => rstn_24, -- TODO
269 272
270 273 grspw_tick => swno.tickout,
271 274 apbi => apbi_ext,
272 275 apbo => apbo_ext(6),
273 276
274 277 HK_sample => sample_s(8),
275 278 HK_val => sample_val,
276 279 HK_sel => HK_SEL,
277 280
278 281 DAC_SDO => DAC_SDO,
279 282 DAC_SCK => DAC_SCK,
280 283 DAC_SYNC => DAC_SYNC,
281 284 DAC_CAL_EN => DAC_CAL_EN,
282 285
283 286 coarse_time => coarse_time,
284 287 fine_time => fine_time,
285 288 LFR_soft_rstn => LFR_soft_rstn
286 289 );
287 290
288 291 -----------------------------------------------------------------------
289 292 --- SpaceWire --------------------------------------------------------
290 293 -----------------------------------------------------------------------
291 294
292 295 ------------------------------------------------------------------------------
293 296 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
294 297 ------------------------------------------------------------------------------
295 298 spw1_en <= '1';
296 299 spw2_en <= '1';
297 300 ------------------------------------------------------------------------------
298 301 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
299 302 ------------------------------------------------------------------------------
300 303
301 304 --spw_clk <= clk50MHz;
302 305 --spw_rxtxclk <= spw_clk;
303 306 --spw_rxclkn <= NOT spw_rxtxclk;
304 307
305 308 -- PADS for SPW1
306 309 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
307 310 PORT MAP (spw1_din, dtmp(0));
308 311 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
309 312 PORT MAP (spw1_sin, stmp(0));
310 313 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
311 314 PORT MAP (spw1_dout, swno.d(0));
312 315 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
313 316 PORT MAP (spw1_sout, swno.s(0));
314 317 -- PADS FOR SPW2
315 318 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
316 319 PORT MAP (spw2_din, dtmp(1));
317 320 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
318 321 PORT MAP (spw2_sin, stmp(1));
319 322 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
320 323 PORT MAP (spw2_dout, swno.d(1));
321 324 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
322 325 PORT MAP (spw2_sout, swno.s(1));
323 326
324 327 -- GRSPW PHY
325 328 --spw1_input: if CFG_SPW_GRSPW = 1 generate
326 329 spw_inputloop : FOR j IN 0 TO 1 GENERATE
327 330 spw_phy0 : grspw_phy
328 331 GENERIC MAP(
329 332 tech => apa3e,
330 333 rxclkbuftype => 1,
331 334 scantest => 0)
332 335 PORT MAP(
333 336 rxrst => swno.rxrst,
334 337 di => dtmp(j),
335 338 si => stmp(j),
336 339 rxclko => spw_rxclk(j),
337 340 do => swni.d(j),
338 341 ndo => swni.nd(j*5+4 DOWNTO j*5),
339 342 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
340 343 END GENERATE spw_inputloop;
341 344
342 345 -- SPW core
343 346 sw0 : grspwm GENERIC MAP(
344 347 tech => apa3e,
345 348 hindex => 1,
346 349 pindex => 5,
347 350 paddr => 5,
348 351 pirq => 11,
349 352 sysfreq => 25000, -- CPU_FREQ
350 353 rmap => 1,
351 354 rmapcrc => 1,
352 355 fifosize1 => 16,
353 356 fifosize2 => 16,
354 357 rxclkbuftype => 1,
355 358 rxunaligned => 0,
356 359 rmapbufs => 4,
357 360 ft => 0,
358 361 netlist => 0,
359 362 ports => 2,
360 363 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
361 364 memtech => apa3e,
362 365 destkey => 2,
363 366 spwcore => 1
364 367 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
365 368 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
366 369 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
367 370 )
368 371 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
369 372 spw_rxclk(1),
370 373 clk50MHz_int,
371 374 clk50MHz_int,
372 375 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
373 376 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
374 377 swni, swno);
375 378
376 379 swni.tickin <= '0';
377 380 swni.rmapen <= '1';
378 381 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
379 382 swni.tickinraw <= '0';
380 383 swni.timein <= (OTHERS => '0');
381 384 swni.dcrstval <= (OTHERS => '0');
382 385 swni.timerrstval <= (OTHERS => '0');
383 386
384 387 -------------------------------------------------------------------------------
385 388 -- LFR ------------------------------------------------------------------------
386 389 -------------------------------------------------------------------------------
387 390 LFR_rstn <= LFR_soft_rstn AND rstn_25;
388 391
389 392 lpp_lfr_1 : lpp_lfr
390 393 GENERIC MAP (
391 Mem_use => use_RAM,
394 Mem_use => Mem_use,
392 395 nb_data_by_buffer_size => 32,
393 396 --nb_word_by_buffer_size => 30,
394 397 nb_snapshot_param_size => 32,
395 398 delta_vector_size => 32,
396 399 delta_vector_size_f0_2 => 7, -- log2(96)
397 400 pindex => 15,
398 401 paddr => 15,
399 402 pmask => 16#fff#,
400 403 pirq_ms => 6,
401 404 pirq_wfp => 14,
402 405 hindex => 2,
403 406 top_lfr_version => X"020144") -- aa.bb.cc version
404 407 -- AA : BOARD NUMBER
405 408 -- 0 => MINI_LFR
406 409 -- 1 => EM
407 410 -- 2 => EQM (with A3PE3000)
408 411 PORT MAP (
409 412 clk => clk_25,
410 413 rstn => LFR_rstn,
411 414 sample_B => sample_s(2 DOWNTO 0),
412 415 sample_E => sample_s(7 DOWNTO 3),
413 416 sample_val => sample_val,
414 417 apbi => apbi_ext,
415 418 apbo => apbo_ext(15),
416 419 ahbi => ahbi_m_ext,
417 420 ahbo => ahbo_m_ext(2),
418 421 coarse_time => coarse_time,
419 422 fine_time => fine_time,
420 423 data_shaping_BW => bias_fail_sw,
421 424 debug_vector => OPEN,
422 425 debug_vector_ms => OPEN); --,
423 426 --observation_vector_0 => OPEN,
424 427 --observation_vector_1 => OPEN,
425 428 --observation_reg => observation_reg);
426 429
427 430
428 431 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
429 432 sample_s(I) <= sample(I) & '0' & '0';
430 433 END GENERATE all_sample;
431 434 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
432 435
433 436 -----------------------------------------------------------------------------
434 437 --
435 438 -----------------------------------------------------------------------------
436 439 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
437 440 GENERIC MAP (
438 441 ChanelCount => 9,
439 442 ncycle_cnv_high => 13,
440 443 ncycle_cnv => 25,
441 444 FILTER_ENABLED => 16#FF#)
442 445 PORT MAP (
443 446 cnv_clk => clk_24,
444 447 cnv_rstn => rstn_24,
445 448 cnv => ADC_smpclk_s,
446 449 clk => clk_25,
447 450 rstn => rstn_25,
448 451 ADC_data => ADC_data,
449 452 ADC_nOE => ADC_OEB_bar_CH_s,
450 453 sample => sample,
451 454 sample_val => sample_val);
452 455
453 456 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
454 457
455 458 ADC_smpclk <= ADC_smpclk_s;
456 459 HK_smpclk <= ADC_smpclk_s;
457 460
458 461 TAG8 <= nSRAM_BUSY;
459 462
460 463 -----------------------------------------------------------------------------
461 464 -- HK
462 465 -----------------------------------------------------------------------------
463 466 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
464 467
465 468 END beh;
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@@ -1,55 +1,55
1 1 #GRLIB=../..
2 2 VHDLIB=../..
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=LFR_EQM
6 6 BOARD=LFR-EQM
7 7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 11 EFFORT=high
12 12 XSTOPT=
13 13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 16 VHDLSYNFILES=LFR-EQM.vhd
17 17 VHDLSIMFILES=testbench.vhd
18 18 #SIMTOP=testbench
19 19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
20 20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
21 21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
22 22
23 23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
24 24 CLEAN=soft-clean
25 25
26 TECHLIBS = proasic3e
26 TECHLIBS = proasic3l
27 27
28 28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
29 29 tmtc openchip hynix ihp gleichmann micron usbhc
30 30
31 31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
32 32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
33 33 ./amba_lcd_16x2_ctrlr \
34 34 ./general_purpose/lpp_AMR \
35 35 ./general_purpose/lpp_balise \
36 36 ./general_purpose/lpp_delay \
37 37 ./lpp_bootloader \
38 38 ./dsp/lpp_fft_rtax \
39 39 ./lpp_uart \
40 40 ./lpp_usb \
41 41 ./lpp_sim/CY7C1061DV33 \
42 42
43 43 FILESKIP = i2cmst.vhd \
44 44 APB_MULTI_DIODE.vhd \
45 45 APB_MULTI_DIODE.vhd \
46 46 Top_MatrixSpec.vhd \
47 47 APB_FFT.vhd\
48 48 CoreFFT_simu.vhd \
49 49 lpp_lfr_apbreg_simu.vhd
50 50
51 51 include $(GRLIB)/bin/Makefile
52 52 include $(GRLIB)/software/leon3/Makefile
53 53
54 54 ################## project specific targets ##########################
55 55
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@@ -1,740 +1,757
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116
117 --==========================================================================
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 -- when enabled, chip enable polarity should be reversed and bank size also
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 --==========================================================================
125
116 126 SIGNAL clk_50_s : STD_LOGIC := '0';
117 127 SIGNAL clk_25 : STD_LOGIC := '0';
118 128 SIGNAL clk_24 : STD_LOGIC := '0';
119 129 -----------------------------------------------------------------------------
120 130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 132 --
123 133 SIGNAL errorn : STD_LOGIC;
124 134 -- UART AHB ---------------------------------------------------------------
125 135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 137
128 138 -- UART APB ---------------------------------------------------------------
129 139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 141 --
132 142 SIGNAL I00_s : STD_LOGIC;
133 143
134 144 -- CONSTANTS
135 145 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 146 --
137 147 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 148 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 149 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 150
141 151 SIGNAL apbi_ext : apb_slv_in_type;
142 152 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 153 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 154 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 155 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 156 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 157
148 158 -- Spacewire signals
149 159 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 160 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 161 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 162 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 163 SIGNAL spw_rxclkn : STD_ULOGIC;
154 164 SIGNAL spw_clk : STD_LOGIC;
155 165 SIGNAL swni : grspw_in_type;
156 166 SIGNAL swno : grspw_out_type;
157 167 -- SIGNAL clkmn : STD_ULOGIC;
158 168 -- SIGNAL txclk : STD_ULOGIC;
159 169
160 170 --GPIO
161 171 SIGNAL gpioi : gpio_in_type;
162 172 SIGNAL gpioo : gpio_out_type;
163 173
164 174 -- AD Converter ADS7886
165 175 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 176 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 177 SIGNAL sample_val : STD_LOGIC;
168 178 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 179 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 180 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 181
172 182 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 183
174 184 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 185 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 186 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 187 -----------------------------------------------------------------------------
178 188
179 189 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 190 SIGNAL LFR_rstn : STD_LOGIC;
181 191
182 192
183 193 SIGNAL rstn_25 : STD_LOGIC;
184 194 SIGNAL rstn_25_d1 : STD_LOGIC;
185 195 SIGNAL rstn_25_d2 : STD_LOGIC;
186 196 SIGNAL rstn_25_d3 : STD_LOGIC;
187 197
188 198 SIGNAL rstn_24 : STD_LOGIC;
189 199 SIGNAL rstn_24_d1 : STD_LOGIC;
190 200 SIGNAL rstn_24_d2 : STD_LOGIC;
191 201 SIGNAL rstn_24_d3 : STD_LOGIC;
192 202
193 203 SIGNAL rstn_50 : STD_LOGIC;
194 204 SIGNAL rstn_50_d1 : STD_LOGIC;
195 205 SIGNAL rstn_50_d2 : STD_LOGIC;
196 206 SIGNAL rstn_50_d3 : STD_LOGIC;
197 207
198 208 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
199 209 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
200 210
201 211 --
202 212 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 213
204 214 --
205 215 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
206 216 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
207 217
208 218 BEGIN -- beh
209 219
210 220 -----------------------------------------------------------------------------
211 221 -- CLK
212 222 -----------------------------------------------------------------------------
213 223
214 224 --PROCESS(clk_50)
215 225 --BEGIN
216 226 -- IF clk_50'EVENT AND clk_50 = '1' THEN
217 227 -- clk_50_s <= NOT clk_50_s;
218 228 -- END IF;
219 229 --END PROCESS;
220 230
221 231 --PROCESS(clk_50_s)
222 232 --BEGIN
223 233 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
224 234 -- clk_25 <= NOT clk_25;
225 235 -- END IF;
226 236 --END PROCESS;
227 237
228 238 --PROCESS(clk_49)
229 239 --BEGIN
230 240 -- IF clk_49'EVENT AND clk_49 = '1' THEN
231 241 -- clk_24 <= NOT clk_24;
232 242 -- END IF;
233 243 --END PROCESS;
234 244
235 245 --PROCESS(clk_25)
236 246 --BEGIN
237 247 -- IF clk_25'EVENT AND clk_25 = '1' THEN
238 248 -- rstn_25 <= reset;
239 249 -- END IF;
240 250 --END PROCESS;
241 251
242 252 PROCESS (clk_50, reset)
243 253 BEGIN -- PROCESS
244 254 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
245 255 clk_50_s <= NOT clk_50_s;
246 256 END IF;
247 257 END PROCESS;
248 258
249 259 PROCESS (clk_50_s, reset)
250 260 BEGIN -- PROCESS
251 261 IF reset = '0' THEN -- asynchronous reset (active low)
252 262 clk_25 <= '0';
253 263 rstn_25 <= '0';
254 264 rstn_25_d1 <= '0';
255 265 rstn_25_d2 <= '0';
256 266 rstn_25_d3 <= '0';
257 267 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
258 268 clk_25 <= NOT clk_25;
259 269 rstn_25_d1 <= '1';
260 270 rstn_25_d2 <= rstn_25_d1;
261 271 rstn_25_d3 <= rstn_25_d2;
262 272 rstn_25 <= rstn_25_d3;
263 273 END IF;
264 274 END PROCESS;
265 275
266 276 PROCESS (clk_49, reset)
267 277 BEGIN -- PROCESS
268 278 IF reset = '0' THEN -- asynchronous reset (active low)
269 279 clk_24 <= '0';
270 280 rstn_24_d1 <= '0';
271 281 rstn_24_d2 <= '0';
272 282 rstn_24_d3 <= '0';
273 283 rstn_24 <= '0';
274 284 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
275 285 clk_24 <= NOT clk_24;
276 286 rstn_24_d1 <= '1';
277 287 rstn_24_d2 <= rstn_24_d1;
278 288 rstn_24_d3 <= rstn_24_d2;
279 289 rstn_24 <= rstn_24_d3;
280 290 END IF;
281 291 END PROCESS;
282 292
283 293 -----------------------------------------------------------------------------
284 294
285 295 PROCESS (clk_25, rstn_25)
286 296 BEGIN -- PROCESS
287 297 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
288 298 LED0 <= '0';
289 299 LED1 <= '0';
290 300 LED2 <= '0';
291 301 --IO1 <= '0';
292 302 --IO2 <= '1';
293 303 --IO3 <= '0';
294 304 --IO4 <= '0';
295 305 --IO5 <= '0';
296 306 --IO6 <= '0';
297 307 --IO7 <= '0';
298 308 --IO8 <= '0';
299 309 --IO9 <= '0';
300 310 --IO10 <= '0';
301 311 --IO11 <= '0';
302 312 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
303 313 LED0 <= '0';
304 314 LED1 <= '1';
305 315 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
306 316 --IO1 <= '1';
307 317 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
308 318 --IO3 <= ADC_SDO(0);
309 319 --IO4 <= ADC_SDO(1);
310 320 --IO5 <= ADC_SDO(2);
311 321 --IO6 <= ADC_SDO(3);
312 322 --IO7 <= ADC_SDO(4);
313 323 --IO8 <= ADC_SDO(5);
314 324 --IO9 <= ADC_SDO(6);
315 325 --IO10 <= ADC_SDO(7);
316 326 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
317 327 END IF;
318 328 END PROCESS;
319 329
320 330 PROCESS (clk_24, rstn_24)
321 331 BEGIN -- PROCESS
322 332 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
323 333 I00_s <= '0';
324 334 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
325 335 I00_s <= NOT I00_s;
326 336 END IF;
327 337 END PROCESS;
328 338 -- IO0 <= I00_s;
329 339
330 340 --UARTs
331 341 nCTS1 <= '1';
332 342 nCTS2 <= '1';
333 343 nDCD2 <= '1';
334 344
335 345 --
336 346
337 347 leon3_soc_1 : leon3_soc
338 348 GENERIC MAP (
339 349 fabtech => apa3e,
340 350 memtech => apa3e,
341 351 padtech => inferred,
342 352 clktech => inferred,
343 353 disas => 0,
344 354 dbguart => 0,
345 355 pclow => 2,
346 356 clk_freq => 25000,
347 357 IS_RADHARD => 0,
348 358 NB_CPU => 1,
349 359 ENABLE_FPU => 1,
350 360 FPU_NETLIST => 0,
351 361 ENABLE_DSU => 1,
352 362 ENABLE_AHB_UART => 1,
353 363 ENABLE_APB_UART => 1,
354 364 ENABLE_IRQMP => 1,
355 365 ENABLE_GPT => 1,
356 366 NB_AHB_MASTER => NB_AHB_MASTER,
357 367 NB_AHB_SLAVE => NB_AHB_SLAVE,
358 368 NB_APB_SLAVE => NB_APB_SLAVE,
359 369 ADDRESS_SIZE => 20,
360 USES_IAP_MEMCTRLR => 0)
370 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
371 SRBANKSZ => 9)
361 372 PORT MAP (
362 373 clk => clk_25,
363 374 reset => rstn_25,
364 375 errorn => errorn,
365 376 ahbrxd => TXD1,
366 377 ahbtxd => RXD1,
367 378 urxd1 => TXD2,
368 379 utxd1 => RXD2,
369 380 address => SRAM_A,
370 381 data => SRAM_DQ,
371 382 nSRAM_BE0 => SRAM_nBE(0),
372 383 nSRAM_BE1 => SRAM_nBE(1),
373 384 nSRAM_BE2 => SRAM_nBE(2),
374 385 nSRAM_BE3 => SRAM_nBE(3),
375 386 nSRAM_WE => SRAM_nWE,
376 387 nSRAM_CE => SRAM_CE_s,
377 388 nSRAM_OE => SRAM_nOE,
378 nSRAM_READY => '0',
389 nSRAM_READY => '1',
379 390 SRAM_MBE => OPEN,
380 391 apbi_ext => apbi_ext,
381 392 apbo_ext => apbo_ext,
382 393 ahbi_s_ext => ahbi_s_ext,
383 394 ahbo_s_ext => ahbo_s_ext,
384 395 ahbi_m_ext => ahbi_m_ext,
385 396 ahbo_m_ext => ahbo_m_ext);
386 397
387 SRAM_CE <= SRAM_CE_s(0);
398 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
399 SRAM_CE <= not SRAM_CE_s(0);
400 END GENERATE;
401
402 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
403 SRAM_CE <= SRAM_CE_s(0);
404 END GENERATE;
388 405 -------------------------------------------------------------------------------
389 406 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
390 407 -------------------------------------------------------------------------------
391 408 apb_lfr_management_1 : apb_lfr_management
392 409 GENERIC MAP (
393 410 tech => apa3e,
394 411 pindex => 6,
395 412 paddr => 6,
396 413 pmask => 16#fff#,
397 414 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
398 415 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
399 416 PORT MAP (
400 417 clk25MHz => clk_25,
401 418 resetn_25MHz => rstn_25, -- TODO
402 419 clk24_576MHz => clk_24, -- 49.152MHz/2
403 420 resetn_24_576MHz => rstn_24, -- TODO
404 421 grspw_tick => swno.tickout,
405 422 apbi => apbi_ext,
406 423 apbo => apbo_ext(6),
407 424 HK_sample => sample_hk,
408 425 HK_val => sample_val,
409 426 HK_sel => HK_SEL,
410 427 DAC_SDO => OPEN,
411 428 DAC_SCK => OPEN,
412 429 DAC_SYNC => OPEN,
413 430 DAC_CAL_EN => OPEN,
414 431 coarse_time => coarse_time,
415 432 fine_time => fine_time,
416 433 LFR_soft_rstn => LFR_soft_rstn
417 434 );
418 435
419 436 -----------------------------------------------------------------------
420 437 --- SpaceWire --------------------------------------------------------
421 438 -----------------------------------------------------------------------
422 439
423 440 SPW_EN <= '1';
424 441
425 442 spw_clk <= clk_50_s;
426 443 spw_rxtxclk <= spw_clk;
427 444 spw_rxclkn <= NOT spw_rxtxclk;
428 445
429 446 -- PADS for SPW1
430 447 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
431 448 PORT MAP (SPW_NOM_DIN, dtmp(0));
432 449 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
433 450 PORT MAP (SPW_NOM_SIN, stmp(0));
434 451 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
435 452 PORT MAP (SPW_NOM_DOUT, swno.d(0));
436 453 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
437 454 PORT MAP (SPW_NOM_SOUT, swno.s(0));
438 455 -- PADS FOR SPW2
439 456 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
440 457 PORT MAP (SPW_RED_SIN, dtmp(1));
441 458 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
442 459 PORT MAP (SPW_RED_DIN, stmp(1));
443 460 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
444 461 PORT MAP (SPW_RED_DOUT, swno.d(1));
445 462 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
446 463 PORT MAP (SPW_RED_SOUT, swno.s(1));
447 464
448 465 -- GRSPW PHY
449 466 --spw1_input: if CFG_SPW_GRSPW = 1 generate
450 467 spw_inputloop : FOR j IN 0 TO 1 GENERATE
451 468 spw_phy0 : grspw_phy
452 469 GENERIC MAP(
453 470 tech => apa3e,
454 471 rxclkbuftype => 1,
455 472 scantest => 0)
456 473 PORT MAP(
457 474 rxrst => swno.rxrst,
458 475 di => dtmp(j),
459 476 si => stmp(j),
460 477 rxclko => spw_rxclk(j),
461 478 do => swni.d(j),
462 479 ndo => swni.nd(j*5+4 DOWNTO j*5),
463 480 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
464 481 END GENERATE spw_inputloop;
465 482
466 483 swni.rmapnodeaddr <= (OTHERS => '0');
467 484
468 485 -- SPW core
469 486 sw0 : grspwm GENERIC MAP(
470 487 tech => apa3e,
471 488 hindex => 1,
472 489 pindex => 5,
473 490 paddr => 5,
474 491 pirq => 11,
475 492 sysfreq => 25000, -- CPU_FREQ
476 493 rmap => 1,
477 494 rmapcrc => 1,
478 495 fifosize1 => 16,
479 496 fifosize2 => 16,
480 497 rxclkbuftype => 1,
481 498 rxunaligned => 0,
482 499 rmapbufs => 4,
483 500 ft => 0,
484 501 netlist => 0,
485 502 ports => 2,
486 503 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
487 504 memtech => apa3e,
488 505 destkey => 2,
489 506 spwcore => 1
490 507 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
491 508 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
492 509 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
493 510 )
494 511 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
495 512 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
496 513 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
497 514 swni, swno);
498 515
499 516 swni.tickin <= '0';
500 517 swni.rmapen <= '1';
501 518 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
502 519 swni.tickinraw <= '0';
503 520 swni.timein <= (OTHERS => '0');
504 521 swni.dcrstval <= (OTHERS => '0');
505 522 swni.timerrstval <= (OTHERS => '0');
506 523
507 524 -------------------------------------------------------------------------------
508 525 -- LFR ------------------------------------------------------------------------
509 526 -------------------------------------------------------------------------------
510 527
511 528
512 529 LFR_rstn <= LFR_soft_rstn AND rstn_25;
513 530 --LFR_rstn <= rstn_25;
514 531
515 532 lpp_lfr_1 : lpp_lfr
516 533 GENERIC MAP (
517 534 Mem_use => use_RAM,
518 535 nb_data_by_buffer_size => 32,
519 536 nb_snapshot_param_size => 32,
520 537 delta_vector_size => 32,
521 538 delta_vector_size_f0_2 => 7, -- log2(96)
522 539 pindex => 15,
523 540 paddr => 15,
524 541 pmask => 16#fff#,
525 542 pirq_ms => 6,
526 543 pirq_wfp => 14,
527 544 hindex => 2,
528 545 top_lfr_version => X"000144") -- aa.bb.cc version
529 546 PORT MAP (
530 547 clk => clk_25,
531 548 rstn => LFR_rstn,
532 549 sample_B => sample_s(2 DOWNTO 0),
533 550 sample_E => sample_s(7 DOWNTO 3),
534 551 sample_val => sample_val,
535 552 apbi => apbi_ext,
536 553 apbo => apbo_ext(15),
537 554 ahbi => ahbi_m_ext,
538 555 ahbo => ahbo_m_ext(2),
539 556 coarse_time => coarse_time,
540 557 fine_time => fine_time,
541 558 data_shaping_BW => bias_fail_sw_sig,
542 559 debug_vector => lfr_debug_vector,
543 560 debug_vector_ms => lfr_debug_vector_ms
544 561 );
545 562
546 563 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
547 564 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
548 565 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
549 566 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
550 567 IO0 <= rstn_25;
551 568 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
552 569 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
553 570 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
554 571 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
555 572 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
556 573 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
557 574 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
558 575
559 576 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
560 577 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
561 578 END GENERATE all_sample;
562 579
563 580 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
564 581 GENERIC MAP(
565 582 ChannelCount => 8,
566 583 SampleNbBits => 14,
567 584 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
568 585 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
569 586 PORT MAP (
570 587 -- CONV
571 588 cnv_clk => clk_24,
572 589 cnv_rstn => rstn_24,
573 590 cnv => ADC_nCS_sig,
574 591 -- DATA
575 592 clk => clk_25,
576 593 rstn => rstn_25,
577 594 sck => ADC_CLK_sig,
578 595 sdo => ADC_SDO_sig,
579 596 -- SAMPLE
580 597 sample => sample,
581 598 sample_val => sample_val);
582 599
583 600 --IO10 <= ADC_SDO_sig(5);
584 601 --IO9 <= ADC_SDO_sig(4);
585 602 --IO8 <= ADC_SDO_sig(3);
586 603
587 604 ADC_nCS <= ADC_nCS_sig;
588 605 ADC_CLK <= ADC_CLK_sig;
589 606 ADC_SDO_sig <= ADC_SDO;
590 607
591 608 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
592 609 "0010001000100010" WHEN HK_SEL = "01" ELSE
593 610 "0100010001000100" WHEN HK_SEL = "10" ELSE
594 611 (OTHERS => '0');
595 612
596 613
597 614 ----------------------------------------------------------------------
598 615 --- GPIO -----------------------------------------------------------
599 616 ----------------------------------------------------------------------
600 617
601 618 grgpio0 : grgpio
602 619 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
603 620 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
604 621
605 622 gpioi.sig_en <= (OTHERS => '0');
606 623 gpioi.sig_in <= (OTHERS => '0');
607 624 gpioi.din <= (OTHERS => '0');
608 625 --pio_pad_0 : iopad
609 626 -- GENERIC MAP (tech => CFG_PADTECH)
610 627 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
611 628 --pio_pad_1 : iopad
612 629 -- GENERIC MAP (tech => CFG_PADTECH)
613 630 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
614 631 --pio_pad_2 : iopad
615 632 -- GENERIC MAP (tech => CFG_PADTECH)
616 633 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
617 634 --pio_pad_3 : iopad
618 635 -- GENERIC MAP (tech => CFG_PADTECH)
619 636 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
620 637 --pio_pad_4 : iopad
621 638 -- GENERIC MAP (tech => CFG_PADTECH)
622 639 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
623 640 --pio_pad_5 : iopad
624 641 -- GENERIC MAP (tech => CFG_PADTECH)
625 642 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
626 643 --pio_pad_6 : iopad
627 644 -- GENERIC MAP (tech => CFG_PADTECH)
628 645 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
629 646 --pio_pad_7 : iopad
630 647 -- GENERIC MAP (tech => CFG_PADTECH)
631 648 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
632 649
633 650 PROCESS (clk_25, rstn_25)
634 651 BEGIN -- PROCESS
635 652 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
636 653 -- --IO0 <= '0';
637 654 -- IO1 <= '0';
638 655 -- IO2 <= '0';
639 656 -- IO3 <= '0';
640 657 -- IO4 <= '0';
641 658 -- IO5 <= '0';
642 659 -- IO6 <= '0';
643 660 -- IO7 <= '0';
644 661 IO8 <= '0';
645 662 IO9 <= '0';
646 663 IO10 <= '0';
647 664 IO11 <= '0';
648 665 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
649 666 CASE gpioo.dout(2 DOWNTO 0) IS
650 667 WHEN "011" =>
651 668 -- --IO0 <= observation_reg(0 );
652 669 -- IO1 <= observation_reg(1 );
653 670 -- IO2 <= observation_reg(2 );
654 671 -- IO3 <= observation_reg(3 );
655 672 -- IO4 <= observation_reg(4 );
656 673 -- IO5 <= observation_reg(5 );
657 674 -- IO6 <= observation_reg(6 );
658 675 -- IO7 <= observation_reg(7 );
659 676 IO8 <= observation_reg(8);
660 677 IO9 <= observation_reg(9);
661 678 IO10 <= observation_reg(10);
662 679 IO11 <= observation_reg(11);
663 680 WHEN "001" =>
664 681 -- --IO0 <= observation_reg(0 + 12);
665 682 -- IO1 <= observation_reg(1 + 12);
666 683 -- IO2 <= observation_reg(2 + 12);
667 684 -- IO3 <= observation_reg(3 + 12);
668 685 -- IO4 <= observation_reg(4 + 12);
669 686 -- IO5 <= observation_reg(5 + 12);
670 687 -- IO6 <= observation_reg(6 + 12);
671 688 -- IO7 <= observation_reg(7 + 12);
672 689 IO8 <= observation_reg(8 + 12);
673 690 IO9 <= observation_reg(9 + 12);
674 691 IO10 <= observation_reg(10 + 12);
675 692 IO11 <= observation_reg(11 + 12);
676 693 WHEN "010" =>
677 694 -- --IO0 <= observation_reg(0 + 12 + 12);
678 695 -- IO1 <= observation_reg(1 + 12 + 12);
679 696 -- IO2 <= observation_reg(2 + 12 + 12);
680 697 -- IO3 <= observation_reg(3 + 12 + 12);
681 698 -- IO4 <= observation_reg(4 + 12 + 12);
682 699 -- IO5 <= observation_reg(5 + 12 + 12);
683 700 -- IO6 <= observation_reg(6 + 12 + 12);
684 701 -- IO7 <= observation_reg(7 + 12 + 12);
685 702 IO8 <= '0';
686 703 IO9 <= '0';
687 704 IO10 <= '0';
688 705 IO11 <= '0';
689 706 WHEN "000" =>
690 707 -- --IO0 <= observation_vector_0(0 );
691 708 -- IO1 <= observation_vector_0(1 );
692 709 -- IO2 <= observation_vector_0(2 );
693 710 -- IO3 <= observation_vector_0(3 );
694 711 -- IO4 <= observation_vector_0(4 );
695 712 -- IO5 <= observation_vector_0(5 );
696 713 -- IO6 <= observation_vector_0(6 );
697 714 -- IO7 <= observation_vector_0(7 );
698 715 IO8 <= observation_vector_0(8);
699 716 IO9 <= observation_vector_0(9);
700 717 IO10 <= observation_vector_0(10);
701 718 IO11 <= observation_vector_0(11);
702 719 WHEN "100" =>
703 720 -- --IO0 <= observation_vector_1(0 );
704 721 -- IO1 <= observation_vector_1(1 );
705 722 -- IO2 <= observation_vector_1(2 );
706 723 -- IO3 <= observation_vector_1(3 );
707 724 -- IO4 <= observation_vector_1(4 );
708 725 -- IO5 <= observation_vector_1(5 );
709 726 -- IO6 <= observation_vector_1(6 );
710 727 -- IO7 <= observation_vector_1(7 );
711 728 IO8 <= observation_vector_1(8);
712 729 IO9 <= observation_vector_1(9);
713 730 IO10 <= observation_vector_1(10);
714 731 IO11 <= observation_vector_1(11);
715 732 WHEN OTHERS => NULL;
716 733 END CASE;
717 734
718 735 END IF;
719 736 END PROCESS;
720 737 -----------------------------------------------------------------------------
721 738 --
722 739 -----------------------------------------------------------------------------
723 740 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
724 741 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
725 742 apbo_ext(I) <= apb_none;
726 743 END GENERATE apbo_ext_not_used;
727 744 END GENERATE all_apbo_ext;
728 745
729 746
730 747 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
731 748 ahbo_s_ext(I) <= ahbs_none;
732 749 END GENERATE all_ahbo_ext;
733 750
734 751 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
735 752 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
736 753 ahbo_m_ext(I) <= ahbm_none;
737 754 END GENERATE ahbo_m_ext_not_used;
738 755 END GENERATE all_ahbo_m_ext;
739 756
740 757 END beh;
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@@ -1,517 +1,523
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:17:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: apb_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 30 USE lpp.lpp_lfr_management.ALL;
31 31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 32 USE lpp.lpp_cna.ALL;
33 33 LIBRARY techmap;
34 34 USE techmap.gencomp.ALL;
35 35
36 36
37 37 ENTITY apb_lfr_management IS
38 38
39 39 GENERIC(
40 40 tech : INTEGER := 0;
41 41 pindex : INTEGER := 0; --! APB slave index
42 42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
43 43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
44 FIRST_DIVISION : INTEGER := 374;
44 -- FIRST_DIVISION : INTEGER := 374;
45 45 NB_SECOND_DESYNC : INTEGER := 60
46 46 );
47 47
48 48 PORT (
49 49 clk25MHz : IN STD_LOGIC; --! Clock
50 50 resetn_25MHz : IN STD_LOGIC; --! Reset
51 clk24_576MHz : IN STD_LOGIC; --! secondary clock
52 resetn_24_576MHz : IN STD_LOGIC; --! Reset
51 -- clk24_576MHz : IN STD_LOGIC; --! secondary clock
52 -- resetn_24_576MHz : IN STD_LOGIC; --! Reset
53 53
54 54 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
55 55
56 56 apbi : IN apb_slv_in_type; --! APB slave input signals
57 57 apbo : OUT apb_slv_out_type; --! APB slave output signals
58 58 ---------------------------------------------------------------------------
59 59 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
60 60 HK_val : IN STD_LOGIC;
61 61 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
62 62 ---------------------------------------------------------------------------
63 63 DAC_SDO : OUT STD_LOGIC;
64 64 DAC_SCK : OUT STD_LOGIC;
65 65 DAC_SYNC : OUT STD_LOGIC;
66 66 DAC_CAL_EN : OUT STD_LOGIC;
67 67 ---------------------------------------------------------------------------
68 68 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
69 69 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
70 70 ---------------------------------------------------------------------------
71 71 LFR_soft_rstn : OUT STD_LOGIC
72 72 );
73 73
74 74 END apb_lfr_management;
75 75
76 76 ARCHITECTURE Behavioral OF apb_lfr_management IS
77 77
78 78 CONSTANT REVISION : INTEGER := 1;
79 79 CONSTANT pconfig : apb_config_type := (
80 80 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
81 81 1 => apb_iobar(paddr, pmask)
82 82 );
83 83
84 84 TYPE apb_lfr_time_management_Reg IS RECORD
85 85 ctrl : STD_LOGIC;
86 86 soft_reset : STD_LOGIC;
87 87 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
88 88 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
90 90 LFR_soft_reset : STD_LOGIC;
91 91 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 92 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 93 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
94 94 END RECORD;
95 95 SIGNAL r : apb_lfr_time_management_Reg;
96 96
97 97 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 SIGNAL force_tick : STD_LOGIC;
99 99 SIGNAL previous_force_tick : STD_LOGIC;
100 100 SIGNAL soft_tick : STD_LOGIC;
101 101
102 102 SIGNAL coarsetime_reg_updated : STD_LOGIC;
103 103 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
104 104
105 105 --SIGNAL coarse_time_new : STD_LOGIC;
106 106 SIGNAL coarse_time_new_49 : STD_LOGIC;
107 107 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 109
110 110 --SIGNAL fine_time_new : STD_LOGIC;
111 111 --SIGNAL fine_time_new_temp : STD_LOGIC;
112 112 SIGNAL fine_time_new_49 : STD_LOGIC;
113 113 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
114 114 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
115 115 SIGNAL tick : STD_LOGIC;
116 116 SIGNAL new_timecode : STD_LOGIC;
117 117 SIGNAL new_coarsetime : STD_LOGIC;
118 118
119 119 SIGNAL time_new_49 : STD_LOGIC;
120 120 SIGNAL time_new : STD_LOGIC;
121 121
122 122 -----------------------------------------------------------------------------
123 123 SIGNAL force_reset : STD_LOGIC;
124 124 SIGNAL previous_force_reset : STD_LOGIC;
125 125 SIGNAL soft_reset : STD_LOGIC;
126 126 SIGNAL soft_reset_sync : STD_LOGIC;
127 127 -----------------------------------------------------------------------------
128 128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 129
130 130 SIGNAL previous_fine_time_bit : STD_LOGIC;
131 131
132 132 SIGNAL rstn_LFR_TM : STD_LOGIC;
133 133
134 134 -----------------------------------------------------------------------------
135 135 -- DAC
136 136 -----------------------------------------------------------------------------
137 137 CONSTANT PRESZ : INTEGER := 8;
138 138 CONSTANT CPTSZ : INTEGER := 16;
139 139 CONSTANT datawidth : INTEGER := 18;
140 140 CONSTANT dacresolution : INTEGER := 12;
141 141 CONSTANT abits : INTEGER := 8;
142 142
143 143 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
144 144 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
145 145 SIGNAL Reload : STD_LOGIC;
146 146 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
147 147 SIGNAL WEN : STD_LOGIC;
148 148 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
149 149 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 150 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
151 151 SIGNAL INTERLEAVED : STD_LOGIC;
152 152 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 153 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
154 154
155 155 BEGIN
156 156
157 157 LFR_soft_rstn <= NOT r.LFR_soft_reset;
158 158
159 159 PROCESS(resetn_25MHz, clk25MHz)
160 160 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
161 161 BEGIN
162 162
163 163 IF resetn_25MHz = '0' THEN
164 164 Rdata <= (OTHERS => '0');
165 165 r.coarse_time_load <= (OTHERS => '0');
166 166 r.soft_reset <= '0';
167 167 r.ctrl <= '0';
168 168 r.LFR_soft_reset <= '1';
169 169
170 170 force_tick <= '0';
171 171 previous_force_tick <= '0';
172 172 soft_tick <= '0';
173 173
174 174 coarsetime_reg_updated <= '0';
175 175 --DAC
176 176 pre <= (OTHERS => '1');
177 177 N <= (OTHERS => '1');
178 178 Reload <= '1';
179 179 DATA_IN <= (OTHERS => '0');
180 180 WEN <= '1';
181 181 LOAD_ADDRESSN <= '1';
182 182 ADDRESS_IN <= (OTHERS => '1');
183 183 INTERLEAVED <= '0';
184 184 DAC_CFG <= (OTHERS => '0');
185 185 --
186 186 DAC_CAL_EN_s <= '0';
187 187 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
188 188 coarsetime_reg_updated <= '0';
189 189
190 190 force_tick <= r.ctrl;
191 191 previous_force_tick <= force_tick;
192 192 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
193 193 soft_tick <= '1';
194 194 ELSE
195 195 soft_tick <= '0';
196 196 END IF;
197 197
198 198 force_reset <= r.soft_reset;
199 199 previous_force_reset <= force_reset;
200 200 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
201 201 soft_reset <= '1';
202 202 ELSE
203 203 soft_reset <= '0';
204 204 END IF;
205 205
206 206 paddr := "000000";
207 207 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
208 208 Rdata <= (OTHERS => '0');
209 209
210 210 LOAD_ADDRESSN <= '1';
211 211 WEN <= '1';
212 212
213 213 IF apbi.psel(pindex) = '1' THEN
214 214 --APB READ OP
215 215 CASE paddr(7 DOWNTO 2) IS
216 216 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
217 217 Rdata(0) <= r.ctrl;
218 218 Rdata(1) <= r.soft_reset;
219 219 Rdata(2) <= r.LFR_soft_reset;
220 220 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
221 221 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
222 222 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
223 223 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
224 224 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
225 225 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
226 226 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
227 227 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
228 228 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
229 229 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
230 230 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
231 231 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
232 232 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
233 233 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
234 234 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
235 235 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
236 236 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
237 237 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
238 238 Rdata(3 DOWNTO 0) <= DAC_CFG;
239 239 Rdata(4) <= Reload;
240 240 Rdata(5) <= INTERLEAVED;
241 241 Rdata(6) <= DAC_CAL_EN_s;
242 242 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
243 243 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
244 244 Rdata(PRESZ-1 DOWNTO 0) <= pre;
245 245 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
246 246 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
247 247 Rdata(CPTSZ-1 DOWNTO 0) <= N;
248 248 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
249 249 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
250 250 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
251 251 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
252 252 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
253 253 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
254 254 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
255 255 WHEN OTHERS =>
256 256 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
257 257 END CASE;
258 258
259 259 --APB Write OP
260 260 IF (apbi.pwrite AND apbi.penable) = '1' THEN
261 261 CASE paddr(7 DOWNTO 2) IS
262 262 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
263 263 r.ctrl <= apbi.pwdata(0);
264 264 r.soft_reset <= apbi.pwdata(1);
265 265 r.LFR_soft_reset <= apbi.pwdata(2);
266 266 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
267 267 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
268 268 coarsetime_reg_updated <= '1';
269 269 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
270 270 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
271 271 Reload <= apbi.pwdata(4);
272 272 INTERLEAVED <= apbi.pwdata(5);
273 273 DAC_CAL_EN_s <= apbi.pwdata(6);
274 274 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
275 275 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
276 276 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
277 277 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
278 278 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
279 279 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
280 280 LOAD_ADDRESSN <= '0';
281 281 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
282 282 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
283 283 WEN <= '0';
284 284
285 285 WHEN OTHERS =>
286 286 NULL;
287 287 END CASE;
288 288 ELSE
289 289 IF r.ctrl = '1' THEN
290 290 r.ctrl <= '0';
291 291 END IF;
292 292 IF r.soft_reset = '1' THEN
293 293 r.soft_reset <= '0';
294 294 END IF;
295 295 END IF;
296 296
297 297 END IF;
298 298
299 299 END IF;
300 300 END PROCESS;
301 301
302 302 apbo.pirq <= (OTHERS => '0');
303 303 apbo.prdata <= Rdata;
304 304 apbo.pconfig <= pconfig;
305 305 apbo.pindex <= pindex;
306 306
307
308
309
310
311
312
313
314
315
316
317
318
319
307 320 -----------------------------------------------------------------------------
308 321 -- IN
309 322 coarse_time <= r.coarse_time;
310 323 fine_time <= r.fine_time;
311 324 coarsetime_reg <= r.coarse_time_load;
312 325 -----------------------------------------------------------------------------
313 326
314 327 -----------------------------------------------------------------------------
315 328 -- OUT
316 329 r.coarse_time <= coarse_time_s;
317 330 r.fine_time <= fine_time_s;
318 331 -----------------------------------------------------------------------------
319 332
320 333 -----------------------------------------------------------------------------
321 334 tick <= grspw_tick OR soft_tick;
322 335
323 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
324 GENERIC MAP (
325 NB_FF_OF_SYNC => 2)
326 PORT MAP (
327 clk_in => clk25MHz,
328 rstn_in => resetn_25MHz,
329 clk_out => clk24_576MHz,
330 rstn_out => resetn_24_576MHz,
331 sin => tick,
332 sout => new_timecode);
336 --SYNC_VALID_BIT_1 : SYNC_VALID_BIT
337 -- GENERIC MAP (
338 -- NB_FF_OF_SYNC => 2)
339 -- PORT MAP (
340 -- clk_in => clk25MHz,
341 -- rstn_in => resetn_25MHz,
342 -- clk_out => clk24_576MHz,
343 -- rstn_out => resetn_24_576MHz,
344 -- sin => tick,
345 -- sout => new_timecode);
346 new_timecode <= tick;
333 347
334 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
335 GENERIC MAP (
336 NB_FF_OF_SYNC => 2)
337 PORT MAP (
338 clk_in => clk25MHz,
339 rstn_in => resetn_25MHz,
340 clk_out => clk24_576MHz,
341 rstn_out => resetn_24_576MHz,
342 sin => coarsetime_reg_updated,
343 sout => new_coarsetime);
344
345 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
346 GENERIC MAP (
347 NB_FF_OF_SYNC => 2)
348 PORT MAP (
349 clk_in => clk25MHz,
350 rstn_in => resetn_25MHz,
351 clk_out => clk24_576MHz,
352 rstn_out => resetn_24_576MHz,
353 sin => soft_reset,
354 sout => soft_reset_sync);
355
356 -----------------------------------------------------------------------------
357 --SYNC_FF_1 : SYNC_FF
348 --SYNC_VALID_BIT_2 : SYNC_VALID_BIT
358 349 -- GENERIC MAP (
359 350 -- NB_FF_OF_SYNC => 2)
360 351 -- PORT MAP (
361 -- clk => clk25MHz,
362 -- rstn => resetn,
363 -- A => fine_time_new_49,
364 -- A_sync => fine_time_new_temp);
352 -- clk_in => clk25MHz,
353 -- rstn_in => resetn_25MHz,
354 -- clk_out => clk24_576MHz,
355 -- rstn_out => resetn_24_576MHz,
356 -- sin => coarsetime_reg_updated,
357 -- sout => new_coarsetime);
358
359 new_coarsetime <= coarsetime_reg_updated;
360
361 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
362 -- GENERIC MAP (
363 -- NB_FF_OF_SYNC => 2)
364 -- PORT MAP (
365 -- clk_in => clk25MHz,
366 -- rstn_in => resetn_25MHz,
367 -- clk_out => clk24_576MHz,
368 -- rstn_out => resetn_24_576MHz,
369 -- sin => soft_reset,
370 -- sout => soft_reset_sync);
371
365 372
366 --lpp_front_detection_1 : lpp_front_detection
367 -- PORT MAP (
368 -- clk => clk25MHz,
369 -- rstn => resetn,
370 -- sin => fine_time_new_temp,
371 -- sout => fine_time_new);
373 -----------------------------------------------------------------------------
374 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
372 375
373 376 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
374 377 -- GENERIC MAP (
375 378 -- NB_FF_OF_SYNC => 2)
376 379 -- PORT MAP (
377 380 -- clk_in => clk24_576MHz,
381 -- rstn_in => resetn_24_576MHz,
378 382 -- clk_out => clk25MHz,
379 -- rstn => resetn,
380 -- sin => coarse_time_new_49,
381 -- sout => coarse_time_new);
382
383 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
383 -- rstn_out => resetn_25MHz,
384 -- sin => time_new_49,
385 -- sout => time_new);
384 386
385 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
386 GENERIC MAP (
387 NB_FF_OF_SYNC => 2)
388 PORT MAP (
389 clk_in => clk24_576MHz,
390 rstn_in => resetn_24_576MHz,
391 clk_out => clk25MHz,
392 rstn_out => resetn_25MHz,
393 sin => time_new_49,
394 sout => time_new);
395
396
387 time_new <= time_new_49;
397 388
398 PROCESS (clk25MHz, resetn_25MHz)
399 BEGIN -- PROCESS
400 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
401 fine_time_s <= (OTHERS => '0');
402 coarse_time_s <= (OTHERS => '0');
403 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
404 IF time_new = '1' THEN
405 fine_time_s <= fine_time_49;
406 coarse_time_s <= coarse_time_49;
407 END IF;
408 END IF;
409 END PROCESS;
389 --PROCESS (clk25MHz, resetn_25MHz)
390 --BEGIN -- PROCESS
391 -- IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
392 -- fine_time_s <= (OTHERS => '0');
393 -- coarse_time_s <= (OTHERS => '0');
394 -- ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
395 -- IF time_new = '1' THEN
396 -- END IF;
397 -- END IF;
398 --END PROCESS;
399
400 fine_time_s <= fine_time_49;
401 coarse_time_s <= coarse_time_49;
402
410 403
411
412 rstn_LFR_TM <= '0' WHEN resetn_24_576MHz = '0' ELSE
413 '0' WHEN soft_reset_sync = '1' ELSE
404 rstn_LFR_TM <= '0' WHEN resetn_25MHz = '0' ELSE
405 '0' WHEN soft_reset = '1' ELSE
414 406 '1';
415
416
407
417 408 -----------------------------------------------------------------------------
418 409 -- LFR_TIME_MANAGMENT
419 410 -----------------------------------------------------------------------------
420 411 lfr_time_management_1 : lfr_time_management
421 412 GENERIC MAP (
422 FIRST_DIVISION => FIRST_DIVISION,
413 --FIRST_DIVISION => FIRST_DIVISION,
423 414 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
424 415 PORT MAP (
425 clk => clk24_576MHz,
416 clk => clk25MHz,
426 417 rstn => rstn_LFR_TM,
427 418
428 419 tick => new_timecode,
429 420 new_coarsetime => new_coarsetime,
430 421 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
431 422
432 423 fine_time => fine_time_49,
433 424 fine_time_new => fine_time_new_49,
434 425 coarse_time => coarse_time_49,
435 426 coarse_time_new => coarse_time_new_49);
436 427
428
429
437 430 -----------------------------------------------------------------------------
438 431 -- HK
439 432 -----------------------------------------------------------------------------
440 433
441 434 PROCESS (clk25MHz, resetn_25MHz)
442 435 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
443 436 -- for each HK, the update frequency is freq/3
444 437 --
445 438 -- for 14, the update frequency is
446 439 -- 4Hz and update for each
447 440 -- HK is 1.33Hz
448 441 BEGIN -- PROCESS
449 442 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
450 443
451 444 r.HK_temp_0 <= (OTHERS => '0');
452 445 r.HK_temp_1 <= (OTHERS => '0');
453 446 r.HK_temp_2 <= (OTHERS => '0');
454 447
455 448 HK_sel_s <= "00";
456 449
457 450 previous_fine_time_bit <= '0';
458 451
459 452 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
460 453
461 454 IF HK_val = '1' THEN
462 455 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
463 456 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
464 457 CASE HK_sel_s IS
465 458 WHEN "00" =>
466 459 r.HK_temp_0 <= HK_sample;
467 460 HK_sel_s <= "01";
468 461 WHEN "01" =>
469 462 r.HK_temp_1 <= HK_sample;
470 463 HK_sel_s <= "10";
471 464 WHEN "10" =>
472 465 r.HK_temp_2 <= HK_sample;
473 466 HK_sel_s <= "00";
474 467 WHEN OTHERS => NULL;
475 468 END CASE;
476 469 END IF;
477 470 END IF;
478 471
479 472 END IF;
480 473 END PROCESS;
481 474
482 475 HK_sel <= HK_sel_s;
483 476
477
478
479
480
481
482
483
484
485
486
487
488
489
484 490 -----------------------------------------------------------------------------
485 491 -- DAC
486 492 -----------------------------------------------------------------------------
487 493 cal : lfr_cal_driver
488 494 GENERIC MAP(
489 495 tech => tech,
490 496 PRESZ => PRESZ,
491 497 CPTSZ => CPTSZ,
492 498 datawidth => datawidth,
493 499 abits => abits
494 500 )
495 501 PORT MAP(
496 502 clk => clk25MHz,
497 503 rstn => resetn_25MHz,
498 504
499 505 pre => pre,
500 506 N => N,
501 507 Reload => Reload,
502 508 DATA_IN => DATA_IN,
503 509 WEN => WEN,
504 510 LOAD_ADDRESSN => LOAD_ADDRESSN,
505 511 ADDRESS_IN => ADDRESS_IN,
506 512 ADDRESS_OUT => ADDRESS_OUT,
507 513 INTERLEAVED => INTERLEAVED,
508 514 DAC_CFG => DAC_CFG,
509 515
510 516 SYNC => DAC_SYNC,
511 517 DOUT => DAC_SDO,
512 518 SCLK => DAC_SCK,
513 519 SMPCLK => OPEN --DAC_SMPCLK
514 520 );
515 521
516 522 DAC_CAL_EN <= DAC_CAL_EN_s;
517 END Behavioral; No newline at end of file
523 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,123 +1,124
1 1 LIBRARY IEEE;
2 2 USE IEEE.STD_LOGIC_1164.ALL;
3 3 USE IEEE.NUMERIC_STD.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.general_purpose.ALL;
7 7
8 8 ENTITY coarse_time_counter IS
9 9 GENERIC (
10 10 NB_SECOND_DESYNC : INTEGER := 60);
11 11
12 12 PORT (
13 13 clk : IN STD_LOGIC;
14 14 rstn : IN STD_LOGIC;
15 15
16 16 tick : IN STD_LOGIC;
17 17 set_TCU : IN STD_LOGIC;
18 18 new_TCU : IN STD_LOGIC;
19 19 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
20 20 CT_add1 : IN STD_LOGIC;
21 21 fsm_desync : IN STD_LOGIC;
22 22 FT_max : IN STD_LOGIC;
23 23
24 24 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
25 25 coarse_time_new : OUT STD_LOGIC
26 26
27 27 );
28 28
29 29 END coarse_time_counter;
30 30
31 31 ARCHITECTURE beh OF coarse_time_counter IS
32 32
33 33 SIGNAL add1_bit31 : STD_LOGIC;
34 34 SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
35 35 SIGNAL coarse_time_new_counter : STD_LOGIC;
36 36 SIGNAL coarse_time_31 : STD_LOGIC;
37 37 SIGNAL coarse_time_31_reg : STD_LOGIC;
38 38
39 39 SIGNAL set_synchronized : STD_LOGIC;
40 40 SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
41 41
42 42 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 ;
43 43 SIGNAL set_TCU_reg : STD_LOGIC;
44 44
45 45 BEGIN -- beh
46 46
47 47 -----------------------------------------------------------------------------
48 48 -- COARSE_TIME( 30 DOWNTO 0)
49 49 -----------------------------------------------------------------------------
50 50 counter_1 : general_counter
51 51 GENERIC MAP (
52 52 CYCLIC => '1',
53 53 NB_BITS_COUNTER => 31,
54 54 RST_VALUE => 0)
55 55 PORT MAP (
56 56 clk => clk,
57 57 rstn => rstn,
58 58 MAX_VALUE => "111" & X"FFFFFFF" ,
59 59 set => set_TCU_reg,
60 60 set_value => set_TCU_value(30 DOWNTO 0),
61 61 add1 => CT_add1,
62 62 counter => coarse_time(30 DOWNTO 0));
63 63
64 64
65 65 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
66 66
67 67 -----------------------------------------------------------------------------
68 68 -- COARSE_TIME(31)
69 69 -----------------------------------------------------------------------------
70 70
71 71 --set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
72 72 --set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
73 73 -- (OTHERS => '0');
74 74 set_synchronized <= tick AND ((NOT coarse_time_31) OR (coarse_time_31 AND new_TCU));
75 75 set_synchronized_value <= (OTHERS => '0');
76 76
77 77 counter_2 : general_counter
78 78 GENERIC MAP (
79 79 CYCLIC => '0',
80 80 NB_BITS_COUNTER => 6,
81 81 RST_VALUE => NB_SECOND_DESYNC
82 82 )
83 83 PORT MAP (
84 84 clk => clk,
85 85 rstn => rstn,
86 86 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
87 87 set => set_synchronized,
88 88 set_value => set_synchronized_value,
89 89 add1 => add1_bit31,
90 90 counter => nb_second_counter);
91 91
92 92 coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
93 93 coarse_time(31) <= coarse_time_31;
94 94 coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
95 95
96 96 PROCESS (clk, rstn)
97 97 BEGIN -- PROCESS
98 98 IF rstn = '0' THEN -- asynchronous reset (active low)
99 99 coarse_time_new_counter <= '0';
100 100 coarse_time_31_reg <= '0';
101 101 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
102 102 coarse_time_31_reg <= coarse_time_31;
103 103 IF set_TCU_reg = '1' OR CT_add1 = '1' THEN
104 104 coarse_time_new_counter <= '1';
105 105 ELSE
106 106 coarse_time_new_counter <= '0';
107 107 END IF;
108 108 END IF;
109 109 END PROCESS;
110 110
111 111 -----------------------------------------------------------------------------
112 112 -- Just to try to limit the constraint
113 PROCESS (clk, rstn)
114 BEGIN -- PROCESS
115 IF rstn = '0' THEN -- asynchronous reset (active low)
116 set_TCU_reg <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 set_TCU_reg <= set_TCU;
119 END IF;
120 END PROCESS;
113 --PROCESS (clk, rstn)
114 --BEGIN -- PROCESS
115 -- IF rstn = '0' THEN -- asynchronous reset (active low)
116 -- set_TCU_reg <= '0';
117 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 -- set_TCU_reg <= set_TCU;
119 -- END IF;
120 --END PROCESS;
121 121 -----------------------------------------------------------------------------
122
123 END beh; No newline at end of file
122 set_TCU_reg <= set_TCU;
123
124 END beh;
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@@ -1,94 +1,106
1 1 LIBRARY IEEE;
2 2 USE IEEE.STD_LOGIC_1164.ALL;
3 3 USE IEEE.NUMERIC_STD.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.general_purpose.ALL;
7 USE lpp.lpp_lfr_management.ALL;
7 8
8 9 ENTITY fine_time_counter IS
9 10
10 11 GENERIC (
11 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040";
12 FIRST_DIVISION : INTEGER := 374
12 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040"
13 13 );
14 14
15 15 PORT (
16 16 clk : IN STD_LOGIC;
17 17 rstn : IN STD_LOGIC;
18 18 --
19 19 tick : IN STD_LOGIC;
20 20 fsm_transition : IN STD_LOGIC;
21 21
22 22 FT_max : OUT STD_LOGIC;
23 23 FT_half : OUT STD_LOGIC;
24 24 FT_wait : OUT STD_LOGIC;
25 25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
26 26 fine_time_new : OUT STD_LOGIC
27 27 );
28 28
29 29 END fine_time_counter;
30 30
31 31 ARCHITECTURE beh OF fine_time_counter IS
32 32
33 33 SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
34 34 SIGNAL new_ft : STD_LOGIC;
35 35 SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
36
37 SIGNAL fine_time_max_value : STD_LOGIC_VECTOR(8 DOWNTO 0);
38 SIGNAL tick_value_gen : STD_LOGIC;
39 SIGNAL FT_max_s : STD_LOGIC;
36 40
37 -- CONSTANT FIRST_DIVISION : INTEGER := 20; -- TODO : 374
38
39 41 BEGIN -- beh
40 42
43 tick_value_gen <= tick OR FT_max_s;
41 44
45 fine_time_max_value_gen_1: fine_time_max_value_gen
46 PORT MAP (
47 clk => clk,
48 rstn => rstn,
49 tick => tick_value_gen,
50 fine_time_add => new_ft,
51 fine_time_max_value => fine_time_max_value);
42 52
43 53 counter_1 : general_counter
44 54 GENERIC MAP (
45 55 CYCLIC => '1',
46 56 NB_BITS_COUNTER => 9,
47 57 RST_VALUE => 0
48 58 )
49 59 PORT MAP (
50 60 clk => clk,
51 61 rstn => rstn,
52 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
62 MAX_VALUE => fine_time_max_value,
53 63 set => tick,
54 64 set_value => (OTHERS => '0'),
55 65 add1 => '1',
56 66 counter => new_ft_counter);
57 67
58 new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0';
68 new_ft <= '1' WHEN new_ft_counter = fine_time_max_value ELSE '0';
59 69
60 70 counter_2 : general_counter
61 71 GENERIC MAP (
62 72 CYCLIC => '1',
63 73 NB_BITS_COUNTER => 16,
64 74 RST_VALUE => 0
65 75 )
66 76 PORT MAP (
67 77 clk => clk,
68 78 rstn => rstn,
69 79 MAX_VALUE => X"FFFF",
70 80 set => tick,
71 81 set_value => (OTHERS => '0'),
72 82 add1 => new_ft,
73 83 counter => fine_time_counter);
74 84
75 FT_max <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
85 FT_max_s <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
86
87 FT_max <= FT_max_s;
76 88 FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
77 89 FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
78 90
79 91 fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
80 92
81 93 PROCESS (clk, rstn)
82 94 BEGIN -- PROCESS
83 95 IF rstn = '0' THEN -- asynchronous reset (active low)
84 96 fine_time_new <= '0';
85 97 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
86 98 IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
87 99 fine_time_new <= '1';
88 100 ELSE
89 101 fine_time_new <= '0';
90 102 END IF;
91 103 END IF;
92 104 END PROCESS;
93 105
94 106 END beh;
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@@ -1,174 +1,172
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:14:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY lpp;
24 24 USE lpp.lpp_lfr_management.ALL;
25 25
26 26 ENTITY lfr_time_management IS
27 27 GENERIC (
28 FIRST_DIVISION : INTEGER := 374;
29 28 NB_SECOND_DESYNC : INTEGER := 60);
30 29 PORT (
31 30 clk : IN STD_LOGIC;
32 31 rstn : IN STD_LOGIC;
33 32
34 33 tick : IN STD_LOGIC; -- transition signal information
35 34
36 35 new_coarsetime : IN STD_LOGIC; -- transition signal information
37 36 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
38 37
39 38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
40 39 fine_time_new : OUT STD_LOGIC;
41 40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
42 41 coarse_time_new : OUT STD_LOGIC
43 42 );
44 43 END lfr_time_management;
45 44
46 45 ARCHITECTURE Behavioral OF lfr_time_management IS
47 46
48 47 SIGNAL FT_max : STD_LOGIC;
49 48 SIGNAL FT_half : STD_LOGIC;
50 49 SIGNAL FT_wait : STD_LOGIC;
51 50
52 51 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
53 52 SIGNAL state : state_fsm_time_management;
54 53
55 54 SIGNAL fsm_desync : STD_LOGIC;
56 55 SIGNAL fsm_transition : STD_LOGIC;
57 56
58 57 SIGNAL set_TCU : STD_LOGIC;
59 58 SIGNAL CT_add1 : STD_LOGIC;
60 59
61 60 SIGNAL new_coarsetime_reg : STD_LOGIC;
62 61
63 62 BEGIN
64 63
65 64 -----------------------------------------------------------------------------
66 65 --
67 66 -----------------------------------------------------------------------------
68 67 PROCESS (clk, rstn)
69 68 BEGIN -- PROCESS
70 69 IF rstn = '0' THEN -- asynchronous reset (active low)
71 70 new_coarsetime_reg <= '0';
72 71 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
73 72 IF new_coarsetime = '1' THEN
74 73 new_coarsetime_reg <= '1';
75 74 ELSIF tick = '1' THEN
76 75 new_coarsetime_reg <= '0';
77 76 END IF;
78 77 END IF;
79 78 END PROCESS;
80 79
81 80 -----------------------------------------------------------------------------
82 81 -- FINE_TIME
83 82 -----------------------------------------------------------------------------
84 83 fine_time_counter_1: fine_time_counter
85 84 GENERIC MAP (
86 WAITING_TIME => X"0040",
87 FIRST_DIVISION => FIRST_DIVISION)
85 WAITING_TIME => X"0040")
88 86 PORT MAP (
89 87 clk => clk,
90 88 rstn => rstn,
91 89 tick => tick,
92 90 fsm_transition => fsm_transition, -- todo
93 91 FT_max => FT_max,
94 92 FT_half => FT_half,
95 93 FT_wait => FT_wait,
96 94 fine_time => fine_time,
97 95 fine_time_new => fine_time_new);
98 96
99 97 -----------------------------------------------------------------------------
100 98 -- COARSE_TIME
101 99 -----------------------------------------------------------------------------
102 100 coarse_time_counter_1: coarse_time_counter
103 101 GENERIC MAP(
104 102 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
105 103 PORT MAP (
106 104 clk => clk,
107 105 rstn => rstn,
108 106 tick => tick,
109 107 set_TCU => set_TCU, -- todo
110 108 new_TCU => new_coarsetime_reg,
111 109 set_TCU_value => coarsetime_reg, -- todo
112 110 CT_add1 => CT_add1, -- todo
113 111 fsm_desync => fsm_desync, -- todo
114 112 FT_max => FT_max,
115 113 coarse_time => coarse_time,
116 114 coarse_time_new => coarse_time_new);
117 115
118 116 -----------------------------------------------------------------------------
119 117 -- FSM
120 118 -----------------------------------------------------------------------------
121 119 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
122 120 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
123 121
124 122 PROCESS (clk, rstn)
125 123 BEGIN -- PROCESS
126 124 IF rstn = '0' THEN -- asynchronous reset (active low)
127 125 state <= DESYNC;
128 126 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
129 127 --CT_add1 <= '0';
130 128 set_TCU <= '0';
131 129 CASE state IS
132 130 WHEN DESYNC =>
133 131 IF tick = '1' THEN
134 132 state <= SYNC;
135 133 set_TCU <= new_coarsetime_reg;
136 134 --IF new_coarsetime = '0' AND FT_half = '1' THEN
137 135 -- CT_add1 <= '1';
138 136 --END IF;
139 137 --ELSIF FT_max = '1' THEN
140 138 -- CT_add1 <= '1';
141 139 END IF;
142 140 WHEN TRANSITION =>
143 141 IF tick = '1' THEN
144 142 state <= SYNC;
145 143 set_TCU <= new_coarsetime_reg;
146 144 --IF new_coarsetime = '0' THEN
147 145 -- CT_add1 <= '1';
148 146 --END IF;
149 147 ELSIF FT_wait = '1' THEN
150 148 --CT_add1 <= '1';
151 149 state <= DESYNC;
152 150 END IF;
153 151 WHEN SYNC =>
154 152 IF tick = '1' THEN
155 153 set_TCU <= new_coarsetime_reg;
156 154 --IF new_coarsetime = '0' THEN
157 155 -- CT_add1 <= '1';
158 156 --END IF;
159 157 ELSIF FT_max = '1' THEN
160 158 state <= TRANSITION;
161 159 END IF;
162 160 WHEN OTHERS => NULL;
163 161 END CASE;
164 162 END IF;
165 163 END PROCESS;
166 164
167 165
168 166 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
169 167 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
170 168 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
171 169 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
172 170 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
173 171 '0';
174 172 END Behavioral;
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@@ -1,111 +1,119
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
26
27 PACKAGE lpp_lfr_management IS
28
29 --***************************
30 -- APB_LFR_MANAGEMENT
31
32 COMPONENT apb_lfr_management
33 GENERIC (
34 tech : INTEGER;
35 pindex : INTEGER;
36 paddr : INTEGER;
37 pmask : INTEGER;
38 FIRST_DIVISION : INTEGER;
39 NB_SECOND_DESYNC : INTEGER);
40 PORT (
41 clk25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
43 clk24_576MHz : IN STD_LOGIC;
44 resetn_24_576MHz : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
46 apbi : IN apb_slv_in_type;
47 apbo : OUT apb_slv_out_type;
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 HK_val : IN STD_LOGIC;
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 DAC_SDO : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
57 LFR_soft_rstn : OUT STD_LOGIC);
58 END COMPONENT;
59
60 COMPONENT lfr_time_management
61 GENERIC (
62 FIRST_DIVISION : INTEGER;
63 NB_SECOND_DESYNC : INTEGER);
64 PORT (
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 tick : IN STD_LOGIC;
68 new_coarsetime : IN STD_LOGIC;
69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
71 fine_time_new : OUT STD_LOGIC;
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 coarse_time_new : OUT STD_LOGIC);
74 END COMPONENT;
75
76 COMPONENT coarse_time_counter
77 GENERIC (
78 NB_SECOND_DESYNC : INTEGER);
79 PORT (
80 clk : IN STD_LOGIC;
81 rstn : IN STD_LOGIC;
82 tick : IN STD_LOGIC;
83 set_TCU : IN STD_LOGIC;
84 new_TCU : IN STD_LOGIC;
85 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 CT_add1 : IN STD_LOGIC;
87 fsm_desync : IN STD_LOGIC;
88 FT_max : IN STD_LOGIC;
89 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 coarse_time_new : OUT STD_LOGIC);
91 END COMPONENT;
92
93 COMPONENT fine_time_counter
94 GENERIC (
95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
96 FIRST_DIVISION : INTEGER);
97 PORT (
98 clk : IN STD_LOGIC;
99 rstn : IN STD_LOGIC;
100 tick : IN STD_LOGIC;
101 fsm_transition : IN STD_LOGIC;
102 FT_max : OUT STD_LOGIC;
103 FT_half : OUT STD_LOGIC;
104 FT_wait : OUT STD_LOGIC;
105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
106 fine_time_new : OUT STD_LOGIC);
107 END COMPONENT;
108
109
110 END lpp_lfr_management;
111
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
26
27 PACKAGE lpp_lfr_management IS
28
29 --***************************
30 -- APB_LFR_MANAGEMENT
31
32 COMPONENT apb_lfr_management
33 GENERIC (
34 tech : INTEGER;
35 pindex : INTEGER;
36 paddr : INTEGER;
37 pmask : INTEGER;
38 -- FIRST_DIVISION : INTEGER;
39 NB_SECOND_DESYNC : INTEGER);
40 PORT (
41 clk25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
43 -- clk24_576MHz : IN STD_LOGIC;
44 -- resetn_24_576MHz : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
46 apbi : IN apb_slv_in_type;
47 apbo : OUT apb_slv_out_type;
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 HK_val : IN STD_LOGIC;
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 DAC_SDO : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
57 LFR_soft_rstn : OUT STD_LOGIC);
58 END COMPONENT;
59
60 COMPONENT lfr_time_management
61 GENERIC (
62 --FIRST_DIVISION : INTEGER;
63 NB_SECOND_DESYNC : INTEGER);
64 PORT (
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 tick : IN STD_LOGIC;
68 new_coarsetime : IN STD_LOGIC;
69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
71 fine_time_new : OUT STD_LOGIC;
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 coarse_time_new : OUT STD_LOGIC);
74 END COMPONENT;
75
76 COMPONENT coarse_time_counter
77 GENERIC (
78 NB_SECOND_DESYNC : INTEGER);
79 PORT (
80 clk : IN STD_LOGIC;
81 rstn : IN STD_LOGIC;
82 tick : IN STD_LOGIC;
83 set_TCU : IN STD_LOGIC;
84 new_TCU : IN STD_LOGIC;
85 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 CT_add1 : IN STD_LOGIC;
87 fsm_desync : IN STD_LOGIC;
88 FT_max : IN STD_LOGIC;
89 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 coarse_time_new : OUT STD_LOGIC);
91 END COMPONENT;
92
93 COMPONENT fine_time_counter
94 GENERIC (
95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0));--;
96 -- FIRST_DIVISION : INTEGER);
97 PORT (
98 clk : IN STD_LOGIC;
99 rstn : IN STD_LOGIC;
100 tick : IN STD_LOGIC;
101 fsm_transition : IN STD_LOGIC;
102 FT_max : OUT STD_LOGIC;
103 FT_half : OUT STD_LOGIC;
104 FT_wait : OUT STD_LOGIC;
105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
106 fine_time_new : OUT STD_LOGIC);
107 END COMPONENT;
108
109 COMPONENT fine_time_max_value_gen
110 PORT (
111 clk : IN STD_LOGIC;
112 rstn : IN STD_LOGIC;
113 tick : IN STD_LOGIC;
114 fine_time_add : IN STD_LOGIC;
115 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
116 END COMPONENT;
117
118 END lpp_lfr_management;
119
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@@ -1,6 +1,7
1 1 lpp_lfr_management.vhd
2 2 lpp_lfr_management_apbreg_pkg.vhd
3 3 apb_lfr_management.vhd
4 4 lfr_time_management.vhd
5 5 fine_time_counter.vhd
6 6 coarse_time_counter.vhd
7 fine_time_max_value_gen.vhd
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@@ -1,195 +1,196
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 USE ieee.numeric_std.ALL;
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_amba.ALL;
34 34 USE lpp.apb_devices_list.ALL;
35 35 USE lpp.lpp_memory.ALL;
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 39 ENTITY lpp_dma_send_16word IS
40 40 PORT (
41 41 -- AMBA AHB system signals
42 42 HCLK : IN STD_ULOGIC;
43 43 HRESETn : IN STD_ULOGIC;
44 44
45 45 -- DMA
46 46 DMAIn : OUT DMA_In_Type;
47 47 DMAOut : IN DMA_OUt_Type;
48 48
49 49 --
50 50 send : IN STD_LOGIC;
51 51 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 53 ren : OUT STD_LOGIC;
54 54 --
55 55 send_ok : OUT STD_LOGIC;
56 56 send_ko : OUT STD_LOGIC
57
57
58 58 );
59 59 END lpp_dma_send_16word;
60 60
61 61 ARCHITECTURE beh OF lpp_dma_send_16word IS
62 62
63 63 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
64 64 SIGNAL state : state_fsm_send_16word;
65 65
66 66 SIGNAL data_counter : INTEGER;
67 67 SIGNAL grant_counter : INTEGER;
68 68
69 69 BEGIN -- beh
70 70
71 71 DMAIn.Beat <= HINCR16;
72 72 DMAIn.Size <= HSIZE32;
73 73
74 74 PROCESS (HCLK, HRESETn)
75 75 BEGIN -- PROCESS
76 76 IF HRESETn = '0' THEN -- asynchronous reset (active low)
77 77 state <= IDLE;
78 78 send_ok <= '0';
79 79 send_ko <= '0';
80 80
81 81 DMAIn.Reset <= '1';
82 82 DMAIn.Address <= (OTHERS => '0');
83 83 DMAIn.Request <= '0';
84 84 DMAIn.Store <= '0';
85 85 DMAIn.Burst <= '1';
86 86 DMAIn.Lock <= '0';
87 87 data_counter <= 0;
88 88 grant_counter <= 0;
89 89 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
90 90
91 DMAIn.Reset <= '0';
92
91 DMAIn.Reset <= '0';
92
93 93 CASE state IS
94 94 WHEN IDLE =>
95 95 DMAIn.Store <= '1';
96 96 DMAIn.Request <= '0';
97 97 send_ok <= '0';
98 98 send_ko <= '0';
99 99 DMAIn.Address <= address;
100 100 data_counter <= 0;
101 DMAIn.Lock <= '0'; -- FIX test
101 DMAIn.Lock <= '0';
102 102 IF send = '1' THEN
103 103 state <= REQUEST_BUS;
104 104 DMAIn.Request <= '1';
105 DMAIn.Lock <= '1'; -- FIX test
105 DMAIn.Lock <= '1';
106 106 DMAIn.Store <= '1';
107 107 END IF;
108 108 WHEN REQUEST_BUS =>
109 109 IF DMAOut.Grant = '1' THEN
110 110 data_counter <= 1;
111 111 grant_counter <= 1;
112 112 state <= SEND_DATA;
113 113 END IF;
114 114 WHEN SEND_DATA =>
115 115
116 116 IF DMAOut.Fault = '1' THEN
117 117 DMAIn.Reset <= '0';
118 118 DMAIn.Address <= (OTHERS => '0');
119 119 DMAIn.Request <= '0';
120 120 DMAIn.Store <= '0';
121 121 DMAIn.Burst <= '0';
122 122 state <= ERROR0;
123 123 ELSE
124 124
125 125 IF DMAOut.Grant = '1' THEN
126 126 IF grant_counter = 15 THEN
127 DMAIn.Reset <= '0';
127 DMAIn.Reset <= '0';
128 128 DMAIn.Request <= '0';
129 DMAIn.Store <= '0';
130 DMAIn.Burst <= '0';
129 DMAIn.Store <= '0';
130 DMAIn.Burst <= '0';
131 131 ELSE
132 132 grant_counter <= grant_counter+1;
133 133 END IF;
134 134 END IF;
135 135
136 136 IF DMAOut.OKAY = '1' THEN
137 137 IF data_counter = 15 THEN
138 --DMAIn.Request <= '0'; -- FIX Test 31/03/2014 to handle burst interruption
138 139 DMAIn.Address <= (OTHERS => '0');
139 140 state <= WAIT_LAST_READY;
140 141 ELSE
141 142 data_counter <= data_counter + 1;
142 143 END IF;
143 144 END IF;
144 145 END IF;
145 146
146 147
147 148 WHEN WAIT_LAST_READY =>
148 149 IF DMAOut.Ready = '1' THEN
149 150 IF grant_counter = 15 THEN
150 151 state <= IDLE;
151 152 send_ok <= '1';
152 153 send_ko <= '0';
153 154 ELSE
154 155 state <= ERROR0;
155 156 END IF;
156 157 END IF;
157 158
158 159 WHEN ERROR0 =>
159 160 state <= ERROR1;
160 161 WHEN ERROR1 =>
161 162 send_ok <= '0';
162 163 send_ko <= '1';
163 164 state <= IDLE;
164 165 WHEN OTHERS => NULL;
165 166 END CASE;
166 167 END IF;
167 168 END PROCESS;
168 169
169 170 DMAIn.Data <= data;
170
171
171 172 ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE
172 173 '1';
173 174
174 175 -- \/ JC - 20/01/2014 \/
175 176 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
176 177 -- '1';
177 178 -- /\ JC - 20/01/2014 /\
178
179
179 180 -- \/ JC - 11/12/2013 \/
180 181 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
181 182 -- '1';
182 183 -- /\ JC - 11/12/2013 /\
183 184
184 185 -- \/ JC - 10/12/2013 \/
185 186 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
186 187 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
187 188 -- '1';
188 189 -- /\ JC - 10/12/2013 /\
189 190
190 191 -- \/ JC - 09/12/2013 \/
191 192 --ren <= '0' WHEN state = SEND_DATA ELSE
192 193 -- '1';
193 194 -- /\ JC - 09/12/2013 /\
194
195
195 196 END beh;
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@@ -1,566 +1,569
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 43 LIBRARY iap;
44 44 USE iap.memctrl.ALL;
45 45
46 46
47 47 ENTITY leon3_soc IS
48 48 GENERIC (
49 49 fabtech : INTEGER := apa3e;
50 50 memtech : INTEGER := apa3e;
51 51 padtech : INTEGER := inferred;
52 52 clktech : INTEGER := inferred;
53 53 disas : INTEGER := 0; -- Enable disassembly to console
54 54 dbguart : INTEGER := 0; -- Print UART on console
55 55 pclow : INTEGER := 2;
56 56 --
57 57 clk_freq : INTEGER := 25000; --kHz
58 58 --
59 59 IS_RADHARD : INTEGER := 0;
60 60 --
61 61 NB_CPU : INTEGER := 1;
62 62 ENABLE_FPU : INTEGER := 1;
63 63 FPU_NETLIST : INTEGER := 1;
64 64 ENABLE_DSU : INTEGER := 1;
65 65 ENABLE_AHB_UART : INTEGER := 1;
66 66 ENABLE_APB_UART : INTEGER := 1;
67 67 ENABLE_IRQMP : INTEGER := 1;
68 68 ENABLE_GPT : INTEGER := 1;
69 69 --
70 70 NB_AHB_MASTER : INTEGER := 1;
71 71 NB_AHB_SLAVE : INTEGER := 1;
72 72 NB_APB_SLAVE : INTEGER := 1;
73 73 --
74 74 ADDRESS_SIZE : INTEGER := 20;
75 USES_IAP_MEMCTRLR : INTEGER := 0
75 USES_IAP_MEMCTRLR : INTEGER := 0;
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 SRBANKSZ : INTEGER := 8
76 78
77 79 );
78 80 PORT (
79 81 clk : IN STD_ULOGIC;
80 82 reset : IN STD_ULOGIC;
81 83
82 84 errorn : OUT STD_ULOGIC;
83 85
84 86 -- UART AHB ---------------------------------------------------------------
85 87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
86 88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
87 89
88 90 -- UART APB ---------------------------------------------------------------
89 91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
90 92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
91 93
92 94 -- RAM --------------------------------------------------------------------
93 95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
94 96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 97 nSRAM_BE0 : OUT STD_LOGIC;
96 98 nSRAM_BE1 : OUT STD_LOGIC;
97 99 nSRAM_BE2 : OUT STD_LOGIC;
98 100 nSRAM_BE3 : OUT STD_LOGIC;
99 101 nSRAM_WE : OUT STD_LOGIC;
100 102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 103 nSRAM_OE : OUT STD_LOGIC;
102 104 nSRAM_READY : IN STD_LOGIC;
103 105 SRAM_MBE : INOUT STD_LOGIC;
104 106 -- APB --------------------------------------------------------------------
105 107 apbi_ext : OUT apb_slv_in_type;
106 108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
107 109 -- AHB_Slave --------------------------------------------------------------
108 110 ahbi_s_ext : OUT ahb_slv_in_type;
109 111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
110 112 -- AHB_Master -------------------------------------------------------------
111 113 ahbi_m_ext : OUT AHB_Mst_In_Type;
112 114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
113 115
114 116 );
115 117 END;
116 118
117 119 ARCHITECTURE Behavioral OF leon3_soc IS
118 120
119 121 -----------------------------------------------------------------------------
120 122 -- CONFIG -------------------------------------------------------------------
121 123 -----------------------------------------------------------------------------
122 124
123 125 -- Clock generator
124 126 CONSTANT CFG_CLKMUL : INTEGER := (1);
125 127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
126 128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
127 129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
128 130 -- LEON3 processor core
129 131 CONSTANT CFG_LEON3 : INTEGER := 1;
130 132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
131 133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
132 134 CONSTANT CFG_V8 : INTEGER := 0;
133 135 CONSTANT CFG_MAC : INTEGER := 0;
134 136 CONSTANT CFG_SVT : INTEGER := 0;
135 137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
136 138 CONSTANT CFG_LDDEL : INTEGER := (1);
137 139 CONSTANT CFG_NWP : INTEGER := (0);
138 140 CONSTANT CFG_PWD : INTEGER := 1*2;
139 141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
140 142 -- 1*(8 + 16 * 0) => grfpu-light
141 143 -- 1*(8 + 16 * 1) => netlist
142 144 -- 0*(8 + 16 * 0) => No FPU
143 145 -- 0*(8 + 16 * 1) => No FPU;
144 146 CONSTANT CFG_ICEN : INTEGER := 1;
145 147 CONSTANT CFG_ISETS : INTEGER := 1;
146 148 CONSTANT CFG_ISETSZ : INTEGER := 4;
147 149 CONSTANT CFG_ILINE : INTEGER := 4;
148 150 CONSTANT CFG_IREPL : INTEGER := 0;
149 151 CONSTANT CFG_ILOCK : INTEGER := 0;
150 152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
151 153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
152 154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
153 155 CONSTANT CFG_DCEN : INTEGER := 1;
154 156 CONSTANT CFG_DSETS : INTEGER := 1;
155 157 CONSTANT CFG_DSETSZ : INTEGER := 4;
156 158 CONSTANT CFG_DLINE : INTEGER := 4;
157 159 CONSTANT CFG_DREPL : INTEGER := 0;
158 160 CONSTANT CFG_DLOCK : INTEGER := 0;
159 161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
160 162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
161 163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
162 164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
163 165 CONSTANT CFG_MMUEN : INTEGER := 0;
164 166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
165 167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
166 168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
167 169 CONSTANT CFG_TLB_REP : INTEGER := 1;
168 170
169 171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
170 172 CONSTANT CFG_ITBSZ : INTEGER := 0;
171 173 CONSTANT CFG_ATBSZ : INTEGER := 0;
172 174
173 175 -- AMBA settings
174 176 CONSTANT CFG_DEFMST : INTEGER := (0);
175 177 CONSTANT CFG_RROBIN : INTEGER := 1;
176 178 CONSTANT CFG_SPLIT : INTEGER := 0;
177 179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
178 180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
179 181
180 182 -- DSU UART
181 183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
182 184
183 185 -- LEON2 memory controller
184 186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
185 187
186 188 -- UART 1
187 189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
188 190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
189 191
190 192 -- LEON3 interrupt controller
191 193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
192 194
193 195 -- Modular timer
194 196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
195 197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
196 198 CONSTANT CFG_GPT_SW : INTEGER := (8);
197 199 CONSTANT CFG_GPT_TW : INTEGER := (32);
198 200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
199 201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
200 202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
201 203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
202 204 -----------------------------------------------------------------------------
203 205
204 206 -----------------------------------------------------------------------------
205 207 -- SIGNALs
206 208 -----------------------------------------------------------------------------
207 209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
208 210 -- CLK & RST --
209 211 SIGNAL clk2x : STD_ULOGIC;
210 212 SIGNAL clkmn : STD_ULOGIC;
211 213 SIGNAL clkm : STD_ULOGIC;
212 214 SIGNAL rstn : STD_ULOGIC;
213 215 SIGNAL rstraw : STD_ULOGIC;
214 216 SIGNAL pciclk : STD_ULOGIC;
215 217 SIGNAL sdclkl : STD_ULOGIC;
216 218 SIGNAL cgi : clkgen_in_type;
217 219 SIGNAL cgo : clkgen_out_type;
218 220 --- AHB / APB
219 221 SIGNAL apbi : apb_slv_in_type;
220 222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
221 223 SIGNAL ahbsi : ahb_slv_in_type;
222 224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
223 225 SIGNAL ahbmi : ahb_mst_in_type;
224 226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
225 227 --UART
226 228 SIGNAL ahbuarti : uart_in_type;
227 229 SIGNAL ahbuarto : uart_out_type;
228 230 SIGNAL apbuarti : uart_in_type;
229 231 SIGNAL apbuarto : uart_out_type;
230 232 --MEM CTRLR
231 233 SIGNAL memi : memory_in_type;
232 234 SIGNAL memo : memory_out_type;
233 235 SIGNAL wpo : wprot_out_type;
234 236 SIGNAL sdo : sdram_out_type;
235 237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
236 238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
237 239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
238 240 SIGNAL nSRAM_OE_s : STD_LOGIC;
239 241 --IRQ
240 242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
241 243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
242 244 --Timer
243 245 SIGNAL gpti : gptimer_in_type;
244 246 SIGNAL gpto : gptimer_out_type;
245 247 --DSU
246 248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
247 249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
248 250 SIGNAL dsui : dsu_in_type;
249 251 SIGNAL dsuo : dsu_out_type;
250 252 -----------------------------------------------------------------------------
251 253
252 254
253 255 BEGIN
254 256
255 257
256 258 ----------------------------------------------------------------------
257 259 --- Reset and Clock generation -------------------------------------
258 260 ----------------------------------------------------------------------
259 261
260 262 cgi.pllctrl <= "00";
261 263 cgi.pllrst <= rstraw;
262 264
263 265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
264 266
265 267 clkgen0 : clkgen -- clock generator
266 268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
267 269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
268 270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
269 271
270 272 ----------------------------------------------------------------------
271 273 --- LEON3 processor / DSU / IRQ ------------------------------------
272 274 ----------------------------------------------------------------------
273 275
274 276 l3 : IF CFG_LEON3 = 1 GENERATE
275 277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
276 278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
277 279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
278 280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
279 281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
280 282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
281 283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
282 284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
283 285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
284 286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
285 287 irqi(i), irqo(i), dbgi(i), dbgo(i));
286 288 END GENERATE leon3_non_radhard;
287 289
288 290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
289 291 cpu : ENTITY gaisler.leon3ft
290 292 GENERIC MAP (
291 293 HINDEX => i, --: integer; --CPU_HINDEX,
292 294 FABTECH => fabtech, --CFG_TECH,
293 295 MEMTECH => memtech, --CFG_TECH,
294 296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
295 297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
296 298 FPU => CFG_FPU, --CFG_FPU,
297 299 V8 => CFG_V8, --CFG_V8,
298 300 CP => 0, --CFG_CP,
299 301 MAC => CFG_MAC, --CFG_MAC,
300 302 PCLOW => pclow, --CFG_PCLOW,
301 303 NOTAG => 0, --CFG_NOTAG,
302 304 NWP => CFG_NWP, --CFG_NWP,
303 305 ICEN => CFG_ICEN, --CFG_ICEN,
304 306 IREPL => CFG_IREPL, --CFG_IREPL,
305 307 ISETS => CFG_ISETS, --CFG_ISETS,
306 308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
307 309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
308 310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
309 311 DCEN => CFG_DCEN, --CFG_DCEN,
310 312 DREPL => CFG_DREPL, --CFG_DREPL,
311 313 DSETS => CFG_DSETS, --CFG_DSETS,
312 314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
313 315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
314 316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
315 317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
316 318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
317 319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
318 320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
319 321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
320 322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
321 323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
322 324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
323 325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
324 326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
325 327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
326 328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
327 329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
328 330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
329 331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
330 332 PWD => CFG_PWD, --CFG_PWD,
331 333 SVT => CFG_SVT, --CFG_SVT,
332 334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
333 335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
334 336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
335 337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
336 338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
337 339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
338 340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
339 341 CACHED => 0, --: integer; --CFG_DFIXED,
340 342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
341 343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
342 344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
343 345 BP => 1) --CFG_BP
344 346 PORT MAP ( --
345 347 rstn => rstn, --rst_n,
346 348 clk => clkm, --clk,
347 349 ahbi => ahbmi, --ahbmi,
348 350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
349 351 ahbsi => ahbsi, --ahbsi,
350 352 ahbso => ahbso, --ahbso,
351 353 irqi => irqi(i), --irqi(CPU_HINDEX),
352 354 irqo => irqo(i), --irqo(CPU_HINDEX),
353 355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
354 356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
355 357 gclk => clkm --clk
356 358 );
357 359 END GENERATE leon3_radhard_i;
358 360
359 361 END GENERATE;
360 362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
361 363
362 364 dsugen : IF CFG_DSU = 1 GENERATE
363 365 dsu0 : dsu3 -- LEON3 Debug Support Unit
364 366 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
365 367 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
366 368 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
367 369 dsui.enable <= '1';
368 370 dsui.break <= '0';
369 371 END GENERATE;
370 372 END GENERATE;
371 373
372 374 nodsu : IF CFG_DSU = 0 GENERATE
373 375 ahbso(2) <= ahbs_none;
374 376 dsuo.tstop <= '0';
375 377 dsuo.active <= '0';
376 378 END GENERATE;
377 379
378 380 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
379 381 irqctrl0 : irqmp -- interrupt controller
380 382 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
381 383 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
382 384 END GENERATE;
383 385 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
384 386 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
385 387 irqi(i).irl <= "0000";
386 388 END GENERATE;
387 389 apbo(2) <= apb_none;
388 390 END GENERATE;
389 391
390 392 ----------------------------------------------------------------------
391 393 --- Memory controllers ---------------------------------------------
392 394 ----------------------------------------------------------------------
393 395 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
394 396 memctrlr : mctrl GENERIC MAP (
395 397 hindex => 0,
396 398 pindex => 0,
397 399 paddr => 0,
398 400 srbanks => 1
399 401 )
400 402 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
401 403 memi.bexcn <= '1';
402 404 memi.brdyn <= '1';
403 405
404 406 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
405 407 nSRAM_OE_s <= memo.ramoen(0);
406 408 END GENERATE;
407 409
408 410 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
409 411 memctrlr : srctrle_0ws
410 412 GENERIC MAP(
411 413 hindex => 0,
412 414 pindex => 0,
413 415 paddr => 0,
414 416 srbanks => 2,
415 banksz => 8, --512k * 32
417 banksz => SRBANKSZ, --512k * 32
416 418 rmw => 1,
417 419 --Aeroflex memory generics:
420 mbpbusy => BYPASS_EDAC_MEMCTRLR,
418 421 mprog => 1, -- program memory by default values after reset
419 422 mpsrate => 15, -- default scrub rate period
420 423 mpb2s => 14, -- default busy to scrub delay
421 424 mpapb => 1, -- instantiate apb register
422 425 mchipcnt => 2,
423 426 mpenall => 1 -- when 0 program only E1 chip, else program all dies
424 427 )
425 428 PORT MAP (
426 429 rst => rstn,
427 430 clk => clkm,
428 431 ahbsi => ahbsi,
429 432 ahbso => ahbso(0),
430 433 apbi => apbi,
431 434 apbo => apbo(0),
432 435 sri => memi,
433 436 sro => memo,
434 437 --Aeroflex memory signals:
435 438 ucerr => OPEN, -- uncorrectable error signal
436 439 mbe => mbe, -- enable memory programming
437 440 mbe_drive => mbe_drive -- drive the MBE memory signal
438 441 );
439 442
440 443 memi.brdyn <= nSRAM_READY;
441 444
442 445 mbe_pad : iopad
443 GENERIC MAP(tech => padtech)
446 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
444 447 PORT MAP(pad => SRAM_MBE,
445 448 i => mbe,
446 449 en => mbe_drive,
447 450 o => memi.bexcn);
448 451
449 452 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
450 453 nSRAM_OE_s <= memo.oen;
451 454
452 455 END GENERATE;
453 456
454 457
455 458 memi.writen <= '1';
456 459 memi.wrn <= "1111";
457 460 memi.bwidth <= "10";
458 461
459 462 bdr : FOR i IN 0 TO 3 GENERATE
460 463 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
461 464 PORT MAP (
462 465 data(31-i*8 DOWNTO 24-i*8),
463 466 memo.data(31-i*8 DOWNTO 24-i*8),
464 467 memo.bdrive(i),
465 468 memi.data(31-i*8 DOWNTO 24-i*8));
466 469 END GENERATE;
467 470
468 471 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
469 472 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
470 473 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
471 474 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
472 475 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
473 476 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
474 477 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
475 478 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
476 479 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
477 480
478 481
479 482
480 483 ----------------------------------------------------------------------
481 484 --- AHB CONTROLLER -------------------------------------------------
482 485 ----------------------------------------------------------------------
483 486 ahb0 : ahbctrl -- AHB arbiter/multiplexer
484 487 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
485 488 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
486 489 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
487 490 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
488 491
489 492 ----------------------------------------------------------------------
490 493 --- AHB UART -------------------------------------------------------
491 494 ----------------------------------------------------------------------
492 495 dcomgen : IF CFG_AHB_UART = 1 GENERATE
493 496 dcom0 : ahbuart
494 497 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
495 498 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
496 499 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
497 500 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
498 501 END GENERATE;
499 502 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
500 503
501 504 ----------------------------------------------------------------------
502 505 --- APB Bridge -----------------------------------------------------
503 506 ----------------------------------------------------------------------
504 507 apb0 : apbctrl -- AHB/APB bridge
505 508 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
506 509 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
507 510
508 511 ----------------------------------------------------------------------
509 512 --- GPT Timer ------------------------------------------------------
510 513 ----------------------------------------------------------------------
511 514 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
512 515 timer0 : gptimer -- timer unit
513 516 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
514 517 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
515 518 nbits => CFG_GPT_TW)
516 519 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
517 520 gpti.dhalt <= dsuo.tstop;
518 521 gpti.extclk <= '0';
519 522 END GENERATE;
520 523 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
521 524
522 525
523 526 ----------------------------------------------------------------------
524 527 --- APB UART -------------------------------------------------------
525 528 ----------------------------------------------------------------------
526 529 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
527 530 uart1 : apbuart -- UART 1
528 531 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
529 532 fifosize => CFG_UART1_FIFO)
530 533 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
531 534 apbuarti.rxd <= urxd1;
532 535 apbuarti.extclk <= '0';
533 536 utxd1 <= apbuarto.txd;
534 537 apbuarti.ctsn <= '0';
535 538 END GENERATE;
536 539 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
537 540
538 541 -------------------------------------------------------------------------------
539 542 -- AMBA BUS -------------------------------------------------------------------
540 543 -------------------------------------------------------------------------------
541 544
542 545 -- APB --------------------------------------------------------------------
543 546 apbi_ext <= apbi;
544 547 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
545 548 max_16_apb : IF I + 5 < 16 GENERATE
546 549 apbo(I+5) <= apbo_ext(I+5);
547 550 END GENERATE max_16_apb;
548 551 END GENERATE all_apb;
549 552 -- AHB_Slave --------------------------------------------------------------
550 553 ahbi_s_ext <= ahbsi;
551 554 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
552 555 max_16_ahbs : IF I + 3 < 16 GENERATE
553 556 ahbso(I+3) <= ahbo_s_ext(I+3);
554 557 END GENERATE max_16_ahbs;
555 558 END GENERATE all_ahbs;
556 559 -- AHB_Master -------------------------------------------------------------
557 560 ahbi_m_ext <= ahbmi;
558 561 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
559 562 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
560 563 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
561 564 END GENERATE max_16_ahbm;
562 565 END GENERATE all_ahbm;
563 566
564 567
565 568
566 569 END Behavioral;
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@@ -1,143 +1,145
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27
28 28 PACKAGE lpp_leon3_soc_pkg IS
29 29
30 30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
31 31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
32 32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
33 33
34 34 COMPONENT leon3_soc
35 35 GENERIC (
36 36 fabtech : INTEGER;
37 37 memtech : INTEGER;
38 38 padtech : INTEGER;
39 39 clktech : INTEGER;
40 40 disas : INTEGER;
41 41 dbguart : INTEGER;
42 42 pclow : INTEGER;
43 43 clk_freq : INTEGER;
44 44 IS_RADHARD : INTEGER;
45 45 NB_CPU : INTEGER;
46 46 ENABLE_FPU : INTEGER;
47 47 FPU_NETLIST : INTEGER;
48 48 ENABLE_DSU : INTEGER;
49 49 ENABLE_AHB_UART : INTEGER;
50 50 ENABLE_APB_UART : INTEGER;
51 51 ENABLE_IRQMP : INTEGER;
52 52 ENABLE_GPT : INTEGER;
53 53 NB_AHB_MASTER : INTEGER;
54 54 NB_AHB_SLAVE : INTEGER;
55 55 NB_APB_SLAVE : INTEGER;
56 56 ADDRESS_SIZE : INTEGER;
57 USES_IAP_MEMCTRLR : INTEGER
57 USES_IAP_MEMCTRLR : INTEGER;
58 BYPASS_EDAC_MEMCTRLR : STD_LOGIC;
59 SRBANKSZ : INTEGER := 8
58 60 );
59 61 PORT (
60 62 clk : IN STD_ULOGIC;
61 63 reset : IN STD_ULOGIC;
62 64
63 65 errorn : OUT STD_ULOGIC;
64 66
65 67 -- UART AHB ---------------------------------------------------------------
66 68 ahbrxd : IN STD_ULOGIC; -- DSU rx data
67 69 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
68 70
69 71 -- UART APB ---------------------------------------------------------------
70 72 urxd1 : IN STD_ULOGIC; -- UART1 rx data
71 73 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
72 74
73 75 -- RAM --------------------------------------------------------------------
74 76 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
75 77 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 78 nSRAM_BE0 : OUT STD_LOGIC;
77 79 nSRAM_BE1 : OUT STD_LOGIC;
78 80 nSRAM_BE2 : OUT STD_LOGIC;
79 81 nSRAM_BE3 : OUT STD_LOGIC;
80 82 nSRAM_WE : OUT STD_LOGIC;
81 83 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
82 84 nSRAM_OE : OUT STD_LOGIC;
83 85 nSRAM_READY : IN STD_LOGIC;
84 86 SRAM_MBE : INOUT STD_LOGIC;
85 87 -- APB --------------------------------------------------------------------
86 88 apbi_ext : OUT apb_slv_in_type;
87 89 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
88 90 -- AHB_Slave --------------------------------------------------------------
89 91 ahbi_s_ext : OUT ahb_slv_in_type;
90 92 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
91 93 -- AHB_Master -------------------------------------------------------------
92 94 ahbi_m_ext : OUT AHB_Mst_In_Type;
93 95 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
94 96 END COMPONENT;
95 97
96 98
97 99 --COMPONENT leon3ft_soc
98 100 -- GENERIC (
99 101 -- fabtech : INTEGER;
100 102 -- memtech : INTEGER;
101 103 -- padtech : INTEGER;
102 104 -- clktech : INTEGER;
103 105 -- disas : INTEGER;
104 106 -- dbguart : INTEGER;
105 107 -- pclow : INTEGER;
106 108 -- clk_freq : INTEGER;
107 109 -- NB_CPU : INTEGER;
108 110 -- ENABLE_FPU : INTEGER;
109 111 -- FPU_NETLIST : INTEGER;
110 112 -- ENABLE_DSU : INTEGER;
111 113 -- ENABLE_AHB_UART : INTEGER;
112 114 -- ENABLE_APB_UART : INTEGER;
113 115 -- ENABLE_IRQMP : INTEGER;
114 116 -- ENABLE_GPT : INTEGER;
115 117 -- NB_AHB_MASTER : INTEGER;
116 118 -- NB_AHB_SLAVE : INTEGER;
117 119 -- NB_APB_SLAVE : INTEGER);
118 120 -- PORT (
119 121 -- clk : IN STD_ULOGIC;
120 122 -- reset : IN STD_ULOGIC;
121 123 -- errorn : OUT STD_ULOGIC;
122 124 -- ahbrxd : IN STD_ULOGIC;
123 125 -- ahbtxd : OUT STD_ULOGIC;
124 126 -- urxd1 : IN STD_ULOGIC;
125 127 -- utxd1 : OUT STD_ULOGIC;
126 128 -- address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
127 129 -- data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 130 -- nSRAM_BE0 : OUT STD_LOGIC;
129 131 -- nSRAM_BE1 : OUT STD_LOGIC;
130 132 -- nSRAM_BE2 : OUT STD_LOGIC;
131 133 -- nSRAM_BE3 : OUT STD_LOGIC;
132 134 -- nSRAM_WE : OUT STD_LOGIC;
133 135 -- nSRAM_CE : OUT STD_LOGIC;
134 136 -- nSRAM_OE : OUT STD_LOGIC;
135 137 -- apbi_ext : OUT apb_slv_in_type;
136 138 -- apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
137 139 -- ahbi_s_ext : OUT ahb_slv_in_type;
138 140 -- ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
139 141 -- ahbi_m_ext : OUT AHB_Mst_In_Type;
140 142 -- ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
141 143 --END COMPONENT;
142 144
143 145 END;
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