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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Few updates....
Jean-christophe Pellion -
r676:0a7aa144c9d5 default draft
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=testbench
5 BOARD=LFR-FM
6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=
9 QSF=
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT=
13 VHDLSYNFILES=
14 VHDLSIMFILES= tb.vhd
15 SIMTOP=testbench
16 CLEAN=soft-clean
17
18 TECHLIBS = axcelerator
19
20 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi
22
23 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
24 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
25 grlfpc \
26 ./dsp/lpp_fft_rtax \
27 ./amba_lcd_16x2_ctrlr \
28 ./general_purpose/lpp_AMR \
29 ./general_purpose/lpp_balise \
30 ./general_purpose/lpp_delay \
31 ./lpp_bootloader \
32 ./lfr_management \
33 ./lpp_sim/CY7C1061DV33 \
34 ./lpp_cna \
35 ./lpp_uart \
36 ./lpp_usb \
37 ./dsp/lpp_fft \
38 ./lpp_leon3_soc \
39 ./lpp_debug_lfr
40
41 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
45 APB_FFT.vhd \
46 lpp_lfr_ms_FFT.vhd \
47 lpp_lfr_apbreg.vhd \
48 CoreFFT.vhd \
49 lpp_lfr_ms.vhd \
50 lpp_lfr_sim_pkg.vhd \
51 mtie_maps.vhd \
52 ftsrctrlc.vhd \
53 ftsdctrl.vhd \
54 ftsrctrl8.vhd \
55 ftmctrl.vhd \
56 ftsdctrl64.vhd \
57 ftahbram.vhd \
58 ftahbram2.vhd \
59 sramft.vhd \
60 nandfctrlx.vhd
61
62 include $(GRLIB)/bin/Makefile
63 include $(GRLIB)/software/leon3/Makefile
64 ################## project specific targets ##########################
65 distclean:myclean
66
67 myclean:
68 rm -f input.txt output_f*.txt *.log
69 rm -rf ./2016*
70 rm -f ./RAM*.txt run.do
71
72 generate :
73 python ./generate.py
74
75 archivate:
76 python ./archivate.py
77
78 test: test-vsim
79
80 test-vsim: custom-vsim-run archivate
81
82 custom-vsim-run: | vsim generate
83 vsim -c -do run.do
84
85
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1 {
2 "cells": [
3 {
4 "cell_type": "code",
5 "execution_count": null,
6 "metadata": {
7 "collapsed": false
8 },
9 "outputs": [],
10 "source": [
11 "#%matplotlib qt\n",
12 "%matplotlib notebook\n",
13 "import matplotlib.pyplot as plt\n",
14 "#plt.rcParams[\"figure.figsize\"] = [12,12]\n",
15 "import numpy as np\n",
16 "import pandas as pds"
17 ]
18 },
19 {
20 "cell_type": "code",
21 "execution_count": null,
22 "metadata": {
23 "collapsed": false
24 },
25 "outputs": [],
26 "source": [
27 "def try_plot(df,ax,left,right):\n",
28 " try:\n",
29 " df[(df.index >= left) & (df.index <= right)].plot(ax=ax,subplots=True,legend=False)\n",
30 " except:\n",
31 " pass\n",
32 " \n",
33 "def make_plots(path=\"./\",left=50e-3,right=100e-3):\n",
34 " inputSig = pds.read_csv(path+\"/input.txt\",delim_whitespace=True,header=None,names=[\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
35 " inputSig.index.name=\"TSTAMP\"\n",
36 " inputSig.index*=1./98304.\n",
37 " fXSig=[]\n",
38 " G=[0.89,0.87,0.89]\n",
39 " [fXSig.append(pds.read_csv(\n",
40 " path+\"./output_f{0}.txt\".format(F),index_col=0,delim_whitespace=True,header=None,\n",
41 " names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])) for F in range(3) ]\n",
42 " for F in range(3):\n",
43 " if len(fXSig[F].index):\n",
44 " fXSig[F].index*=1e-9\n",
45 " fXSig[F]/=G[F]\n",
46 " axes=inputSig[(inputSig.index >= left) & (inputSig.index <= right)].filter([\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"]).plot(subplots=True,layout=(3,2)) \n",
47 " [ try_plot(df,axes,left,right) for df in fXSig ]\n",
48 " return inputSig,fXSig\n",
49 " "
50 ]
51 },
52 {
53 "cell_type": "code",
54 "execution_count": null,
55 "metadata": {
56 "collapsed": false
57 },
58 "outputs": [],
59 "source": [
60 "inputSig,fXSig=make_plots(left=0)"
61 ]
62 }
63 ],
64 "metadata": {
65 "kernelspec": {
66 "display_name": "Python 3",
67 "language": "python",
68 "name": "python3"
69 },
70 "language_info": {
71 "codemirror_mode": {
72 "name": "ipython",
73 "version": 3
74 },
75 "file_extension": ".py",
76 "mimetype": "text/x-python",
77 "name": "python",
78 "nbconvert_exporter": "python",
79 "pygments_lexer": "ipython3",
80 "version": "3.5.2"
81 }
82 },
83 "nbformat": 4,
84 "nbformat_minor": 1
85 }
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1 import os
2 import shutil
3 import datetime as dt
4 import glob
5
6 folder=dt.datetime.today().strftime("%Y-%m-%d_%H-%M-%S")
7 os.mkdir(folder)
8 shutil.copy("input.txt",folder+"/input.txt")
9 for file in glob.glob("output_f*.txt"):
10 shutil.copy(file, folder)
11
12 for file in glob.glob("RAM*.txt"):
13 shutil.copy(file, folder)
14
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1 import numpy as np
2 import random
3 import time
4 import shutil
5 import os
6
7 DOFILE="run.do.in"
8 RAM1={
9 "instance":"/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd",
10 "abits":10,
11 "dbits":36,
12 "name":"RAM1.txt"
13 }
14 RAM2={
15 "instance":"/testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd",
16 "abits":10,
17 "dbits":36,
18 "name":"RAM2.txt"
19 }
20 RAM3={
21 "instance":"/testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd",
22 "abits":10,
23 "dbits":36,
24 "name":"RAM3.txt"
25 }
26 RAM4={
27 "instance":"/testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd",
28 "abits":10,
29 "dbits":36,
30 "name":"RAM4.txt"
31 }
32 RAM5={
33 "instance":"/testbench/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd",
34 "abits":10,
35 "dbits":36,
36 "name":"RAM5.txt"
37 }
38 RAM6={
39 "instance":"/testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(1)/u0/u0/rp/rfd",
40 "abits":10,
41 "dbits":36,
42 "name":"RAM6.txt"
43 }
44
45
46
47 RAMS=[RAM1,RAM2,RAM3,RAM4,RAM5,RAM6]
48
49
50
51
52
53
54
55 def mkram(length,width,gentype='rand',**kwargs):
56 return toBinStr(gen(length,width,gentype,**kwargs),width)
57
58 def toBinStr(data,width):
59 return [format(val, 'b').zfill(width) for val in data]
60
61 def gen(length,width,gentype='rand',**kwargs):
62 LUT={
63 "rand":gen_rand,
64 "const":gen_const
65 }
66 return LUT[gentype](length,width,**kwargs)
67
68 def gen_rand(length,width,**kwargs):
69 random.seed(time.time())
70 mask=(2**width)-1
71 data=[]
72 for line in range(length):
73 data.append(int(2**32*random.random())&mask)
74 return data
75
76 def gen_const(length,width, value):
77 mask=(2**width)-1
78 return [value&mask for i in range(length)]
79
80 def save(data,file):
81 f = open(file,"w")
82 [f.write(line+'\n') for line in data]
83 f.close()
84
85 if not os.path.exists("simulation"):
86 os.mkdir('simulation')
87
88 args=""
89 for RAM in RAMS:
90 save(mkram(2**RAM["abits"],RAM["dbits"],gentype='rand',value=0),""+RAM["name"])
91 args = args +"mem load -i {RAMFILE} -format binary {PATH}\n".format(RAMFILE=RAM["name"], PATH=RAM["instance"])
92 with open("run.do.in","r") as inFile, open("run.do","w") as outFile:
93 input = inFile.read()
94 outFile.write(input.replace("#RAM_INIT#",args))
95
96 W,H=8,400
97 test = np.ones((H,W))*[(random.random()*65535)-32768 for col in range(W)]
98 np.savetxt("input.txt", test,fmt="%d", delimiter=" ")
99
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1 quietly set ACTELLIBNAME Axcelerator
2 quietly set PROJECT_DIR "C:/opt/VHDLIB/tests/Validation_LFR_Filter_Ram_Init"
3
4
5 vsim -L Axcelerator -L presynth -L grlib -L synplify -L techmap -L spw -L eth -L gaisler -L esa -L fmf -L spansion -L gsi -L iap -L lpp -L cypress -t 1ps work.testbench
6 # The following lines are commented because no testbench is associated with the project
7 # do "wave.do"
8
9 #RAM_INIT#
10
11 run 20000ms
12 quit
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 use ieee.numeric_std.all;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
7
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
10
11 library std;
12 use std.textio.all;
13
14 LIBRARY lpp;
15 USE lpp.iir_filter.ALL;
16 USE lpp.lpp_ad_conv.ALL;
17 USE lpp.FILTERcfg.ALL;
18 USE lpp.lpp_lfr_filter_coeff.ALL;
19 USE lpp.general_purpose.ALL;
20 USE lpp.data_type_pkg.ALL;
21 USE lpp.lpp_lfr_pkg.ALL;
22 USE lpp.general_purpose.ALL;
23 USE lpp.lpp_sim_pkg.ALL;
24
25 ENTITY testbench IS
26 GENERIC(
27 tech : INTEGER := axcel; --axcel,0
28 Mem_use : INTEGER := use_RAM --use_RAM,use_CEL
29 );
30 END;
31
32 ARCHITECTURE behav OF testbench IS
33 CONSTANT ChanelCount : INTEGER := 8;
34
35 SIGNAL TSTAMP : INTEGER:=0;
36 SIGNAL clk : STD_LOGIC := '0';
37 SIGNAL clk_98304Hz : STD_LOGIC := '0';
38 SIGNAL clk_98304Hz_r : STD_LOGIC := '0';
39 SIGNAL rstn : STD_LOGIC;
40
41 SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,15 downto 0);
42
43 SIGNAL sample : Samples(7 DOWNTO 0);
44
45 SIGNAL sample_val : STD_LOGIC;
46
47 SIGNAL sample_f0_val : STD_LOGIC;
48 SIGNAL sample_f1_val : STD_LOGIC;
49 SIGNAL sample_f2_val : STD_LOGIC;
50 SIGNAL sample_f3_val : STD_LOGIC;
51
52 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
53 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
54 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
55 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
56
57 SIGNAL signal_f0_rec : sample_vector(0 to 5,15 downto 0);
58 SIGNAL signal_f1_rec : sample_vector(0 to 5,15 downto 0);
59 SIGNAL signal_f2_rec : sample_vector(0 to 5,15 downto 0);
60 SIGNAL signal_f3_rec : sample_vector(0 to 5,15 downto 0);
61
62 SIGNAL end_of_simu : STD_LOGIC := '0';
63
64 CONSTANT half_samplig_period : time := 5086263 ps;--INTEGER( REAL(REAL(1000**4) / REAL(2.0*4.0*24576.0))) * 1 ps;
65
66
67
68 BEGIN
69
70 -----------------------------------------------------------------------------
71 -- CLOCK and RESET
72 -----------------------------------------------------------------------------
73 PROCESS
74 BEGIN -- PROCESS
75 WAIT UNTIL clk = '1';
76 rstn <= '0';
77 WAIT UNTIL clk = '1';
78 WAIT UNTIL clk = '1';
79 WAIT UNTIL clk = '1';
80 rstn <= '1';
81 WAIT UNTIL end_of_simu = '1';
82 WAIT FOR 10 ps;
83 assert false report "end of test" severity note;
84 -- Wait forever; this will finish the simulation.
85 wait;
86 END PROCESS;
87 -----------------------------------------------------------------------------
88
89
90 clk_98304Hz_gen:PROCESS
91 BEGIN
92 IF end_of_simu /= '1' THEN
93 clk_98304Hz <= NOT clk_98304Hz;
94 WAIT FOR half_samplig_period;
95 ELSE
96 WAIT FOR 10 ps;
97 assert false report "end of test" severity note;
98 WAIT;
99 END IF;
100 END PROCESS;
101
102 clk_25M_gen:PROCESS
103 BEGIN
104 IF end_of_simu /= '1' THEN
105 clk <= NOT clk;
106 TSTAMP <= TSTAMP+20;
107 WAIT FOR 20 ns;
108 ELSE
109 WAIT FOR 10 ps;
110 assert false report "end of test" severity note;
111 WAIT;
112 END IF;
113 END PROCESS;
114
115
116 -----------------------------------------------------------------------------
117 -- LPP_LFR_FILTER
118 -----------------------------------------------------------------------------
119 lpp_lfr_filter_1: lpp_lfr_filter
120 GENERIC MAP (
121 tech => tech,
122 Mem_use => Mem_use,
123 RTL_DESIGN_LIGHT =>0,
124 DATA_SHAPING_SATURATION => 0
125 )
126 PORT MAP (
127 sample => sample,
128 sample_val => sample_val,
129 sample_time => (others=>'0'),
130 clk => clk,
131 rstn => rstn,
132
133 data_shaping_SP0 => '0',
134 data_shaping_SP1 => '0',
135 data_shaping_R0 => '0',
136 data_shaping_R1 => '0',
137 data_shaping_R2 => '0',
138
139 sample_f0_val => sample_f0_val,
140 sample_f1_val => sample_f1_val,
141 sample_f2_val => sample_f2_val,
142 sample_f3_val => sample_f3_val,
143
144 sample_f0_wdata => sample_f0_wdata,
145 sample_f1_wdata => sample_f1_wdata,
146 sample_f2_wdata => sample_f2_wdata,
147 sample_f3_wdata => sample_f3_wdata
148 );
149 -----------------------------------------------------------------------------
150
151
152 -----------------------------------------------------------------------------
153 -- SAMPLE PULSE GENERATION
154 -----------------------------------------------------------------------------
155 PROCESS (clk, rstn)
156 BEGIN -- PROCESS
157 IF rstn = '0' THEN -- asynchronous reset (active low)
158 sample_val <= '0';
159 clk_98304Hz_r <= '0';
160 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
161 IF end_of_simu /= '1' THEN
162 clk_98304Hz_r <= clk_98304Hz;
163 IF clk_98304Hz = '1' AND clk_98304Hz_r = '0' THEN
164 sample_val <= '1';
165 ELSE
166 sample_val <= '0';
167 END IF;
168 END IF;
169 END IF;
170 END PROCESS;
171 -----------------------------------------------------------------------------
172
173
174 -----------------------------------------------------------------------------
175 -- READ INPUT SIGNALS
176 -----------------------------------------------------------------------------
177 gen: sig_reader
178 GENERIC MAP(
179 FNAME => "input.txt",
180 WIDTH => ChanelCount,
181 RESOLUTION => 16,
182 GAIN => 1.0
183 )
184 PORT MAP(
185 clk => sample_val,
186 end_of_simu => end_of_simu,
187 out_signal => signal_gen
188 );
189
190 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
191 SampleLoop : FOR j IN 0 TO 15 GENERATE
192 sample(I)(J) <= signal_gen(I,J);
193 END GENERATE;
194 END GENERATE;
195
196 output_splitter: FOR CHAN IN 0 TO 5 GENERATE
197 bits_splitter: FOR BIT IN 0 TO 15 GENERATE
198 signal_f0_rec(CHAN,BIT) <= sample_f0_wdata((CHAN*16) + BIT);
199 signal_f1_rec(CHAN,BIT) <= sample_f1_wdata((CHAN*16) + BIT);
200 signal_f2_rec(CHAN,BIT) <= sample_f2_wdata((CHAN*16) + BIT);
201 signal_f3_rec(CHAN,BIT) <= sample_f3_wdata((CHAN*16) + BIT);
202 END GENERATE bits_splitter;
203 END GENERATE output_splitter;
204
205
206 -----------------------------------------------------------------------------
207 -- RECORD SIGNALS
208 -----------------------------------------------------------------------------
209
210 f0_rec : sig_recorder
211 GENERIC MAP(
212 FNAME => "output_f0.txt",
213 WIDTH => 6,
214 RESOLUTION => 16
215 )
216 PORT MAP(
217 clk => sample_f0_val,
218 end_of_simu => end_of_simu,
219 timestamp => TSTAMP,
220 input_signal => signal_f0_rec
221 );
222
223 f1_rec : sig_recorder
224 GENERIC MAP(
225 FNAME => "output_f1.txt",
226 WIDTH => 6,
227 RESOLUTION => 16
228 )
229 PORT MAP(
230 clk => sample_f1_val,
231 end_of_simu => end_of_simu,
232 timestamp => TSTAMP,
233 input_signal => signal_f1_rec
234 );
235
236 f2_rec : sig_recorder
237 GENERIC MAP(
238 FNAME => "output_f2.txt",
239 WIDTH => 6,
240 RESOLUTION => 16
241 )
242 PORT MAP(
243 clk => sample_f2_val,
244 end_of_simu => end_of_simu,
245 timestamp => TSTAMP,
246 input_signal => signal_f2_rec
247 );
248
249 f3_rec : sig_recorder
250 GENERIC MAP(
251 FNAME => "output_f3.txt",
252 WIDTH => 6,
253 RESOLUTION => 16
254 )
255 PORT MAP(
256 clk => sample_f3_val,
257 end_of_simu => end_of_simu,
258 timestamp => TSTAMP,
259 input_signal => signal_f3_rec
260 );
261
262 END;
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@@ -1,4 +1,4
1 lpp_sim_pkg.vhd
1 2 sig_reader.vhd
2 3 sig_recorder.vhd
3 lpp_sim_pkg.vhd
4 4 lpp_lfr_sim_pkg.vhd
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@@ -2,7 +2,7 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=testbench
5 BOARD=LFR-EQM
5 BOARD=LFR-FM
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=
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@@ -2,7 +2,7 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=testbench
5 BOARD=LFR-EQM
5 BOARD=LFR-FM
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=
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@@ -3,7 +3,7 SELFDIR := $(dir $(lastword $(MAKEFILE_L
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=testbench
6 BOARD=LFR-EQM
6 BOARD=LFR-FM
7 7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 UCF=
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@@ -120,7 +120,8 BEGIN
120 120 GENERIC MAP (
121 121 tech => tech,
122 122 Mem_use => Mem_use,
123 RTL_DESIGN_LIGHT =>0
123 RTL_DESIGN_LIGHT =>0,
124 DATA_SHAPING_SATURATION => 0
124 125 )
125 126 PORT MAP (
126 127 sample => sample,
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@@ -2,7 +2,7 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=testbench
5 BOARD=LFR-EQM
5 BOARD=LFR-FM
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=
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@@ -2,7 +2,7 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=testbench
5 BOARD=LFR-EQM
5 BOARD=LFR-FM
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=
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