diff --git a/lib/lpp/lpp_sim/vhdlsim.txt b/lib/lpp/lpp_sim/vhdlsim.txt --- a/lib/lpp/lpp_sim/vhdlsim.txt +++ b/lib/lpp/lpp_sim/vhdlsim.txt @@ -1,4 +1,4 @@ +lpp_sim_pkg.vhd sig_reader.vhd sig_recorder.vhd -lpp_sim_pkg.vhd lpp_lfr_sim_pkg.vhd diff --git a/tests/Validation_IIR_f0_LFR/Makefile b/tests/Validation_IIR_f0_LFR/Makefile --- a/tests/Validation_IIR_f0_LFR/Makefile +++ b/tests/Validation_IIR_f0_LFR/Makefile @@ -2,7 +2,7 @@ VHDLIB=../.. SCRIPTSDIR=$(VHDLIB)/scripts/ GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) TOP=testbench -BOARD=LFR-EQM +BOARD=LFR-FM include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) UCF= diff --git a/tests/Validation_IIR_f1_LFR/Makefile b/tests/Validation_IIR_f1_LFR/Makefile --- a/tests/Validation_IIR_f1_LFR/Makefile +++ b/tests/Validation_IIR_f1_LFR/Makefile @@ -2,7 +2,7 @@ VHDLIB=../.. SCRIPTSDIR=$(VHDLIB)/scripts/ GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) TOP=testbench -BOARD=LFR-EQM +BOARD=LFR-FM include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) UCF= diff --git a/tests/Validation_LFR_Filter_Ram_Init/Makefile b/tests/Validation_LFR_Filter_Ram_Init/Makefile new file mode 100644 --- /dev/null +++ b/tests/Validation_LFR_Filter_Ram_Init/Makefile @@ -0,0 +1,85 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=testbench +BOARD=LFR-FM +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF= +QSF= +EFFORT=high +XSTOPT= +SYNPOPT= +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +CLEAN=soft-clean + +TECHLIBS = axcelerator + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi + +DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \ + grlfpc \ + ./dsp/lpp_fft_rtax \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lfr_management \ + ./lpp_sim/CY7C1061DV33 \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft \ + ./lpp_leon3_soc \ + ./lpp_debug_lfr + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_ms_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd \ + lpp_lfr_ms.vhd \ + lpp_lfr_sim_pkg.vhd \ + mtie_maps.vhd \ + ftsrctrlc.vhd \ + ftsdctrl.vhd \ + ftsrctrl8.vhd \ + ftmctrl.vhd \ + ftsdctrl64.vhd \ + ftahbram.vhd \ + ftahbram2.vhd \ + sramft.vhd \ + nandfctrlx.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile +################## project specific targets ########################## +distclean:myclean + +myclean: + rm -f input.txt output_f*.txt *.log + rm -rf ./2016* + rm -f ./RAM*.txt run.do + +generate : + python ./generate.py + +archivate: + python ./archivate.py + +test: test-vsim + +test-vsim: custom-vsim-run archivate + +custom-vsim-run: | vsim generate + vsim -c -do run.do + + diff --git a/tests/Validation_LFR_Filter_Ram_Init/PlotResults.ipynb b/tests/Validation_LFR_Filter_Ram_Init/PlotResults.ipynb new file mode 100644 --- /dev/null +++ b/tests/Validation_LFR_Filter_Ram_Init/PlotResults.ipynb @@ -0,0 +1,85 @@ +{ + "cells": [ + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "#%matplotlib qt\n", + "%matplotlib notebook\n", + "import matplotlib.pyplot as plt\n", + "#plt.rcParams[\"figure.figsize\"] = [12,12]\n", + "import numpy as np\n", + "import pandas as pds" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "def try_plot(df,ax,left,right):\n", + " try:\n", + " df[(df.index >= left) & (df.index <= right)].plot(ax=ax,subplots=True,legend=False)\n", + " except:\n", + " pass\n", + " \n", + "def make_plots(path=\"./\",left=50e-3,right=100e-3):\n", + " inputSig = pds.read_csv(path+\"/input.txt\",delim_whitespace=True,header=None,names=[\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n", + " inputSig.index.name=\"TSTAMP\"\n", + " inputSig.index*=1./98304.\n", + " fXSig=[]\n", + " G=[0.89,0.87,0.89]\n", + " [fXSig.append(pds.read_csv(\n", + " path+\"./output_f{0}.txt\".format(F),index_col=0,delim_whitespace=True,header=None,\n", + " names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])) for F in range(3) ]\n", + " for F in range(3):\n", + " if len(fXSig[F].index):\n", + " fXSig[F].index*=1e-9\n", + " fXSig[F]/=G[F]\n", + " axes=inputSig[(inputSig.index >= left) & (inputSig.index <= right)].filter([\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"]).plot(subplots=True,layout=(3,2)) \n", + " [ try_plot(df,axes,left,right) for df in fXSig ]\n", + " return inputSig,fXSig\n", + " " + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "inputSig,fXSig=make_plots(left=0)" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.5.2" + } + }, + "nbformat": 4, + "nbformat_minor": 1 +} diff --git a/tests/Validation_LFR_Filter_Ram_Init/archivate.py b/tests/Validation_LFR_Filter_Ram_Init/archivate.py new file mode 100644 --- /dev/null +++ b/tests/Validation_LFR_Filter_Ram_Init/archivate.py @@ -0,0 +1,14 @@ +import os +import shutil +import datetime as dt +import glob + +folder=dt.datetime.today().strftime("%Y-%m-%d_%H-%M-%S") +os.mkdir(folder) +shutil.copy("input.txt",folder+"/input.txt") +for file in glob.glob("output_f*.txt"): + shutil.copy(file, folder) + +for file in glob.glob("RAM*.txt"): + shutil.copy(file, folder) + diff --git a/tests/Validation_LFR_Filter_Ram_Init/generate.py b/tests/Validation_LFR_Filter_Ram_Init/generate.py new file mode 100644 --- /dev/null +++ b/tests/Validation_LFR_Filter_Ram_Init/generate.py @@ -0,0 +1,99 @@ +import numpy as np +import random +import time +import shutil +import os + +DOFILE="run.do.in" +RAM1={ +"instance":"/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd", +"abits":10, +"dbits":36, +"name":"RAM1.txt" +} +RAM2={ +"instance":"/testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd", +"abits":10, +"dbits":36, +"name":"RAM2.txt" +} +RAM3={ +"instance":"/testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd", +"abits":10, +"dbits":36, +"name":"RAM3.txt" +} +RAM4={ +"instance":"/testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd", +"abits":10, +"dbits":36, +"name":"RAM4.txt" +} +RAM5={ +"instance":"/testbench/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/rp/rfd", +"abits":10, +"dbits":36, +"name":"RAM5.txt" +} +RAM6={ +"instance":"/testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(1)/u0/u0/rp/rfd", +"abits":10, +"dbits":36, +"name":"RAM6.txt" +} + + + +RAMS=[RAM1,RAM2,RAM3,RAM4,RAM5,RAM6] + + + + + + + +def mkram(length,width,gentype='rand',**kwargs): + return toBinStr(gen(length,width,gentype,**kwargs),width) + +def toBinStr(data,width): + return [format(val, 'b').zfill(width) for val in data] + +def gen(length,width,gentype='rand',**kwargs): + LUT={ + "rand":gen_rand, + "const":gen_const + } + return LUT[gentype](length,width,**kwargs) + +def gen_rand(length,width,**kwargs): + random.seed(time.time()) + mask=(2**width)-1 + data=[] + for line in range(length): + data.append(int(2**32*random.random())&mask) + return data + +def gen_const(length,width, value): + mask=(2**width)-1 + return [value&mask for i in range(length)] + +def save(data,file): + f = open(file,"w") + [f.write(line+'\n') for line in data] + f.close() + +if not os.path.exists("simulation"): + os.mkdir('simulation') + +args="" +for RAM in RAMS: + save(mkram(2**RAM["abits"],RAM["dbits"],gentype='rand',value=0),""+RAM["name"]) + args = args +"mem load -i {RAMFILE} -format binary {PATH}\n".format(RAMFILE=RAM["name"], PATH=RAM["instance"]) +with open("run.do.in","r") as inFile, open("run.do","w") as outFile: + input = inFile.read() + outFile.write(input.replace("#RAM_INIT#",args)) + +W,H=8,400 +test = np.ones((H,W))*[(random.random()*65535)-32768 for col in range(W)] +np.savetxt("input.txt", test,fmt="%d", delimiter=" ") + diff --git a/tests/Validation_LFR_Filter_Ram_Init/run.do.in b/tests/Validation_LFR_Filter_Ram_Init/run.do.in new file mode 100644 --- /dev/null +++ b/tests/Validation_LFR_Filter_Ram_Init/run.do.in @@ -0,0 +1,12 @@ +quietly set ACTELLIBNAME Axcelerator +quietly set PROJECT_DIR "C:/opt/VHDLIB/tests/Validation_LFR_Filter_Ram_Init" + + +vsim -L Axcelerator -L presynth -L grlib -L synplify -L techmap -L spw -L eth -L gaisler -L esa -L fmf -L spansion -L gsi -L iap -L lpp -L cypress -t 1ps work.testbench +# The following lines are commented because no testbench is associated with the project +# do "wave.do" + +#RAM_INIT# + +run 20000ms +quit diff --git a/tests/Validation_LFR_Filter_Ram_Init/tb.vhd b/tests/Validation_LFR_Filter_Ram_Init/tb.vhd new file mode 100644 --- /dev/null +++ b/tests/Validation_LFR_Filter_Ram_Init/tb.vhd @@ -0,0 +1,262 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +use ieee.numeric_std.all; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +library std; +use std.textio.all; + +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_lfr_filter_coeff.ALL; +USE lpp.general_purpose.ALL; +USE lpp.data_type_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_sim_pkg.ALL; + +ENTITY testbench IS +GENERIC( + tech : INTEGER := axcel; --axcel,0 + Mem_use : INTEGER := use_RAM --use_RAM,use_CEL +); +END; + +ARCHITECTURE behav OF testbench IS + CONSTANT ChanelCount : INTEGER := 8; + + SIGNAL TSTAMP : INTEGER:=0; + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL clk_98304Hz : STD_LOGIC := '0'; + SIGNAL clk_98304Hz_r : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + + SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,15 downto 0); + + SIGNAL sample : Samples(7 DOWNTO 0); + + SIGNAL sample_val : STD_LOGIC; + + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f3_val : STD_LOGIC; + + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + SIGNAL signal_f0_rec : sample_vector(0 to 5,15 downto 0); + SIGNAL signal_f1_rec : sample_vector(0 to 5,15 downto 0); + SIGNAL signal_f2_rec : sample_vector(0 to 5,15 downto 0); + SIGNAL signal_f3_rec : sample_vector(0 to 5,15 downto 0); + + SIGNAL end_of_simu : STD_LOGIC := '0'; + + CONSTANT half_samplig_period : time := 5086263 ps;--INTEGER( REAL(REAL(1000**4) / REAL(2.0*4.0*24576.0))) * 1 ps; + + + +BEGIN + + ----------------------------------------------------------------------------- + -- CLOCK and RESET + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rstn <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL end_of_simu = '1'; + WAIT FOR 10 ps; + assert false report "end of test" severity note; + -- Wait forever; this will finish the simulation. + wait; + END PROCESS; + ----------------------------------------------------------------------------- + + + clk_98304Hz_gen:PROCESS + BEGIN + IF end_of_simu /= '1' THEN + clk_98304Hz <= NOT clk_98304Hz; + WAIT FOR half_samplig_period; + ELSE + WAIT FOR 10 ps; + assert false report "end of test" severity note; + WAIT; + END IF; + END PROCESS; + + clk_25M_gen:PROCESS + BEGIN + IF end_of_simu /= '1' THEN + clk <= NOT clk; + TSTAMP <= TSTAMP+20; + WAIT FOR 20 ns; + ELSE + WAIT FOR 10 ps; + assert false report "end of test" severity note; + WAIT; + END IF; + END PROCESS; + + + ----------------------------------------------------------------------------- + -- LPP_LFR_FILTER + ----------------------------------------------------------------------------- + lpp_lfr_filter_1: lpp_lfr_filter + GENERIC MAP ( + tech => tech, + Mem_use => Mem_use, + RTL_DESIGN_LIGHT =>0, + DATA_SHAPING_SATURATION => 0 + ) + PORT MAP ( + sample => sample, + sample_val => sample_val, + sample_time => (others=>'0'), + clk => clk, + rstn => rstn, + + data_shaping_SP0 => '0', + data_shaping_SP1 => '0', + data_shaping_R0 => '0', + data_shaping_R1 => '0', + data_shaping_R2 => '0', + + sample_f0_val => sample_f0_val, + sample_f1_val => sample_f1_val, + sample_f2_val => sample_f2_val, + sample_f3_val => sample_f3_val, + + sample_f0_wdata => sample_f0_wdata, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wdata => sample_f2_wdata, + sample_f3_wdata => sample_f3_wdata + ); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- SAMPLE PULSE GENERATION + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val <= '0'; + clk_98304Hz_r <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF end_of_simu /= '1' THEN + clk_98304Hz_r <= clk_98304Hz; + IF clk_98304Hz = '1' AND clk_98304Hz_r = '0' THEN + sample_val <= '1'; + ELSE + sample_val <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- READ INPUT SIGNALS + ----------------------------------------------------------------------------- +gen: sig_reader + GENERIC MAP( + FNAME => "input.txt", + WIDTH => ChanelCount, + RESOLUTION => 16, + GAIN => 1.0 + ) + PORT MAP( + clk => sample_val, + end_of_simu => end_of_simu, + out_signal => signal_gen + ); + +ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE + SampleLoop : FOR j IN 0 TO 15 GENERATE + sample(I)(J) <= signal_gen(I,J); + END GENERATE; +END GENERATE; + +output_splitter: FOR CHAN IN 0 TO 5 GENERATE + bits_splitter: FOR BIT IN 0 TO 15 GENERATE + signal_f0_rec(CHAN,BIT) <= sample_f0_wdata((CHAN*16) + BIT); + signal_f1_rec(CHAN,BIT) <= sample_f1_wdata((CHAN*16) + BIT); + signal_f2_rec(CHAN,BIT) <= sample_f2_wdata((CHAN*16) + BIT); + signal_f3_rec(CHAN,BIT) <= sample_f3_wdata((CHAN*16) + BIT); + END GENERATE bits_splitter; +END GENERATE output_splitter; + + + ----------------------------------------------------------------------------- + -- RECORD SIGNALS + ----------------------------------------------------------------------------- + +f0_rec : sig_recorder + GENERIC MAP( + FNAME => "output_f0.txt", + WIDTH => 6, + RESOLUTION => 16 + ) + PORT MAP( + clk => sample_f0_val, + end_of_simu => end_of_simu, + timestamp => TSTAMP, + input_signal => signal_f0_rec + ); + +f1_rec : sig_recorder + GENERIC MAP( + FNAME => "output_f1.txt", + WIDTH => 6, + RESOLUTION => 16 + ) + PORT MAP( + clk => sample_f1_val, + end_of_simu => end_of_simu, + timestamp => TSTAMP, + input_signal => signal_f1_rec + ); + +f2_rec : sig_recorder + GENERIC MAP( + FNAME => "output_f2.txt", + WIDTH => 6, + RESOLUTION => 16 + ) + PORT MAP( + clk => sample_f2_val, + end_of_simu => end_of_simu, + timestamp => TSTAMP, + input_signal => signal_f2_rec + ); + +f3_rec : sig_recorder + GENERIC MAP( + FNAME => "output_f3.txt", + WIDTH => 6, + RESOLUTION => 16 + ) + PORT MAP( + clk => sample_f3_val, + end_of_simu => end_of_simu, + timestamp => TSTAMP, + input_signal => signal_f3_rec + ); + +END; diff --git a/tests/Validation_LFR_Filters/Makefile b/tests/Validation_LFR_Filters/Makefile --- a/tests/Validation_LFR_Filters/Makefile +++ b/tests/Validation_LFR_Filters/Makefile @@ -3,7 +3,7 @@ SELFDIR := $(dir $(lastword $(MAKEFILE_L SCRIPTSDIR=$(VHDLIB)/scripts/ GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) TOP=testbench -BOARD=LFR-EQM +BOARD=LFR-FM include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) UCF= diff --git a/tests/Validation_LFR_Filters/tb.vhd b/tests/Validation_LFR_Filters/tb.vhd --- a/tests/Validation_LFR_Filters/tb.vhd +++ b/tests/Validation_LFR_Filters/tb.vhd @@ -120,7 +120,8 @@ BEGIN GENERIC MAP ( tech => tech, Mem_use => Mem_use, - RTL_DESIGN_LIGHT =>0 + RTL_DESIGN_LIGHT =>0, + DATA_SHAPING_SATURATION => 0 ) PORT MAP ( sample => sample, diff --git a/tests/Validation_LFR_Filters_ShapingSaturation_DISABLED/Makefile b/tests/Validation_LFR_Filters_ShapingSaturation_DISABLED/Makefile --- a/tests/Validation_LFR_Filters_ShapingSaturation_DISABLED/Makefile +++ b/tests/Validation_LFR_Filters_ShapingSaturation_DISABLED/Makefile @@ -2,7 +2,7 @@ VHDLIB=../.. SCRIPTSDIR=$(VHDLIB)/scripts/ GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) TOP=testbench -BOARD=LFR-EQM +BOARD=LFR-FM include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) UCF= diff --git a/tests/Validation_LFR_Filters_ShapingSaturation_ENABLED/Makefile b/tests/Validation_LFR_Filters_ShapingSaturation_ENABLED/Makefile --- a/tests/Validation_LFR_Filters_ShapingSaturation_ENABLED/Makefile +++ b/tests/Validation_LFR_Filters_ShapingSaturation_ENABLED/Makefile @@ -2,7 +2,7 @@ VHDLIB=../.. SCRIPTSDIR=$(VHDLIB)/scripts/ GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) TOP=testbench -BOARD=LFR-EQM +BOARD=LFR-FM include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) UCF=